Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit c8577819009473311d5f74112e136f17d7859ee1

Authored by David S. Miller 2014-11-21 13:07:51 +0800

Exists in ti-lsk-linux-4.1.y and in 10 other branches

Merge tag 'master-2014-11-20' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless

John W. Linville says:

====================
pull request: wireless 2014-11-20

Please full this little batch of fixes intended for the 3.18 stream!

For the mac80211 patch, Johannes says:

"Here's another last minute fix, for minstrel HT crashing
depending on the value of some uninitialised stack."

On top of that...

Ben Greear fixes an ath9k regression in which a BSSID mask is
miscalculated.

Dmitry Torokhov corrects an error handling routing in brcmfmac which
was checking an unsigned variable for a negative value.

Johannes Berg avoids a build problem in brcmfmac for arches where
linux/unaligned/access_ok.h and asm/unaligned.h conflict.

Mathy Vanhoef addresses another brcmfmac issue so as to eliminate a
use-after-free of the URB transfer buffer if a timeout occurs.

Please let me know if there are problems!
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 5 changed files Inline Diff

drivers/net/wireless/ath/ath9k/main.c
drivers/net/wireless/brcm80211/brcmfmac/of.c
drivers/net/wireless/brcm80211/brcmfmac/pcie.c
drivers/net/wireless/brcm80211/brcmfmac/usb.c
net/mac80211/rc80211_minstrel_ht.c

drivers/net/wireless/ath/ath9k/main.c

Diff comments View file @ c857781

 /*
  * Copyright (c) 2008-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
  *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include <linux/nl80211.h>
 #include <linux/delay.h>
 #include "ath9k.h"
 #include "btcoex.h"
 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
 {
 	/*
 	 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 	 *   0 for no restriction
 	 *   1 for 1/4 us
 	 *   2 for 1/2 us
 	 *   3 for 1 us
 	 *   4 for 2 us
 	 *   5 for 4 us
 	 *   6 for 8 us
 	 *   7 for 16 us
 	 */
 	switch (mpdudensity) {
 	case 0:
 		return 0;
 	case 1:
 	case 2:
 	case 3:
 		/* Our lower layer calculations limit our precision to
 		   1 microsecond */
 		return 1;
 	case 4:
 		return 2;
 	case 5:
 		return 4;
 	case 6:
 		return 8;
 	case 7:
 		return 16;
 	default:
 		return 0;
 	}
 }
 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
 {
 	bool pending = false;
 	spin_lock_bh(&txq->axq_lock);
 	if (txq->axq_depth) {
 		pending = true;
 		goto out;
 	}
 	if (txq->mac80211_qnum >= 0) {
 		struct list_head *list;
 		list = &sc->cur_chan->acq[txq->mac80211_qnum];
 		if (!list_empty(list))
 			pending = true;
 	}
 out:
 	spin_unlock_bh(&txq->axq_lock);
 	return pending;
 }
 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 {
 	unsigned long flags;
 	bool ret;
 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
 	ret = ath9k_hw_setpower(sc->sc_ah, mode);
 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 	return ret;
 }
 void ath_ps_full_sleep(unsigned long data)
 {
 	struct ath_softc *sc = (struct ath_softc *) data;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	bool reset;
 	spin_lock(&common->cc_lock);
 	ath_hw_cycle_counters_update(common);
 	spin_unlock(&common->cc_lock);
 	ath9k_hw_setrxabort(sc->sc_ah, 1);
 	ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
 	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 }
 void ath9k_ps_wakeup(struct ath_softc *sc)
 {
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	unsigned long flags;
 	enum ath9k_power_mode power_mode;
 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
 	if (++sc->ps_usecount != 1)
 		goto unlock;
 	del_timer_sync(&sc->sleep_timer);
 	power_mode = sc->sc_ah->power_mode;
 	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 	/*
 	 * While the hardware is asleep, the cycle counters contain no
 	 * useful data. Better clear them now so that they don't mess up
 	 * survey data results.
 	 */
 	if (power_mode != ATH9K_PM_AWAKE) {
 		spin_lock(&common->cc_lock);
 		ath_hw_cycle_counters_update(common);
 		memset(&common->cc_survey, 0, sizeof(common->cc_survey));
 		memset(&common->cc_ani, 0, sizeof(common->cc_ani));
 		spin_unlock(&common->cc_lock);
 	}
  unlock:
 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 }
 void ath9k_ps_restore(struct ath_softc *sc)
 {
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	enum ath9k_power_mode mode;
 	unsigned long flags;
 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
 	if (--sc->ps_usecount != 0)
 		goto unlock;
 	if (sc->ps_idle) {
 		mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
 		goto unlock;
 	}
 	if (sc->ps_enabled &&
 		   !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
 				     PS_WAIT_FOR_CAB |
 				     PS_WAIT_FOR_PSPOLL_DATA |
 				     PS_WAIT_FOR_TX_ACK |
 				     PS_WAIT_FOR_ANI))) {
 		mode = ATH9K_PM_NETWORK_SLEEP;
 		if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
 			ath9k_btcoex_stop_gen_timer(sc);
 	} else {
 		goto unlock;
 	}
 	spin_lock(&common->cc_lock);
 	ath_hw_cycle_counters_update(common);
 	spin_unlock(&common->cc_lock);
 	ath9k_hw_setpower(sc->sc_ah, mode);
  unlock:
 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 }
 static void __ath_cancel_work(struct ath_softc *sc)
 {
 	cancel_work_sync(&sc->paprd_work);
 	cancel_delayed_work_sync(&sc->tx_complete_work);
 	cancel_delayed_work_sync(&sc->hw_pll_work);
 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 	if (ath9k_hw_mci_is_enabled(sc->sc_ah))
 		cancel_work_sync(&sc->mci_work);
 #endif
 }
 void ath_cancel_work(struct ath_softc *sc)
 {
 	__ath_cancel_work(sc);
 	cancel_work_sync(&sc->hw_reset_work);
 }
 void ath_restart_work(struct ath_softc *sc)
 {
 	ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
 	if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
 		ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
 				     msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
 	ath_start_ani(sc);
 }
 static bool ath_prepare_reset(struct ath_softc *sc)
 {
 	struct ath_hw *ah = sc->sc_ah;
 	bool ret = true;
 	ieee80211_stop_queues(sc->hw);
 	ath_stop_ani(sc);
 	ath9k_hw_disable_interrupts(ah);
 	if (!ath_drain_all_txq(sc))
 		ret = false;
 	if (!ath_stoprecv(sc))
 		ret = false;
 	return ret;
 }
 static bool ath_complete_reset(struct ath_softc *sc, bool start)
 {
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	unsigned long flags;
 	ath9k_calculate_summary_state(sc, sc->cur_chan);
 	ath_startrecv(sc);
 	ath9k_cmn_update_txpow(ah, sc->curtxpow,
 			       sc->cur_chan->txpower, &sc->curtxpow);
 	clear_bit(ATH_OP_HW_RESET, &common->op_flags);
 	if (!sc->cur_chan->offchannel && start) {
 		/* restore per chanctx TSF timer */
 		if (sc->cur_chan->tsf_val) {
 			u32 offset;
 			offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
 							 NULL);
 			ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
 		}
 		if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
 			goto work;
 		if (ah->opmode == NL80211_IFTYPE_STATION &&
 		    test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
 			spin_lock_irqsave(&sc->sc_pm_lock, flags);
 			sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
 			spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 		} else {
 			ath9k_set_beacon(sc);
 		}
 	work:
 		ath_restart_work(sc);
 		ath_txq_schedule_all(sc);
 	}
 	sc->gtt_cnt = 0;
 	ath9k_hw_set_interrupts(ah);
 	ath9k_hw_enable_interrupts(ah);
 	ieee80211_wake_queues(sc->hw);
 	ath9k_p2p_ps_timer(sc);
 	return true;
 }
 int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
 {
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	struct ath9k_hw_cal_data *caldata = NULL;
 	bool fastcc = true;
 	int r;
 	__ath_cancel_work(sc);
 	tasklet_disable(&sc->intr_tq);
 	spin_lock_bh(&sc->sc_pcu_lock);
 	if (!sc->cur_chan->offchannel) {
 		fastcc = false;
 		caldata = &sc->cur_chan->caldata;
 	}
 	if (!hchan) {
 		fastcc = false;
 		hchan = ah->curchan;
 	}
 	if (!ath_prepare_reset(sc))
 		fastcc = false;
 	if (ath9k_is_chanctx_enabled())
 		fastcc = false;
 	spin_lock_bh(&sc->chan_lock);
 	sc->cur_chandef = sc->cur_chan->chandef;
 	spin_unlock_bh(&sc->chan_lock);
 	ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
 		hchan->channel, IS_CHAN_HT40(hchan), fastcc);
 	r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
 	if (r) {
 		ath_err(common,
 			"Unable to reset channel, reset status %d\n", r);
 		ath9k_hw_enable_interrupts(ah);
 		ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
 		goto out;
 	}
 	if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
 	    sc->cur_chan->offchannel)
 		ath9k_mci_set_txpower(sc, true, false);
 	if (!ath_complete_reset(sc, true))
 		r = -EIO;
 out:
 	spin_unlock_bh(&sc->sc_pcu_lock);
 	tasklet_enable(&sc->intr_tq);
 	return r;
 }
 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
 			    struct ieee80211_vif *vif)
 {
 	struct ath_node *an;
 	an = (struct ath_node *)sta->drv_priv;
 	an->sc = sc;
 	an->sta = sta;
 	an->vif = vif;
 	memset(&an->key_idx, 0, sizeof(an->key_idx));
 	ath_tx_node_init(sc, an);
 	ath_dynack_node_init(sc->sc_ah, an);
 }
 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 {
 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
 	ath_tx_node_cleanup(sc, an);
 	ath_dynack_node_deinit(sc->sc_ah, an);
 }
 void ath9k_tasklet(unsigned long data)
 {
 	struct ath_softc *sc = (struct ath_softc *)data;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	enum ath_reset_type type;
 	unsigned long flags;
 	u32 status = sc->intrstatus;
 	u32 rxmask;
 	ath9k_ps_wakeup(sc);
 	spin_lock(&sc->sc_pcu_lock);
 	if (status & ATH9K_INT_FATAL) {
 		type = RESET_TYPE_FATAL_INT;
 		ath9k_queue_reset(sc, type);
 		/*
 		 * Increment the ref. counter here so that
 		 * interrupts are enabled in the reset routine.
 		 */
 		atomic_inc(&ah->intr_ref_cnt);
 		ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
 		goto out;
 	}
 	if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
 	    (status & ATH9K_INT_BB_WATCHDOG)) {
 		spin_lock(&common->cc_lock);
 		ath_hw_cycle_counters_update(common);
 		ar9003_hw_bb_watchdog_dbg_info(ah);
 		spin_unlock(&common->cc_lock);
 		if (ar9003_hw_bb_watchdog_check(ah)) {
 			type = RESET_TYPE_BB_WATCHDOG;
 			ath9k_queue_reset(sc, type);
 			/*
 			 * Increment the ref. counter here so that
 			 * interrupts are enabled in the reset routine.
 			 */
 			atomic_inc(&ah->intr_ref_cnt);
 			ath_dbg(common, RESET,
 				"BB_WATCHDOG: Skipping interrupts\n");
 			goto out;
 		}
 	}
 	if (status & ATH9K_INT_GTT) {
 		sc->gtt_cnt++;
 		if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
 			type = RESET_TYPE_TX_GTT;
 			ath9k_queue_reset(sc, type);
 			atomic_inc(&ah->intr_ref_cnt);
 			ath_dbg(common, RESET,
 				"GTT: Skipping interrupts\n");
 			goto out;
 		}
 	}
 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
 	if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 		/*
 		 * TSF sync does not look correct; remain awake to sync with
 		 * the next Beacon.
 		 */
 		ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
 		sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
 	}
 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 		rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
 			  ATH9K_INT_RXORN);
 	else
 		rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 	if (status & rxmask) {
 		/* Check for high priority Rx first */
 		if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
 		    (status & ATH9K_INT_RXHP))
 			ath_rx_tasklet(sc, 0, true);
 		ath_rx_tasklet(sc, 0, false);
 	}
 	if (status & ATH9K_INT_TX) {
 		if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 			/*
 			 * For EDMA chips, TX completion is enabled for the
 			 * beacon queue, so if a beacon has been transmitted
 			 * successfully after a GTT interrupt, the GTT counter
 			 * gets reset to zero here.
 			 */
 			sc->gtt_cnt = 0;
 			ath_tx_edma_tasklet(sc);
 		} else {
 			ath_tx_tasklet(sc);
 		}
 		wake_up(&sc->tx_wait);
 	}
 	if (status & ATH9K_INT_GENTIMER)
 		ath_gen_timer_isr(sc->sc_ah);
 	ath9k_btcoex_handle_interrupt(sc, status);
 	/* re-enable hardware interrupt */
 	ath9k_hw_enable_interrupts(ah);
 out:
 	spin_unlock(&sc->sc_pcu_lock);
 	ath9k_ps_restore(sc);
 }
 irqreturn_t ath_isr(int irq, void *dev)
 {
 #define SCHED_INTR (				\
 		ATH9K_INT_FATAL |		\
 		ATH9K_INT_BB_WATCHDOG |		\
 		ATH9K_INT_RXORN |		\
 		ATH9K_INT_RXEOL |		\
 		ATH9K_INT_RX |			\
 		ATH9K_INT_RXLP |		\
 		ATH9K_INT_RXHP |		\
 		ATH9K_INT_TX |			\
 		ATH9K_INT_BMISS |		\
 		ATH9K_INT_CST |			\
 		ATH9K_INT_GTT |			\
 		ATH9K_INT_TSFOOR |		\
 		ATH9K_INT_GENTIMER |		\
 		ATH9K_INT_MCI)
 	struct ath_softc *sc = dev;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	enum ath9k_int status;
 	u32 sync_cause = 0;
 	bool sched = false;
 	/*
 	 * The hardware is not ready/present, don't
 	 * touch anything. Note this can happen early
 	 * on if the IRQ is shared.
 	 */
 	if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
 		return IRQ_NONE;
 	/* shared irq, not for us */
 	if (!ath9k_hw_intrpend(ah))
 		return IRQ_NONE;
 	if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
 		ath9k_hw_kill_interrupts(ah);
 		return IRQ_HANDLED;
 	}
 	/*
 	 * Figure out the reason(s) for the interrupt.  Note
 	 * that the hal returns a pseudo-ISR that may include
 	 * bits we haven't explicitly enabled so we mask the
 	 * value to insure we only process bits we requested.
 	 */
 	ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
 	ath9k_debug_sync_cause(sc, sync_cause);
 	status &= ah->imask;	/* discard unasked-for bits */
 	/*
 	 * If there are no status bits set, then this interrupt was not
 	 * for me (should have been caught above).
 	 */
 	if (!status)
 		return IRQ_NONE;
 	/* Cache the status */
 	sc->intrstatus = status;
 	if (status & SCHED_INTR)
 		sched = true;
 	/*
 	 * If a FATAL or RXORN interrupt is received, we have to reset the
 	 * chip immediately.
 	 */
 	if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
 	    !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
 		goto chip_reset;
 	if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
 	    (status & ATH9K_INT_BB_WATCHDOG))
 		goto chip_reset;
 #ifdef CONFIG_ATH9K_WOW
 	if (status & ATH9K_INT_BMISS) {
 		if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
 			atomic_inc(&sc->wow_got_bmiss_intr);
 			atomic_dec(&sc->wow_sleep_proc_intr);
 		}
 	}
 #endif
 	if (status & ATH9K_INT_SWBA)
 		tasklet_schedule(&sc->bcon_tasklet);
 	if (status & ATH9K_INT_TXURN)
 		ath9k_hw_updatetxtriglevel(ah, true);
 	if (status & ATH9K_INT_RXEOL) {
 		ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 		ath9k_hw_set_interrupts(ah);
 	}
 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 		if (status & ATH9K_INT_TIM_TIMER) {
 			if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
 				goto chip_reset;
 			/* Clear RxAbort bit so that we can
 			 * receive frames */
 			ath9k_setpower(sc, ATH9K_PM_AWAKE);
 			spin_lock(&sc->sc_pm_lock);
 			ath9k_hw_setrxabort(sc->sc_ah, 0);
 			sc->ps_flags |= PS_WAIT_FOR_BEACON;
 			spin_unlock(&sc->sc_pm_lock);
 		}
 chip_reset:
 	ath_debug_stat_interrupt(sc, status);
 	if (sched) {
 		/* turn off every interrupt */
 		ath9k_hw_disable_interrupts(ah);
 		tasklet_schedule(&sc->intr_tq);
 	}
 	return IRQ_HANDLED;
 #undef SCHED_INTR
 }
 int ath_reset(struct ath_softc *sc)
 {
 	int r;
 	ath9k_ps_wakeup(sc);
 	r = ath_reset_internal(sc, NULL);
 	ath9k_ps_restore(sc);
 	return r;
 }
 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
 {
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 #ifdef CONFIG_ATH9K_DEBUGFS
 	RESET_STAT_INC(sc, type);
 #endif
 	set_bit(ATH_OP_HW_RESET, &common->op_flags);
 	ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
 }
 void ath_reset_work(struct work_struct *work)
 {
 	struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
 	ath_reset(sc);
 }
 /**********************/
 /* mac80211 callbacks */
 /**********************/
 static int ath9k_start(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
 	struct ath_chanctx *ctx = sc->cur_chan;
 	struct ath9k_channel *init_channel;
 	int r;
 	ath_dbg(common, CONFIG,
 		"Starting driver with initial channel: %d MHz\n",
 		curchan->center_freq);
 	ath9k_ps_wakeup(sc);
 	mutex_lock(&sc->mutex);
 	init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
 	sc->cur_chandef = hw->conf.chandef;
 	/* Reset SERDES registers */
 	ath9k_hw_configpcipowersave(ah, false);
 	/*
 	 * The basic interface to setting the hardware in a good
 	 * state is ``reset''.  On return the hardware is known to
 	 * be powered up and with interrupts disabled.  This must
 	 * be followed by initialization of the appropriate bits
 	 * and then setup of the interrupt mask.
 	 */
 	spin_lock_bh(&sc->sc_pcu_lock);
 	atomic_set(&ah->intr_ref_cnt, -1);
 	r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
 	if (r) {
 		ath_err(common,
 			"Unable to reset hardware; reset status %d (freq %u MHz)\n",
 			r, curchan->center_freq);
 		ah->reset_power_on = false;
 	}
 	/* Setup our intr mask. */
 	ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
 		    ATH9K_INT_RXORN | ATH9K_INT_FATAL |
 		    ATH9K_INT_GLOBAL;
 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 		ah->imask |= ATH9K_INT_RXHP |
 			     ATH9K_INT_RXLP;
 	else
 		ah->imask |= ATH9K_INT_RX;
 	if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
 		ah->imask |= ATH9K_INT_BB_WATCHDOG;
 	/*
 	 * Enable GTT interrupts only for AR9003/AR9004 chips
 	 * for now.
 	 */
 	if (AR_SREV_9300_20_OR_LATER(ah))
 		ah->imask |= ATH9K_INT_GTT;
 	if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
 		ah->imask |= ATH9K_INT_CST;
 	ath_mci_enable(sc);
 	clear_bit(ATH_OP_INVALID, &common->op_flags);
 	sc->sc_ah->is_monitoring = false;
 	if (!ath_complete_reset(sc, false))
 		ah->reset_power_on = false;
 	if (ah->led_pin >= 0) {
 		ath9k_hw_cfg_output(ah, ah->led_pin,
 				    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 		ath9k_hw_set_gpio(ah, ah->led_pin, 0);
 	}
 	/*
 	 * Reset key cache to sane defaults (all entries cleared) instead of
 	 * semi-random values after suspend/resume.
 	 */
 	ath9k_cmn_init_crypto(sc->sc_ah);
 	ath9k_hw_reset_tsf(ah);
 	spin_unlock_bh(&sc->sc_pcu_lock);
 	mutex_unlock(&sc->mutex);
 	ath9k_ps_restore(sc);
 	return 0;
 }
 static void ath9k_tx(struct ieee80211_hw *hw,
 		     struct ieee80211_tx_control *control,
 		     struct sk_buff *skb)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_tx_control txctl;
 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
 	unsigned long flags;
 	if (sc->ps_enabled) {
 		/*
 		 * mac80211 does not set PM field for normal data frames, so we
 		 * need to update that based on the current PS mode.
 		 */
 		if (ieee80211_is_data(hdr->frame_control) &&
 		    !ieee80211_is_nullfunc(hdr->frame_control) &&
 		    !ieee80211_has_pm(hdr->frame_control)) {
 			ath_dbg(common, PS,
 				"Add PM=1 for a TX frame while in PS mode\n");
 			hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
 		}
 	}
 	if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
 		/*
 		 * We are using PS-Poll and mac80211 can request TX while in
 		 * power save mode. Need to wake up hardware for the TX to be
 		 * completed and if needed, also for RX of buffered frames.
 		 */
 		ath9k_ps_wakeup(sc);
 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
 		if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 			ath9k_hw_setrxabort(sc->sc_ah, 0);
 		if (ieee80211_is_pspoll(hdr->frame_control)) {
 			ath_dbg(common, PS,
 				"Sending PS-Poll to pick a buffered frame\n");
 			sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
 		} else {
 			ath_dbg(common, PS, "Wake up to complete TX\n");
 			sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
 		}
 		/*
 		 * The actual restore operation will happen only after
 		 * the ps_flags bit is cleared. We are just dropping
 		 * the ps_usecount here.
 		 */
 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 		ath9k_ps_restore(sc);
 	}
 	/*
 	 * Cannot tx while the hardware is in full sleep, it first needs a full
 	 * chip reset to recover from that
 	 */
 	if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
 		ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
 		goto exit;
 	}
 	memset(&txctl, 0, sizeof(struct ath_tx_control));
 	txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
 	txctl.sta = control->sta;
 	ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
 	if (ath_tx_start(hw, skb, &txctl) != 0) {
 		ath_dbg(common, XMIT, "TX failed\n");
 		TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
 		goto exit;
 	}
 	return;
 exit:
 	ieee80211_free_txskb(hw, skb);
 }
 static void ath9k_stop(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	bool prev_idle;
 	ath9k_deinit_channel_context(sc);
 	mutex_lock(&sc->mutex);
 	ath_cancel_work(sc);
 	if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
 		ath_dbg(common, ANY, "Device not present\n");
 		mutex_unlock(&sc->mutex);
 		return;
 	}
 	/* Ensure HW is awake when we try to shut it down. */
 	ath9k_ps_wakeup(sc);
 	spin_lock_bh(&sc->sc_pcu_lock);
 	/* prevent tasklets to enable interrupts once we disable them */
 	ah->imask &= ~ATH9K_INT_GLOBAL;
 	/* make sure h/w will not generate any interrupt
 	 * before setting the invalid flag. */
 	ath9k_hw_disable_interrupts(ah);
 	spin_unlock_bh(&sc->sc_pcu_lock);
 	/* we can now sync irq and kill any running tasklets, since we already
 	 * disabled interrupts and not holding a spin lock */
 	synchronize_irq(sc->irq);
 	tasklet_kill(&sc->intr_tq);
 	tasklet_kill(&sc->bcon_tasklet);
 	prev_idle = sc->ps_idle;
 	sc->ps_idle = true;
 	spin_lock_bh(&sc->sc_pcu_lock);
 	if (ah->led_pin >= 0) {
 		ath9k_hw_set_gpio(ah, ah->led_pin, 1);
 		ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
 	}
 	ath_prepare_reset(sc);
 	if (sc->rx.frag) {
 		dev_kfree_skb_any(sc->rx.frag);
 		sc->rx.frag = NULL;
 	}
 	if (!ah->curchan)
 		ah->curchan = ath9k_cmn_get_channel(hw, ah,
 						    &sc->cur_chan->chandef);
 	ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
 	ath9k_hw_phy_disable(ah);
 	ath9k_hw_configpcipowersave(ah, true);
 	spin_unlock_bh(&sc->sc_pcu_lock);
 	ath9k_ps_restore(sc);
 	set_bit(ATH_OP_INVALID, &common->op_flags);
 	sc->ps_idle = prev_idle;
 	mutex_unlock(&sc->mutex);
 	ath_dbg(common, CONFIG, "Driver halt\n");
 }
 static bool ath9k_uses_beacons(int type)
 {
 	switch (type) {
 	case NL80211_IFTYPE_AP:
 	case NL80211_IFTYPE_ADHOC:
 	case NL80211_IFTYPE_MESH_POINT:
 		return true;
 	default:
 		return false;
 	}
 }
 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
 			   u8 *mac, struct ieee80211_vif *vif)
 {
 	struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
 	int i;
 	if (iter_data->has_hw_macaddr) {
 		for (i = 0; i < ETH_ALEN; i++)
 			iter_data->mask[i] &=
 				~(iter_data->hw_macaddr[i] ^ mac[i]);
 	} else {
 		memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
 		iter_data->has_hw_macaddr = true;
 	}
 	if (!vif->bss_conf.use_short_slot)
 		iter_data->slottime = ATH9K_SLOT_TIME_20;
 	switch (vif->type) {
 	case NL80211_IFTYPE_AP:
 		iter_data->naps++;
 		break;
 	case NL80211_IFTYPE_STATION:
 		iter_data->nstations++;
 		if (avp->assoc && !iter_data->primary_sta)
 			iter_data->primary_sta = vif;
 		break;
 	case NL80211_IFTYPE_ADHOC:
 		iter_data->nadhocs++;
 		if (vif->bss_conf.enable_beacon)
 			iter_data->beacons = true;
 		break;
 	case NL80211_IFTYPE_MESH_POINT:
 		iter_data->nmeshes++;
 		if (vif->bss_conf.enable_beacon)
 			iter_data->beacons = true;
 		break;
 	case NL80211_IFTYPE_WDS:
 		iter_data->nwds++;
 		break;
 	default:
 		break;
 	}
 }
 static void ath9k_update_bssid_mask(struct ath_softc *sc,
 				    struct ath_chanctx *ctx,
 				    struct ath9k_vif_iter_data *iter_data)
 {
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_vif *avp;
 	int i;
 	if (!ath9k_is_chanctx_enabled())
 		return;
 	list_for_each_entry(avp, &ctx->vifs, list) {
 		if (ctx->nvifs_assigned != 1)
 			continue;
 		if (!avp->vif->p2p || !iter_data->has_hw_macaddr)
 			continue;
 		ether_addr_copy(common->curbssid, avp->bssid);
 		/* perm_addr will be used as the p2p device address. */
 		for (i = 0; i < ETH_ALEN; i++)
 			iter_data->mask[i] &=
 				~(iter_data->hw_macaddr[i] ^
 				  sc->hw->wiphy->perm_addr[i]);
 	}
 }
 /* Called with sc->mutex held. */
 void ath9k_calculate_iter_data(struct ath_softc *sc,
 			       struct ath_chanctx *ctx,
 			       struct ath9k_vif_iter_data *iter_data)
 {
 	struct ath_vif *avp;
 	/*
-	 * Pick the MAC address of the first interface as the new hardware
+	 * The hardware will use primary station addr together with the
-	 * MAC address. The hardware will use it together with the BSSID mask
+	 * BSSID mask when matching addresses.
-	 * when matching addresses.
 	 */
 	memset(iter_data, 0, sizeof(*iter_data));
 	memset(&iter_data->mask, 0xff, ETH_ALEN);
 	iter_data->slottime = ATH9K_SLOT_TIME_9;
 	list_for_each_entry(avp, &ctx->vifs, list)
 		ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
 	ath9k_update_bssid_mask(sc, ctx, iter_data);
 }
 static void ath9k_set_assoc_state(struct ath_softc *sc,
 				  struct ieee80211_vif *vif, bool changed)
 {
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
 	unsigned long flags;
 	set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
 	ether_addr_copy(common->curbssid, avp->bssid);
 	common->curaid = avp->aid;
 	ath9k_hw_write_associd(sc->sc_ah);
 	if (changed) {
 		common->last_rssi = ATH_RSSI_DUMMY_MARKER;
 		sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
 		sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 	}
 	if (ath9k_hw_mci_is_enabled(sc->sc_ah))
 		ath9k_mci_update_wlan_channels(sc, false);
 	ath_dbg(common, CONFIG,
 		"Primary Station interface: %pM, BSSID: %pM\n",
 		vif->addr, common->curbssid);
 }
 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 static void ath9k_set_offchannel_state(struct ath_softc *sc)
 {
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	struct ieee80211_vif *vif = NULL;
 	ath9k_ps_wakeup(sc);
 	if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
 		vif = sc->offchannel.scan_vif;
 	else
 		vif = sc->offchannel.roc_vif;
 	if (WARN_ON(!vif))
 		goto exit;
 	eth_zero_addr(common->curbssid);
 	eth_broadcast_addr(common->bssidmask);
 	ether_addr_copy(common->macaddr, vif->addr);
 	common->curaid = 0;
 	ah->opmode = vif->type;
 	ah->imask &= ~ATH9K_INT_SWBA;
 	ah->imask &= ~ATH9K_INT_TSFOOR;
 	ah->slottime = ATH9K_SLOT_TIME_9;
 	ath_hw_setbssidmask(common);
 	ath9k_hw_setopmode(ah);
 	ath9k_hw_write_associd(sc->sc_ah);
 	ath9k_hw_set_interrupts(ah);
 	ath9k_hw_init_global_settings(ah);
 exit:
 	ath9k_ps_restore(sc);
 }
 #endif
 /* Called with sc->mutex held. */
 void ath9k_calculate_summary_state(struct ath_softc *sc,
 				   struct ath_chanctx *ctx)
 {
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	struct ath9k_vif_iter_data iter_data;
 	struct ath_beacon_config *cur_conf;
 	ath_chanctx_check_active(sc, ctx);
 	if (ctx != sc->cur_chan)
 		return;
 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 	if (ctx == &sc->offchannel.chan)
 		return ath9k_set_offchannel_state(sc);
 #endif
 	ath9k_ps_wakeup(sc);
 	ath9k_calculate_iter_data(sc, ctx, &iter_data);
 	if (iter_data.has_hw_macaddr)
 		ether_addr_copy(common->macaddr, iter_data.hw_macaddr);
 	memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
 	ath_hw_setbssidmask(common);
 	if (iter_data.naps > 0) {
 		cur_conf = &ctx->beacon;
 		ath9k_hw_set_tsfadjust(ah, true);
 		ah->opmode = NL80211_IFTYPE_AP;
 		if (cur_conf->enable_beacon)
 			iter_data.beacons = true;
 	} else {
 		ath9k_hw_set_tsfadjust(ah, false);
 		if (iter_data.nmeshes)
 			ah->opmode = NL80211_IFTYPE_MESH_POINT;
 		else if (iter_data.nwds)
 			ah->opmode = NL80211_IFTYPE_AP;
 		else if (iter_data.nadhocs)
 			ah->opmode = NL80211_IFTYPE_ADHOC;
 		else
 			ah->opmode = NL80211_IFTYPE_STATION;
 	}
 	ath9k_hw_setopmode(ah);
 	ctx->switch_after_beacon = false;
 	if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
 		ah->imask |= ATH9K_INT_TSFOOR;
 	else {
 		ah->imask &= ~ATH9K_INT_TSFOOR;
 		if (iter_data.naps == 1 && iter_data.beacons)
 			ctx->switch_after_beacon = true;
 	}
 	ah->imask &= ~ATH9K_INT_SWBA;
 	if (ah->opmode == NL80211_IFTYPE_STATION) {
 		bool changed = (iter_data.primary_sta != ctx->primary_sta);
 		if (iter_data.primary_sta) {
 			iter_data.beacons = true;
 			ath9k_set_assoc_state(sc, iter_data.primary_sta,
 					      changed);
 			ctx->primary_sta = iter_data.primary_sta;
 		} else {
 			ctx->primary_sta = NULL;
 			memset(common->curbssid, 0, ETH_ALEN);
 			common->curaid = 0;
 			ath9k_hw_write_associd(sc->sc_ah);
 			if (ath9k_hw_mci_is_enabled(sc->sc_ah))
 				ath9k_mci_update_wlan_channels(sc, true);
 		}
 	} else if (iter_data.beacons) {
 		ah->imask |= ATH9K_INT_SWBA;
 	}
 	ath9k_hw_set_interrupts(ah);
 	if (iter_data.beacons)
 		set_bit(ATH_OP_BEACONS, &common->op_flags);
 	else
 		clear_bit(ATH_OP_BEACONS, &common->op_flags);
 	if (ah->slottime != iter_data.slottime) {
 		ah->slottime = iter_data.slottime;
 		ath9k_hw_init_global_settings(ah);
 	}
 	if (iter_data.primary_sta)
 		set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
 	else
 		clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
 	ath_dbg(common, CONFIG,
 		"macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
 		common->macaddr, common->curbssid, common->bssidmask);
 	ath9k_ps_restore(sc);
 }
 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
 				   struct ieee80211_vif *vif)
 {
 	int i;
 	if (!ath9k_is_chanctx_enabled())
 		return;
 	for (i = 0; i < IEEE80211_NUM_ACS; i++)
 		vif->hw_queue[i] = i;
 	if (vif->type == NL80211_IFTYPE_AP)
 		vif->cab_queue = hw->queues - 2;
 	else
 		vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
 }
 static int ath9k_add_interface(struct ieee80211_hw *hw,
 			       struct ieee80211_vif *vif)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	struct ath_vif *avp = (void *)vif->drv_priv;
 	struct ath_node *an = &avp->mcast_node;
 	mutex_lock(&sc->mutex);
 	if (config_enabled(CONFIG_ATH9K_TX99)) {
 		if (sc->cur_chan->nvifs >= 1) {
 			mutex_unlock(&sc->mutex);
 			return -EOPNOTSUPP;
 		}
 		sc->tx99_vif = vif;
 	}
 	ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
 	sc->cur_chan->nvifs++;
 	if (ath9k_uses_beacons(vif->type))
 		ath9k_beacon_assign_slot(sc, vif);
 	avp->vif = vif;
 	if (!ath9k_is_chanctx_enabled()) {
 		avp->chanctx = sc->cur_chan;
 		list_add_tail(&avp->list, &avp->chanctx->vifs);
 	}
+	ath9k_calculate_summary_state(sc, avp->chanctx);
 	ath9k_assign_hw_queues(hw, vif);
 	an->sc = sc;
 	an->sta = NULL;
 	an->vif = vif;
 	an->no_ps_filter = true;
 	ath_tx_node_init(sc, an);
 	mutex_unlock(&sc->mutex);
 	return 0;
 }
 static int ath9k_change_interface(struct ieee80211_hw *hw,
 				  struct ieee80211_vif *vif,
 				  enum nl80211_iftype new_type,
 				  bool p2p)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_vif *avp = (void *)vif->drv_priv;
 	mutex_lock(&sc->mutex);
 	if (config_enabled(CONFIG_ATH9K_TX99)) {
 		mutex_unlock(&sc->mutex);
 		return -EOPNOTSUPP;
 	}
 	ath_dbg(common, CONFIG, "Change Interface\n");
 	if (ath9k_uses_beacons(vif->type))
 		ath9k_beacon_remove_slot(sc, vif);
 	vif->type = new_type;
 	vif->p2p = p2p;
 	if (ath9k_uses_beacons(vif->type))
 		ath9k_beacon_assign_slot(sc, vif);
 	ath9k_assign_hw_queues(hw, vif);
 	ath9k_calculate_summary_state(sc, avp->chanctx);
 	mutex_unlock(&sc->mutex);
 	return 0;
 }
 static void ath9k_remove_interface(struct ieee80211_hw *hw,
 				   struct ieee80211_vif *vif)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_vif *avp = (void *)vif->drv_priv;
 	ath_dbg(common, CONFIG, "Detach Interface\n");
 	mutex_lock(&sc->mutex);
 	ath9k_p2p_remove_vif(sc, vif);
 	sc->cur_chan->nvifs--;
 	sc->tx99_vif = NULL;
 	if (!ath9k_is_chanctx_enabled())
 		list_del(&avp->list);
 	if (ath9k_uses_beacons(vif->type))
 		ath9k_beacon_remove_slot(sc, vif);
 	ath_tx_node_cleanup(sc, &avp->mcast_node);
+	ath9k_calculate_summary_state(sc, avp->chanctx);
 	mutex_unlock(&sc->mutex);
 }
 static void ath9k_enable_ps(struct ath_softc *sc)
 {
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	if (config_enabled(CONFIG_ATH9K_TX99))
 		return;
 	sc->ps_enabled = true;
 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
 		if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
 			ah->imask |= ATH9K_INT_TIM_TIMER;
 			ath9k_hw_set_interrupts(ah);
 		}
 		ath9k_hw_setrxabort(ah, 1);
 	}
 	ath_dbg(common, PS, "PowerSave enabled\n");
 }
 static void ath9k_disable_ps(struct ath_softc *sc)
 {
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	if (config_enabled(CONFIG_ATH9K_TX99))
 		return;
 	sc->ps_enabled = false;
 	ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
 		ath9k_hw_setrxabort(ah, 0);
 		sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
 				  PS_WAIT_FOR_CAB |
 				  PS_WAIT_FOR_PSPOLL_DATA |
 				  PS_WAIT_FOR_TX_ACK);
 		if (ah->imask & ATH9K_INT_TIM_TIMER) {
 			ah->imask &= ~ATH9K_INT_TIM_TIMER;
 			ath9k_hw_set_interrupts(ah);
 		}
 	}
 	ath_dbg(common, PS, "PowerSave disabled\n");
 }
 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	u32 rxfilter;
 	if (config_enabled(CONFIG_ATH9K_TX99))
 		return;
 	if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
 		ath_err(common, "spectrum analyzer not implemented on this hardware\n");
 		return;
 	}
 	ath9k_ps_wakeup(sc);
 	rxfilter = ath9k_hw_getrxfilter(ah);
 	ath9k_hw_setrxfilter(ah, rxfilter |
 				 ATH9K_RX_FILTER_PHYRADAR |
 				 ATH9K_RX_FILTER_PHYERR);
 	/* TODO: usually this should not be neccesary, but for some reason
 	 * (or in some mode?) the trigger must be called after the
 	 * configuration, otherwise the register will have its values reset
 	 * (on my ar9220 to value 0x01002310)
 	 */
 	ath9k_spectral_scan_config(hw, sc->spectral_mode);
 	ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
 	ath9k_ps_restore(sc);
 }
 int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
 			       enum spectral_mode spectral_mode)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
 		ath_err(common, "spectrum analyzer not implemented on this hardware\n");
 		return -1;
 	}
 	switch (spectral_mode) {
 	case SPECTRAL_DISABLED:
 		sc->spec_config.enabled = 0;
 		break;
 	case SPECTRAL_BACKGROUND:
 		/* send endless samples.
 		 * TODO: is this really useful for "background"?
 		 */
 		sc->spec_config.endless = 1;
 		sc->spec_config.enabled = 1;
 		break;
 	case SPECTRAL_CHANSCAN:
 	case SPECTRAL_MANUAL:
 		sc->spec_config.endless = 0;
 		sc->spec_config.enabled = 1;
 		break;
 	default:
 		return -1;
 	}
 	ath9k_ps_wakeup(sc);
 	ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
 	ath9k_ps_restore(sc);
 	sc->spectral_mode = spectral_mode;
 	return 0;
 }
 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	struct ieee80211_conf *conf = &hw->conf;
 	struct ath_chanctx *ctx = sc->cur_chan;
 	ath9k_ps_wakeup(sc);
 	mutex_lock(&sc->mutex);
 	if (changed & IEEE80211_CONF_CHANGE_IDLE) {
 		sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
 		if (sc->ps_idle) {
 			ath_cancel_work(sc);
 			ath9k_stop_btcoex(sc);
 		} else {
 			ath9k_start_btcoex(sc);
 			/*
 			 * The chip needs a reset to properly wake up from
 			 * full sleep
 			 */
 			ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
 		}
 	}
 	/*
 	 * We just prepare to enable PS. We have to wait until our AP has
 	 * ACK'd our null data frame to disable RX otherwise we'll ignore
 	 * those ACKs and end up retransmitting the same null data frames.
 	 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
 	 */
 	if (changed & IEEE80211_CONF_CHANGE_PS) {
 		unsigned long flags;
 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
 		if (conf->flags & IEEE80211_CONF_PS)
 			ath9k_enable_ps(sc);
 		else
 			ath9k_disable_ps(sc);
 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 	}
 	if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
 		if (conf->flags & IEEE80211_CONF_MONITOR) {
 			ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
 			sc->sc_ah->is_monitoring = true;
 		} else {
 			ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
 			sc->sc_ah->is_monitoring = false;
 		}
 	}
 	if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
 		ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
 		ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
 	}
 	if (changed & IEEE80211_CONF_CHANGE_POWER) {
 		ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
 		sc->cur_chan->txpower = 2 * conf->power_level;
 		ath9k_cmn_update_txpow(ah, sc->curtxpow,
 				       sc->cur_chan->txpower, &sc->curtxpow);
 	}
 	mutex_unlock(&sc->mutex);
 	ath9k_ps_restore(sc);
 	return 0;
 }
 #define SUPPORTED_FILTERS			\
 	(FIF_PROMISC_IN_BSS |			\
 	FIF_ALLMULTI |				\
 	FIF_CONTROL |				\
 	FIF_PSPOLL |				\
 	FIF_OTHER_BSS |				\
 	FIF_BCN_PRBRESP_PROMISC |		\
 	FIF_PROBE_REQ |				\
 	FIF_FCSFAIL)
 /* FIXME: sc->sc_full_reset ? */
 static void ath9k_configure_filter(struct ieee80211_hw *hw,
 				   unsigned int changed_flags,
 				   unsigned int *total_flags,
 				   u64 multicast)
 {
 	struct ath_softc *sc = hw->priv;
 	u32 rfilt;
 	changed_flags &= SUPPORTED_FILTERS;
 	*total_flags &= SUPPORTED_FILTERS;
 	spin_lock_bh(&sc->chan_lock);
 	sc->cur_chan->rxfilter = *total_flags;
 	spin_unlock_bh(&sc->chan_lock);
 	ath9k_ps_wakeup(sc);
 	rfilt = ath_calcrxfilter(sc);
 	ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
 	ath9k_ps_restore(sc);
 	ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
 		rfilt);
 }
 static int ath9k_sta_add(struct ieee80211_hw *hw,
 			 struct ieee80211_vif *vif,
 			 struct ieee80211_sta *sta)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_node *an = (struct ath_node *) sta->drv_priv;
 	struct ieee80211_key_conf ps_key = { };
 	int key;
 	ath_node_attach(sc, sta, vif);
 	if (vif->type != NL80211_IFTYPE_AP &&
 	    vif->type != NL80211_IFTYPE_AP_VLAN)
 		return 0;
 	key = ath_key_config(common, vif, sta, &ps_key);
 	if (key > 0) {
 		an->ps_key = key;
 		an->key_idx[0] = key;
 	}
 	return 0;
 }
 static void ath9k_del_ps_key(struct ath_softc *sc,
 			     struct ieee80211_vif *vif,
 			     struct ieee80211_sta *sta)
 {
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_node *an = (struct ath_node *) sta->drv_priv;
 	struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
 	if (!an->ps_key)
 	    return;
 	ath_key_delete(common, &ps_key);
 	an->ps_key = 0;
 	an->key_idx[0] = 0;
 }
 static int ath9k_sta_remove(struct ieee80211_hw *hw,
 			    struct ieee80211_vif *vif,
 			    struct ieee80211_sta *sta)
 {
 	struct ath_softc *sc = hw->priv;
 	ath9k_del_ps_key(sc, vif, sta);
 	ath_node_detach(sc, sta);
 	return 0;
 }
 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
 				    struct ath_node *an,
 				    bool set)
 {
 	int i;
 	for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
 		if (!an->key_idx[i])
 			continue;
 		ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
 	}
 }
 static void ath9k_sta_notify(struct ieee80211_hw *hw,
 			 struct ieee80211_vif *vif,
 			 enum sta_notify_cmd cmd,
 			 struct ieee80211_sta *sta)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_node *an = (struct ath_node *) sta->drv_priv;
 	switch (cmd) {
 	case STA_NOTIFY_SLEEP:
 		an->sleeping = true;
 		ath_tx_aggr_sleep(sta, sc, an);
 		ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
 		break;
 	case STA_NOTIFY_AWAKE:
 		ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
 		an->sleeping = false;
 		ath_tx_aggr_wakeup(sc, an);
 		break;
 	}
 }
 static int ath9k_conf_tx(struct ieee80211_hw *hw,
 			 struct ieee80211_vif *vif, u16 queue,
 			 const struct ieee80211_tx_queue_params *params)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_txq *txq;
 	struct ath9k_tx_queue_info qi;
 	int ret = 0;
 	if (queue >= IEEE80211_NUM_ACS)
 		return 0;
 	txq = sc->tx.txq_map[queue];
 	ath9k_ps_wakeup(sc);
 	mutex_lock(&sc->mutex);
 	memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
 	qi.tqi_aifs = params->aifs;
 	qi.tqi_cwmin = params->cw_min;
 	qi.tqi_cwmax = params->cw_max;
 	qi.tqi_burstTime = params->txop * 32;
 	ath_dbg(common, CONFIG,
 		"Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
 		queue, txq->axq_qnum, params->aifs, params->cw_min,
 		params->cw_max, params->txop);
 	ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
 	ret = ath_txq_update(sc, txq->axq_qnum, &qi);
 	if (ret)
 		ath_err(common, "TXQ Update failed\n");
 	mutex_unlock(&sc->mutex);
 	ath9k_ps_restore(sc);
 	return ret;
 }
 static int ath9k_set_key(struct ieee80211_hw *hw,
 			 enum set_key_cmd cmd,
 			 struct ieee80211_vif *vif,
 			 struct ieee80211_sta *sta,
 			 struct ieee80211_key_conf *key)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_node *an = NULL;
 	int ret = 0, i;
 	if (ath9k_modparam_nohwcrypt)
 		return -ENOSPC;
 	if ((vif->type == NL80211_IFTYPE_ADHOC ||
 	     vif->type == NL80211_IFTYPE_MESH_POINT) &&
 	    (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
 	     key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
 	    !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 		/*
 		 * For now, disable hw crypto for the RSN IBSS group keys. This
 		 * could be optimized in the future to use a modified key cache
 		 * design to support per-STA RX GTK, but until that gets
 		 * implemented, use of software crypto for group addressed
 		 * frames is a acceptable to allow RSN IBSS to be used.
 		 */
 		return -EOPNOTSUPP;
 	}
 	mutex_lock(&sc->mutex);
 	ath9k_ps_wakeup(sc);
 	ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
 	if (sta)
 		an = (struct ath_node *)sta->drv_priv;
 	switch (cmd) {
 	case SET_KEY:
 		if (sta)
 			ath9k_del_ps_key(sc, vif, sta);
 		key->hw_key_idx = 0;
 		ret = ath_key_config(common, vif, sta, key);
 		if (ret >= 0) {
 			key->hw_key_idx = ret;
 			/* push IV and Michael MIC generation to stack */
 			key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 			if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
 				key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
 			if (sc->sc_ah->sw_mgmt_crypto &&
 			    key->cipher == WLAN_CIPHER_SUITE_CCMP)
 				key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
 			ret = 0;
 		}
 		if (an && key->hw_key_idx) {
 			for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
 				if (an->key_idx[i])
 					continue;
 				an->key_idx[i] = key->hw_key_idx;
 				break;
 			}
 			WARN_ON(i == ARRAY_SIZE(an->key_idx));
 		}
 		break;
 	case DISABLE_KEY:
 		ath_key_delete(common, key);
 		if (an) {
 			for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
 				if (an->key_idx[i] != key->hw_key_idx)
 					continue;
 				an->key_idx[i] = 0;
 				break;
 			}
 		}
 		key->hw_key_idx = 0;
 		break;
 	default:
 		ret = -EINVAL;
 	}
 	ath9k_ps_restore(sc);
 	mutex_unlock(&sc->mutex);
 	return ret;
 }
 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
 				   struct ieee80211_vif *vif,
 				   struct ieee80211_bss_conf *bss_conf,
 				   u32 changed)
 {
 #define CHECK_ANI				\
 	(BSS_CHANGED_ASSOC |			\
 	 BSS_CHANGED_IBSS |			\
 	 BSS_CHANGED_BEACON_ENABLED)
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	struct ath_vif *avp = (void *)vif->drv_priv;
 	int slottime;
 	ath9k_ps_wakeup(sc);
 	mutex_lock(&sc->mutex);
 	if (changed & BSS_CHANGED_ASSOC) {
 		ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
 			bss_conf->bssid, bss_conf->assoc);
 		ether_addr_copy(avp->bssid, bss_conf->bssid);
 		avp->aid = bss_conf->aid;
 		avp->assoc = bss_conf->assoc;
 		ath9k_calculate_summary_state(sc, avp->chanctx);
 		if (ath9k_is_chanctx_enabled()) {
 			if (bss_conf->assoc)
 				ath_chanctx_event(sc, vif,
 						  ATH_CHANCTX_EVENT_ASSOC);
 		}
 	}
 	if (changed & BSS_CHANGED_IBSS) {
 		memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
 		common->curaid = bss_conf->aid;
 		ath9k_hw_write_associd(sc->sc_ah);
 	}
 	if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
 	    (changed & BSS_CHANGED_BEACON_INT) ||
 	    (changed & BSS_CHANGED_BEACON_INFO)) {
 		ath9k_beacon_config(sc, vif, changed);
 		if (changed & BSS_CHANGED_BEACON_ENABLED)
 			ath9k_calculate_summary_state(sc, avp->chanctx);
 	}
 	if ((avp->chanctx == sc->cur_chan) &&
 	    (changed & BSS_CHANGED_ERP_SLOT)) {
 		if (bss_conf->use_short_slot)
 			slottime = 9;
 		else
 			slottime = 20;
 		if (vif->type == NL80211_IFTYPE_AP) {
 			/*
 			 * Defer update, so that connected stations can adjust
 			 * their settings at the same time.
 			 * See beacon.c for more details
 			 */
 			sc->beacon.slottime = slottime;
 			sc->beacon.updateslot = UPDATE;
 		} else {
 			ah->slottime = slottime;
 			ath9k_hw_init_global_settings(ah);
 		}
 	}
 	if (changed & BSS_CHANGED_P2P_PS)
 		ath9k_p2p_bss_info_changed(sc, vif);
 	if (changed & CHECK_ANI)
 		ath_check_ani(sc);
 	mutex_unlock(&sc->mutex);
 	ath9k_ps_restore(sc);
 #undef CHECK_ANI
 }
 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
 {
 	struct ath_softc *sc = hw->priv;
 	u64 tsf;
 	mutex_lock(&sc->mutex);
 	ath9k_ps_wakeup(sc);
 	tsf = ath9k_hw_gettsf64(sc->sc_ah);
 	ath9k_ps_restore(sc);
 	mutex_unlock(&sc->mutex);
 	return tsf;
 }
 static void ath9k_set_tsf(struct ieee80211_hw *hw,
 			  struct ieee80211_vif *vif,
 			  u64 tsf)
 {
 	struct ath_softc *sc = hw->priv;
 	mutex_lock(&sc->mutex);
 	ath9k_ps_wakeup(sc);
 	ath9k_hw_settsf64(sc->sc_ah, tsf);
 	ath9k_ps_restore(sc);
 	mutex_unlock(&sc->mutex);
 }
 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
 {
 	struct ath_softc *sc = hw->priv;
 	mutex_lock(&sc->mutex);
 	ath9k_ps_wakeup(sc);
 	ath9k_hw_reset_tsf(sc->sc_ah);
 	ath9k_ps_restore(sc);
 	mutex_unlock(&sc->mutex);
 }
 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
 			      struct ieee80211_vif *vif,
 			      enum ieee80211_ampdu_mlme_action action,
 			      struct ieee80211_sta *sta,
 			      u16 tid, u16 *ssn, u8 buf_size)
 {
 	struct ath_softc *sc = hw->priv;
 	bool flush = false;
 	int ret = 0;
 	mutex_lock(&sc->mutex);
 	switch (action) {
 	case IEEE80211_AMPDU_RX_START:
 		break;
 	case IEEE80211_AMPDU_RX_STOP:
 		break;
 	case IEEE80211_AMPDU_TX_START:
 		ath9k_ps_wakeup(sc);
 		ret = ath_tx_aggr_start(sc, sta, tid, ssn);
 		if (!ret)
 			ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
 		ath9k_ps_restore(sc);
 		break;
 	case IEEE80211_AMPDU_TX_STOP_FLUSH:
 	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
 		flush = true;
 	case IEEE80211_AMPDU_TX_STOP_CONT:
 		ath9k_ps_wakeup(sc);
 		ath_tx_aggr_stop(sc, sta, tid);
 		if (!flush)
 			ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
 		ath9k_ps_restore(sc);
 		break;
 	case IEEE80211_AMPDU_TX_OPERATIONAL:
 		ath9k_ps_wakeup(sc);
 		ath_tx_aggr_resume(sc, sta, tid);
 		ath9k_ps_restore(sc);
 		break;
 	default:
 		ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
 	}
 	mutex_unlock(&sc->mutex);
 	return ret;
 }
 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
 			     struct survey_info *survey)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ieee80211_supported_band *sband;
 	struct ieee80211_channel *chan;
 	int pos;
 	if (config_enabled(CONFIG_ATH9K_TX99))
 		return -EOPNOTSUPP;
 	spin_lock_bh(&common->cc_lock);
 	if (idx == 0)
 		ath_update_survey_stats(sc);
 	sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
 	if (sband && idx >= sband->n_channels) {
 		idx -= sband->n_channels;
 		sband = NULL;
 	}
 	if (!sband)
 		sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
 	if (!sband || idx >= sband->n_channels) {
 		spin_unlock_bh(&common->cc_lock);
 		return -ENOENT;
 	}
 	chan = &sband->channels[idx];
 	pos = chan->hw_value;
 	memcpy(survey, &sc->survey[pos], sizeof(*survey));
 	survey->channel = chan;
 	spin_unlock_bh(&common->cc_lock);
 	return 0;
 }
 static void ath9k_enable_dynack(struct ath_softc *sc)
 {
 #ifdef CONFIG_ATH9K_DYNACK
 	u32 rfilt;
 	struct ath_hw *ah = sc->sc_ah;
 	ath_dynack_reset(ah);
 	ah->dynack.enabled = true;
 	rfilt = ath_calcrxfilter(sc);
 	ath9k_hw_setrxfilter(ah, rfilt);
 #endif
 }
 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
 				     s16 coverage_class)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	if (config_enabled(CONFIG_ATH9K_TX99))
 		return;
 	mutex_lock(&sc->mutex);
 	if (coverage_class >= 0) {
 		ah->coverage_class = coverage_class;
 		if (ah->dynack.enabled) {
 			u32 rfilt;
 			ah->dynack.enabled = false;
 			rfilt = ath_calcrxfilter(sc);
 			ath9k_hw_setrxfilter(ah, rfilt);
 		}
 		ath9k_ps_wakeup(sc);
 		ath9k_hw_init_global_settings(ah);
 		ath9k_ps_restore(sc);
 	} else if (!ah->dynack.enabled) {
 		ath9k_enable_dynack(sc);
 	}
 	mutex_unlock(&sc->mutex);
 }
 static bool ath9k_has_tx_pending(struct ath_softc *sc)
 {
 	int i, npend = 0;
 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 		if (!ATH_TXQ_SETUP(sc, i))
 			continue;
 		npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
 		if (npend)
 			break;
 	}
 	return !!npend;
 }
 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 			u32 queues, bool drop)
 {
 	struct ath_softc *sc = hw->priv;
 	mutex_lock(&sc->mutex);
 	__ath9k_flush(hw, queues, drop);
 	mutex_unlock(&sc->mutex);
 }
 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath_common *common = ath9k_hw_common(ah);
 	int timeout = HZ / 5; /* 200 ms */
 	bool drain_txq;
 	cancel_delayed_work_sync(&sc->tx_complete_work);
 	if (ah->ah_flags & AH_UNPLUGGED) {
 		ath_dbg(common, ANY, "Device has been unplugged!\n");
 		return;
 	}
 	if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
 		ath_dbg(common, ANY, "Device not present\n");
 		return;
 	}
 	if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
 			       timeout) > 0)
 		drop = false;
 	if (drop) {
 		ath9k_ps_wakeup(sc);
 		spin_lock_bh(&sc->sc_pcu_lock);
 		drain_txq = ath_drain_all_txq(sc);
 		spin_unlock_bh(&sc->sc_pcu_lock);
 		if (!drain_txq)
 			ath_reset(sc);
 		ath9k_ps_restore(sc);
 	}
 	ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
 }
 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	return ath9k_has_tx_pending(sc);
 }
 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ieee80211_vif *vif;
 	struct ath_vif *avp;
 	struct ath_buf *bf;
 	struct ath_tx_status ts;
 	bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
 	int status;
 	vif = sc->beacon.bslot[0];
 	if (!vif)
 		return 0;
 	if (!vif->bss_conf.enable_beacon)
 		return 0;
 	avp = (void *)vif->drv_priv;
 	if (!sc->beacon.tx_processed && !edma) {
 		tasklet_disable(&sc->bcon_tasklet);
 		bf = avp->av_bcbuf;
 		if (!bf || !bf->bf_mpdu)
 			goto skip;
 		status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
 		if (status == -EINPROGRESS)
 			goto skip;
 		sc->beacon.tx_processed = true;
 		sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
 skip:
 		tasklet_enable(&sc->bcon_tasklet);
 	}
 	return sc->beacon.tx_last;
 }
 static int ath9k_get_stats(struct ieee80211_hw *hw,
 			   struct ieee80211_low_level_stats *stats)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
 	stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
 	stats->dot11RTSFailureCount = mib_stats->rts_bad;
 	stats->dot11FCSErrorCount = mib_stats->fcs_bad;
 	stats->dot11RTSSuccessCount = mib_stats->rts_good;
 	return 0;
 }
 static u32 fill_chainmask(u32 cap, u32 new)
 {
 	u32 filled = 0;
 	int i;
 	for (i = 0; cap && new; i++, cap >>= 1) {
 		if (!(cap & BIT(0)))
 			continue;
 		if (new & BIT(0))
 			filled |= BIT(i);
 		new >>= 1;
 	}
 	return filled;
 }
 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
 {
 	if (AR_SREV_9300_20_OR_LATER(ah))
 		return true;
 	switch (val & 0x7) {
 	case 0x1:
 	case 0x3:
 	case 0x7:
 		return true;
 	case 0x2:
 		return (ah->caps.rx_chainmask == 1);
 	default:
 		return false;
 	}
 }
 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_hw *ah = sc->sc_ah;
 	if (ah->caps.rx_chainmask != 1)
 		rx_ant |= tx_ant;
 	if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
 		return -EINVAL;
 	sc->ant_rx = rx_ant;
 	sc->ant_tx = tx_ant;
 	if (ah->caps.rx_chainmask == 1)
 		return 0;
 	/* AR9100 runs into calibration issues if not all rx chains are enabled */
 	if (AR_SREV_9100(ah))
 		ah->rxchainmask = 0x7;
 	else
 		ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
 	ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
 	ath9k_cmn_reload_chainmask(ah);
 	return 0;
 }
 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
 {
 	struct ath_softc *sc = hw->priv;
 	*tx_ant = sc->ant_tx;
 	*rx_ant = sc->ant_rx;
 	return 0;
 }
 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	set_bit(ATH_OP_SCANNING, &common->op_flags);
 }
 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	clear_bit(ATH_OP_SCANNING, &common->op_flags);
 }
 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 			 struct ieee80211_scan_request *hw_req)
 {
 	struct cfg80211_scan_request *req = &hw_req->req;
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	int ret = 0;
 	mutex_lock(&sc->mutex);
 	if (WARN_ON(sc->offchannel.scan_req)) {
 		ret = -EBUSY;
 		goto out;
 	}
 	ath9k_ps_wakeup(sc);
 	set_bit(ATH_OP_SCANNING, &common->op_flags);
 	sc->offchannel.scan_vif = vif;
 	sc->offchannel.scan_req = req;
 	sc->offchannel.scan_idx = 0;
 	ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
 		vif->addr);
 	if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
 		ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
 		ath_offchannel_next(sc);
 	}
 out:
 	mutex_unlock(&sc->mutex);
 	return ret;
 }
 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
 				 struct ieee80211_vif *vif)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
 	mutex_lock(&sc->mutex);
 	del_timer_sync(&sc->offchannel.timer);
 	ath_scan_complete(sc, true);
 	mutex_unlock(&sc->mutex);
 }
 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
 				   struct ieee80211_vif *vif,
 				   struct ieee80211_channel *chan, int duration,
 				   enum ieee80211_roc_type type)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	int ret = 0;
 	mutex_lock(&sc->mutex);
 	if (WARN_ON(sc->offchannel.roc_vif)) {
 		ret = -EBUSY;
 		goto out;
 	}
 	ath9k_ps_wakeup(sc);
 	sc->offchannel.roc_vif = vif;
 	sc->offchannel.roc_chan = chan;
 	sc->offchannel.roc_duration = duration;
 	ath_dbg(common, CHAN_CTX,
 		"RoC request on vif: %pM, type: %d duration: %d\n",
 		vif->addr, type, duration);
 	if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
 		ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
 		ath_offchannel_next(sc);
 	}
 out:
 	mutex_unlock(&sc->mutex);
 	return ret;
 }
 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	mutex_lock(&sc->mutex);
 	ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
 	del_timer_sync(&sc->offchannel.timer);
 	if (sc->offchannel.roc_vif) {
 		if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
 			ath_roc_complete(sc, true);
 	}
 	mutex_unlock(&sc->mutex);
 	return 0;
 }
 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
 			     struct ieee80211_chanctx_conf *conf)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_chanctx *ctx, **ptr;
 	int pos;
 	mutex_lock(&sc->mutex);
 	ath_for_each_chanctx(sc, ctx) {
 		if (ctx->assigned)
 			continue;
 		ptr = (void *) conf->drv_priv;
 		*ptr = ctx;
 		ctx->assigned = true;
 		pos = ctx - &sc->chanctx[0];
 		ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
 		ath_dbg(common, CHAN_CTX,
 			"Add channel context: %d MHz\n",
 			conf->def.chan->center_freq);
 		ath_chanctx_set_channel(sc, ctx, &conf->def);
 		ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_ASSIGN);
 		mutex_unlock(&sc->mutex);
 		return 0;
 	}
 	mutex_unlock(&sc->mutex);
 	return -ENOSPC;
 }
 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
 				 struct ieee80211_chanctx_conf *conf)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
 	mutex_lock(&sc->mutex);
 	ath_dbg(common, CHAN_CTX,
 		"Remove channel context: %d MHz\n",
 		conf->def.chan->center_freq);
 	ctx->assigned = false;
 	ctx->hw_queue_base = 0;
 	ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
 	mutex_unlock(&sc->mutex);
 }
 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
 				 struct ieee80211_chanctx_conf *conf,
 				 u32 changed)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
 	mutex_lock(&sc->mutex);
 	ath_dbg(common, CHAN_CTX,
 		"Change channel context: %d MHz\n",
 		conf->def.chan->center_freq);
 	ath_chanctx_set_channel(sc, ctx, &conf->def);
 	mutex_unlock(&sc->mutex);
 }
 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
 				    struct ieee80211_vif *vif,
 				    struct ieee80211_chanctx_conf *conf)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_vif *avp = (void *)vif->drv_priv;
 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
 	int i;
 	mutex_lock(&sc->mutex);
 	ath_dbg(common, CHAN_CTX,
 		"Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
 		vif->addr, vif->type, vif->p2p,
 		conf->def.chan->center_freq);
 	avp->chanctx = ctx;
 	ctx->nvifs_assigned++;
 	list_add_tail(&avp->list, &ctx->vifs);
 	ath9k_calculate_summary_state(sc, ctx);
 	for (i = 0; i < IEEE80211_NUM_ACS; i++)
 		vif->hw_queue[i] = ctx->hw_queue_base + i;
 	mutex_unlock(&sc->mutex);
 	return 0;
 }
 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
 				       struct ieee80211_vif *vif,
 				       struct ieee80211_chanctx_conf *conf)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_vif *avp = (void *)vif->drv_priv;
 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
 	int ac;
 	mutex_lock(&sc->mutex);
 	ath_dbg(common, CHAN_CTX,
 		"Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
 		vif->addr, vif->type, vif->p2p,
 		conf->def.chan->center_freq);
 	avp->chanctx = NULL;
 	ctx->nvifs_assigned--;
 	list_del(&avp->list);
 	ath9k_calculate_summary_state(sc, ctx);
 	for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
 		vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
 	mutex_unlock(&sc->mutex);
 }
 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
 				 struct ieee80211_vif *vif)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 	struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
 	bool changed = false;
 	if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
 		return;
 	if (!avp->chanctx)
 		return;
 	mutex_lock(&sc->mutex);
 	spin_lock_bh(&sc->chan_lock);
 	if (sc->next_chan || (sc->cur_chan != avp->chanctx)) {
 		sc->next_chan = avp->chanctx;
 		changed = true;
 	}
 	ath_dbg(common, CHAN_CTX,
 		"%s: Set chanctx state to FORCE_ACTIVE, changed: %d\n",
 		__func__, changed);
 	sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
 	spin_unlock_bh(&sc->chan_lock);
 	if (changed)
 		ath_chanctx_set_next(sc, true);
 	mutex_unlock(&sc->mutex);
 }
 void ath9k_fill_chanctx_ops(void)
 {
 	if (!ath9k_is_chanctx_enabled())
 		return;
 	ath9k_ops.hw_scan                  = ath9k_hw_scan;
 	ath9k_ops.cancel_hw_scan           = ath9k_cancel_hw_scan;
 	ath9k_ops.remain_on_channel        = ath9k_remain_on_channel;
 	ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
 	ath9k_ops.add_chanctx              = ath9k_add_chanctx;
 	ath9k_ops.remove_chanctx           = ath9k_remove_chanctx;
 	ath9k_ops.change_chanctx           = ath9k_change_chanctx;
 	ath9k_ops.assign_vif_chanctx       = ath9k_assign_vif_chanctx;
 	ath9k_ops.unassign_vif_chanctx     = ath9k_unassign_vif_chanctx;
 	ath9k_ops.mgd_prepare_tx           = ath9k_mgd_prepare_tx;
 }
 #endif
 struct ieee80211_ops ath9k_ops = {
 	.tx 		    = ath9k_tx,
 	.start 		    = ath9k_start,
 	.stop 		    = ath9k_stop,
 	.add_interface 	    = ath9k_add_interface,
 	.change_interface   = ath9k_change_interface,
 	.remove_interface   = ath9k_remove_interface,
 	.config 	    = ath9k_config,
 	.configure_filter   = ath9k_configure_filter,
 	.sta_add	    = ath9k_sta_add,
 	.sta_remove	    = ath9k_sta_remove,
 	.sta_notify         = ath9k_sta_notify,
 	.conf_tx 	    = ath9k_conf_tx,
 	.bss_info_changed   = ath9k_bss_info_changed,
 	.set_key            = ath9k_set_key,
 	.get_tsf 	    = ath9k_get_tsf,
 	.set_tsf 	    = ath9k_set_tsf,
 	.reset_tsf 	    = ath9k_reset_tsf,
 	.ampdu_action       = ath9k_ampdu_action,
 	.get_survey	    = ath9k_get_survey,
 	.rfkill_poll        = ath9k_rfkill_poll_state,
 	.set_coverage_class = ath9k_set_coverage_class,
 	.flush		    = ath9k_flush,
 	.tx_frames_pending  = ath9k_tx_frames_pending,
 	.tx_last_beacon     = ath9k_tx_last_beacon,
 	.release_buffered_frames = ath9k_release_buffered_frames,
 	.get_stats	    = ath9k_get_stats,
 	.set_antenna	    = ath9k_set_antenna,
 	.get_antenna	    = ath9k_get_antenna,
 #ifdef CONFIG_ATH9K_WOW
 	.suspend	    = ath9k_suspend,
 	.resume		    = ath9k_resume,
 	.set_wakeup	    = ath9k_set_wakeup,
 #endif
 #ifdef CONFIG_ATH9K_DEBUGFS
 	.get_et_sset_count  = ath9k_get_et_sset_count,
 	.get_et_stats       = ath9k_get_et_stats,
 	.get_et_strings     = ath9k_get_et_strings,
 #endif
 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
 	.sta_add_debugfs    = ath9k_sta_add_debugfs,
 #endif
 	.sw_scan_start	    = ath9k_sw_scan_start,
 	.sw_scan_complete   = ath9k_sw_scan_complete,
 };

drivers/net/wireless/brcm80211/brcmfmac/of.c

Diff comments View file @ c857781

drivers/net/wireless/brcm80211/brcmfmac/pcie.c

Diff comments View file @ c857781

 /* Copyright (c) 2014 Broadcom Corporation
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
  *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/firmware.h>
 #include <linux/pci.h>
 #include <linux/vmalloc.h>
 #include <linux/delay.h>
-#include <linux/unaligned/access_ok.h>
 #include <linux/interrupt.h>
 #include <linux/bcma/bcma.h>
 #include <linux/sched.h>
+#include <asm/unaligned.h>
 #include <soc.h>
 #include <chipcommon.h>
 #include <brcmu_utils.h>
 #include <brcmu_wifi.h>
 #include <brcm_hw_ids.h>
 #include "dhd_dbg.h"
 #include "dhd_bus.h"
 #include "commonring.h"
 #include "msgbuf.h"
 #include "pcie.h"
 #include "firmware.h"
 #include "chip.h"
 enum brcmf_pcie_state {
 	BRCMFMAC_PCIE_STATE_DOWN,
 	BRCMFMAC_PCIE_STATE_UP
 };
 #define BRCMF_PCIE_43602_FW_NAME		"brcm/brcmfmac43602-pcie.bin"
 #define BRCMF_PCIE_43602_NVRAM_NAME		"brcm/brcmfmac43602-pcie.txt"
 #define BRCMF_PCIE_4354_FW_NAME			"brcm/brcmfmac4354-pcie.bin"
 #define BRCMF_PCIE_4354_NVRAM_NAME		"brcm/brcmfmac4354-pcie.txt"
 #define BRCMF_PCIE_4356_FW_NAME			"brcm/brcmfmac4356-pcie.bin"
 #define BRCMF_PCIE_4356_NVRAM_NAME		"brcm/brcmfmac4356-pcie.txt"
 #define BRCMF_PCIE_43570_FW_NAME		"brcm/brcmfmac43570-pcie.bin"
 #define BRCMF_PCIE_43570_NVRAM_NAME		"brcm/brcmfmac43570-pcie.txt"
 #define BRCMF_PCIE_FW_UP_TIMEOUT		2000 /* msec */
 #define BRCMF_PCIE_TCM_MAP_SIZE			(4096 * 1024)
 #define BRCMF_PCIE_REG_MAP_SIZE			(32 * 1024)
 /* backplane addres space accessed by BAR0 */
 #define	BRCMF_PCIE_BAR0_WINDOW			0x80
 #define BRCMF_PCIE_BAR0_REG_SIZE		0x1000
 #define	BRCMF_PCIE_BAR0_WRAPPERBASE		0x70
 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET	0x1000
 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET	0x2000
 #define BRCMF_PCIE_ARMCR4REG_BANKIDX		0x40
 #define BRCMF_PCIE_ARMCR4REG_BANKPDA		0x4C
 #define BRCMF_PCIE_REG_INTSTATUS		0x90
 #define BRCMF_PCIE_REG_INTMASK			0x94
 #define BRCMF_PCIE_REG_SBMBX			0x98
 #define BRCMF_PCIE_PCIE2REG_INTMASK		0x24
 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT		0x48
 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK		0x4C
 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR		0x120
 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA		0x124
 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX		0x140
 #define BRCMF_PCIE_GENREV1			1
 #define BRCMF_PCIE_GENREV2			2
 #define BRCMF_PCIE2_INTA			0x01
 #define BRCMF_PCIE2_INTB			0x02
 #define BRCMF_PCIE_INT_0			0x01
 #define BRCMF_PCIE_INT_1			0x02
 #define BRCMF_PCIE_INT_DEF			(BRCMF_PCIE_INT_0 | \
 						 BRCMF_PCIE_INT_1)
 #define BRCMF_PCIE_MB_INT_FN0_0			0x0100
 #define BRCMF_PCIE_MB_INT_FN0_1			0x0200
 #define	BRCMF_PCIE_MB_INT_D2H0_DB0		0x10000
 #define	BRCMF_PCIE_MB_INT_D2H0_DB1		0x20000
 #define	BRCMF_PCIE_MB_INT_D2H1_DB0		0x40000
 #define	BRCMF_PCIE_MB_INT_D2H1_DB1		0x80000
 #define	BRCMF_PCIE_MB_INT_D2H2_DB0		0x100000
 #define	BRCMF_PCIE_MB_INT_D2H2_DB1		0x200000
 #define	BRCMF_PCIE_MB_INT_D2H3_DB0		0x400000
 #define	BRCMF_PCIE_MB_INT_D2H3_DB1		0x800000
 #define BRCMF_PCIE_MB_INT_D2H_DB		(BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 						 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 						 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 						 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 						 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 						 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 						 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 						 BRCMF_PCIE_MB_INT_D2H3_DB1)
 #define BRCMF_PCIE_MIN_SHARED_VERSION		4
 #define BRCMF_PCIE_MAX_SHARED_VERSION		5
 #define BRCMF_PCIE_SHARED_VERSION_MASK		0x00FF
 #define BRCMF_PCIE_SHARED_TXPUSH_SUPPORT	0x4000
 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT		0x4000
 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT		0x8000
 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET	34
 #define BRCMF_SHARED_RING_BASE_OFFSET		52
 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET	36
 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET	20
 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET	40
 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET	44
 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET	48
 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET	52
 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET	56
 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET	64
 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET	68
 #define BRCMF_RING_H2D_RING_COUNT_OFFSET	0
 #define BRCMF_RING_D2H_RING_COUNT_OFFSET	1
 #define BRCMF_RING_H2D_RING_MEM_OFFSET		4
 #define BRCMF_RING_H2D_RING_STATE_OFFSET	8
 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET		8
 #define BRCMF_RING_MAX_ITEM_OFFSET		4
 #define BRCMF_RING_LEN_ITEMS_OFFSET		6
 #define BRCMF_RING_MEM_SZ			16
 #define BRCMF_RING_STATE_SZ			8
 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET	4
 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET	8
 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET	12
 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET	16
 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET	0
 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES	52
 #define BRCMF_DEF_MAX_RXBUFPOST			255
 #define BRCMF_CONSOLE_BUFADDR_OFFSET		8
 #define BRCMF_CONSOLE_BUFSIZE_OFFSET		12
 #define BRCMF_CONSOLE_WRITEIDX_OFFSET		16
 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN		8
 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN		1024
 #define BRCMF_D2H_DEV_D3_ACK			0x00000001
 #define BRCMF_D2H_DEV_DS_ENTER_REQ		0x00000002
 #define BRCMF_D2H_DEV_DS_EXIT_NOTE		0x00000004
 #define BRCMF_H2D_HOST_D3_INFORM		0x00000001
 #define BRCMF_H2D_HOST_DS_ACK			0x00000002
 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE		0x00000008
 #define BRCMF_H2D_HOST_D0_INFORM		0x00000010
 #define BRCMF_PCIE_MBDATA_TIMEOUT		2000
 #define BRCMF_PCIE_CFGREG_STATUS_CMD		0x4
 #define BRCMF_PCIE_CFGREG_PM_CSR		0x4C
 #define BRCMF_PCIE_CFGREG_MSI_CAP		0x58
 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L		0x5C
 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H		0x60
 #define BRCMF_PCIE_CFGREG_MSI_DATA		0x64
 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL	0xBC
 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2	0xDC
 #define BRCMF_PCIE_CFGREG_RBAR_CTRL		0x228
 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1	0x248
 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG	0x4E0
 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG	0x4F4
 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB	3
 MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
 MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
 MODULE_FIRMWARE(BRCMF_PCIE_4354_FW_NAME);
 MODULE_FIRMWARE(BRCMF_PCIE_4354_NVRAM_NAME);
 MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
 MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
 struct brcmf_pcie_console {
 	u32 base_addr;
 	u32 buf_addr;
 	u32 bufsize;
 	u32 read_idx;
 	u8 log_str[256];
 	u8 log_idx;
 };
 struct brcmf_pcie_shared_info {
 	u32 tcm_base_address;
 	u32 flags;
 	struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 	struct brcmf_pcie_ringbuf *flowrings;
 	u16 max_rxbufpost;
 	u32 nrof_flowrings;
 	u32 rx_dataoffset;
 	u32 htod_mb_data_addr;
 	u32 dtoh_mb_data_addr;
 	u32 ring_info_addr;
 	struct brcmf_pcie_console console;
 	void *scratch;
 	dma_addr_t scratch_dmahandle;
 	void *ringupd;
 	dma_addr_t ringupd_dmahandle;
 };
 struct brcmf_pcie_core_info {
 	u32 base;
 	u32 wrapbase;
 };
 struct brcmf_pciedev_info {
 	enum brcmf_pcie_state state;
 	bool in_irq;
 	bool irq_requested;
 	struct pci_dev *pdev;
 	char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 	char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 	void __iomem *regs;
 	void __iomem *tcm;
 	u32 tcm_size;
 	u32 ram_base;
 	u32 ram_size;
 	struct brcmf_chip *ci;
 	u32 coreid;
 	u32 generic_corerev;
 	struct brcmf_pcie_shared_info shared;
 	void (*ringbell)(struct brcmf_pciedev_info *devinfo);
 	wait_queue_head_t mbdata_resp_wait;
 	bool mbdata_completed;
 	bool irq_allocated;
 	bool wowl_enabled;
 };
 struct brcmf_pcie_ringbuf {
 	struct brcmf_commonring commonring;
 	dma_addr_t dma_handle;
 	u32 w_idx_addr;
 	u32 r_idx_addr;
 	struct brcmf_pciedev_info *devinfo;
 	u8 id;
 };
 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 	BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 	BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 	BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 	BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 	BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 };
 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 	BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 	BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 	BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 	BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 	BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 };
 /* dma flushing needs implementation for mips and arm platforms. Should
  * be put in util. Note, this is not real flushing. It is virtual non
  * cached memory. Only write buffers should have to be drained. Though
  * this may be different depending on platform......
  */
 #define brcmf_dma_flush(addr, len)
 #define brcmf_dma_invalidate_cache(addr, len)
 static u32
 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 {
 	void __iomem *address = devinfo->regs + reg_offset;
 	return (ioread32(address));
 }
 static void
 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 		       u32 value)
 {
 	void __iomem *address = devinfo->regs + reg_offset;
 	iowrite32(value, address);
 }
 static u8
 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 {
 	void __iomem *address = devinfo->tcm + mem_offset;
 	return (ioread8(address));
 }
 static u16
 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 {
 	void __iomem *address = devinfo->tcm + mem_offset;
 	return (ioread16(address));
 }
 static void
 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 		       u16 value)
 {
 	void __iomem *address = devinfo->tcm + mem_offset;
 	iowrite16(value, address);
 }
 static u32
 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 {
 	void __iomem *address = devinfo->tcm + mem_offset;
 	return (ioread32(address));
 }
 static void
 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 		       u32 value)
 {
 	void __iomem *address = devinfo->tcm + mem_offset;
 	iowrite32(value, address);
 }
 static u32
 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 {
 	void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 	return (ioread32(addr));
 }
 static void
 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 		       u32 value)
 {
 	void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 	iowrite32(value, addr);
 }
 static void
 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 			  void *srcaddr, u32 len)
 {
 	void __iomem *address = devinfo->tcm + mem_offset;
 	__le32 *src32;
 	__le16 *src16;
 	u8 *src8;
 	if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
 		if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
 			src8 = (u8 *)srcaddr;
 			while (len) {
 				iowrite8(*src8, address);
 				address++;
 				src8++;
 				len--;
 			}
 		} else {
 			len = len / 2;
 			src16 = (__le16 *)srcaddr;
 			while (len) {
 				iowrite16(le16_to_cpu(*src16), address);
 				address += 2;
 				src16++;
 				len--;
 			}
 		}
 	} else {
 		len = len / 4;
 		src32 = (__le32 *)srcaddr;
 		while (len) {
 			iowrite32(le32_to_cpu(*src32), address);
 			address += 4;
 			src32++;
 			len--;
 		}
 	}
 }
 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 		CHIPCREGOFFS(reg), value)
 static void
 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 {
 	const struct pci_dev *pdev = devinfo->pdev;
 	struct brcmf_core *core;
 	u32 bar0_win;
 	core = brcmf_chip_get_core(devinfo->ci, coreid);
 	if (core) {
 		bar0_win = core->base;
 		pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 		if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 					  &bar0_win) == 0) {
 			if (bar0_win != core->base) {
 				bar0_win = core->base;
 				pci_write_config_dword(pdev,
 						       BRCMF_PCIE_BAR0_WINDOW,
 						       bar0_win);
 			}
 		}
 	} else {
 		brcmf_err("Unsupported core selected %x\n", coreid);
 	}
 }
 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 {
 	u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 			     BRCMF_PCIE_CFGREG_PM_CSR,
 			     BRCMF_PCIE_CFGREG_MSI_CAP,
 			     BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 			     BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 			     BRCMF_PCIE_CFGREG_MSI_DATA,
 			     BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 			     BRCMF_PCIE_CFGREG_RBAR_CTRL,
 			     BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 			     BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 			     BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 	u32 i;
 	u32 val;
 	u32 lsc;
 	if (!devinfo->ci)
 		return;
 	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 			       BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
 	lsc = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 	val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, val);
 	brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 	WRITECC32(devinfo, watchdog, 4);
 	msleep(100);
 	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 			       BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
 	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, lsc);
 	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 	for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 				       cfg_offset[i]);
 		val = brcmf_pcie_read_reg32(devinfo,
 					    BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 		brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 			  cfg_offset[i], val);
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 				       val);
 	}
 }
 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 {
 	u32 config;
 	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 	if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0)
 		brcmf_pcie_reset_device(devinfo);
 	/* BAR1 window may not be sized properly */
 	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 	config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 	device_wakeup_enable(&devinfo->pdev->dev);
 }
 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 {
 	brcmf_chip_enter_download(devinfo->ci);
 	if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 		brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 				       5);
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 				       0);
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 				       7);
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 				       0);
 	}
 	return 0;
 }
 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 					  u32 resetintr)
 {
 	struct brcmf_core *core;
 	if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 		core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 		brcmf_chip_resetcore(core, 0, 0, 0);
 	}
 	return !brcmf_chip_exit_download(devinfo->ci, resetintr);
 }
 static int
 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 {
 	struct brcmf_pcie_shared_info *shared;
 	u32 addr;
 	u32 cur_htod_mb_data;
 	u32 i;
 	shared = &devinfo->shared;
 	addr = shared->htod_mb_data_addr;
 	cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 	if (cur_htod_mb_data != 0)
 		brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 			  cur_htod_mb_data);
 	i = 0;
 	while (cur_htod_mb_data != 0) {
 		msleep(10);
 		i++;
 		if (i > 100)
 			return -EIO;
 		cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 	}
 	brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 	pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 	pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 	return 0;
 }
 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 {
 	struct brcmf_pcie_shared_info *shared;
 	u32 addr;
 	u32 dtoh_mb_data;
 	shared = &devinfo->shared;
 	addr = shared->dtoh_mb_data_addr;
 	dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 	if (!dtoh_mb_data)
 		return;
 	brcmf_pcie_write_tcm32(devinfo, addr, 0);
 	brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 	if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 		brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 		brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 		brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 	}
 	if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 		brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 	if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 		brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 		if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
 			devinfo->mbdata_completed = true;
 			wake_up(&devinfo->mbdata_resp_wait);
 		}
 	}
 }
 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 {
 	struct brcmf_pcie_shared_info *shared;
 	struct brcmf_pcie_console *console;
 	u32 addr;
 	shared = &devinfo->shared;
 	console = &shared->console;
 	addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 	console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 	addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 	console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 	addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 	console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 	brcmf_dbg(PCIE, "Console: base %x, buf %x, size %d\n",
 		  console->base_addr, console->buf_addr, console->bufsize);
 }
 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 {
 	struct brcmf_pcie_console *console;
 	u32 addr;
 	u8 ch;
 	u32 newidx;
 	console = &devinfo->shared.console;
 	addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 	newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 	while (newidx != console->read_idx) {
 		addr = console->buf_addr + console->read_idx;
 		ch = brcmf_pcie_read_tcm8(devinfo, addr);
 		console->read_idx++;
 		if (console->read_idx == console->bufsize)
 			console->read_idx = 0;
 		if (ch == '\r')
 			continue;
 		console->log_str[console->log_idx] = ch;
 		console->log_idx++;
 		if ((ch != '\n') &&
 		    (console->log_idx == (sizeof(console->log_str) - 2))) {
 			ch = '\n';
 			console->log_str[console->log_idx] = ch;
 			console->log_idx++;
 		}
 		if (ch == '\n') {
 			console->log_str[console->log_idx] = 0;
 			brcmf_dbg(PCIE, "CONSOLE: %s\n", console->log_str);
 			console->log_idx = 0;
 		}
 	}
 }
 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
 {
 	u32 reg_value;
 	brcmf_dbg(PCIE, "RING !\n");
 	reg_value = brcmf_pcie_read_reg32(devinfo,
 					  BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 	reg_value |= BRCMF_PCIE2_INTB;
 	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 			       reg_value);
 }
 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
 {
 	brcmf_dbg(PCIE, "RING !\n");
 	/* Any arbitrary value will do, lets use 1 */
 	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 }
 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 {
 	if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 		pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 				       0);
 	else
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 				       0);
 }
 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 {
 	if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 		pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 				       BRCMF_PCIE_INT_DEF);
 	else
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 				       BRCMF_PCIE_MB_INT_D2H_DB |
 				       BRCMF_PCIE_MB_INT_FN0_0 |
 				       BRCMF_PCIE_MB_INT_FN0_1);
 }
 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 	u32 status;
 	status = 0;
 	pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 	if (status) {
 		brcmf_pcie_intr_disable(devinfo);
 		brcmf_dbg(PCIE, "Enter\n");
 		return IRQ_WAKE_THREAD;
 	}
 	return IRQ_NONE;
 }
 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 	if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 		brcmf_pcie_intr_disable(devinfo);
 		brcmf_dbg(PCIE, "Enter\n");
 		return IRQ_WAKE_THREAD;
 	}
 	return IRQ_NONE;
 }
 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 	const struct pci_dev *pdev = devinfo->pdev;
 	u32 status;
 	devinfo->in_irq = true;
 	status = 0;
 	pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 	brcmf_dbg(PCIE, "Enter %x\n", status);
 	if (status) {
 		pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 		if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 			brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
 	}
 	if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 		brcmf_pcie_intr_enable(devinfo);
 	devinfo->in_irq = false;
 	return IRQ_HANDLED;
 }
 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 	u32 status;
 	devinfo->in_irq = true;
 	status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 	brcmf_dbg(PCIE, "Enter %x\n", status);
 	if (status) {
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 				       status);
 		if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 			      BRCMF_PCIE_MB_INT_FN0_1))
 			brcmf_pcie_handle_mb_data(devinfo);
 		if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 			if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 				brcmf_proto_msgbuf_rx_trigger(
 							&devinfo->pdev->dev);
 		}
 	}
 	brcmf_pcie_bus_console_read(devinfo);
 	if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 		brcmf_pcie_intr_enable(devinfo);
 	devinfo->in_irq = false;
 	return IRQ_HANDLED;
 }
 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 {
 	struct pci_dev *pdev;
 	pdev = devinfo->pdev;
 	brcmf_pcie_intr_disable(devinfo);
 	brcmf_dbg(PCIE, "Enter\n");
 	/* is it a v1 or v2 implementation */
 	devinfo->irq_requested = false;
 	if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 		if (request_threaded_irq(pdev->irq,
 					 brcmf_pcie_quick_check_isr_v1,
 					 brcmf_pcie_isr_thread_v1,
 					 IRQF_SHARED, "brcmf_pcie_intr",
 					 devinfo)) {
 			brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 			return -EIO;
 		}
 	} else {
 		if (request_threaded_irq(pdev->irq,
 					 brcmf_pcie_quick_check_isr_v2,
 					 brcmf_pcie_isr_thread_v2,
 					 IRQF_SHARED, "brcmf_pcie_intr",
 					 devinfo)) {
 			brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 			return -EIO;
 		}
 	}
 	devinfo->irq_requested = true;
 	devinfo->irq_allocated = true;
 	return 0;
 }
 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 {
 	struct pci_dev *pdev;
 	u32 status;
 	u32 count;
 	if (!devinfo->irq_allocated)
 		return;
 	pdev = devinfo->pdev;
 	brcmf_pcie_intr_disable(devinfo);
 	if (!devinfo->irq_requested)
 		return;
 	devinfo->irq_requested = false;
 	free_irq(pdev->irq, devinfo);
 	msleep(50);
 	count = 0;
 	while ((devinfo->in_irq) && (count < 20)) {
 		msleep(50);
 		count++;
 	}
 	if (devinfo->in_irq)
 		brcmf_err("Still in IRQ (processing) !!!\n");
 	if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 		status = 0;
 		pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 		pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 	} else {
 		status = brcmf_pcie_read_reg32(devinfo,
 					       BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 				       status);
 	}
 	devinfo->irq_allocated = false;
 }
 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 {
 	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 	struct brcmf_pciedev_info *devinfo = ring->devinfo;
 	struct brcmf_commonring *commonring = &ring->commonring;
 	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 		return -EIO;
 	brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 		  commonring->w_ptr, ring->id);
 	brcmf_pcie_write_tcm16(devinfo, ring->r_idx_addr, commonring->r_ptr);
 	return 0;
 }
 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 {
 	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 	struct brcmf_pciedev_info *devinfo = ring->devinfo;
 	struct brcmf_commonring *commonring = &ring->commonring;
 	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 		return -EIO;
 	brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 		  commonring->r_ptr, ring->id);
 	brcmf_pcie_write_tcm16(devinfo, ring->w_idx_addr, commonring->w_ptr);
 	return 0;
 }
 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 {
 	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 	struct brcmf_pciedev_info *devinfo = ring->devinfo;
 	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 		return -EIO;
 	devinfo->ringbell(devinfo);
 	return 0;
 }
 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 {
 	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 	struct brcmf_pciedev_info *devinfo = ring->devinfo;
 	struct brcmf_commonring *commonring = &ring->commonring;
 	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 		return -EIO;
 	commonring->r_ptr = brcmf_pcie_read_tcm16(devinfo, ring->r_idx_addr);
 	brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 		  commonring->w_ptr, ring->id);
 	return 0;
 }
 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
 {
 	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 	struct brcmf_pciedev_info *devinfo = ring->devinfo;
 	struct brcmf_commonring *commonring = &ring->commonring;
 	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 		return -EIO;
 	commonring->w_ptr = brcmf_pcie_read_tcm16(devinfo, ring->w_idx_addr);
 	brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 		  commonring->r_ptr, ring->id);
 	return 0;
 }
 static void *
 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
 				     u32 size, u32 tcm_dma_phys_addr,
 				     dma_addr_t *dma_handle)
 {
 	void *ring;
 	long long address;
 	ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
 				  GFP_KERNEL);
 	if (!ring)
 		return NULL;
 	address = (long long)(long)*dma_handle;
 	brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
 			       address & 0xffffffff);
 	brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
 	memset(ring, 0, size);
 	return (ring);
 }
 static struct brcmf_pcie_ringbuf *
 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
 			      u32 tcm_ring_phys_addr)
 {
 	void *dma_buf;
 	dma_addr_t dma_handle;
 	struct brcmf_pcie_ringbuf *ring;
 	u32 size;
 	u32 addr;
 	size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
 	dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
 			tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
 			&dma_handle);
 	if (!dma_buf)
 		return NULL;
 	addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
 	brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
 	addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
 	brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
 	ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 	if (!ring) {
 		dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
 				  dma_handle);
 		return NULL;
 	}
 	brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
 				brcmf_ring_itemsize[ring_id], dma_buf);
 	ring->dma_handle = dma_handle;
 	ring->devinfo = devinfo;
 	brcmf_commonring_register_cb(&ring->commonring,
 				     brcmf_pcie_ring_mb_ring_bell,
 				     brcmf_pcie_ring_mb_update_rptr,
 				     brcmf_pcie_ring_mb_update_wptr,
 				     brcmf_pcie_ring_mb_write_rptr,
 				     brcmf_pcie_ring_mb_write_wptr, ring);
 	return (ring);
 }
 static void brcmf_pcie_release_ringbuffer(struct device *dev,
 					  struct brcmf_pcie_ringbuf *ring)
 {
 	void *dma_buf;
 	u32 size;
 	if (!ring)
 		return;
 	dma_buf = ring->commonring.buf_addr;
 	if (dma_buf) {
 		size = ring->commonring.depth * ring->commonring.item_len;
 		dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
 	}
 	kfree(ring);
 }
 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
 {
 	u32 i;
 	for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
 		brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
 					      devinfo->shared.commonrings[i]);
 		devinfo->shared.commonrings[i] = NULL;
 	}
 	kfree(devinfo->shared.flowrings);
 	devinfo->shared.flowrings = NULL;
 }
 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
 {
 	struct brcmf_pcie_ringbuf *ring;
 	struct brcmf_pcie_ringbuf *rings;
 	u32 ring_addr;
 	u32 d2h_w_idx_ptr;
 	u32 d2h_r_idx_ptr;
 	u32 h2d_w_idx_ptr;
 	u32 h2d_r_idx_ptr;
 	u32 addr;
 	u32 ring_mem_ptr;
 	u32 i;
 	u16 max_sub_queues;
 	ring_addr = devinfo->shared.ring_info_addr;
 	brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
 	addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
 	d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
 	addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
 	d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
 	addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
 	h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
 	addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
 	h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
 	addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
 	ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
 	for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
 		ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
 		if (!ring)
 			goto fail;
 		ring->w_idx_addr = h2d_w_idx_ptr;
 		ring->r_idx_addr = h2d_r_idx_ptr;
 		ring->id = i;
 		devinfo->shared.commonrings[i] = ring;
 		h2d_w_idx_ptr += sizeof(u32);
 		h2d_r_idx_ptr += sizeof(u32);
 		ring_mem_ptr += BRCMF_RING_MEM_SZ;
 	}
 	for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
 	     i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
 		ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
 		if (!ring)
 			goto fail;
 		ring->w_idx_addr = d2h_w_idx_ptr;
 		ring->r_idx_addr = d2h_r_idx_ptr;
 		ring->id = i;
 		devinfo->shared.commonrings[i] = ring;
 		d2h_w_idx_ptr += sizeof(u32);
 		d2h_r_idx_ptr += sizeof(u32);
 		ring_mem_ptr += BRCMF_RING_MEM_SZ;
 	}
 	addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
 	max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
 	devinfo->shared.nrof_flowrings =
 			max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
 	rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
 			GFP_KERNEL);
 	if (!rings)
 		goto fail;
 	brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
 		  devinfo->shared.nrof_flowrings);
 	for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
 		ring = &rings[i];
 		ring->devinfo = devinfo;
 		ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
 		brcmf_commonring_register_cb(&ring->commonring,
 					     brcmf_pcie_ring_mb_ring_bell,
 					     brcmf_pcie_ring_mb_update_rptr,
 					     brcmf_pcie_ring_mb_update_wptr,
 					     brcmf_pcie_ring_mb_write_rptr,
 					     brcmf_pcie_ring_mb_write_wptr,
 					     ring);
 		ring->w_idx_addr = h2d_w_idx_ptr;
 		ring->r_idx_addr = h2d_r_idx_ptr;
 		h2d_w_idx_ptr += sizeof(u32);
 		h2d_r_idx_ptr += sizeof(u32);
 	}
 	devinfo->shared.flowrings = rings;
 	return 0;
 fail:
 	brcmf_err("Allocating commonring buffers failed\n");
 	brcmf_pcie_release_ringbuffers(devinfo);
 	return -ENOMEM;
 }
 static void
 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
 {
 	if (devinfo->shared.scratch)
 		dma_free_coherent(&devinfo->pdev->dev,
 				  BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
 				  devinfo->shared.scratch,
 				  devinfo->shared.scratch_dmahandle);
 	if (devinfo->shared.ringupd)
 		dma_free_coherent(&devinfo->pdev->dev,
 				  BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
 				  devinfo->shared.ringupd,
 				  devinfo->shared.ringupd_dmahandle);
 }
 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
 {
 	long long address;
 	u32 addr;
 	devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
 		BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
 		&devinfo->shared.scratch_dmahandle, GFP_KERNEL);
 	if (!devinfo->shared.scratch)
 		goto fail;
 	memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
 	brcmf_dma_flush(devinfo->shared.scratch, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
 	addr = devinfo->shared.tcm_base_address +
 	       BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
 	address = (long long)(long)devinfo->shared.scratch_dmahandle;
 	brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
 	brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
 	addr = devinfo->shared.tcm_base_address +
 	       BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
 	brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
 	devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
 		BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
 		&devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
 	if (!devinfo->shared.ringupd)
 		goto fail;
 	memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
 	brcmf_dma_flush(devinfo->shared.ringupd, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
 	addr = devinfo->shared.tcm_base_address +
 	       BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
 	address = (long long)(long)devinfo->shared.ringupd_dmahandle;
 	brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
 	brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
 	addr = devinfo->shared.tcm_base_address +
 	       BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
 	brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
 	return 0;
 fail:
 	brcmf_err("Allocating scratch buffers failed\n");
 	brcmf_pcie_release_scratchbuffers(devinfo);
 	return -ENOMEM;
 }
 static void brcmf_pcie_down(struct device *dev)
 {
 }
 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
 {
 	return 0;
 }
 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
 				uint len)
 {
 	return 0;
 }
 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
 				uint len)
 {
 	return 0;
 }
 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
 {
 	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
 	struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
 	struct brcmf_pciedev_info *devinfo = buspub->devinfo;
 	brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
 	devinfo->wowl_enabled = enabled;
 	if (enabled)
 		device_set_wakeup_enable(&devinfo->pdev->dev, true);
 	else
 		device_set_wakeup_enable(&devinfo->pdev->dev, false);
 }
 static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
 	.txdata = brcmf_pcie_tx,
 	.stop = brcmf_pcie_down,
 	.txctl = brcmf_pcie_tx_ctlpkt,
 	.rxctl = brcmf_pcie_rx_ctlpkt,
 	.wowl_config = brcmf_pcie_wowl_config,
 };
 static int
 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
 			       u32 sharedram_addr)
 {
 	struct brcmf_pcie_shared_info *shared;
 	u32 addr;
 	u32 version;
 	shared = &devinfo->shared;
 	shared->tcm_base_address = sharedram_addr;
 	shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
 	version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
 	brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
 	if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
 	    (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
 		brcmf_err("Unsupported PCIE version %d\n", version);
 		return -EINVAL;
 	}
 	if (shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT) {
 		brcmf_err("Unsupported legacy TX mode 0x%x\n",
 			  shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT);
 		return -EINVAL;
 	}
 	addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
 	shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
 	if (shared->max_rxbufpost == 0)
 		shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
 	addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
 	shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
 	addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
 	shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 	addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
 	shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 	addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
 	shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 	brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
 		  shared->max_rxbufpost, shared->rx_dataoffset);
 	brcmf_pcie_bus_console_init(devinfo);
 	return 0;
 }
 static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
 {
 	char *fw_name;
 	char *nvram_name;
 	uint fw_len, nv_len;
 	char end;
 	brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
 		  devinfo->ci->chiprev);
 	switch (devinfo->ci->chip) {
 	case BRCM_CC_43602_CHIP_ID:
 		fw_name = BRCMF_PCIE_43602_FW_NAME;
 		nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
 		break;
 	case BRCM_CC_4354_CHIP_ID:
 		fw_name = BRCMF_PCIE_4354_FW_NAME;
 		nvram_name = BRCMF_PCIE_4354_NVRAM_NAME;
 		break;
 	case BRCM_CC_4356_CHIP_ID:
 		fw_name = BRCMF_PCIE_4356_FW_NAME;
 		nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
 		break;
 	case BRCM_CC_43567_CHIP_ID:
 	case BRCM_CC_43569_CHIP_ID:
 	case BRCM_CC_43570_CHIP_ID:
 		fw_name = BRCMF_PCIE_43570_FW_NAME;
 		nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
 		break;
 	default:
 		brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
 		return -ENODEV;
 	}
 	fw_len = sizeof(devinfo->fw_name) - 1;
 	nv_len = sizeof(devinfo->nvram_name) - 1;
 	/* check if firmware path is provided by module parameter */
 	if (brcmf_firmware_path[0] != '\0') {
 		strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
 		strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
 		fw_len -= strlen(devinfo->fw_name);
 		nv_len -= strlen(devinfo->nvram_name);
 		end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
 		if (end != '/') {
 			strncat(devinfo->fw_name, "/", fw_len);
 			strncat(devinfo->nvram_name, "/", nv_len);
 			fw_len--;
 			nv_len--;
 		}
 	}
 	strncat(devinfo->fw_name, fw_name, fw_len);
 	strncat(devinfo->nvram_name, nvram_name, nv_len);
 	return 0;
 }
 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
 					const struct firmware *fw, void *nvram,
 					u32 nvram_len)
 {
 	u32 sharedram_addr;
 	u32 sharedram_addr_written;
 	u32 loop_counter;
 	int err;
 	u32 address;
 	u32 resetintr;
 	devinfo->ringbell = brcmf_pcie_ringbell_v2;
 	devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
 	brcmf_dbg(PCIE, "Halt ARM.\n");
 	err = brcmf_pcie_enter_download_state(devinfo);
 	if (err)
 		return err;
 	brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
 	brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
 				  (void *)fw->data, fw->size);
 	resetintr = get_unaligned_le32(fw->data);
 	release_firmware(fw);
 	/* reset last 4 bytes of RAM address. to be used for shared
 	 * area. This identifies when FW is running
 	 */
 	brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
 	if (nvram) {
 		brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
 		address = devinfo->ci->rambase + devinfo->ci->ramsize -
 			  nvram_len;
 		brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
 		brcmf_fw_nvram_free(nvram);
 	} else {
 		brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
 			  devinfo->nvram_name);
 	}
 	sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
 						       devinfo->ci->ramsize -
 						       4);
 	brcmf_dbg(PCIE, "Bring ARM in running state\n");
 	err = brcmf_pcie_exit_download_state(devinfo, resetintr);
 	if (err)
 		return err;
 	brcmf_dbg(PCIE, "Wait for FW init\n");
 	sharedram_addr = sharedram_addr_written;
 	loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
 	while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
 		msleep(50);
 		sharedram_addr = brcmf_pcie_read_ram32(devinfo,
 						       devinfo->ci->ramsize -
 						       4);
 		loop_counter--;
 	}
 	if (sharedram_addr == sharedram_addr_written) {
 		brcmf_err("FW failed to initialize\n");
 		return -ENODEV;
 	}
 	brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
 	return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
 }
 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
 {
 	struct pci_dev *pdev;
 	int err;
 	phys_addr_t  bar0_addr, bar1_addr;
 	ulong bar1_size;
 	pdev = devinfo->pdev;
 	err = pci_enable_device(pdev);
 	if (err) {
 		brcmf_err("pci_enable_device failed err=%d\n", err);
 		return err;
 	}
 	pci_set_master(pdev);
 	/* Bar-0 mapped address */
 	bar0_addr = pci_resource_start(pdev, 0);
 	/* Bar-1 mapped address */
 	bar1_addr = pci_resource_start(pdev, 2);
 	/* read Bar-1 mapped memory range */
 	bar1_size = pci_resource_len(pdev, 2);
 	if ((bar1_size == 0) || (bar1_addr == 0)) {
 		brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
 			  bar1_size, (unsigned long long)bar1_addr);
 		return -EINVAL;
 	}
 	devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
 	devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
 	devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
 	if (!devinfo->regs || !devinfo->tcm) {
 		brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
 			  devinfo->tcm);
 		return -EINVAL;
 	}
 	brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
 		  devinfo->regs, (unsigned long long)bar0_addr);
 	brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
 		  devinfo->tcm, (unsigned long long)bar1_addr);
 	return 0;
 }
 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
 {
 	if (devinfo->tcm)
 		iounmap(devinfo->tcm);
 	if (devinfo->regs)
 		iounmap(devinfo->regs);
 	pci_disable_device(devinfo->pdev);
 }
 static int brcmf_pcie_attach_bus(struct device *dev)
 {
 	int ret;
 	/* Attach to the common driver interface */
 	ret = brcmf_attach(dev);
 	if (ret) {
 		brcmf_err("brcmf_attach failed\n");
 	} else {
 		ret = brcmf_bus_start(dev);
 		if (ret)
 			brcmf_err("dongle is not responding\n");
 	}
 	return ret;
 }
 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
 {
 	u32 ret_addr;
 	ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
 	addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
 	pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
 	return ret_addr;
 }
 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
 	addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
 	return brcmf_pcie_read_reg32(devinfo, addr);
 }
 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
 	addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
 	brcmf_pcie_write_reg32(devinfo, addr, value);
 }
 static int brcmf_pcie_buscoreprep(void *ctx)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
 	int err;
 	err = brcmf_pcie_get_resource(devinfo);
 	if (err == 0) {
 		/* Set CC watchdog to reset all the cores on the chip to bring
 		 * back dongle to a sane state.
 		 */
 		brcmf_pcie_buscore_write32(ctx, CORE_CC_REG(SI_ENUM_BASE,
 							    watchdog), 4);
 		msleep(100);
 	}
 	return err;
 }
 static void brcmf_pcie_buscore_exitdl(void *ctx, struct brcmf_chip *chip,
 				      u32 rstvec)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
 	brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
 }
 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
 	.prepare = brcmf_pcie_buscoreprep,
 	.exit_dl = brcmf_pcie_buscore_exitdl,
 	.read32 = brcmf_pcie_buscore_read32,
 	.write32 = brcmf_pcie_buscore_write32,
 };
 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
 			     void *nvram, u32 nvram_len)
 {
 	struct brcmf_bus *bus = dev_get_drvdata(dev);
 	struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
 	struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
 	struct brcmf_commonring **flowrings;
 	int ret;
 	u32 i;
 	brcmf_pcie_attach(devinfo);
 	ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
 	if (ret)
 		goto fail;
 	devinfo->state = BRCMFMAC_PCIE_STATE_UP;
 	ret = brcmf_pcie_init_ringbuffers(devinfo);
 	if (ret)
 		goto fail;
 	ret = brcmf_pcie_init_scratchbuffers(devinfo);
 	if (ret)
 		goto fail;
 	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 	ret = brcmf_pcie_request_irq(devinfo);
 	if (ret)
 		goto fail;
 	/* hook the commonrings in the bus structure. */
 	for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
 		bus->msgbuf->commonrings[i] =
 				&devinfo->shared.commonrings[i]->commonring;
 	flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(flowrings),
 			    GFP_KERNEL);
 	if (!flowrings)
 		goto fail;
 	for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
 		flowrings[i] = &devinfo->shared.flowrings[i].commonring;
 	bus->msgbuf->flowrings = flowrings;
 	bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
 	bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
 	bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
 	init_waitqueue_head(&devinfo->mbdata_resp_wait);
 	brcmf_pcie_intr_enable(devinfo);
 	if (brcmf_pcie_attach_bus(bus->dev) == 0)
 		return;
 	brcmf_pcie_bus_console_read(devinfo);
 fail:
 	device_release_driver(dev);
 }
 static int
 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	int ret;
 	struct brcmf_pciedev_info *devinfo;
 	struct brcmf_pciedev *pcie_bus_dev;
 	struct brcmf_bus *bus;
 	brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
 	ret = -ENOMEM;
 	devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
 	if (devinfo == NULL)
 		return ret;
 	devinfo->pdev = pdev;
 	pcie_bus_dev = NULL;
 	devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
 	if (IS_ERR(devinfo->ci)) {
 		ret = PTR_ERR(devinfo->ci);
 		devinfo->ci = NULL;
 		goto fail;
 	}
 	pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
 	if (pcie_bus_dev == NULL) {
 		ret = -ENOMEM;
 		goto fail;
 	}
 	bus = kzalloc(sizeof(*bus), GFP_KERNEL);
 	if (!bus) {
 		ret = -ENOMEM;
 		goto fail;
 	}
 	bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
 	if (!bus->msgbuf) {
 		ret = -ENOMEM;
 		kfree(bus);
 		goto fail;
 	}
 	/* hook it all together. */
 	pcie_bus_dev->devinfo = devinfo;
 	pcie_bus_dev->bus = bus;
 	bus->dev = &pdev->dev;
 	bus->bus_priv.pcie = pcie_bus_dev;
 	bus->ops = &brcmf_pcie_bus_ops;
 	bus->proto_type = BRCMF_PROTO_MSGBUF;
 	bus->chip = devinfo->coreid;
 	bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
 	dev_set_drvdata(&pdev->dev, bus);
 	ret = brcmf_pcie_get_fwnames(devinfo);
 	if (ret)
 		goto fail_bus;
 	ret = brcmf_fw_get_firmwares(bus->dev, BRCMF_FW_REQUEST_NVRAM |
 					       BRCMF_FW_REQ_NV_OPTIONAL,
 				     devinfo->fw_name, devinfo->nvram_name,
 				     brcmf_pcie_setup);
 	if (ret == 0)
 		return 0;
 fail_bus:
 	kfree(bus->msgbuf);
 	kfree(bus);
 fail:
 	brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
 	brcmf_pcie_release_resource(devinfo);
 	if (devinfo->ci)
 		brcmf_chip_detach(devinfo->ci);
 	kfree(pcie_bus_dev);
 	kfree(devinfo);
 	return ret;
 }
 static void
 brcmf_pcie_remove(struct pci_dev *pdev)
 {
 	struct brcmf_pciedev_info *devinfo;
 	struct brcmf_bus *bus;
 	brcmf_dbg(PCIE, "Enter\n");
 	bus = dev_get_drvdata(&pdev->dev);
 	if (bus == NULL)
 		return;
 	devinfo = bus->bus_priv.pcie->devinfo;
 	devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
 	if (devinfo->ci)
 		brcmf_pcie_intr_disable(devinfo);
 	brcmf_detach(&pdev->dev);
 	kfree(bus->bus_priv.pcie);
 	kfree(bus->msgbuf->flowrings);
 	kfree(bus->msgbuf);
 	kfree(bus);
 	brcmf_pcie_release_irq(devinfo);
 	brcmf_pcie_release_scratchbuffers(devinfo);
 	brcmf_pcie_release_ringbuffers(devinfo);
 	brcmf_pcie_reset_device(devinfo);
 	brcmf_pcie_release_resource(devinfo);
 	if (devinfo->ci)
 		brcmf_chip_detach(devinfo->ci);
 	kfree(devinfo);
 	dev_set_drvdata(&pdev->dev, NULL);
 }
 #ifdef CONFIG_PM
 static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
 {
 	struct brcmf_pciedev_info *devinfo;
 	struct brcmf_bus *bus;
 	int err;
 	brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
 	bus = dev_get_drvdata(&pdev->dev);
 	devinfo = bus->bus_priv.pcie->devinfo;
 	brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
 	devinfo->mbdata_completed = false;
 	brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
 	wait_event_timeout(devinfo->mbdata_resp_wait,
 			   devinfo->mbdata_completed,
 			   msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
 	if (!devinfo->mbdata_completed) {
 		brcmf_err("Timeout on response for entering D3 substate\n");
 		return -EIO;
 	}
 	brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
 	err = pci_save_state(pdev);
 	if (err)
 		brcmf_err("pci_save_state failed, err=%d\n", err);
 	if ((err) || (!devinfo->wowl_enabled)) {
 		brcmf_chip_detach(devinfo->ci);
 		devinfo->ci = NULL;
 		brcmf_pcie_remove(pdev);
 		return 0;
 	}
 	return pci_prepare_to_sleep(pdev);
 }
 static int brcmf_pcie_resume(struct pci_dev *pdev)
 {
 	struct brcmf_pciedev_info *devinfo;
 	struct brcmf_bus *bus;
 	int err;
 	bus = dev_get_drvdata(&pdev->dev);
 	brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
 	err = pci_set_power_state(pdev, PCI_D0);
 	if (err) {
 		brcmf_err("pci_set_power_state failed, err=%d\n", err);
 		goto cleanup;
 	}
 	pci_restore_state(pdev);
 	pci_enable_wake(pdev, PCI_D3hot, false);
 	pci_enable_wake(pdev, PCI_D3cold, false);
 	/* Check if device is still up and running, if so we are ready */
 	if (bus) {
 		devinfo = bus->bus_priv.pcie->devinfo;
 		if (brcmf_pcie_read_reg32(devinfo,
 					  BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
 			if (brcmf_pcie_send_mb_data(devinfo,
 						    BRCMF_H2D_HOST_D0_INFORM))
 				goto cleanup;
 			brcmf_dbg(PCIE, "Hot resume, continue....\n");
 			brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 			brcmf_bus_change_state(bus, BRCMF_BUS_DATA);
 			brcmf_pcie_intr_enable(devinfo);
 			return 0;
 		}
 	}
 cleanup:
 	if (bus) {
 		devinfo = bus->bus_priv.pcie->devinfo;
 		brcmf_chip_detach(devinfo->ci);
 		devinfo->ci = NULL;
 		brcmf_pcie_remove(pdev);
 	}
 	err = brcmf_pcie_probe(pdev, NULL);
 	if (err)
 		brcmf_err("probe after resume failed, err=%d\n", err);
 	return err;
 }
 #endif /* CONFIG_PM */
 #define BRCMF_PCIE_DEVICE(dev_id)	{ BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
 	PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
 static struct pci_device_id brcmf_pcie_devid_table[] = {
 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_DEVICE_ID),
 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
 	BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
 	BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
 	BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
 	{ /* end: all zeroes */ }
 };
 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
 static struct pci_driver brcmf_pciedrvr = {
 	.node = {},
 	.name = KBUILD_MODNAME,
 	.id_table = brcmf_pcie_devid_table,
 	.probe = brcmf_pcie_probe,
 	.remove = brcmf_pcie_remove,
 #ifdef CONFIG_PM
 	.suspend = brcmf_pcie_suspend,
 	.resume = brcmf_pcie_resume
 #endif /* CONFIG_PM */
 };
 void brcmf_pcie_register(void)
 {
 	int err;
 	brcmf_dbg(PCIE, "Enter\n");
 	err = pci_register_driver(&brcmf_pciedrvr);
 	if (err)
 		brcmf_err("PCIE driver registration failed, err=%d\n", err);
 }
 void brcmf_pcie_exit(void)
 {
 	brcmf_dbg(PCIE, "Enter\n");
 	pci_unregister_driver(&brcmf_pciedrvr);
 }

drivers/net/wireless/brcm80211/brcmfmac/usb.c

Diff comments View file @ c857781

 /*
  * Copyright (c) 2011 Broadcom Corporation
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
  *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/firmware.h>
 #include <linux/usb.h>
 #include <linux/vmalloc.h>
 #include <brcmu_utils.h>
 #include <brcm_hw_ids.h>
 #include <brcmu_wifi.h>
 #include <dhd_bus.h>
 #include <dhd_dbg.h>
 #include "firmware.h"
 #include "usb_rdl.h"
 #include "usb.h"
 #define IOCTL_RESP_TIMEOUT		2000
 #define BRCMF_USB_RESET_GETVER_SPINWAIT	100	/* in unit of ms */
 #define BRCMF_USB_RESET_GETVER_LOOP_CNT	10
 #define BRCMF_POSTBOOT_ID		0xA123  /* ID to detect if dongle
 						   has boot up */
 #define BRCMF_USB_NRXQ			50
 #define BRCMF_USB_NTXQ			50
 #define BRCMF_USB_CBCTL_WRITE		0
 #define BRCMF_USB_CBCTL_READ		1
 #define BRCMF_USB_MAX_PKT_SIZE		1600
 #define BRCMF_USB_43143_FW_NAME		"brcm/brcmfmac43143.bin"
 #define BRCMF_USB_43236_FW_NAME		"brcm/brcmfmac43236b.bin"
 #define BRCMF_USB_43242_FW_NAME		"brcm/brcmfmac43242a.bin"
 #define BRCMF_USB_43569_FW_NAME		"brcm/brcmfmac43569.bin"
 struct brcmf_usb_image {
 	struct list_head list;
 	s8 *fwname;
 	u8 *image;
 	int image_len;
 };
 struct brcmf_usbdev_info {
 	struct brcmf_usbdev bus_pub; /* MUST BE FIRST */
 	spinlock_t qlock;
 	struct list_head rx_freeq;
 	struct list_head rx_postq;
 	struct list_head tx_freeq;
 	struct list_head tx_postq;
 	uint rx_pipe, tx_pipe;
 	int rx_low_watermark;
 	int tx_low_watermark;
 	int tx_high_watermark;
 	int tx_freecount;
 	bool tx_flowblock;
 	spinlock_t tx_flowblock_lock;
 	struct brcmf_usbreq *tx_reqs;
 	struct brcmf_usbreq *rx_reqs;
 	const u8 *image;	/* buffer for combine fw and nvram */
 	int image_len;
 	struct usb_device *usbdev;
 	struct device *dev;
 	int ctl_in_pipe, ctl_out_pipe;
 	struct urb *ctl_urb; /* URB for control endpoint */
 	struct usb_ctrlrequest ctl_write;
 	struct usb_ctrlrequest ctl_read;
 	u32 ctl_urb_actual_length;
 	int ctl_urb_status;
 	int ctl_completed;
 	wait_queue_head_t ioctl_resp_wait;
 	ulong ctl_op;
 	u8 ifnum;
 	struct urb *bulk_urb; /* used for FW download */
 };
 static void brcmf_usb_rx_refill(struct brcmf_usbdev_info *devinfo,
 				struct brcmf_usbreq  *req);
 static struct brcmf_usbdev *brcmf_usb_get_buspub(struct device *dev)
 {
 	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
 	return bus_if->bus_priv.usb;
 }
 static struct brcmf_usbdev_info *brcmf_usb_get_businfo(struct device *dev)
 {
 	return brcmf_usb_get_buspub(dev)->devinfo;
 }
 static int brcmf_usb_ioctl_resp_wait(struct brcmf_usbdev_info *devinfo)
 {
 	return wait_event_timeout(devinfo->ioctl_resp_wait,
 				  devinfo->ctl_completed,
 				  msecs_to_jiffies(IOCTL_RESP_TIMEOUT));
 }
 static void brcmf_usb_ioctl_resp_wake(struct brcmf_usbdev_info *devinfo)
 {
 	if (waitqueue_active(&devinfo->ioctl_resp_wait))
 		wake_up(&devinfo->ioctl_resp_wait);
 }
 static void
 brcmf_usb_ctl_complete(struct brcmf_usbdev_info *devinfo, int type, int status)
 {
 	brcmf_dbg(USB, "Enter, status=%d\n", status);
 	if (unlikely(devinfo == NULL))
 		return;
 	if (type == BRCMF_USB_CBCTL_READ) {
 		if (status == 0)
 			devinfo->bus_pub.stats.rx_ctlpkts++;
 		else
 			devinfo->bus_pub.stats.rx_ctlerrs++;
 	} else if (type == BRCMF_USB_CBCTL_WRITE) {
 		if (status == 0)
 			devinfo->bus_pub.stats.tx_ctlpkts++;
 		else
 			devinfo->bus_pub.stats.tx_ctlerrs++;
 	}
 	devinfo->ctl_urb_status = status;
 	devinfo->ctl_completed = true;
 	brcmf_usb_ioctl_resp_wake(devinfo);
 }
 static void
 brcmf_usb_ctlread_complete(struct urb *urb)
 {
 	struct brcmf_usbdev_info *devinfo =
 		(struct brcmf_usbdev_info *)urb->context;
 	brcmf_dbg(USB, "Enter\n");
 	devinfo->ctl_urb_actual_length = urb->actual_length;
 	brcmf_usb_ctl_complete(devinfo, BRCMF_USB_CBCTL_READ,
 		urb->status);
 }
 static void
 brcmf_usb_ctlwrite_complete(struct urb *urb)
 {
 	struct brcmf_usbdev_info *devinfo =
 		(struct brcmf_usbdev_info *)urb->context;
 	brcmf_dbg(USB, "Enter\n");
 	brcmf_usb_ctl_complete(devinfo, BRCMF_USB_CBCTL_WRITE,
 		urb->status);
 }
 static int
 brcmf_usb_send_ctl(struct brcmf_usbdev_info *devinfo, u8 *buf, int len)
 {
 	int ret;
 	u16 size;
 	brcmf_dbg(USB, "Enter\n");
 	if (devinfo == NULL || buf == NULL ||
 	    len == 0 || devinfo->ctl_urb == NULL)
 		return -EINVAL;
 	size = len;
 	devinfo->ctl_write.wLength = cpu_to_le16p(&size);
 	devinfo->ctl_urb->transfer_buffer_length = size;
 	devinfo->ctl_urb_status = 0;
 	devinfo->ctl_urb_actual_length = 0;
 	usb_fill_control_urb(devinfo->ctl_urb,
 		devinfo->usbdev,
 		devinfo->ctl_out_pipe,
 		(unsigned char *) &devinfo->ctl_write,
 		buf, size,
 		(usb_complete_t)brcmf_usb_ctlwrite_complete,
 		devinfo);
 	ret = usb_submit_urb(devinfo->ctl_urb, GFP_ATOMIC);
 	if (ret < 0)
 		brcmf_err("usb_submit_urb failed %d\n", ret);
 	return ret;
 }
 static int
 brcmf_usb_recv_ctl(struct brcmf_usbdev_info *devinfo, u8 *buf, int len)
 {
 	int ret;
 	u16 size;
 	brcmf_dbg(USB, "Enter\n");
 	if ((devinfo == NULL) || (buf == NULL) || (len == 0)
 		|| (devinfo->ctl_urb == NULL))
 		return -EINVAL;
 	size = len;
 	devinfo->ctl_read.wLength = cpu_to_le16p(&size);
 	devinfo->ctl_urb->transfer_buffer_length = size;
 	devinfo->ctl_read.bRequestType = USB_DIR_IN
 		| USB_TYPE_CLASS | USB_RECIP_INTERFACE;
 	devinfo->ctl_read.bRequest = 1;
 	usb_fill_control_urb(devinfo->ctl_urb,
 		devinfo->usbdev,
 		devinfo->ctl_in_pipe,
 		(unsigned char *) &devinfo->ctl_read,
 		buf, size,
 		(usb_complete_t)brcmf_usb_ctlread_complete,
 		devinfo);
 	ret = usb_submit_urb(devinfo->ctl_urb, GFP_ATOMIC);
 	if (ret < 0)
 		brcmf_err("usb_submit_urb failed %d\n", ret);
 	return ret;
 }
 static int brcmf_usb_tx_ctlpkt(struct device *dev, u8 *buf, u32 len)
 {
 	int err = 0;
 	int timeout = 0;
 	struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
 	brcmf_dbg(USB, "Enter\n");
 	if (devinfo->bus_pub.state != BRCMFMAC_USB_STATE_UP)
 		return -EIO;
 	if (test_and_set_bit(0, &devinfo->ctl_op))
 		return -EIO;
 	devinfo->ctl_completed = false;
 	err = brcmf_usb_send_ctl(devinfo, buf, len);
 	if (err) {
 		brcmf_err("fail %d bytes: %d\n", err, len);
 		clear_bit(0, &devinfo->ctl_op);
 		return err;
 	}
 	timeout = brcmf_usb_ioctl_resp_wait(devinfo);
 	clear_bit(0, &devinfo->ctl_op);
 	if (!timeout) {
 		brcmf_err("Txctl wait timed out\n");
 		err = -EIO;
 	}
 	return err;
 }
 static int brcmf_usb_rx_ctlpkt(struct device *dev, u8 *buf, u32 len)
 {
 	int err = 0;
 	int timeout = 0;
 	struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
 	brcmf_dbg(USB, "Enter\n");
 	if (devinfo->bus_pub.state != BRCMFMAC_USB_STATE_UP)
 		return -EIO;
 	if (test_and_set_bit(0, &devinfo->ctl_op))
 		return -EIO;
 	devinfo->ctl_completed = false;
 	err = brcmf_usb_recv_ctl(devinfo, buf, len);
 	if (err) {
 		brcmf_err("fail %d bytes: %d\n", err, len);
 		clear_bit(0, &devinfo->ctl_op);
 		return err;
 	}
 	timeout = brcmf_usb_ioctl_resp_wait(devinfo);
 	err = devinfo->ctl_urb_status;
 	clear_bit(0, &devinfo->ctl_op);
 	if (!timeout) {
 		brcmf_err("rxctl wait timed out\n");
 		err = -EIO;
 	}
 	if (!err)
 		return devinfo->ctl_urb_actual_length;
 	else
 		return err;
 }
 static struct brcmf_usbreq *brcmf_usb_deq(struct brcmf_usbdev_info *devinfo,
 					  struct list_head *q, int *counter)
 {
 	unsigned long flags;
 	struct brcmf_usbreq  *req;
 	spin_lock_irqsave(&devinfo->qlock, flags);
 	if (list_empty(q)) {
 		spin_unlock_irqrestore(&devinfo->qlock, flags);
 		return NULL;
 	}
 	req = list_entry(q->next, struct brcmf_usbreq, list);
 	list_del_init(q->next);
 	if (counter)
 		(*counter)--;
 	spin_unlock_irqrestore(&devinfo->qlock, flags);
 	return req;
 }
 static void brcmf_usb_enq(struct brcmf_usbdev_info *devinfo,
 			  struct list_head *q, struct brcmf_usbreq *req,
 			  int *counter)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&devinfo->qlock, flags);
 	list_add_tail(&req->list, q);
 	if (counter)
 		(*counter)++;
 	spin_unlock_irqrestore(&devinfo->qlock, flags);
 }
 static struct brcmf_usbreq *
 brcmf_usbdev_qinit(struct list_head *q, int qsize)
 {
 	int i;
 	struct brcmf_usbreq *req, *reqs;
 	reqs = kcalloc(qsize, sizeof(struct brcmf_usbreq), GFP_ATOMIC);
 	if (reqs == NULL)
 		return NULL;
 	req = reqs;
 	for (i = 0; i < qsize; i++) {
 		req->urb = usb_alloc_urb(0, GFP_ATOMIC);
 		if (!req->urb)
 			goto fail;
 		INIT_LIST_HEAD(&req->list);
 		list_add_tail(&req->list, q);
 		req++;
 	}
 	return reqs;
 fail:
 	brcmf_err("fail!\n");
 	while (!list_empty(q)) {
 		req = list_entry(q->next, struct brcmf_usbreq, list);
 		if (req && req->urb)
 			usb_free_urb(req->urb);
 		list_del(q->next);
 	}
 	return NULL;
 }
 static void brcmf_usb_free_q(struct list_head *q, bool pending)
 {
 	struct brcmf_usbreq *req, *next;
 	int i = 0;
 	list_for_each_entry_safe(req, next, q, list) {
 		if (!req->urb) {
 			brcmf_err("bad req\n");
 			break;
 		}
 		i++;
 		if (pending) {
 			usb_kill_urb(req->urb);
 		} else {
 			usb_free_urb(req->urb);
 			list_del_init(&req->list);
 		}
 	}
 }
 static void brcmf_usb_del_fromq(struct brcmf_usbdev_info *devinfo,
 				struct brcmf_usbreq *req)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&devinfo->qlock, flags);
 	list_del_init(&req->list);
 	spin_unlock_irqrestore(&devinfo->qlock, flags);
 }
 static void brcmf_usb_tx_complete(struct urb *urb)
 {
 	struct brcmf_usbreq *req = (struct brcmf_usbreq *)urb->context;
 	struct brcmf_usbdev_info *devinfo = req->devinfo;
 	unsigned long flags;
 	brcmf_dbg(USB, "Enter, urb->status=%d, skb=%p\n", urb->status,
 		  req->skb);
 	brcmf_usb_del_fromq(devinfo, req);
 	brcmf_txcomplete(devinfo->dev, req->skb, urb->status == 0);
 	req->skb = NULL;
 	brcmf_usb_enq(devinfo, &devinfo->tx_freeq, req, &devinfo->tx_freecount);
 	spin_lock_irqsave(&devinfo->tx_flowblock_lock, flags);
 	if (devinfo->tx_freecount > devinfo->tx_high_watermark &&
 		devinfo->tx_flowblock) {
 		brcmf_txflowblock(devinfo->dev, false);
 		devinfo->tx_flowblock = false;
 	}
 	spin_unlock_irqrestore(&devinfo->tx_flowblock_lock, flags);
 }
 static void brcmf_usb_rx_complete(struct urb *urb)
 {
 	struct brcmf_usbreq  *req = (struct brcmf_usbreq *)urb->context;
 	struct brcmf_usbdev_info *devinfo = req->devinfo;
 	struct sk_buff *skb;
 	brcmf_dbg(USB, "Enter, urb->status=%d\n", urb->status);
 	brcmf_usb_del_fromq(devinfo, req);
 	skb = req->skb;
 	req->skb = NULL;
 	/* zero lenght packets indicate usb "failure". Do not refill */
 	if (urb->status != 0 || !urb->actual_length) {
 		brcmu_pkt_buf_free_skb(skb);
 		brcmf_usb_enq(devinfo, &devinfo->rx_freeq, req, NULL);
 		return;
 	}
 	if (devinfo->bus_pub.state == BRCMFMAC_USB_STATE_UP) {
 		skb_put(skb, urb->actual_length);
 		brcmf_rx_frame(devinfo->dev, skb);
 		brcmf_usb_rx_refill(devinfo, req);
 	} else {
 		brcmu_pkt_buf_free_skb(skb);
 		brcmf_usb_enq(devinfo, &devinfo->rx_freeq, req, NULL);
 	}
 	return;
 }
 static void brcmf_usb_rx_refill(struct brcmf_usbdev_info *devinfo,
 				struct brcmf_usbreq  *req)
 {
 	struct sk_buff *skb;
 	int ret;
 	if (!req || !devinfo)
 		return;
 	skb = dev_alloc_skb(devinfo->bus_pub.bus_mtu);
 	if (!skb) {
 		brcmf_usb_enq(devinfo, &devinfo->rx_freeq, req, NULL);
 		return;
 	}
 	req->skb = skb;
 	usb_fill_bulk_urb(req->urb, devinfo->usbdev, devinfo->rx_pipe,
 			  skb->data, skb_tailroom(skb), brcmf_usb_rx_complete,
 			  req);
 	req->devinfo = devinfo;
 	brcmf_usb_enq(devinfo, &devinfo->rx_postq, req, NULL);
 	ret = usb_submit_urb(req->urb, GFP_ATOMIC);
 	if (ret) {
 		brcmf_usb_del_fromq(devinfo, req);
 		brcmu_pkt_buf_free_skb(req->skb);
 		req->skb = NULL;
 		brcmf_usb_enq(devinfo, &devinfo->rx_freeq, req, NULL);
 	}
 	return;
 }
 static void brcmf_usb_rx_fill_all(struct brcmf_usbdev_info *devinfo)
 {
 	struct brcmf_usbreq *req;
 	if (devinfo->bus_pub.state != BRCMFMAC_USB_STATE_UP) {
 		brcmf_err("bus is not up=%d\n", devinfo->bus_pub.state);
 		return;
 	}
 	while ((req = brcmf_usb_deq(devinfo, &devinfo->rx_freeq, NULL)) != NULL)
 		brcmf_usb_rx_refill(devinfo, req);
 }
 static void
 brcmf_usb_state_change(struct brcmf_usbdev_info *devinfo, int state)
 {
 	struct brcmf_bus *bcmf_bus = devinfo->bus_pub.bus;
 	int old_state;
 	brcmf_dbg(USB, "Enter, current state=%d, new state=%d\n",
 		  devinfo->bus_pub.state, state);
 	if (devinfo->bus_pub.state == state)
 		return;
 	old_state = devinfo->bus_pub.state;
 	devinfo->bus_pub.state = state;
 	/* update state of upper layer */
 	if (state == BRCMFMAC_USB_STATE_DOWN) {
 		brcmf_dbg(USB, "DBUS is down\n");
 		brcmf_bus_change_state(bcmf_bus, BRCMF_BUS_DOWN);
 	} else if (state == BRCMFMAC_USB_STATE_UP) {
 		brcmf_dbg(USB, "DBUS is up\n");
 		brcmf_bus_change_state(bcmf_bus, BRCMF_BUS_DATA);
 	} else {
 		brcmf_dbg(USB, "DBUS current state=%d\n", state);
 	}
 }
 static int brcmf_usb_tx(struct device *dev, struct sk_buff *skb)
 {
 	struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
 	struct brcmf_usbreq  *req;
 	int ret;
 	unsigned long flags;
 	brcmf_dbg(USB, "Enter, skb=%p\n", skb);
 	if (devinfo->bus_pub.state != BRCMFMAC_USB_STATE_UP) {
 		ret = -EIO;
 		goto fail;
 	}
 	req = brcmf_usb_deq(devinfo, &devinfo->tx_freeq,
 					&devinfo->tx_freecount);
 	if (!req) {
 		brcmf_err("no req to send\n");
 		ret = -ENOMEM;
 		goto fail;
 	}
 	req->skb = skb;
 	req->devinfo = devinfo;
 	usb_fill_bulk_urb(req->urb, devinfo->usbdev, devinfo->tx_pipe,
 			  skb->data, skb->len, brcmf_usb_tx_complete, req);
 	req->urb->transfer_flags |= URB_ZERO_PACKET;
 	brcmf_usb_enq(devinfo, &devinfo->tx_postq, req, NULL);
 	ret = usb_submit_urb(req->urb, GFP_ATOMIC);
 	if (ret) {
 		brcmf_err("brcmf_usb_tx usb_submit_urb FAILED\n");
 		brcmf_usb_del_fromq(devinfo, req);
 		req->skb = NULL;
 		brcmf_usb_enq(devinfo, &devinfo->tx_freeq, req,
 			      &devinfo->tx_freecount);
 		goto fail;
 	}
 	spin_lock_irqsave(&devinfo->tx_flowblock_lock, flags);
 	if (devinfo->tx_freecount < devinfo->tx_low_watermark &&
 	    !devinfo->tx_flowblock) {
 		brcmf_txflowblock(dev, true);
 		devinfo->tx_flowblock = true;
 	}
 	spin_unlock_irqrestore(&devinfo->tx_flowblock_lock, flags);
 	return 0;
 fail:
 	return ret;
 }
 static int brcmf_usb_up(struct device *dev)
 {
 	struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
 	brcmf_dbg(USB, "Enter\n");
 	if (devinfo->bus_pub.state == BRCMFMAC_USB_STATE_UP)
 		return 0;
 	/* Success, indicate devinfo is fully up */
 	brcmf_usb_state_change(devinfo, BRCMFMAC_USB_STATE_UP);
 	if (devinfo->ctl_urb) {
 		devinfo->ctl_in_pipe = usb_rcvctrlpipe(devinfo->usbdev, 0);
 		devinfo->ctl_out_pipe = usb_sndctrlpipe(devinfo->usbdev, 0);
 		/* CTL Write */
 		devinfo->ctl_write.bRequestType =
 			USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
 		devinfo->ctl_write.bRequest = 0;
 		devinfo->ctl_write.wValue = cpu_to_le16(0);
 		devinfo->ctl_write.wIndex = cpu_to_le16(devinfo->ifnum);
 		/* CTL Read */
 		devinfo->ctl_read.bRequestType =
 			USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
 		devinfo->ctl_read.bRequest = 1;
 		devinfo->ctl_read.wValue = cpu_to_le16(0);
 		devinfo->ctl_read.wIndex = cpu_to_le16(devinfo->ifnum);
 	}
 	brcmf_usb_rx_fill_all(devinfo);
 	return 0;
 }
 static void brcmf_usb_down(struct device *dev)
 {
 	struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
 	brcmf_dbg(USB, "Enter\n");
 	if (devinfo == NULL)
 		return;
 	if (devinfo->bus_pub.state == BRCMFMAC_USB_STATE_DOWN)
 		return;
 	brcmf_usb_state_change(devinfo, BRCMFMAC_USB_STATE_DOWN);
 	if (devinfo->ctl_urb)
 		usb_kill_urb(devinfo->ctl_urb);
 	if (devinfo->bulk_urb)
 		usb_kill_urb(devinfo->bulk_urb);
 	brcmf_usb_free_q(&devinfo->tx_postq, true);
 	brcmf_usb_free_q(&devinfo->rx_postq, true);
 }
 static void
 brcmf_usb_sync_complete(struct urb *urb)
 {
 	struct brcmf_usbdev_info *devinfo =
 			(struct brcmf_usbdev_info *)urb->context;
 	devinfo->ctl_completed = true;
 	brcmf_usb_ioctl_resp_wake(devinfo);
 }
 static int brcmf_usb_dl_cmd(struct brcmf_usbdev_info *devinfo, u8 cmd,
 			    void *buffer, int buflen)
 {
 	int ret;
 	char *tmpbuf;
 	u16 size;
 	if ((!devinfo) || (devinfo->ctl_urb == NULL))
 		return -EINVAL;
 	tmpbuf = kmalloc(buflen, GFP_ATOMIC);
 	if (!tmpbuf)
 		return -ENOMEM;
 	size = buflen;
 	devinfo->ctl_urb->transfer_buffer_length = size;
 	devinfo->ctl_read.wLength = cpu_to_le16p(&size);
 	devinfo->ctl_read.bRequestType = USB_DIR_IN | USB_TYPE_VENDOR |
 		USB_RECIP_INTERFACE;
 	devinfo->ctl_read.bRequest = cmd;
 	usb_fill_control_urb(devinfo->ctl_urb,
 		devinfo->usbdev,
 		usb_rcvctrlpipe(devinfo->usbdev, 0),
 		(unsigned char *) &devinfo->ctl_read,
 		(void *) tmpbuf, size,
 		(usb_complete_t)brcmf_usb_sync_complete, devinfo);
 	devinfo->ctl_completed = false;
 	ret = usb_submit_urb(devinfo->ctl_urb, GFP_ATOMIC);
 	if (ret < 0) {
 		brcmf_err("usb_submit_urb failed %d\n", ret);
 		goto finalize;
 	}
-	if (!brcmf_usb_ioctl_resp_wait(devinfo))
+	if (!brcmf_usb_ioctl_resp_wait(devinfo)) {
+		usb_kill_urb(devinfo->ctl_urb);
 		ret = -ETIMEDOUT;
-	else
+	} else {
 		memcpy(buffer, tmpbuf, buflen);
+	}
 finalize:
 	kfree(tmpbuf);
 	return ret;
 }
 static bool
 brcmf_usb_dlneeded(struct brcmf_usbdev_info *devinfo)
 {
 	struct bootrom_id_le id;
 	u32 chipid, chiprev;
 	brcmf_dbg(USB, "Enter\n");
 	if (devinfo == NULL)
 		return false;
 	/* Check if firmware downloaded already by querying runtime ID */
 	id.chip = cpu_to_le32(0xDEAD);
 	brcmf_usb_dl_cmd(devinfo, DL_GETVER, &id, sizeof(id));
 	chipid = le32_to_cpu(id.chip);
 	chiprev = le32_to_cpu(id.chiprev);
 	if ((chipid & 0x4300) == 0x4300)
 		brcmf_dbg(USB, "chip %x rev 0x%x\n", chipid, chiprev);
 	else
 		brcmf_dbg(USB, "chip %d rev 0x%x\n", chipid, chiprev);
 	if (chipid == BRCMF_POSTBOOT_ID) {
 		brcmf_dbg(USB, "firmware already downloaded\n");
 		brcmf_usb_dl_cmd(devinfo, DL_RESETCFG, &id, sizeof(id));
 		return false;
 	} else {
 		devinfo->bus_pub.devid = chipid;
 		devinfo->bus_pub.chiprev = chiprev;
 	}
 	return true;
 }
 static int
 brcmf_usb_resetcfg(struct brcmf_usbdev_info *devinfo)
 {
 	struct bootrom_id_le id;
 	u32 loop_cnt;
 	int err;
 	brcmf_dbg(USB, "Enter\n");
 	loop_cnt = 0;
 	do {
 		mdelay(BRCMF_USB_RESET_GETVER_SPINWAIT);
 		loop_cnt++;
 		id.chip = cpu_to_le32(0xDEAD);       /* Get the ID */
 		err = brcmf_usb_dl_cmd(devinfo, DL_GETVER, &id, sizeof(id));
 		if ((err) && (err != -ETIMEDOUT))
 			return err;
 		if (id.chip == cpu_to_le32(BRCMF_POSTBOOT_ID))
 			break;
 	} while (loop_cnt < BRCMF_USB_RESET_GETVER_LOOP_CNT);
 	if (id.chip == cpu_to_le32(BRCMF_POSTBOOT_ID)) {
 		brcmf_dbg(USB, "postboot chip 0x%x/rev 0x%x\n",
 			  le32_to_cpu(id.chip), le32_to_cpu(id.chiprev));
 		brcmf_usb_dl_cmd(devinfo, DL_RESETCFG, &id, sizeof(id));
 		return 0;
 	} else {
 		brcmf_err("Cannot talk to Dongle. Firmware is not UP, %d ms\n",
 			  BRCMF_USB_RESET_GETVER_SPINWAIT * loop_cnt);
 		return -EINVAL;
 	}
 }
 static int
 brcmf_usb_dl_send_bulk(struct brcmf_usbdev_info *devinfo, void *buffer, int len)
 {
 	int ret;
 	if ((devinfo == NULL) || (devinfo->bulk_urb == NULL))
 		return -EINVAL;
 	/* Prepare the URB */
 	usb_fill_bulk_urb(devinfo->bulk_urb, devinfo->usbdev,
 			  devinfo->tx_pipe, buffer, len,
 			  (usb_complete_t)brcmf_usb_sync_complete, devinfo);
 	devinfo->bulk_urb->transfer_flags |= URB_ZERO_PACKET;
 	devinfo->ctl_completed = false;
 	ret = usb_submit_urb(devinfo->bulk_urb, GFP_ATOMIC);
 	if (ret) {
 		brcmf_err("usb_submit_urb failed %d\n", ret);
 		return ret;
 	}
 	ret = brcmf_usb_ioctl_resp_wait(devinfo);
 	return (ret == 0);
 }
 static int
 brcmf_usb_dl_writeimage(struct brcmf_usbdev_info *devinfo, u8 *fw, int fwlen)
 {
 	unsigned int sendlen, sent, dllen;
 	char *bulkchunk = NULL, *dlpos;
 	struct rdl_state_le state;
 	u32 rdlstate, rdlbytes;
 	int err = 0;
 	brcmf_dbg(USB, "Enter, fw %p, len %d\n", fw, fwlen);
 	bulkchunk = kmalloc(RDL_CHUNK, GFP_ATOMIC);
 	if (bulkchunk == NULL) {
 		err = -ENOMEM;
 		goto fail;
 	}
 	/* 1) Prepare USB boot loader for runtime image */
 	brcmf_usb_dl_cmd(devinfo, DL_START, &state, sizeof(state));
 	rdlstate = le32_to_cpu(state.state);
 	rdlbytes = le32_to_cpu(state.bytes);
 	/* 2) Check we are in the Waiting state */
 	if (rdlstate != DL_WAITING) {
 		brcmf_err("Failed to DL_START\n");
 		err = -EINVAL;
 		goto fail;
 	}
 	sent = 0;
 	dlpos = fw;
 	dllen = fwlen;
 	/* Get chip id and rev */
 	while (rdlbytes != dllen) {
 		/* Wait until the usb device reports it received all
 		 * the bytes we sent */
 		if ((rdlbytes == sent) && (rdlbytes != dllen)) {
 			if ((dllen-sent) < RDL_CHUNK)
 				sendlen = dllen-sent;
 			else
 				sendlen = RDL_CHUNK;
 			/* simply avoid having to send a ZLP by ensuring we
 			 * never have an even
 			 * multiple of 64
 			 */
 			if (!(sendlen % 64))
 				sendlen -= 4;
 			/* send data */
 			memcpy(bulkchunk, dlpos, sendlen);
 			if (brcmf_usb_dl_send_bulk(devinfo, bulkchunk,
 						   sendlen)) {
 				brcmf_err("send_bulk failed\n");
 				err = -EINVAL;
 				goto fail;
 			}
 			dlpos += sendlen;
 			sent += sendlen;
 		}
 		err = brcmf_usb_dl_cmd(devinfo, DL_GETSTATE, &state,
 				       sizeof(state));
 		if (err) {
 			brcmf_err("DL_GETSTATE Failed\n");
 			goto fail;
 		}
 		rdlstate = le32_to_cpu(state.state);
 		rdlbytes = le32_to_cpu(state.bytes);
 		/* restart if an error is reported */
 		if (rdlstate == DL_BAD_HDR || rdlstate == DL_BAD_CRC) {
 			brcmf_err("Bad Hdr or Bad CRC state %d\n",
 				  rdlstate);
 			err = -EINVAL;
 			goto fail;
 		}
 	}
 fail:
 	kfree(bulkchunk);
 	brcmf_dbg(USB, "Exit, err=%d\n", err);
 	return err;
 }
 static int brcmf_usb_dlstart(struct brcmf_usbdev_info *devinfo, u8 *fw, int len)
 {
 	int err;
 	brcmf_dbg(USB, "Enter\n");
 	if (devinfo == NULL)
 		return -EINVAL;
 	if (devinfo->bus_pub.devid == 0xDEAD)
 		return -EINVAL;
 	err = brcmf_usb_dl_writeimage(devinfo, fw, len);
 	if (err == 0)
 		devinfo->bus_pub.state = BRCMFMAC_USB_STATE_DL_DONE;
 	else
 		devinfo->bus_pub.state = BRCMFMAC_USB_STATE_DL_FAIL;
 	brcmf_dbg(USB, "Exit, err=%d\n", err);
 	return err;
 }
 static int brcmf_usb_dlrun(struct brcmf_usbdev_info *devinfo)
 {
 	struct rdl_state_le state;
 	brcmf_dbg(USB, "Enter\n");
 	if (!devinfo)
 		return -EINVAL;
 	if (devinfo->bus_pub.devid == 0xDEAD)
 		return -EINVAL;
 	/* Check we are runnable */
 	state.state = 0;
 	brcmf_usb_dl_cmd(devinfo, DL_GETSTATE, &state, sizeof(state));
 	/* Start the image */
 	if (state.state == cpu_to_le32(DL_RUNNABLE)) {
 		if (brcmf_usb_dl_cmd(devinfo, DL_GO, &state, sizeof(state)))
 			return -ENODEV;
 		if (brcmf_usb_resetcfg(devinfo))
 			return -ENODEV;
 		/* The Dongle may go for re-enumeration. */
 	} else {
 		brcmf_err("Dongle not runnable\n");
 		return -EINVAL;
 	}
 	brcmf_dbg(USB, "Exit\n");
 	return 0;
 }
 static bool brcmf_usb_chip_support(int chipid, int chiprev)
 {
 	switch(chipid) {
 	case BRCM_CC_43143_CHIP_ID:
 		return true;
 	case BRCM_CC_43235_CHIP_ID:
 	case BRCM_CC_43236_CHIP_ID:
 	case BRCM_CC_43238_CHIP_ID:
 		return (chiprev == 3);
 	case BRCM_CC_43242_CHIP_ID:
 		return true;
 	case BRCM_CC_43566_CHIP_ID:
 	case BRCM_CC_43569_CHIP_ID:
 		return true;
 	default:
 		break;
 	}
 	return false;
 }
 static int
 brcmf_usb_fw_download(struct brcmf_usbdev_info *devinfo)
 {
 	int devid, chiprev;
 	int err;
 	brcmf_dbg(USB, "Enter\n");
 	if (devinfo == NULL)
 		return -ENODEV;
 	devid = devinfo->bus_pub.devid;
 	chiprev = devinfo->bus_pub.chiprev;
 	if (!brcmf_usb_chip_support(devid, chiprev)) {
 		brcmf_err("unsupported chip %d rev %d\n",
 			  devid, chiprev);
 		return -EINVAL;
 	}
 	if (!devinfo->image) {
 		brcmf_err("No firmware!\n");
 		return -ENOENT;
 	}
 	err = brcmf_usb_dlstart(devinfo,
 		(u8 *)devinfo->image, devinfo->image_len);
 	if (err == 0)
 		err = brcmf_usb_dlrun(devinfo);
 	return err;
 }
 static void brcmf_usb_detach(struct brcmf_usbdev_info *devinfo)
 {
 	brcmf_dbg(USB, "Enter, devinfo %p\n", devinfo);
 	/* free the URBS */
 	brcmf_usb_free_q(&devinfo->rx_freeq, false);
 	brcmf_usb_free_q(&devinfo->tx_freeq, false);
 	usb_free_urb(devinfo->ctl_urb);
 	usb_free_urb(devinfo->bulk_urb);
 	kfree(devinfo->tx_reqs);
 	kfree(devinfo->rx_reqs);
 }
 #define TRX_MAGIC       0x30524448      /* "HDR0" */
 #define TRX_VERSION     1               /* Version 1 */
 #define TRX_MAX_LEN     0x3B0000        /* Max length */
 #define TRX_NO_HEADER   1               /* Do not write TRX header */
 #define TRX_MAX_OFFSET  3               /* Max number of individual files */
 #define TRX_UNCOMP_IMAGE        0x20    /* Trx contains uncompressed image */
 struct trx_header_le {
 	__le32 magic;		/* "HDR0" */
 	__le32 len;		/* Length of file including header */
 	__le32 crc32;		/* CRC from flag_version to end of file */
 	__le32 flag_version;	/* 0:15 flags, 16:31 version */
 	__le32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of
 					 * header */
 };
 static int check_file(const u8 *headers)
 {
 	struct trx_header_le *trx;
 	int actual_len = -1;
 	brcmf_dbg(USB, "Enter\n");
 	/* Extract trx header */
 	trx = (struct trx_header_le *) headers;
 	if (trx->magic != cpu_to_le32(TRX_MAGIC))
 		return -1;
 	headers += sizeof(struct trx_header_le);
 	if (le32_to_cpu(trx->flag_version) & TRX_UNCOMP_IMAGE) {
 		actual_len = le32_to_cpu(trx->offsets[TRX_OFFSETS_DLFWLEN_IDX]);
 		return actual_len + sizeof(struct trx_header_le);
 	}
 	return -1;
 }
 static const char *brcmf_usb_get_fwname(struct brcmf_usbdev_info *devinfo)
 {
 	switch (devinfo->bus_pub.devid) {
 	case BRCM_CC_43143_CHIP_ID:
 		return BRCMF_USB_43143_FW_NAME;
 	case BRCM_CC_43235_CHIP_ID:
 	case BRCM_CC_43236_CHIP_ID:
 	case BRCM_CC_43238_CHIP_ID:
 		return BRCMF_USB_43236_FW_NAME;
 	case BRCM_CC_43242_CHIP_ID:
 		return BRCMF_USB_43242_FW_NAME;
 	case BRCM_CC_43566_CHIP_ID:
 	case BRCM_CC_43569_CHIP_ID:
 		return BRCMF_USB_43569_FW_NAME;
 	default:
 		return NULL;
 	}
 }
 static
 struct brcmf_usbdev *brcmf_usb_attach(struct brcmf_usbdev_info *devinfo,
 				      int nrxq, int ntxq)
 {
 	brcmf_dbg(USB, "Enter\n");
 	devinfo->bus_pub.nrxq = nrxq;
 	devinfo->rx_low_watermark = nrxq / 2;
 	devinfo->bus_pub.devinfo = devinfo;
 	devinfo->bus_pub.ntxq = ntxq;
 	devinfo->bus_pub.state = BRCMFMAC_USB_STATE_DOWN;
 	/* flow control when too many tx urbs posted */
 	devinfo->tx_low_watermark = ntxq / 4;
 	devinfo->tx_high_watermark = devinfo->tx_low_watermark * 3;
 	devinfo->bus_pub.bus_mtu = BRCMF_USB_MAX_PKT_SIZE;
 	/* Initialize other structure content */
 	init_waitqueue_head(&devinfo->ioctl_resp_wait);
 	/* Initialize the spinlocks */
 	spin_lock_init(&devinfo->qlock);
 	spin_lock_init(&devinfo->tx_flowblock_lock);
 	INIT_LIST_HEAD(&devinfo->rx_freeq);
 	INIT_LIST_HEAD(&devinfo->rx_postq);
 	INIT_LIST_HEAD(&devinfo->tx_freeq);
 	INIT_LIST_HEAD(&devinfo->tx_postq);
 	devinfo->tx_flowblock = false;
 	devinfo->rx_reqs = brcmf_usbdev_qinit(&devinfo->rx_freeq, nrxq);
 	if (!devinfo->rx_reqs)
 		goto error;
 	devinfo->tx_reqs = brcmf_usbdev_qinit(&devinfo->tx_freeq, ntxq);
 	if (!devinfo->tx_reqs)
 		goto error;
 	devinfo->tx_freecount = ntxq;
 	devinfo->ctl_urb = usb_alloc_urb(0, GFP_ATOMIC);
 	if (!devinfo->ctl_urb) {
 		brcmf_err("usb_alloc_urb (ctl) failed\n");
 		goto error;
 	}
 	devinfo->bulk_urb = usb_alloc_urb(0, GFP_ATOMIC);
 	if (!devinfo->bulk_urb) {
 		brcmf_err("usb_alloc_urb (bulk) failed\n");
 		goto error;
 	}
 	return &devinfo->bus_pub;
 error:
 	brcmf_err("failed!\n");
 	brcmf_usb_detach(devinfo);
 	return NULL;
 }
 static struct brcmf_bus_ops brcmf_usb_bus_ops = {
 	.txdata = brcmf_usb_tx,
 	.stop = brcmf_usb_down,
 	.txctl = brcmf_usb_tx_ctlpkt,
 	.rxctl = brcmf_usb_rx_ctlpkt,
 };
 static int brcmf_usb_bus_setup(struct brcmf_usbdev_info *devinfo)
 {
 	int ret;
 	/* Attach to the common driver interface */
 	ret = brcmf_attach(devinfo->dev);
 	if (ret) {
 		brcmf_err("brcmf_attach failed\n");
 		return ret;
 	}
 	ret = brcmf_usb_up(devinfo->dev);
 	if (ret)
 		goto fail;
 	ret = brcmf_bus_start(devinfo->dev);
 	if (ret)
 		goto fail;
 	return 0;
 fail:
 	brcmf_detach(devinfo->dev);
 	return ret;
 }
 static void brcmf_usb_probe_phase2(struct device *dev,
 				   const struct firmware *fw,
 				   void *nvram, u32 nvlen)
 {
 	struct brcmf_bus *bus = dev_get_drvdata(dev);
 	struct brcmf_usbdev_info *devinfo;
 	int ret;
 	brcmf_dbg(USB, "Start fw downloading\n");
 	ret = check_file(fw->data);
 	if (ret < 0) {
 		brcmf_err("invalid firmware\n");
 		release_firmware(fw);
 		goto error;
 	}
 	devinfo = bus->bus_priv.usb->devinfo;
 	devinfo->image = fw->data;
 	devinfo->image_len = fw->size;
 	ret = brcmf_usb_fw_download(devinfo);
 	release_firmware(fw);
 	if (ret)
 		goto error;
 	ret = brcmf_usb_bus_setup(devinfo);
 	if (ret)
 		goto error;
 	return;
 error:
 	brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), ret);
 	device_release_driver(dev);
 }
 static int brcmf_usb_probe_cb(struct brcmf_usbdev_info *devinfo)
 {
 	struct brcmf_bus *bus = NULL;
 	struct brcmf_usbdev *bus_pub = NULL;
 	struct device *dev = devinfo->dev;
 	int ret;
 	brcmf_dbg(USB, "Enter\n");
 	bus_pub = brcmf_usb_attach(devinfo, BRCMF_USB_NRXQ, BRCMF_USB_NTXQ);
 	if (!bus_pub)
 		return -ENODEV;
 	bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
 	if (!bus) {
 		ret = -ENOMEM;
 		goto fail;
 	}
 	bus->dev = dev;
 	bus_pub->bus = bus;
 	bus->bus_priv.usb = bus_pub;
 	dev_set_drvdata(dev, bus);
 	bus->ops = &brcmf_usb_bus_ops;
 	bus->proto_type = BRCMF_PROTO_BCDC;
 	bus->always_use_fws_queue = true;
 	if (!brcmf_usb_dlneeded(devinfo)) {
 		ret = brcmf_usb_bus_setup(devinfo);
 		if (ret)
 			goto fail;
 	}
 	bus->chip = bus_pub->devid;
 	bus->chiprev = bus_pub->chiprev;
 	/* request firmware here */
 	brcmf_fw_get_firmwares(dev, 0, brcmf_usb_get_fwname(devinfo), NULL,
 			       brcmf_usb_probe_phase2);
 	return 0;
 fail:
 	/* Release resources in reverse order */
 	kfree(bus);
 	brcmf_usb_detach(devinfo);
 	return ret;
 }
 static void
 brcmf_usb_disconnect_cb(struct brcmf_usbdev_info *devinfo)
 {
 	if (!devinfo)
 		return;
 	brcmf_dbg(USB, "Enter, bus_pub %p\n", devinfo);
 	brcmf_detach(devinfo->dev);
 	kfree(devinfo->bus_pub.bus);
 	brcmf_usb_detach(devinfo);
 }
 static int
 brcmf_usb_probe(struct usb_interface *intf, const struct usb_device_id *id)
 {
 	struct usb_device *usb = interface_to_usbdev(intf);
 	struct brcmf_usbdev_info *devinfo;
 	struct usb_interface_descriptor	*desc;
 	struct usb_endpoint_descriptor *endpoint;
 	int ret = 0;
 	u32 num_of_eps;
 	u8 endpoint_num, ep;
 	brcmf_dbg(USB, "Enter 0x%04x:0x%04x\n", id->idVendor, id->idProduct);
 	devinfo = kzalloc(sizeof(*devinfo), GFP_ATOMIC);
 	if (devinfo == NULL)
 		return -ENOMEM;
 	devinfo->usbdev = usb;
 	devinfo->dev = &usb->dev;
 	usb_set_intfdata(intf, devinfo);
 	/* Check that the device supports only one configuration */
 	if (usb->descriptor.bNumConfigurations != 1) {
 		brcmf_err("Number of configurations: %d not supported\n",
 			  usb->descriptor.bNumConfigurations);
 		ret = -ENODEV;
 		goto fail;
 	}
 	if ((usb->descriptor.bDeviceClass != USB_CLASS_VENDOR_SPEC) &&
 	    (usb->descriptor.bDeviceClass != USB_CLASS_MISC) &&
 	    (usb->descriptor.bDeviceClass != USB_CLASS_WIRELESS_CONTROLLER)) {
 		brcmf_err("Device class: 0x%x not supported\n",
 			  usb->descriptor.bDeviceClass);
 		ret = -ENODEV;
 		goto fail;
 	}
 	desc = &intf->altsetting[0].desc;
 	if ((desc->bInterfaceClass != USB_CLASS_VENDOR_SPEC) ||
 	    (desc->bInterfaceSubClass != 2) ||
 	    (desc->bInterfaceProtocol != 0xff)) {
 		brcmf_err("non WLAN interface %d: 0x%x:0x%x:0x%x\n",
 			  desc->bInterfaceNumber, desc->bInterfaceClass,
 			  desc->bInterfaceSubClass, desc->bInterfaceProtocol);
 		ret = -ENODEV;
 		goto fail;
 	}
 	num_of_eps = desc->bNumEndpoints;
 	for (ep = 0; ep < num_of_eps; ep++) {
 		endpoint = &intf->altsetting[0].endpoint[ep].desc;
 		endpoint_num = usb_endpoint_num(endpoint);
 		if (!usb_endpoint_xfer_bulk(endpoint))
 			continue;
 		if (usb_endpoint_dir_in(endpoint)) {
 			if (!devinfo->rx_pipe)
 				devinfo->rx_pipe =
 					usb_rcvbulkpipe(usb, endpoint_num);
 		} else {
 			if (!devinfo->tx_pipe)
 				devinfo->tx_pipe =
 					usb_sndbulkpipe(usb, endpoint_num);
 		}
 	}
 	if (devinfo->rx_pipe == 0) {
 		brcmf_err("No RX (in) Bulk EP found\n");
 		ret = -ENODEV;
 		goto fail;
 	}
 	if (devinfo->tx_pipe == 0) {
 		brcmf_err("No TX (out) Bulk EP found\n");
 		ret = -ENODEV;
 		goto fail;
 	}
 	devinfo->ifnum = desc->bInterfaceNumber;
 	if (usb->speed == USB_SPEED_SUPER)
 		brcmf_dbg(USB, "Broadcom super speed USB WLAN interface detected\n");
 	else if (usb->speed == USB_SPEED_HIGH)
 		brcmf_dbg(USB, "Broadcom high speed USB WLAN interface detected\n");
 	else
 		brcmf_dbg(USB, "Broadcom full speed USB WLAN interface detected\n");
 	ret = brcmf_usb_probe_cb(devinfo);
 	if (ret)
 		goto fail;
 	/* Success */
 	return 0;
 fail:
 	kfree(devinfo);
 	usb_set_intfdata(intf, NULL);
 	return ret;
 }
 static void
 brcmf_usb_disconnect(struct usb_interface *intf)
 {
 	struct brcmf_usbdev_info *devinfo;
 	brcmf_dbg(USB, "Enter\n");
 	devinfo = (struct brcmf_usbdev_info *)usb_get_intfdata(intf);
 	brcmf_usb_disconnect_cb(devinfo);
 	kfree(devinfo);
 	brcmf_dbg(USB, "Exit\n");
 }
 /*
  * only need to signal the bus being down and update the state.
  */
 static int brcmf_usb_suspend(struct usb_interface *intf, pm_message_t state)
 {
 	struct usb_device *usb = interface_to_usbdev(intf);
 	struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(&usb->dev);
 	brcmf_dbg(USB, "Enter\n");
 	devinfo->bus_pub.state = BRCMFMAC_USB_STATE_SLEEP;
 	brcmf_detach(&usb->dev);
 	return 0;
 }
 /*
  * (re-) start the bus.
  */
 static int brcmf_usb_resume(struct usb_interface *intf)
 {
 	struct usb_device *usb = interface_to_usbdev(intf);
 	struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(&usb->dev);
 	brcmf_dbg(USB, "Enter\n");
 	return brcmf_usb_bus_setup(devinfo);
 }
 static int brcmf_usb_reset_resume(struct usb_interface *intf)
 {
 	struct usb_device *usb = interface_to_usbdev(intf);
 	struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(&usb->dev);
 	brcmf_dbg(USB, "Enter\n");
 	return brcmf_fw_get_firmwares(&usb->dev, 0,
 				      brcmf_usb_get_fwname(devinfo), NULL,
 				      brcmf_usb_probe_phase2);
 }
 #define BRCMF_USB_DEVICE(dev_id)	\
 	{ USB_DEVICE(BRCM_USB_VENDOR_ID_BROADCOM, dev_id) }
 static struct usb_device_id brcmf_usb_devid_table[] = {
 	BRCMF_USB_DEVICE(BRCM_USB_43143_DEVICE_ID),
 	BRCMF_USB_DEVICE(BRCM_USB_43236_DEVICE_ID),
 	BRCMF_USB_DEVICE(BRCM_USB_43242_DEVICE_ID),
 	BRCMF_USB_DEVICE(BRCM_USB_43569_DEVICE_ID),
 	/* special entry for device with firmware loaded and running */
 	BRCMF_USB_DEVICE(BRCM_USB_BCMFW_DEVICE_ID),
 	{ /* end: all zeroes */ }
 };
 MODULE_DEVICE_TABLE(usb, brcmf_usb_devid_table);
 MODULE_FIRMWARE(BRCMF_USB_43143_FW_NAME);
 MODULE_FIRMWARE(BRCMF_USB_43236_FW_NAME);
 MODULE_FIRMWARE(BRCMF_USB_43242_FW_NAME);
 MODULE_FIRMWARE(BRCMF_USB_43569_FW_NAME);
 static struct usb_driver brcmf_usbdrvr = {
 	.name = KBUILD_MODNAME,
 	.probe = brcmf_usb_probe,
 	.disconnect = brcmf_usb_disconnect,
 	.id_table = brcmf_usb_devid_table,
 	.suspend = brcmf_usb_suspend,
 	.resume = brcmf_usb_resume,
 	.reset_resume = brcmf_usb_reset_resume,
 	.supports_autosuspend = 1,
 	.disable_hub_initiated_lpm = 1,
 };
 static int brcmf_usb_reset_device(struct device *dev, void *notused)
 {
 	/* device past is the usb interface so we
 	 * need to use parent here.
 	 */
 	brcmf_dev_reset(dev->parent);
 	return 0;
 }
 void brcmf_usb_exit(void)
 {
 	struct device_driver *drv = &brcmf_usbdrvr.drvwrap.driver;
 	int ret;
 	brcmf_dbg(USB, "Enter\n");
 	ret = driver_for_each_device(drv, NULL, NULL,
 				     brcmf_usb_reset_device);
 	usb_deregister(&brcmf_usbdrvr);
 }
 void brcmf_usb_register(void)
 {
 	brcmf_dbg(USB, "Enter\n");
 	usb_register(&brcmf_usbdrvr);
 }

net/mac80211/rc80211_minstrel_ht.c

Diff comments View file @ c857781

 /*
  * Copyright (C) 2010-2013 Felix Fietkau <nbd@openwrt.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/netdevice.h>
 #include <linux/types.h>
 #include <linux/skbuff.h>
 #include <linux/debugfs.h>
 #include <linux/random.h>
 #include <linux/ieee80211.h>
 #include <net/mac80211.h>
 #include "rate.h"
 #include "rc80211_minstrel.h"
 #include "rc80211_minstrel_ht.h"
 #define AVG_PKT_SIZE	1200
 /* Number of bits for an average sized packet */
 #define MCS_NBITS (AVG_PKT_SIZE << 3)
 /* Number of symbols for a packet with (bps) bits per symbol */
 #define MCS_NSYMS(bps) DIV_ROUND_UP(MCS_NBITS, (bps))
 /* Transmission time (nanoseconds) for a packet containing (syms) symbols */
 #define MCS_SYMBOL_TIME(sgi, syms)					\
 	(sgi ?								\
 	  ((syms) * 18000 + 4000) / 5 :	/* syms * 3.6 us */		\
 	  ((syms) * 1000) << 2		/* syms * 4 us */		\
 	)
 /* Transmit duration for the raw data part of an average sized packet */
 #define MCS_DURATION(streams, sgi, bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps)))
 /*
  * Define group sort order: HT40 -> SGI -> #streams
  */
 #define GROUP_IDX(_streams, _sgi, _ht40)	\
 	MINSTREL_MAX_STREAMS * 2 * _ht40 +	\
 	MINSTREL_MAX_STREAMS * _sgi +		\
 	_streams - 1
 /* MCS rate information for an MCS group */
 #define MCS_GROUP(_streams, _sgi, _ht40)				\
 	[GROUP_IDX(_streams, _sgi, _ht40)] = {				\
 	.streams = _streams,						\
 	.flags =							\
 		(_sgi ? IEEE80211_TX_RC_SHORT_GI : 0) |			\
 		(_ht40 ? IEEE80211_TX_RC_40_MHZ_WIDTH : 0),		\
 	.duration = {							\
 		MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26),		\
 		MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52),		\
 		MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78),		\
 		MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104),	\
 		MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156),	\
 		MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208),	\
 		MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234),	\
 		MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260)		\
 	}								\
 }
 #define CCK_DURATION(_bitrate, _short, _len)		\
 	(1000 * (10 /* SIFS */ +			\
 	 (_short ? 72 + 24 : 144 + 48) +		\
 	 (8 * (_len + 4) * 10) / (_bitrate)))
 #define CCK_ACK_DURATION(_bitrate, _short)			\
 	(CCK_DURATION((_bitrate > 10 ? 20 : 10), false, 60) +	\
 	 CCK_DURATION(_bitrate, _short, AVG_PKT_SIZE))
 #define CCK_DURATION_LIST(_short)			\
 	CCK_ACK_DURATION(10, _short),			\
 	CCK_ACK_DURATION(20, _short),			\
 	CCK_ACK_DURATION(55, _short),			\
 	CCK_ACK_DURATION(110, _short)
 #define CCK_GROUP						\
 	[MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS] = {	\
 		.streams = 0,					\
 		.duration = {					\
 			CCK_DURATION_LIST(false),		\
 			CCK_DURATION_LIST(true)			\
 		}						\
 	}
 /*
  * To enable sufficiently targeted rate sampling, MCS rates are divided into
  * groups, based on the number of streams and flags (HT40, SGI) that they
  * use.
  *
  * Sortorder has to be fixed for GROUP_IDX macro to be applicable:
  * HT40 -> SGI -> #streams
  */
 const struct mcs_group minstrel_mcs_groups[] = {
 	MCS_GROUP(1, 0, 0),
 	MCS_GROUP(2, 0, 0),
 #if MINSTREL_MAX_STREAMS >= 3
 	MCS_GROUP(3, 0, 0),
 #endif
 	MCS_GROUP(1, 1, 0),
 	MCS_GROUP(2, 1, 0),
 #if MINSTREL_MAX_STREAMS >= 3
 	MCS_GROUP(3, 1, 0),
 #endif
 	MCS_GROUP(1, 0, 1),
 	MCS_GROUP(2, 0, 1),
 #if MINSTREL_MAX_STREAMS >= 3
 	MCS_GROUP(3, 0, 1),
 #endif
 	MCS_GROUP(1, 1, 1),
 	MCS_GROUP(2, 1, 1),
 #if MINSTREL_MAX_STREAMS >= 3
 	MCS_GROUP(3, 1, 1),
 #endif
 	/* must be last */
 	CCK_GROUP
 };
 #define MINSTREL_CCK_GROUP	(ARRAY_SIZE(minstrel_mcs_groups) - 1)
 static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES] __read_mostly;
 static void
 minstrel_ht_update_rates(struct minstrel_priv *mp, struct minstrel_ht_sta *mi);
 /*
  * Look up an MCS group index based on mac80211 rate information
  */
 static int
 minstrel_ht_get_group_idx(struct ieee80211_tx_rate *rate)
 {
 	return GROUP_IDX((rate->idx / MCS_GROUP_RATES) + 1,
 			 !!(rate->flags & IEEE80211_TX_RC_SHORT_GI),
 			 !!(rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH));
 }
 static struct minstrel_rate_stats *
 minstrel_ht_get_stats(struct minstrel_priv *mp, struct minstrel_ht_sta *mi,
 		      struct ieee80211_tx_rate *rate)
 {
 	int group, idx;
 	if (rate->flags & IEEE80211_TX_RC_MCS) {
 		group = minstrel_ht_get_group_idx(rate);
 		idx = rate->idx % 8;
 	} else {
 		group = MINSTREL_CCK_GROUP;
 		for (idx = 0; idx < ARRAY_SIZE(mp->cck_rates); idx++)
 			if (rate->idx == mp->cck_rates[idx])
 				break;
 		/* short preamble */
 		if (!(mi->groups[group].supported & BIT(idx)))
 			idx += 4;
 	}
 	return &mi->groups[group].rates[idx];
 }
 static inline struct minstrel_rate_stats *
 minstrel_get_ratestats(struct minstrel_ht_sta *mi, int index)
 {
 	return &mi->groups[index / MCS_GROUP_RATES].rates[index % MCS_GROUP_RATES];
 }
 /*
  * Recalculate success probabilities and counters for a rate using EWMA
  */
 static void
 minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr)
 {
 	if (unlikely(mr->attempts > 0)) {
 		mr->sample_skipped = 0;
 		mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
 		if (!mr->att_hist)
 			mr->probability = mr->cur_prob;
 		else
 			mr->probability = minstrel_ewma(mr->probability,
 				mr->cur_prob, EWMA_LEVEL);
 		mr->att_hist += mr->attempts;
 		mr->succ_hist += mr->success;
 	} else {
 		mr->sample_skipped++;
 	}
 	mr->last_success = mr->success;
 	mr->last_attempts = mr->attempts;
 	mr->success = 0;
 	mr->attempts = 0;
 }
 /*
  * Calculate throughput based on the average A-MPDU length, taking into account
  * the expected number of retransmissions and their expected length
  */
 static void
 minstrel_ht_calc_tp(struct minstrel_ht_sta *mi, int group, int rate)
 {
 	struct minstrel_rate_stats *mr;
 	unsigned int nsecs = 0;
 	unsigned int tp;
 	unsigned int prob;
 	mr = &mi->groups[group].rates[rate];
 	prob = mr->probability;
 	if (prob < MINSTREL_FRAC(1, 10)) {
 		mr->cur_tp = 0;
 		return;
 	}
 	/*
 	 * For the throughput calculation, limit the probability value to 90% to
 	 * account for collision related packet error rate fluctuation
 	 */
 	if (prob > MINSTREL_FRAC(9, 10))
 		prob = MINSTREL_FRAC(9, 10);
 	if (group != MINSTREL_CCK_GROUP)
 		nsecs = 1000 * mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
 	nsecs += minstrel_mcs_groups[group].duration[rate];
 	/* prob is scaled - see MINSTREL_FRAC above */
 	tp = 1000000 * ((prob * 1000) / nsecs);
 	mr->cur_tp = MINSTREL_TRUNC(tp);
 }
 /*
  * Find & sort topmost throughput rates
  *
  * If multiple rates provide equal throughput the sorting is based on their
  * current success probability. Higher success probability is preferred among
  * MCS groups, CCK rates do not provide aggregation and are therefore at last.
  */
 static void
 minstrel_ht_sort_best_tp_rates(struct minstrel_ht_sta *mi, u8 index,
 			       u8 *tp_list)
 {
 	int cur_group, cur_idx, cur_thr, cur_prob;
 	int tmp_group, tmp_idx, tmp_thr, tmp_prob;
 	int j = MAX_THR_RATES;
 	cur_group = index / MCS_GROUP_RATES;
 	cur_idx = index  % MCS_GROUP_RATES;
 	cur_thr = mi->groups[cur_group].rates[cur_idx].cur_tp;
 	cur_prob = mi->groups[cur_group].rates[cur_idx].probability;
-	tmp_group = tp_list[j - 1] / MCS_GROUP_RATES;
+	do {
-	tmp_idx = tp_list[j - 1] % MCS_GROUP_RATES;
-	tmp_thr = mi->groups[tmp_group].rates[tmp_idx].cur_tp;
-	tmp_prob = mi->groups[tmp_group].rates[tmp_idx].probability;
-	while (j > 0 && (cur_thr > tmp_thr ||
-	      (cur_thr == tmp_thr && cur_prob > tmp_prob))) {
-		j--;
 		tmp_group = tp_list[j - 1] / MCS_GROUP_RATES;
 		tmp_idx = tp_list[j - 1] % MCS_GROUP_RATES;
 		tmp_thr = mi->groups[tmp_group].rates[tmp_idx].cur_tp;
 		tmp_prob = mi->groups[tmp_group].rates[tmp_idx].probability;
-	}
+		if (cur_thr < tmp_thr ||
+		    (cur_thr == tmp_thr && cur_prob <= tmp_prob))
+			break;
+		j--;
+	} while (j > 0);
 	if (j < MAX_THR_RATES - 1) {
 		memmove(&tp_list[j + 1], &tp_list[j], (sizeof(*tp_list) *
 		       (MAX_THR_RATES - (j + 1))));
 	}
 	if (j < MAX_THR_RATES)
 		tp_list[j] = index;
 }
 /*
  * Find and set the topmost probability rate per sta and per group
  */
 static void
 minstrel_ht_set_best_prob_rate(struct minstrel_ht_sta *mi, u8 index)
 {
 	struct minstrel_mcs_group_data *mg;
 	struct minstrel_rate_stats *mr;
 	int tmp_group, tmp_idx, tmp_tp, tmp_prob, max_tp_group;
 	mg = &mi->groups[index / MCS_GROUP_RATES];
 	mr = &mg->rates[index % MCS_GROUP_RATES];
 	tmp_group = mi->max_prob_rate / MCS_GROUP_RATES;
 	tmp_idx = mi->max_prob_rate % MCS_GROUP_RATES;
 	tmp_tp = mi->groups[tmp_group].rates[tmp_idx].cur_tp;
 	tmp_prob = mi->groups[tmp_group].rates[tmp_idx].probability;
 	/* if max_tp_rate[0] is from MCS_GROUP max_prob_rate get selected from
 	 * MCS_GROUP as well as CCK_GROUP rates do not allow aggregation */
 	max_tp_group = mi->max_tp_rate[0] / MCS_GROUP_RATES;
 	if((index / MCS_GROUP_RATES == MINSTREL_CCK_GROUP) &&
 	    (max_tp_group != MINSTREL_CCK_GROUP))
 		return;
 	if (mr->probability > MINSTREL_FRAC(75, 100)) {
 		if (mr->cur_tp > tmp_tp)
 			mi->max_prob_rate = index;
 		if (mr->cur_tp > mg->rates[mg->max_group_prob_rate].cur_tp)
 			mg->max_group_prob_rate = index;
 	} else {
 		if (mr->probability > tmp_prob)
 			mi->max_prob_rate = index;
 		if (mr->probability > mg->rates[mg->max_group_prob_rate].probability)
 			mg->max_group_prob_rate = index;
 	}
 }
 /*
  * Assign new rate set per sta and use CCK rates only if the fastest
  * rate (max_tp_rate[0]) is from CCK group. This prohibits such sorted
  * rate sets where MCS and CCK rates are mixed, because CCK rates can
  * not use aggregation.
  */
 static void
 minstrel_ht_assign_best_tp_rates(struct minstrel_ht_sta *mi,
 				 u8 tmp_mcs_tp_rate[MAX_THR_RATES],
 				 u8 tmp_cck_tp_rate[MAX_THR_RATES])
 {
 	unsigned int tmp_group, tmp_idx, tmp_cck_tp, tmp_mcs_tp;
 	int i;
 	tmp_group = tmp_cck_tp_rate[0] / MCS_GROUP_RATES;
 	tmp_idx = tmp_cck_tp_rate[0] % MCS_GROUP_RATES;
 	tmp_cck_tp = mi->groups[tmp_group].rates[tmp_idx].cur_tp;
 	tmp_group = tmp_mcs_tp_rate[0] / MCS_GROUP_RATES;
 	tmp_idx = tmp_mcs_tp_rate[0] % MCS_GROUP_RATES;
 	tmp_mcs_tp = mi->groups[tmp_group].rates[tmp_idx].cur_tp;
 	if (tmp_cck_tp > tmp_mcs_tp) {
 		for(i = 0; i < MAX_THR_RATES; i++) {
 			minstrel_ht_sort_best_tp_rates(mi, tmp_cck_tp_rate[i],
 						       tmp_mcs_tp_rate);
 		}
 	}
 }
 /*
  * Try to increase robustness of max_prob rate by decrease number of
  * streams if possible.
  */
 static inline void
 minstrel_ht_prob_rate_reduce_streams(struct minstrel_ht_sta *mi)
 {
 	struct minstrel_mcs_group_data *mg;
 	struct minstrel_rate_stats *mr;
 	int tmp_max_streams, group;
 	int tmp_tp = 0;
 	tmp_max_streams = minstrel_mcs_groups[mi->max_tp_rate[0] /
 			  MCS_GROUP_RATES].streams;
 	for (group = 0; group < ARRAY_SIZE(minstrel_mcs_groups); group++) {
 		mg = &mi->groups[group];
 		if (!mg->supported || group == MINSTREL_CCK_GROUP)
 			continue;
 		mr = minstrel_get_ratestats(mi, mg->max_group_prob_rate);
 		if (tmp_tp < mr->cur_tp &&
 		   (minstrel_mcs_groups[group].streams < tmp_max_streams)) {
 				mi->max_prob_rate = mg->max_group_prob_rate;
 				tmp_tp = mr->cur_tp;
 		}
 	}
 }
 /*
  * Update rate statistics and select new primary rates
  *
  * Rules for rate selection:
  *  - max_prob_rate must use only one stream, as a tradeoff between delivery
  *    probability and throughput during strong fluctuations
  *  - as long as the max prob rate has a probability of more than 75%, pick
  *    higher throughput rates, even if the probablity is a bit lower
  */
 static void
 minstrel_ht_update_stats(struct minstrel_priv *mp, struct minstrel_ht_sta *mi)
 {
 	struct minstrel_mcs_group_data *mg;
 	struct minstrel_rate_stats *mr;
 	int group, i, j;
 	u8 tmp_mcs_tp_rate[MAX_THR_RATES], tmp_group_tp_rate[MAX_THR_RATES];
 	u8 tmp_cck_tp_rate[MAX_THR_RATES], index;
 	if (mi->ampdu_packets > 0) {
 		mi->avg_ampdu_len = minstrel_ewma(mi->avg_ampdu_len,
 			MINSTREL_FRAC(mi->ampdu_len, mi->ampdu_packets), EWMA_LEVEL);
 		mi->ampdu_len = 0;
 		mi->ampdu_packets = 0;
 	}
 	mi->sample_slow = 0;
 	mi->sample_count = 0;
 	/* Initialize global rate indexes */
 	for(j = 0; j < MAX_THR_RATES; j++){
 		tmp_mcs_tp_rate[j] = 0;
 		tmp_cck_tp_rate[j] = 0;
 	}
 	/* Find best rate sets within all MCS groups*/
 	for (group = 0; group < ARRAY_SIZE(minstrel_mcs_groups); group++) {
 		mg = &mi->groups[group];
 		if (!mg->supported)
 			continue;
 		mi->sample_count++;
 		/* (re)Initialize group rate indexes */
 		for(j = 0; j < MAX_THR_RATES; j++)
 			tmp_group_tp_rate[j] = group;
 		for (i = 0; i < MCS_GROUP_RATES; i++) {
 			if (!(mg->supported & BIT(i)))
 				continue;
 			index = MCS_GROUP_RATES * group + i;
 			mr = &mg->rates[i];
 			mr->retry_updated = false;
 			minstrel_calc_rate_ewma(mr);
 			minstrel_ht_calc_tp(mi, group, i);
 			if (!mr->cur_tp)
 				continue;
 			/* Find max throughput rate set */
 			if (group != MINSTREL_CCK_GROUP) {
 				minstrel_ht_sort_best_tp_rates(mi, index,
 							       tmp_mcs_tp_rate);
 			} else if (group == MINSTREL_CCK_GROUP) {
 				minstrel_ht_sort_best_tp_rates(mi, index,
 							       tmp_cck_tp_rate);
 			}
 			/* Find max throughput rate set within a group */
 			minstrel_ht_sort_best_tp_rates(mi, index,
 						       tmp_group_tp_rate);
 			/* Find max probability rate per group and global */
 			minstrel_ht_set_best_prob_rate(mi, index);
 		}
 		memcpy(mg->max_group_tp_rate, tmp_group_tp_rate,
 		       sizeof(mg->max_group_tp_rate));
 	}
 	/* Assign new rate set per sta */
 	minstrel_ht_assign_best_tp_rates(mi, tmp_mcs_tp_rate, tmp_cck_tp_rate);
 	memcpy(mi->max_tp_rate, tmp_mcs_tp_rate, sizeof(mi->max_tp_rate));
 	/* Try to increase robustness of max_prob_rate*/
 	minstrel_ht_prob_rate_reduce_streams(mi);
 	/* try to sample all available rates during each interval */
 	mi->sample_count *= 8;
 #ifdef CONFIG_MAC80211_DEBUGFS
 	/* use fixed index if set */
 	if (mp->fixed_rate_idx != -1) {
 		for (i = 0; i < 4; i++)
 			mi->max_tp_rate[i] = mp->fixed_rate_idx;
 		mi->max_prob_rate = mp->fixed_rate_idx;
 	}
 #endif
 	/* Reset update timer */
 	mi->stats_update = jiffies;
 }
 static bool
 minstrel_ht_txstat_valid(struct minstrel_priv *mp, struct ieee80211_tx_rate *rate)
 {
 	if (rate->idx < 0)
 		return false;
 	if (!rate->count)
 		return false;
 	if (rate->flags & IEEE80211_TX_RC_MCS)
 		return true;
 	return rate->idx == mp->cck_rates[0] ||
 	       rate->idx == mp->cck_rates[1] ||
 	       rate->idx == mp->cck_rates[2] ||
 	       rate->idx == mp->cck_rates[3];
 }
 static void
 minstrel_next_sample_idx(struct minstrel_ht_sta *mi)
 {
 	struct minstrel_mcs_group_data *mg;
 	for (;;) {
 		mi->sample_group++;
 		mi->sample_group %= ARRAY_SIZE(minstrel_mcs_groups);
 		mg = &mi->groups[mi->sample_group];
 		if (!mg->supported)
 			continue;
 		if (++mg->index >= MCS_GROUP_RATES) {
 			mg->index = 0;
 			if (++mg->column >= ARRAY_SIZE(sample_table))
 				mg->column = 0;
 		}
 		break;
 	}
 }
 static void
 minstrel_downgrade_rate(struct minstrel_ht_sta *mi, u8 *idx, bool primary)
 {
 	int group, orig_group;
 	orig_group = group = *idx / MCS_GROUP_RATES;
 	while (group > 0) {
 		group--;
 		if (!mi->groups[group].supported)
 			continue;
 		if (minstrel_mcs_groups[group].streams >
 		    minstrel_mcs_groups[orig_group].streams)
 			continue;
 		if (primary)
 			*idx = mi->groups[group].max_group_tp_rate[0];
 		else
 			*idx = mi->groups[group].max_group_tp_rate[1];
 		break;
 	}
 }
 static void
 minstrel_aggr_check(struct ieee80211_sta *pubsta, struct sk_buff *skb)
 {
 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
 	struct sta_info *sta = container_of(pubsta, struct sta_info, sta);
 	u16 tid;
 	if (unlikely(!ieee80211_is_data_qos(hdr->frame_control)))
 		return;
 	if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE)))
 		return;
 	tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
 	if (likely(sta->ampdu_mlme.tid_tx[tid]))
 		return;
 	if (skb_get_queue_mapping(skb) == IEEE80211_AC_VO)
 		return;
 	ieee80211_start_tx_ba_session(pubsta, tid, 5000);
 }
 static void
 minstrel_ht_tx_status(void *priv, struct ieee80211_supported_band *sband,
                       struct ieee80211_sta *sta, void *priv_sta,
                       struct sk_buff *skb)
 {
 	struct minstrel_ht_sta_priv *msp = priv_sta;
 	struct minstrel_ht_sta *mi = &msp->ht;
 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 	struct ieee80211_tx_rate *ar = info->status.rates;
 	struct minstrel_rate_stats *rate, *rate2;
 	struct minstrel_priv *mp = priv;
 	bool last, update = false;
 	int i;
 	if (!msp->is_ht)
 		return mac80211_minstrel.tx_status(priv, sband, sta, &msp->legacy, skb);
 	/* This packet was aggregated but doesn't carry status info */
 	if ((info->flags & IEEE80211_TX_CTL_AMPDU) &&
 	    !(info->flags & IEEE80211_TX_STAT_AMPDU))
 		return;
 	if (!(info->flags & IEEE80211_TX_STAT_AMPDU)) {
 		info->status.ampdu_ack_len =
 			(info->flags & IEEE80211_TX_STAT_ACK ? 1 : 0);
 		info->status.ampdu_len = 1;
 	}
 	mi->ampdu_packets++;
 	mi->ampdu_len += info->status.ampdu_len;
 	if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) {
 		mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
 		mi->sample_tries = 1;
 		mi->sample_count--;
 	}
 	if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
 		mi->sample_packets += info->status.ampdu_len;
 	last = !minstrel_ht_txstat_valid(mp, &ar[0]);
 	for (i = 0; !last; i++) {
 		last = (i == IEEE80211_TX_MAX_RATES - 1) ||
 		       !minstrel_ht_txstat_valid(mp, &ar[i + 1]);
 		rate = minstrel_ht_get_stats(mp, mi, &ar[i]);
 		if (last)
 			rate->success += info->status.ampdu_ack_len;
 		rate->attempts += ar[i].count * info->status.ampdu_len;
 	}
 	/*
 	 * check for sudden death of spatial multiplexing,
 	 * downgrade to a lower number of streams if necessary.
 	 */
 	rate = minstrel_get_ratestats(mi, mi->max_tp_rate[0]);
 	if (rate->attempts > 30 &&
 	    MINSTREL_FRAC(rate->success, rate->attempts) <
 	    MINSTREL_FRAC(20, 100)) {
 		minstrel_downgrade_rate(mi, &mi->max_tp_rate[0], true);
 		update = true;
 	}
 	rate2 = minstrel_get_ratestats(mi, mi->max_tp_rate[1]);
 	if (rate2->attempts > 30 &&
 	    MINSTREL_FRAC(rate2->success, rate2->attempts) <
 	    MINSTREL_FRAC(20, 100)) {
 		minstrel_downgrade_rate(mi, &mi->max_tp_rate[1], false);
 		update = true;
 	}
 	if (time_after(jiffies, mi->stats_update + (mp->update_interval / 2 * HZ) / 1000)) {
 		update = true;
 		minstrel_ht_update_stats(mp, mi);
 		if (!(info->flags & IEEE80211_TX_CTL_AMPDU) &&
 		    mi->max_prob_rate / MCS_GROUP_RATES != MINSTREL_CCK_GROUP)
 			minstrel_aggr_check(sta, skb);
 	}
 	if (update)
 		minstrel_ht_update_rates(mp, mi);
 }
 static void
 minstrel_calc_retransmit(struct minstrel_priv *mp, struct minstrel_ht_sta *mi,
                          int index)
 {
 	struct minstrel_rate_stats *mr;
 	const struct mcs_group *group;
 	unsigned int tx_time, tx_time_rtscts, tx_time_data;
 	unsigned int cw = mp->cw_min;
 	unsigned int ctime = 0;
 	unsigned int t_slot = 9; /* FIXME */
 	unsigned int ampdu_len = MINSTREL_TRUNC(mi->avg_ampdu_len);
 	unsigned int overhead = 0, overhead_rtscts = 0;
 	mr = minstrel_get_ratestats(mi, index);
 	if (mr->probability < MINSTREL_FRAC(1, 10)) {
 		mr->retry_count = 1;
 		mr->retry_count_rtscts = 1;
 		return;
 	}
 	mr->retry_count = 2;
 	mr->retry_count_rtscts = 2;
 	mr->retry_updated = true;
 	group = &minstrel_mcs_groups[index / MCS_GROUP_RATES];
 	tx_time_data = group->duration[index % MCS_GROUP_RATES] * ampdu_len / 1000;
 	/* Contention time for first 2 tries */
 	ctime = (t_slot * cw) >> 1;
 	cw = min((cw << 1) | 1, mp->cw_max);
 	ctime += (t_slot * cw) >> 1;
 	cw = min((cw << 1) | 1, mp->cw_max);
 	if (index / MCS_GROUP_RATES != MINSTREL_CCK_GROUP) {
 		overhead = mi->overhead;
 		overhead_rtscts = mi->overhead_rtscts;
 	}
 	/* Total TX time for data and Contention after first 2 tries */
 	tx_time = ctime + 2 * (overhead + tx_time_data);
 	tx_time_rtscts = ctime + 2 * (overhead_rtscts + tx_time_data);
 	/* See how many more tries we can fit inside segment size */
 	do {
 		/* Contention time for this try */
 		ctime = (t_slot * cw) >> 1;
 		cw = min((cw << 1) | 1, mp->cw_max);
 		/* Total TX time after this try */
 		tx_time += ctime + overhead + tx_time_data;
 		tx_time_rtscts += ctime + overhead_rtscts + tx_time_data;
 		if (tx_time_rtscts < mp->segment_size)
 			mr->retry_count_rtscts++;
 	} while ((tx_time < mp->segment_size) &&
 	         (++mr->retry_count < mp->max_retry));
 }
 static void
 minstrel_ht_set_rate(struct minstrel_priv *mp, struct minstrel_ht_sta *mi,
                      struct ieee80211_sta_rates *ratetbl, int offset, int index)
 {
 	const struct mcs_group *group = &minstrel_mcs_groups[index / MCS_GROUP_RATES];
 	struct minstrel_rate_stats *mr;
 	u8 idx;
 	u16 flags;
 	mr = minstrel_get_ratestats(mi, index);
 	if (!mr->retry_updated)
 		minstrel_calc_retransmit(mp, mi, index);
 	if (mr->probability < MINSTREL_FRAC(20, 100) || !mr->retry_count) {
 		ratetbl->rate[offset].count = 2;
 		ratetbl->rate[offset].count_rts = 2;
 		ratetbl->rate[offset].count_cts = 2;
 	} else {
 		ratetbl->rate[offset].count = mr->retry_count;
 		ratetbl->rate[offset].count_cts = mr->retry_count;
 		ratetbl->rate[offset].count_rts = mr->retry_count_rtscts;
 	}
 	if (index / MCS_GROUP_RATES == MINSTREL_CCK_GROUP) {
 		idx = mp->cck_rates[index % ARRAY_SIZE(mp->cck_rates)];
 		flags = 0;
 	} else {
 		idx = index % MCS_GROUP_RATES + (group->streams - 1) * 8;
 		flags = IEEE80211_TX_RC_MCS | group->flags;
 	}
 	if (offset > 0) {
 		ratetbl->rate[offset].count = ratetbl->rate[offset].count_rts;
 		flags |= IEEE80211_TX_RC_USE_RTS_CTS;
 	}
 	ratetbl->rate[offset].idx = idx;
 	ratetbl->rate[offset].flags = flags;
 }
 static void
 minstrel_ht_update_rates(struct minstrel_priv *mp, struct minstrel_ht_sta *mi)
 {
 	struct ieee80211_sta_rates *rates;
 	int i = 0;
 	rates = kzalloc(sizeof(*rates), GFP_ATOMIC);
 	if (!rates)
 		return;
 	/* Start with max_tp_rate[0] */
 	minstrel_ht_set_rate(mp, mi, rates, i++, mi->max_tp_rate[0]);
 	if (mp->hw->max_rates >= 3) {
 		/* At least 3 tx rates supported, use max_tp_rate[1] next */
 		minstrel_ht_set_rate(mp, mi, rates, i++, mi->max_tp_rate[1]);
 	}
 	if (mp->hw->max_rates >= 2) {
 		/*
 		 * At least 2 tx rates supported, use max_prob_rate next */
 		minstrel_ht_set_rate(mp, mi, rates, i++, mi->max_prob_rate);
 	}
 	rates->rate[i].idx = -1;
 	rate_control_set_rates(mp->hw, mi->sta, rates);
 }
 static inline int
 minstrel_get_duration(int index)
 {
 	const struct mcs_group *group = &minstrel_mcs_groups[index / MCS_GROUP_RATES];
 	return group->duration[index % MCS_GROUP_RATES];
 }
 static int
 minstrel_get_sample_rate(struct minstrel_priv *mp, struct minstrel_ht_sta *mi)
 {
 	struct minstrel_rate_stats *mr;
 	struct minstrel_mcs_group_data *mg;
 	unsigned int sample_dur, sample_group, cur_max_tp_streams;
 	int sample_idx = 0;
 	if (mi->sample_wait > 0) {
 		mi->sample_wait--;
 		return -1;
 	}
 	if (!mi->sample_tries)
 		return -1;
 	sample_group = mi->sample_group;
 	mg = &mi->groups[sample_group];
 	sample_idx = sample_table[mg->column][mg->index];
 	minstrel_next_sample_idx(mi);
 	if (!(mg->supported & BIT(sample_idx)))
 		return -1;
 	mr = &mg->rates[sample_idx];
 	sample_idx += sample_group * MCS_GROUP_RATES;
 	/*
 	 * Sampling might add some overhead (RTS, no aggregation)
 	 * to the frame. Hence, don't use sampling for the currently
 	 * used rates.
 	 */
 	if (sample_idx == mi->max_tp_rate[0] ||
 	    sample_idx == mi->max_tp_rate[1] ||
 	    sample_idx == mi->max_prob_rate)
 		return -1;
 	/*
 	 * Do not sample if the probability is already higher than 95%
 	 * to avoid wasting airtime.
 	 */
 	if (mr->probability > MINSTREL_FRAC(95, 100))
 		return -1;
 	/*
 	 * Make sure that lower rates get sampled only occasionally,
 	 * if the link is working perfectly.
 	 */
 	cur_max_tp_streams = minstrel_mcs_groups[mi->max_tp_rate[0] /
 		MCS_GROUP_RATES].streams;
 	sample_dur = minstrel_get_duration(sample_idx);
 	if (sample_dur >= minstrel_get_duration(mi->max_tp_rate[1]) &&
 	    (cur_max_tp_streams - 1 <
 	     minstrel_mcs_groups[sample_group].streams ||
 	     sample_dur >= minstrel_get_duration(mi->max_prob_rate))) {
 		if (mr->sample_skipped < 20)
 			return -1;
 		if (mi->sample_slow++ > 2)
 			return -1;
 	}
 	mi->sample_tries--;
 	return sample_idx;
 }
 static void
 minstrel_ht_check_cck_shortpreamble(struct minstrel_priv *mp,
 				    struct minstrel_ht_sta *mi, bool val)
 {
 	u8 supported = mi->groups[MINSTREL_CCK_GROUP].supported;
 	if (!supported || !mi->cck_supported_short)
 		return;
 	if (supported & (mi->cck_supported_short << (val * 4)))
 		return;
 	supported ^= mi->cck_supported_short | (mi->cck_supported_short << 4);
 	mi->groups[MINSTREL_CCK_GROUP].supported = supported;
 }
 static void
 minstrel_ht_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
                      struct ieee80211_tx_rate_control *txrc)
 {
 	const struct mcs_group *sample_group;
 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(txrc->skb);
 	struct ieee80211_tx_rate *rate = &info->status.rates[0];
 	struct minstrel_ht_sta_priv *msp = priv_sta;
 	struct minstrel_ht_sta *mi = &msp->ht;
 	struct minstrel_priv *mp = priv;
 	int sample_idx;
 	if (rate_control_send_low(sta, priv_sta, txrc))
 		return;
 	if (!msp->is_ht)
 		return mac80211_minstrel.get_rate(priv, sta, &msp->legacy, txrc);
 	info->flags |= mi->tx_flags;
 	minstrel_ht_check_cck_shortpreamble(mp, mi, txrc->short_preamble);
 #ifdef CONFIG_MAC80211_DEBUGFS
 	if (mp->fixed_rate_idx != -1)
 		return;
 #endif
 	/* Don't use EAPOL frames for sampling on non-mrr hw */
 	if (mp->hw->max_rates == 1 &&
 	    (info->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO))
 		sample_idx = -1;
 	else
 		sample_idx = minstrel_get_sample_rate(mp, mi);
 	mi->total_packets++;
 	/* wraparound */
 	if (mi->total_packets == ~0) {
 		mi->total_packets = 0;
 		mi->sample_packets = 0;
 	}
 	if (sample_idx < 0)
 		return;
 	sample_group = &minstrel_mcs_groups[sample_idx / MCS_GROUP_RATES];
 	info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
 	rate->count = 1;
 	if (sample_idx / MCS_GROUP_RATES == MINSTREL_CCK_GROUP) {
 		int idx = sample_idx % ARRAY_SIZE(mp->cck_rates);
 		rate->idx = mp->cck_rates[idx];
 		rate->flags = 0;
 		return;
 	}
 	rate->idx = sample_idx % MCS_GROUP_RATES +
 		    (sample_group->streams - 1) * 8;
 	rate->flags = IEEE80211_TX_RC_MCS | sample_group->flags;
 }
 static void
 minstrel_ht_update_cck(struct minstrel_priv *mp, struct minstrel_ht_sta *mi,
 		       struct ieee80211_supported_band *sband,
 		       struct ieee80211_sta *sta)
 {
 	int i;
 	if (sband->band != IEEE80211_BAND_2GHZ)
 		return;
 	if (!(mp->hw->flags & IEEE80211_HW_SUPPORTS_HT_CCK_RATES))
 		return;
 	mi->cck_supported = 0;
 	mi->cck_supported_short = 0;
 	for (i = 0; i < 4; i++) {
 		if (!rate_supported(sta, sband->band, mp->cck_rates[i]))
 			continue;
 		mi->cck_supported |= BIT(i);
 		if (sband->bitrates[i].flags & IEEE80211_RATE_SHORT_PREAMBLE)
 			mi->cck_supported_short |= BIT(i);
 	}
 	mi->groups[MINSTREL_CCK_GROUP].supported = mi->cck_supported;
 }
 static void
 minstrel_ht_update_caps(void *priv, struct ieee80211_supported_band *sband,
 			struct cfg80211_chan_def *chandef,
                         struct ieee80211_sta *sta, void *priv_sta)
 {
 	struct minstrel_priv *mp = priv;
 	struct minstrel_ht_sta_priv *msp = priv_sta;
 	struct minstrel_ht_sta *mi = &msp->ht;
 	struct ieee80211_mcs_info *mcs = &sta->ht_cap.mcs;
 	u16 sta_cap = sta->ht_cap.cap;
 	int n_supported = 0;
 	int ack_dur;
 	int stbc;
 	int i;
 	/* fall back to the old minstrel for legacy stations */
 	if (!sta->ht_cap.ht_supported)
 		goto use_legacy;
 	BUILD_BUG_ON(ARRAY_SIZE(minstrel_mcs_groups) !=
 		MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS + 1);
 	msp->is_ht = true;
 	memset(mi, 0, sizeof(*mi));
 	mi->sta = sta;
 	mi->stats_update = jiffies;
 	ack_dur = ieee80211_frame_duration(sband->band, 10, 60, 1, 1, 0);
 	mi->overhead = ieee80211_frame_duration(sband->band, 0, 60, 1, 1, 0);
 	mi->overhead += ack_dur;
 	mi->overhead_rtscts = mi->overhead + 2 * ack_dur;
 	mi->avg_ampdu_len = MINSTREL_FRAC(1, 1);
 	/* When using MRR, sample more on the first attempt, without delay */
 	if (mp->has_mrr) {
 		mi->sample_count = 16;
 		mi->sample_wait = 0;
 	} else {
 		mi->sample_count = 8;
 		mi->sample_wait = 8;
 	}
 	mi->sample_tries = 4;
 	stbc = (sta_cap & IEEE80211_HT_CAP_RX_STBC) >>
 		IEEE80211_HT_CAP_RX_STBC_SHIFT;
 	mi->tx_flags |= stbc << IEEE80211_TX_CTL_STBC_SHIFT;
 	if (sta_cap & IEEE80211_HT_CAP_LDPC_CODING)
 		mi->tx_flags |= IEEE80211_TX_CTL_LDPC;
 	for (i = 0; i < ARRAY_SIZE(mi->groups); i++) {
 		mi->groups[i].supported = 0;
 		if (i == MINSTREL_CCK_GROUP) {
 			minstrel_ht_update_cck(mp, mi, sband, sta);
 			continue;
 		}
 		if (minstrel_mcs_groups[i].flags & IEEE80211_TX_RC_SHORT_GI) {
 			if (minstrel_mcs_groups[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) {
 				if (!(sta_cap & IEEE80211_HT_CAP_SGI_40))
 					continue;
 			} else {
 				if (!(sta_cap & IEEE80211_HT_CAP_SGI_20))
 					continue;
 			}
 		}
 		if (minstrel_mcs_groups[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH &&
 		    sta->bandwidth < IEEE80211_STA_RX_BW_40)
 			continue;
 		/* Mark MCS > 7 as unsupported if STA is in static SMPS mode */
 		if (sta->smps_mode == IEEE80211_SMPS_STATIC &&
 		    minstrel_mcs_groups[i].streams > 1)
 			continue;
 		mi->groups[i].supported =
 			mcs->rx_mask[minstrel_mcs_groups[i].streams - 1];
 		if (mi->groups[i].supported)
 			n_supported++;
 	}
 	if (!n_supported)
 		goto use_legacy;
 	/* create an initial rate table with the lowest supported rates */
 	minstrel_ht_update_stats(mp, mi);
 	minstrel_ht_update_rates(mp, mi);
 	return;
 use_legacy:
 	msp->is_ht = false;
 	memset(&msp->legacy, 0, sizeof(msp->legacy));
 	msp->legacy.r = msp->ratelist;
 	msp->legacy.sample_table = msp->sample_table;
 	return mac80211_minstrel.rate_init(priv, sband, chandef, sta,
 					   &msp->legacy);
 }
 static void
 minstrel_ht_rate_init(void *priv, struct ieee80211_supported_band *sband,
 		      struct cfg80211_chan_def *chandef,
                       struct ieee80211_sta *sta, void *priv_sta)
 {
 	minstrel_ht_update_caps(priv, sband, chandef, sta, priv_sta);
 }
 static void
 minstrel_ht_rate_update(void *priv, struct ieee80211_supported_band *sband,
 			struct cfg80211_chan_def *chandef,
                         struct ieee80211_sta *sta, void *priv_sta,
                         u32 changed)
 {
 	minstrel_ht_update_caps(priv, sband, chandef, sta, priv_sta);
 }
 static void *
 minstrel_ht_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp)
 {
 	struct ieee80211_supported_band *sband;
 	struct minstrel_ht_sta_priv *msp;
 	struct minstrel_priv *mp = priv;
 	struct ieee80211_hw *hw = mp->hw;
 	int max_rates = 0;
 	int i;
 	for (i = 0; i < IEEE80211_NUM_BANDS; i++) {
 		sband = hw->wiphy->bands[i];
 		if (sband && sband->n_bitrates > max_rates)
 			max_rates = sband->n_bitrates;
 	}
 	msp = kzalloc(sizeof(*msp), gfp);
 	if (!msp)
 		return NULL;
 	msp->ratelist = kzalloc(sizeof(struct minstrel_rate) * max_rates, gfp);
 	if (!msp->ratelist)
 		goto error;
 	msp->sample_table = kmalloc(SAMPLE_COLUMNS * max_rates, gfp);
 	if (!msp->sample_table)
 		goto error1;
 	return msp;
 error1:
 	kfree(msp->ratelist);
 error:
 	kfree(msp);
 	return NULL;
 }
 static void
 minstrel_ht_free_sta(void *priv, struct ieee80211_sta *sta, void *priv_sta)
 {
 	struct minstrel_ht_sta_priv *msp = priv_sta;
 	kfree(msp->sample_table);
 	kfree(msp->ratelist);
 	kfree(msp);
 }
 static void *
 minstrel_ht_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)
 {
 	return mac80211_minstrel.alloc(hw, debugfsdir);
 }
 static void
 minstrel_ht_free(void *priv)
 {
 	mac80211_minstrel.free(priv);
 }
 static u32 minstrel_ht_get_expected_throughput(void *priv_sta)
 {
 	struct minstrel_ht_sta_priv *msp = priv_sta;
 	struct minstrel_ht_sta *mi = &msp->ht;
 	int i, j;
 	if (!msp->is_ht)
 		return mac80211_minstrel.get_expected_throughput(priv_sta);
 	i = mi->max_tp_rate[0] / MCS_GROUP_RATES;
 	j = mi->max_tp_rate[0] % MCS_GROUP_RATES;
 	/* convert cur_tp from pkt per second in kbps */
 	return mi->groups[i].rates[j].cur_tp * AVG_PKT_SIZE * 8 / 1024;
 }
 static const struct rate_control_ops mac80211_minstrel_ht = {
 	.name = "minstrel_ht",
 	.tx_status = minstrel_ht_tx_status,
 	.get_rate = minstrel_ht_get_rate,
 	.rate_init = minstrel_ht_rate_init,
 	.rate_update = minstrel_ht_rate_update,
 	.alloc_sta = minstrel_ht_alloc_sta,
 	.free_sta = minstrel_ht_free_sta,
 	.alloc = minstrel_ht_alloc,
 	.free = minstrel_ht_free,
 #ifdef CONFIG_MAC80211_DEBUGFS
 	.add_sta_debugfs = minstrel_ht_add_sta_debugfs,
 	.remove_sta_debugfs = minstrel_ht_remove_sta_debugfs,
 #endif
 	.get_expected_throughput = minstrel_ht_get_expected_throughput,
 };
 static void __init init_sample_table(void)
 {
 	int col, i, new_idx;
 	u8 rnd[MCS_GROUP_RATES];
 	memset(sample_table, 0xff, sizeof(sample_table));
 	for (col = 0; col < SAMPLE_COLUMNS; col++) {
 		prandom_bytes(rnd, sizeof(rnd));
 		for (i = 0; i < MCS_GROUP_RATES; i++) {
 			new_idx = (i + rnd[i]) % MCS_GROUP_RATES;
 			while (sample_table[col][new_idx] != 0xff)
 				new_idx = (new_idx + 1) % MCS_GROUP_RATES;
 			sample_table[col][new_idx] = i;
 		}
 	}
 }
 int __init
 rc80211_minstrel_ht_init(void)
 {
 	init_sample_table();
 	return ieee80211_rate_control_register(&mac80211_minstrel_ht);
 }
 void
 rc80211_minstrel_ht_exit(void)

1	/*	1	/*
2	* Copyright (c) 2014 Broadcom Corporation	2	* Copyright (c) 2014 Broadcom Corporation
3	*	3	*
4	* Permission to use, copy, modify, and/or distribute this software for any	4	* Permission to use, copy, modify, and/or distribute this software for any
5	* purpose with or without fee is hereby granted, provided that the above	5	* purpose with or without fee is hereby granted, provided that the above
6	* copyright notice and this permission notice appear in all copies.	6	* copyright notice and this permission notice appear in all copies.
7	*	7	*
8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15	*/	15	*/
16	#include <linux/init.h>	16	#include <linux/init.h>
17	#include <linux/of.h>	17	#include <linux/of.h>
18	#include <linux/of_irq.h>	18	#include <linux/of_irq.h>
19	#include <linux/mmc/card.h>	19	#include <linux/mmc/card.h>
20	#include <linux/platform_data/brcmfmac-sdio.h>	20	#include <linux/platform_data/brcmfmac-sdio.h>
21	#include <linux/mmc/sdio_func.h>	21	#include <linux/mmc/sdio_func.h>
22		22
23	#include <defs.h>	23	#include <defs.h>
24	#include "dhd_dbg.h"	24	#include "dhd_dbg.h"
25	#include "sdio_host.h"	25	#include "sdio_host.h"
26		26
27	void brcmf_of_probe(struct brcmf_sdio_dev *sdiodev)	27	void brcmf_of_probe(struct brcmf_sdio_dev *sdiodev)
28	{	28	{
29	struct device *dev = sdiodev->dev;	29	struct device *dev = sdiodev->dev;
30	struct device_node *np = dev->of_node;	30	struct device_node *np = dev->of_node;
31	int irq;	31	int irq;
32	u32 irqf;	32	u32 irqf;
33	u32 val;	33	u32 val;
34		34
35	if (!np \|\| !of_device_is_compatible(np, "brcm,bcm4329-fmac"))	35	if (!np \|\| !of_device_is_compatible(np, "brcm,bcm4329-fmac"))
36	return;	36	return;
37		37
38	sdiodev->pdata = devm_kzalloc(dev, sizeof(*sdiodev->pdata), GFP_KERNEL);	38	sdiodev->pdata = devm_kzalloc(dev, sizeof(*sdiodev->pdata), GFP_KERNEL);
39	if (!sdiodev->pdata)	39	if (!sdiodev->pdata)
40	return;	40	return;
41		41
42	irq = irq_of_parse_and_map(np, 0);	42	irq = irq_of_parse_and_map(np, 0);
43	if (irq < 0) {	43	if (!irq) {
44	brcmf_err("interrupt could not be mapped: err=%d\n", irq);	44	brcmf_err("interrupt could not be mapped\n");
45	devm_kfree(dev, sdiodev->pdata);	45	devm_kfree(dev, sdiodev->pdata);
46	return;	46	return;
47	}	47	}
48	irqf = irqd_get_trigger_type(irq_get_irq_data(irq));	48	irqf = irqd_get_trigger_type(irq_get_irq_data(irq));
49		49
50	sdiodev->pdata->oob_irq_supported = true;	50	sdiodev->pdata->oob_irq_supported = true;
51	sdiodev->pdata->oob_irq_nr = irq;	51	sdiodev->pdata->oob_irq_nr = irq;
52	sdiodev->pdata->oob_irq_flags = irqf;	52	sdiodev->pdata->oob_irq_flags = irqf;
53		53
54	if (of_property_read_u32(np, "brcm,drive-strength", &val) == 0)	54	if (of_property_read_u32(np, "brcm,drive-strength", &val) == 0)
55	sdiodev->pdata->drive_strength = val;	55	sdiodev->pdata->drive_strength = val;
56	}	56	}
57		57