Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit cda2109a26eb6fa58acfeae878eed87492480eae

Authored by Grygorii Strashko 2013-06-08 02:46:07 +0800

Committed by Wolfram Sang 2013-08-19 20:08:19 +0800

i2c: omap: query STP always when NACK is received

According to I2C specification the NACK should be handled as folowing:
"When SDA remains HIGH during this ninth clock pulse, this is defined as the Not
Acknowledge signal. The master can then gene rate either a STOP condition to
abort the transfer, or a repeated START condition to start a new transfer."
[http://www.nxp.com/documents/user_manual/UM10204.pdf]

The same is recomened by TI I2C wiki:
 http://processors.wiki.ti.com/index.php/I2C_Tips

Currently, the OMAP I2C driver interrupts I2C trunsfer in case of NACK, but
It queries Stop condition OMAP_I2C_CON_REG.STP=1 only if NACK has been received
during the last message transmitting/recieving.
This may lead to stuck Bus in "Bus Busy" until I2C IP reset (idle/enable).

Hence, fix it by querying Stop condition (STP) always when NACK is received.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Hein Tibosch <hein_tibosch@yahoo.es>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

Showing 1 changed file with 4 additions and 5 deletions Inline Diff

drivers/i2c/busses/i2c-omap.c

drivers/i2c/busses/i2c-omap.c

Diff comments View file @ cda2109

1	/*	1	/*
2	* TI OMAP I2C master mode driver	2	* TI OMAP I2C master mode driver
3	*	3	*
4	* Copyright (C) 2003 MontaVista Software, Inc.	4	* Copyright (C) 2003 MontaVista Software, Inc.
5	* Copyright (C) 2005 Nokia Corporation	5	* Copyright (C) 2005 Nokia Corporation
6	* Copyright (C) 2004 - 2007 Texas Instruments.	6	* Copyright (C) 2004 - 2007 Texas Instruments.
7	*	7	*
8	* Originally written by MontaVista Software, Inc.	8	* Originally written by MontaVista Software, Inc.
9	* Additional contributions by:	9	* Additional contributions by:
10	* Tony Lindgren <tony@atomide.com>	10	* Tony Lindgren <tony@atomide.com>
11	* Imre Deak <imre.deak@nokia.com>	11	* Imre Deak <imre.deak@nokia.com>
12	* Juha Yrjölä <juha.yrjola@solidboot.com>	12	* Juha Yrjölä <juha.yrjola@solidboot.com>
13	* Syed Khasim <x0khasim@ti.com>	13	* Syed Khasim <x0khasim@ti.com>
14	* Nishant Menon <nm@ti.com>	14	* Nishant Menon <nm@ti.com>
15	*	15	*
16	* This program is free software; you can redistribute it and/or modify	16	* This program is free software; you can redistribute it and/or modify
17	* it under the terms of the GNU General Public License as published by	17	* it under the terms of the GNU General Public License as published by
18	* the Free Software Foundation; either version 2 of the License, or	18	* the Free Software Foundation; either version 2 of the License, or
19	* (at your option) any later version.	19	* (at your option) any later version.
20	*	20	*
21	* This program is distributed in the hope that it will be useful,	21	* This program is distributed in the hope that it will be useful,
22	* but WITHOUT ANY WARRANTY; without even the implied warranty of	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24	* GNU General Public License for more details.	24	* GNU General Public License for more details.
25	*	25	*
26	* You should have received a copy of the GNU General Public License	26	* You should have received a copy of the GNU General Public License
27	* along with this program; if not, write to the Free Software	27	* along with this program; if not, write to the Free Software
28	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.	28	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29	*/	29	*/
30		30
31	#include <linux/module.h>	31	#include <linux/module.h>
32	#include <linux/delay.h>	32	#include <linux/delay.h>
33	#include <linux/i2c.h>	33	#include <linux/i2c.h>
34	#include <linux/err.h>	34	#include <linux/err.h>
35	#include <linux/interrupt.h>	35	#include <linux/interrupt.h>
36	#include <linux/completion.h>	36	#include <linux/completion.h>
37	#include <linux/platform_device.h>	37	#include <linux/platform_device.h>
38	#include <linux/clk.h>	38	#include <linux/clk.h>
39	#include <linux/io.h>	39	#include <linux/io.h>
40	#include <linux/of.h>	40	#include <linux/of.h>
41	#include <linux/of_i2c.h>	41	#include <linux/of_i2c.h>
42	#include <linux/of_device.h>	42	#include <linux/of_device.h>
43	#include <linux/slab.h>	43	#include <linux/slab.h>
44	#include <linux/i2c-omap.h>	44	#include <linux/i2c-omap.h>
45	#include <linux/pm_runtime.h>	45	#include <linux/pm_runtime.h>
46		46
47	/* I2C controller revisions */	47	/* I2C controller revisions */
48	#define OMAP_I2C_OMAP1_REV_2 0x20	48	#define OMAP_I2C_OMAP1_REV_2 0x20
49		49
50	/* I2C controller revisions present on specific hardware */	50	/* I2C controller revisions present on specific hardware */
51	#define OMAP_I2C_REV_ON_2430 0x00000036	51	#define OMAP_I2C_REV_ON_2430 0x00000036
52	#define OMAP_I2C_REV_ON_3430_3530 0x0000003C	52	#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
53	#define OMAP_I2C_REV_ON_3630 0x00000040	53	#define OMAP_I2C_REV_ON_3630 0x00000040
54	#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002	54	#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
55		55
56	/* timeout waiting for the controller to respond */	56	/* timeout waiting for the controller to respond */
57	#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))	57	#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
58		58
59	/* timeout for pm runtime autosuspend */	59	/* timeout for pm runtime autosuspend */
60	#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */	60	#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
61		61
62	/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */	62	/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
63	enum {	63	enum {
64	OMAP_I2C_REV_REG = 0,	64	OMAP_I2C_REV_REG = 0,
65	OMAP_I2C_IE_REG,	65	OMAP_I2C_IE_REG,
66	OMAP_I2C_STAT_REG,	66	OMAP_I2C_STAT_REG,
67	OMAP_I2C_IV_REG,	67	OMAP_I2C_IV_REG,
68	OMAP_I2C_WE_REG,	68	OMAP_I2C_WE_REG,
69	OMAP_I2C_SYSS_REG,	69	OMAP_I2C_SYSS_REG,
70	OMAP_I2C_BUF_REG,	70	OMAP_I2C_BUF_REG,
71	OMAP_I2C_CNT_REG,	71	OMAP_I2C_CNT_REG,
72	OMAP_I2C_DATA_REG,	72	OMAP_I2C_DATA_REG,
73	OMAP_I2C_SYSC_REG,	73	OMAP_I2C_SYSC_REG,
74	OMAP_I2C_CON_REG,	74	OMAP_I2C_CON_REG,
75	OMAP_I2C_OA_REG,	75	OMAP_I2C_OA_REG,
76	OMAP_I2C_SA_REG,	76	OMAP_I2C_SA_REG,
77	OMAP_I2C_PSC_REG,	77	OMAP_I2C_PSC_REG,
78	OMAP_I2C_SCLL_REG,	78	OMAP_I2C_SCLL_REG,
79	OMAP_I2C_SCLH_REG,	79	OMAP_I2C_SCLH_REG,
80	OMAP_I2C_SYSTEST_REG,	80	OMAP_I2C_SYSTEST_REG,
81	OMAP_I2C_BUFSTAT_REG,	81	OMAP_I2C_BUFSTAT_REG,
82	/* only on OMAP4430 */	82	/* only on OMAP4430 */
83	OMAP_I2C_IP_V2_REVNB_LO,	83	OMAP_I2C_IP_V2_REVNB_LO,
84	OMAP_I2C_IP_V2_REVNB_HI,	84	OMAP_I2C_IP_V2_REVNB_HI,
85	OMAP_I2C_IP_V2_IRQSTATUS_RAW,	85	OMAP_I2C_IP_V2_IRQSTATUS_RAW,
86	OMAP_I2C_IP_V2_IRQENABLE_SET,	86	OMAP_I2C_IP_V2_IRQENABLE_SET,
87	OMAP_I2C_IP_V2_IRQENABLE_CLR,	87	OMAP_I2C_IP_V2_IRQENABLE_CLR,
88	};	88	};
89		89
90	/* I2C Interrupt Enable Register (OMAP_I2C_IE): */	90	/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
91	#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */	91	#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
92	#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */	92	#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
93	#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */	93	#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
94	#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */	94	#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
95	#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */	95	#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
96	#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */	96	#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
97	#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */	97	#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
98		98
99	/* I2C Status Register (OMAP_I2C_STAT): */	99	/* I2C Status Register (OMAP_I2C_STAT): */
100	#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */	100	#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
101	#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */	101	#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
102	#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */	102	#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
103	#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */	103	#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
104	#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */	104	#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
105	#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */	105	#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
106	#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */	106	#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
107	#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */	107	#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
108	#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */	108	#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
109	#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */	109	#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
110	#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */	110	#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
111	#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */	111	#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
112		112
113	/* I2C WE wakeup enable register */	113	/* I2C WE wakeup enable register */
114	#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */	114	#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
115	#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */	115	#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
116	#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/	116	#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
117	#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */	117	#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
118	#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */	118	#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
119	#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */	119	#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
120	#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */	120	#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
121	#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */	121	#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
122	#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */	122	#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
123	#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */	123	#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
124		124
125	#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE \| OMAP_I2C_WE_RDR_WE \| \	125	#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE \| OMAP_I2C_WE_RDR_WE \| \
126	OMAP_I2C_WE_AAS_WE \| OMAP_I2C_WE_BF_WE \| \	126	OMAP_I2C_WE_AAS_WE \| OMAP_I2C_WE_BF_WE \| \
127	OMAP_I2C_WE_STC_WE \| OMAP_I2C_WE_GC_WE \| \	127	OMAP_I2C_WE_STC_WE \| OMAP_I2C_WE_GC_WE \| \
128	OMAP_I2C_WE_DRDY_WE \| OMAP_I2C_WE_ARDY_WE \| \	128	OMAP_I2C_WE_DRDY_WE \| OMAP_I2C_WE_ARDY_WE \| \
129	OMAP_I2C_WE_NACK_WE \| OMAP_I2C_WE_AL_WE)	129	OMAP_I2C_WE_NACK_WE \| OMAP_I2C_WE_AL_WE)
130		130
131	/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */	131	/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
132	#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */	132	#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
133	#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */	133	#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
134	#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */	134	#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
135	#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */	135	#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
136		136
137	/* I2C Configuration Register (OMAP_I2C_CON): */	137	/* I2C Configuration Register (OMAP_I2C_CON): */
138	#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */	138	#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
139	#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */	139	#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
140	#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */	140	#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
141	#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */	141	#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
142	#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */	142	#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
143	#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */	143	#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
144	#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */	144	#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
145	#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */	145	#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
146	#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */	146	#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
147	#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */	147	#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
148		148
149	/* I2C SCL time value when Master */	149	/* I2C SCL time value when Master */
150	#define OMAP_I2C_SCLL_HSSCLL 8	150	#define OMAP_I2C_SCLL_HSSCLL 8
151	#define OMAP_I2C_SCLH_HSSCLH 8	151	#define OMAP_I2C_SCLH_HSSCLH 8
152		152
153	/* I2C System Test Register (OMAP_I2C_SYSTEST): */	153	/* I2C System Test Register (OMAP_I2C_SYSTEST): */
154	#ifdef DEBUG	154	#ifdef DEBUG
155	#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */	155	#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
156	#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */	156	#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
157	#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */	157	#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
158	#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */	158	#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
159	#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */	159	#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
160	#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */	160	#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
161	#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */	161	#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
162	#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */	162	#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
163	#endif	163	#endif
164		164
165	/* OCP_SYSSTATUS bit definitions */	165	/* OCP_SYSSTATUS bit definitions */
166	#define SYSS_RESETDONE_MASK (1 << 0)	166	#define SYSS_RESETDONE_MASK (1 << 0)
167		167
168	/* OCP_SYSCONFIG bit definitions */	168	/* OCP_SYSCONFIG bit definitions */
169	#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)	169	#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
170	#define SYSC_SIDLEMODE_MASK (0x3 << 3)	170	#define SYSC_SIDLEMODE_MASK (0x3 << 3)
171	#define SYSC_ENAWAKEUP_MASK (1 << 2)	171	#define SYSC_ENAWAKEUP_MASK (1 << 2)
172	#define SYSC_SOFTRESET_MASK (1 << 1)	172	#define SYSC_SOFTRESET_MASK (1 << 1)
173	#define SYSC_AUTOIDLE_MASK (1 << 0)	173	#define SYSC_AUTOIDLE_MASK (1 << 0)
174		174
175	#define SYSC_IDLEMODE_SMART 0x2	175	#define SYSC_IDLEMODE_SMART 0x2
176	#define SYSC_CLOCKACTIVITY_FCLK 0x2	176	#define SYSC_CLOCKACTIVITY_FCLK 0x2
177		177
178	/* Errata definitions */	178	/* Errata definitions */
179	#define I2C_OMAP_ERRATA_I207 (1 << 0)	179	#define I2C_OMAP_ERRATA_I207 (1 << 0)
180	#define I2C_OMAP_ERRATA_I462 (1 << 1)	180	#define I2C_OMAP_ERRATA_I462 (1 << 1)
181		181
182	#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF	182	#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
183		183
184	struct omap_i2c_dev {	184	struct omap_i2c_dev {
185	spinlock_t lock; /* IRQ synchronization */	185	spinlock_t lock; /* IRQ synchronization */
186	struct device *dev;	186	struct device *dev;
187	void __iomem base; / virtual */	187	void __iomem base; / virtual */
188	int irq;	188	int irq;
189	int reg_shift; /* bit shift for I2C register addresses */	189	int reg_shift; /* bit shift for I2C register addresses */
190	struct completion cmd_complete;	190	struct completion cmd_complete;
191	struct resource *ioarea;	191	struct resource *ioarea;
192	u32 latency; /* maximum mpu wkup latency */	192	u32 latency; /* maximum mpu wkup latency */
193	void (set_mpu_wkup_lat)(struct device dev,	193	void (set_mpu_wkup_lat)(struct device dev,
194	long latency);	194	long latency);
195	u32 speed; /* Speed of bus in kHz */	195	u32 speed; /* Speed of bus in kHz */
196	u32 flags;	196	u32 flags;
197	u16 scheme;	197	u16 scheme;
198	u16 cmd_err;	198	u16 cmd_err;
199	u8 *buf;	199	u8 *buf;
200	u8 *regs;	200	u8 *regs;
201	size_t buf_len;	201	size_t buf_len;
202	struct i2c_adapter adapter;	202	struct i2c_adapter adapter;
203	u8 threshold;	203	u8 threshold;
204	u8 fifo_size; /* use as flag and value	204	u8 fifo_size; /* use as flag and value
205	* fifo_size==0 implies no fifo	205	* fifo_size==0 implies no fifo
206	* if set, should be trsh+1	206	* if set, should be trsh+1
207	*/	207	*/
208	u32 rev;	208	u32 rev;
209	unsigned b_hw:1; /* bad h/w fixes */	209	unsigned b_hw:1; /* bad h/w fixes */
210	unsigned receiver:1; /* true when we're in receiver mode */	210	unsigned receiver:1; /* true when we're in receiver mode */
211	u16 iestate; /* Saved interrupt register */	211	u16 iestate; /* Saved interrupt register */
212	u16 pscstate;	212	u16 pscstate;
213	u16 scllstate;	213	u16 scllstate;
214	u16 sclhstate;	214	u16 sclhstate;
215	u16 syscstate;	215	u16 syscstate;
216	u16 westate;	216	u16 westate;
217	u16 errata;	217	u16 errata;
218	};	218	};
219		219
220	static const u8 reg_map_ip_v1[] = {	220	static const u8 reg_map_ip_v1[] = {
221	[OMAP_I2C_REV_REG] = 0x00,	221	[OMAP_I2C_REV_REG] = 0x00,
222	[OMAP_I2C_IE_REG] = 0x01,	222	[OMAP_I2C_IE_REG] = 0x01,
223	[OMAP_I2C_STAT_REG] = 0x02,	223	[OMAP_I2C_STAT_REG] = 0x02,
224	[OMAP_I2C_IV_REG] = 0x03,	224	[OMAP_I2C_IV_REG] = 0x03,
225	[OMAP_I2C_WE_REG] = 0x03,	225	[OMAP_I2C_WE_REG] = 0x03,
226	[OMAP_I2C_SYSS_REG] = 0x04,	226	[OMAP_I2C_SYSS_REG] = 0x04,
227	[OMAP_I2C_BUF_REG] = 0x05,	227	[OMAP_I2C_BUF_REG] = 0x05,
228	[OMAP_I2C_CNT_REG] = 0x06,	228	[OMAP_I2C_CNT_REG] = 0x06,
229	[OMAP_I2C_DATA_REG] = 0x07,	229	[OMAP_I2C_DATA_REG] = 0x07,
230	[OMAP_I2C_SYSC_REG] = 0x08,	230	[OMAP_I2C_SYSC_REG] = 0x08,
231	[OMAP_I2C_CON_REG] = 0x09,	231	[OMAP_I2C_CON_REG] = 0x09,
232	[OMAP_I2C_OA_REG] = 0x0a,	232	[OMAP_I2C_OA_REG] = 0x0a,
233	[OMAP_I2C_SA_REG] = 0x0b,	233	[OMAP_I2C_SA_REG] = 0x0b,
234	[OMAP_I2C_PSC_REG] = 0x0c,	234	[OMAP_I2C_PSC_REG] = 0x0c,
235	[OMAP_I2C_SCLL_REG] = 0x0d,	235	[OMAP_I2C_SCLL_REG] = 0x0d,
236	[OMAP_I2C_SCLH_REG] = 0x0e,	236	[OMAP_I2C_SCLH_REG] = 0x0e,
237	[OMAP_I2C_SYSTEST_REG] = 0x0f,	237	[OMAP_I2C_SYSTEST_REG] = 0x0f,
238	[OMAP_I2C_BUFSTAT_REG] = 0x10,	238	[OMAP_I2C_BUFSTAT_REG] = 0x10,
239	};	239	};
240		240
241	static const u8 reg_map_ip_v2[] = {	241	static const u8 reg_map_ip_v2[] = {
242	[OMAP_I2C_REV_REG] = 0x04,	242	[OMAP_I2C_REV_REG] = 0x04,
243	[OMAP_I2C_IE_REG] = 0x2c,	243	[OMAP_I2C_IE_REG] = 0x2c,
244	[OMAP_I2C_STAT_REG] = 0x28,	244	[OMAP_I2C_STAT_REG] = 0x28,
245	[OMAP_I2C_IV_REG] = 0x34,	245	[OMAP_I2C_IV_REG] = 0x34,
246	[OMAP_I2C_WE_REG] = 0x34,	246	[OMAP_I2C_WE_REG] = 0x34,
247	[OMAP_I2C_SYSS_REG] = 0x90,	247	[OMAP_I2C_SYSS_REG] = 0x90,
248	[OMAP_I2C_BUF_REG] = 0x94,	248	[OMAP_I2C_BUF_REG] = 0x94,
249	[OMAP_I2C_CNT_REG] = 0x98,	249	[OMAP_I2C_CNT_REG] = 0x98,
250	[OMAP_I2C_DATA_REG] = 0x9c,	250	[OMAP_I2C_DATA_REG] = 0x9c,
251	[OMAP_I2C_SYSC_REG] = 0x10,	251	[OMAP_I2C_SYSC_REG] = 0x10,
252	[OMAP_I2C_CON_REG] = 0xa4,	252	[OMAP_I2C_CON_REG] = 0xa4,
253	[OMAP_I2C_OA_REG] = 0xa8,	253	[OMAP_I2C_OA_REG] = 0xa8,
254	[OMAP_I2C_SA_REG] = 0xac,	254	[OMAP_I2C_SA_REG] = 0xac,
255	[OMAP_I2C_PSC_REG] = 0xb0,	255	[OMAP_I2C_PSC_REG] = 0xb0,
256	[OMAP_I2C_SCLL_REG] = 0xb4,	256	[OMAP_I2C_SCLL_REG] = 0xb4,
257	[OMAP_I2C_SCLH_REG] = 0xb8,	257	[OMAP_I2C_SCLH_REG] = 0xb8,
258	[OMAP_I2C_SYSTEST_REG] = 0xbC,	258	[OMAP_I2C_SYSTEST_REG] = 0xbC,
259	[OMAP_I2C_BUFSTAT_REG] = 0xc0,	259	[OMAP_I2C_BUFSTAT_REG] = 0xc0,
260	[OMAP_I2C_IP_V2_REVNB_LO] = 0x00,	260	[OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
261	[OMAP_I2C_IP_V2_REVNB_HI] = 0x04,	261	[OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
262	[OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,	262	[OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
263	[OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,	263	[OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
264	[OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,	264	[OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
265	};	265	};
266		266
267	static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,	267	static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
268	int reg, u16 val)	268	int reg, u16 val)
269	{	269	{
270	__raw_writew(val, i2c_dev->base +	270	__raw_writew(val, i2c_dev->base +
271	(i2c_dev->regs[reg] << i2c_dev->reg_shift));	271	(i2c_dev->regs[reg] << i2c_dev->reg_shift));
272	}	272	}
273		273
274	static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)	274	static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
275	{	275	{
276	return __raw_readw(i2c_dev->base +	276	return __raw_readw(i2c_dev->base +
277	(i2c_dev->regs[reg] << i2c_dev->reg_shift));	277	(i2c_dev->regs[reg] << i2c_dev->reg_shift));
278	}	278	}
279		279
280	static void __omap_i2c_init(struct omap_i2c_dev *dev)	280	static void __omap_i2c_init(struct omap_i2c_dev *dev)
281	{	281	{
282		282
283	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);	283	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
284		284
285	/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */	285	/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
286	omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);	286	omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
287		287
288	/* SCL low and high time values */	288	/* SCL low and high time values */
289	omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);	289	omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
290	omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);	290	omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
291	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)	291	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
292	omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);	292	omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
293		293
294	/* Take the I2C module out of reset: */	294	/* Take the I2C module out of reset: */
295	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);	295	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
296		296
297	/*	297	/*
298	* Don't write to this register if the IE state is 0 as it can	298	* Don't write to this register if the IE state is 0 as it can
299	* cause deadlock.	299	* cause deadlock.
300	*/	300	*/
301	if (dev->iestate)	301	if (dev->iestate)
302	omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);	302	omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
303	}	303	}
304		304
305	static int omap_i2c_reset(struct omap_i2c_dev *dev)	305	static int omap_i2c_reset(struct omap_i2c_dev *dev)
306	{	306	{
307	unsigned long timeout;	307	unsigned long timeout;
308	u16 sysc;	308	u16 sysc;
309		309
310	if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {	310	if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
311	sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);	311	sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
312		312
313	/* Disable I2C controller before soft reset */	313	/* Disable I2C controller before soft reset */
314	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,	314	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
315	omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &	315	omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
316	~(OMAP_I2C_CON_EN));	316	~(OMAP_I2C_CON_EN));
317		317
318	omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);	318	omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
319	/* For some reason we need to set the EN bit before the	319	/* For some reason we need to set the EN bit before the
320	* reset done bit gets set. */	320	* reset done bit gets set. */
321	timeout = jiffies + OMAP_I2C_TIMEOUT;	321	timeout = jiffies + OMAP_I2C_TIMEOUT;
322	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);	322	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
323	while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &	323	while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
324	SYSS_RESETDONE_MASK)) {	324	SYSS_RESETDONE_MASK)) {
325	if (time_after(jiffies, timeout)) {	325	if (time_after(jiffies, timeout)) {
326	dev_warn(dev->dev, "timeout waiting "	326	dev_warn(dev->dev, "timeout waiting "
327	"for controller reset\n");	327	"for controller reset\n");
328	return -ETIMEDOUT;	328	return -ETIMEDOUT;
329	}	329	}
330	msleep(1);	330	msleep(1);
331	}	331	}
332		332
333	/* SYSC register is cleared by the reset; rewrite it */	333	/* SYSC register is cleared by the reset; rewrite it */
334	omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);	334	omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
335		335
336	}	336	}
337	return 0;	337	return 0;
338	}	338	}
339		339
340	static int omap_i2c_init(struct omap_i2c_dev *dev)	340	static int omap_i2c_init(struct omap_i2c_dev *dev)
341	{	341	{
342	u16 psc = 0, scll = 0, sclh = 0;	342	u16 psc = 0, scll = 0, sclh = 0;
343	u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;	343	u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
344	unsigned long fclk_rate = 12000000;	344	unsigned long fclk_rate = 12000000;
345	unsigned long internal_clk = 0;	345	unsigned long internal_clk = 0;
346	struct clk *fclk;	346	struct clk *fclk;
347		347
348	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {	348	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
349	/*	349	/*
350	* Enabling all wakup sources to stop I2C freezing on	350	* Enabling all wakup sources to stop I2C freezing on
351	* WFI instruction.	351	* WFI instruction.
352	* REVISIT: Some wkup sources might not be needed.	352	* REVISIT: Some wkup sources might not be needed.
353	*/	353	*/
354	dev->westate = OMAP_I2C_WE_ALL;	354	dev->westate = OMAP_I2C_WE_ALL;
355	}	355	}
356		356
357	if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {	357	if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
358	/*	358	/*
359	* The I2C functional clock is the armxor_ck, so there's	359	* The I2C functional clock is the armxor_ck, so there's
360	* no need to get "armxor_ck" separately. Now, if OMAP2420	360	* no need to get "armxor_ck" separately. Now, if OMAP2420
361	* always returns 12MHz for the functional clock, we can	361	* always returns 12MHz for the functional clock, we can
362	* do this bit unconditionally.	362	* do this bit unconditionally.
363	*/	363	*/
364	fclk = clk_get(dev->dev, "fck");	364	fclk = clk_get(dev->dev, "fck");
365	fclk_rate = clk_get_rate(fclk);	365	fclk_rate = clk_get_rate(fclk);
366	clk_put(fclk);	366	clk_put(fclk);
367		367
368	/* TRM for 5912 says the I2C clock must be prescaled to be	368	/* TRM for 5912 says the I2C clock must be prescaled to be
369	* between 7 - 12 MHz. The XOR input clock is typically	369	* between 7 - 12 MHz. The XOR input clock is typically
370	* 12, 13 or 19.2 MHz. So we should have code that produces:	370	* 12, 13 or 19.2 MHz. So we should have code that produces:
371	*	371	*
372	* XOR MHz Divider Prescaler	372	* XOR MHz Divider Prescaler
373	* 12 1 0	373	* 12 1 0
374	* 13 2 1	374	* 13 2 1
375	* 19.2 2 1	375	* 19.2 2 1
376	*/	376	*/
377	if (fclk_rate > 12000000)	377	if (fclk_rate > 12000000)
378	psc = fclk_rate / 12000000;	378	psc = fclk_rate / 12000000;
379	}	379	}
380		380
381	if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {	381	if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
382		382
383	/*	383	/*
384	* HSI2C controller internal clk rate should be 19.2 Mhz for	384	* HSI2C controller internal clk rate should be 19.2 Mhz for
385	* HS and for all modes on 2430. On 34xx we can use lower rate	385	* HS and for all modes on 2430. On 34xx we can use lower rate
386	* to get longer filter period for better noise suppression.	386	* to get longer filter period for better noise suppression.
387	* The filter is iclk (fclk for HS) period.	387	* The filter is iclk (fclk for HS) period.
388	*/	388	*/
389	if (dev->speed > 400 \|\|	389	if (dev->speed > 400 \|\|
390	dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)	390	dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
391	internal_clk = 19200;	391	internal_clk = 19200;
392	else if (dev->speed > 100)	392	else if (dev->speed > 100)
393	internal_clk = 9600;	393	internal_clk = 9600;
394	else	394	else
395	internal_clk = 4000;	395	internal_clk = 4000;
396	fclk = clk_get(dev->dev, "fck");	396	fclk = clk_get(dev->dev, "fck");
397	fclk_rate = clk_get_rate(fclk) / 1000;	397	fclk_rate = clk_get_rate(fclk) / 1000;
398	clk_put(fclk);	398	clk_put(fclk);
399		399
400	/* Compute prescaler divisor */	400	/* Compute prescaler divisor */
401	psc = fclk_rate / internal_clk;	401	psc = fclk_rate / internal_clk;
402	psc = psc - 1;	402	psc = psc - 1;
403		403
404	/* If configured for High Speed */	404	/* If configured for High Speed */
405	if (dev->speed > 400) {	405	if (dev->speed > 400) {
406	unsigned long scl;	406	unsigned long scl;
407		407
408	/* For first phase of HS mode */	408	/* For first phase of HS mode */
409	scl = internal_clk / 400;	409	scl = internal_clk / 400;
410	fsscll = scl - (scl / 3) - 7;	410	fsscll = scl - (scl / 3) - 7;
411	fssclh = (scl / 3) - 5;	411	fssclh = (scl / 3) - 5;
412		412
413	/* For second phase of HS mode */	413	/* For second phase of HS mode */
414	scl = fclk_rate / dev->speed;	414	scl = fclk_rate / dev->speed;
415	hsscll = scl - (scl / 3) - 7;	415	hsscll = scl - (scl / 3) - 7;
416	hssclh = (scl / 3) - 5;	416	hssclh = (scl / 3) - 5;
417	} else if (dev->speed > 100) {	417	} else if (dev->speed > 100) {
418	unsigned long scl;	418	unsigned long scl;
419		419
420	/* Fast mode */	420	/* Fast mode */
421	scl = internal_clk / dev->speed;	421	scl = internal_clk / dev->speed;
422	fsscll = scl - (scl / 3) - 7;	422	fsscll = scl - (scl / 3) - 7;
423	fssclh = (scl / 3) - 5;	423	fssclh = (scl / 3) - 5;
424	} else {	424	} else {
425	/* Standard mode */	425	/* Standard mode */
426	fsscll = internal_clk / (dev->speed * 2) - 7;	426	fsscll = internal_clk / (dev->speed * 2) - 7;
427	fssclh = internal_clk / (dev->speed * 2) - 5;	427	fssclh = internal_clk / (dev->speed * 2) - 5;
428	}	428	}
429	scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) \| fsscll;	429	scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) \| fsscll;
430	sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) \| fssclh;	430	sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) \| fssclh;
431	} else {	431	} else {
432	/* Program desired operating rate */	432	/* Program desired operating rate */
433	fclk_rate /= (psc + 1) * 1000;	433	fclk_rate /= (psc + 1) * 1000;
434	if (psc > 2)	434	if (psc > 2)
435	psc = 2;	435	psc = 2;
436	scll = fclk_rate / (dev->speed * 2) - 7 + psc;	436	scll = fclk_rate / (dev->speed * 2) - 7 + psc;
437	sclh = fclk_rate / (dev->speed * 2) - 7 + psc;	437	sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
438	}	438	}
439		439
440	dev->iestate = (OMAP_I2C_IE_XRDY \| OMAP_I2C_IE_RRDY \|	440	dev->iestate = (OMAP_I2C_IE_XRDY \| OMAP_I2C_IE_RRDY \|
441	OMAP_I2C_IE_ARDY \| OMAP_I2C_IE_NACK \|	441	OMAP_I2C_IE_ARDY \| OMAP_I2C_IE_NACK \|
442	OMAP_I2C_IE_AL) \| ((dev->fifo_size) ?	442	OMAP_I2C_IE_AL) \| ((dev->fifo_size) ?
443	(OMAP_I2C_IE_RDR \| OMAP_I2C_IE_XDR) : 0);	443	(OMAP_I2C_IE_RDR \| OMAP_I2C_IE_XDR) : 0);
444		444
445	dev->pscstate = psc;	445	dev->pscstate = psc;
446	dev->scllstate = scll;	446	dev->scllstate = scll;
447	dev->sclhstate = sclh;	447	dev->sclhstate = sclh;
448		448
449	__omap_i2c_init(dev);	449	__omap_i2c_init(dev);
450		450
451	return 0;	451	return 0;
452	}	452	}
453		453
454	/*	454	/*
455	* Waiting on Bus Busy	455	* Waiting on Bus Busy
456	*/	456	*/
457	static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)	457	static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
458	{	458	{
459	unsigned long timeout;	459	unsigned long timeout;
460		460
461	timeout = jiffies + OMAP_I2C_TIMEOUT;	461	timeout = jiffies + OMAP_I2C_TIMEOUT;
462	while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {	462	while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
463	if (time_after(jiffies, timeout)) {	463	if (time_after(jiffies, timeout)) {
464	dev_warn(dev->dev, "timeout waiting for bus ready\n");	464	dev_warn(dev->dev, "timeout waiting for bus ready\n");
465	return -ETIMEDOUT;	465	return -ETIMEDOUT;
466	}	466	}
467	msleep(1);	467	msleep(1);
468	}	468	}
469		469
470	return 0;	470	return 0;
471	}	471	}
472		472
473	static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)	473	static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
474	{	474	{
475	u16 buf;	475	u16 buf;
476		476
477	if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)	477	if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
478	return;	478	return;
479		479
480	/*	480	/*
481	* Set up notification threshold based on message size. We're doing	481	* Set up notification threshold based on message size. We're doing
482	* this to try and avoid draining feature as much as possible. Whenever	482	* this to try and avoid draining feature as much as possible. Whenever
483	* we have big messages to transfer (bigger than our total fifo size)	483	* we have big messages to transfer (bigger than our total fifo size)
484	* then we might use draining feature to transfer the remaining bytes.	484	* then we might use draining feature to transfer the remaining bytes.
485	*/	485	*/
486		486
487	dev->threshold = clamp(size, (u8) 1, dev->fifo_size);	487	dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
488		488
489	buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);	489	buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
490		490
491	if (is_rx) {	491	if (is_rx) {
492	/* Clear RX Threshold */	492	/* Clear RX Threshold */
493	buf &= ~(0x3f << 8);	493	buf &= ~(0x3f << 8);
494	buf \|= ((dev->threshold - 1) << 8) \| OMAP_I2C_BUF_RXFIF_CLR;	494	buf \|= ((dev->threshold - 1) << 8) \| OMAP_I2C_BUF_RXFIF_CLR;
495	} else {	495	} else {
496	/* Clear TX Threshold */	496	/* Clear TX Threshold */
497	buf &= ~0x3f;	497	buf &= ~0x3f;
498	buf \|= (dev->threshold - 1) \| OMAP_I2C_BUF_TXFIF_CLR;	498	buf \|= (dev->threshold - 1) \| OMAP_I2C_BUF_TXFIF_CLR;
499	}	499	}
500		500
501	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);	501	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
502		502
503	if (dev->rev < OMAP_I2C_REV_ON_3630)	503	if (dev->rev < OMAP_I2C_REV_ON_3630)
504	dev->b_hw = 1; /* Enable hardware fixes */	504	dev->b_hw = 1; /* Enable hardware fixes */
505		505
506	/* calculate wakeup latency constraint for MPU */	506	/* calculate wakeup latency constraint for MPU */
507	if (dev->set_mpu_wkup_lat != NULL)	507	if (dev->set_mpu_wkup_lat != NULL)
508	dev->latency = (1000000 * dev->threshold) /	508	dev->latency = (1000000 * dev->threshold) /
509	(1000 * dev->speed / 8);	509	(1000 * dev->speed / 8);
510	}	510	}
511		511
512	/*	512	/*
513	* Low level master read/write transaction.	513	* Low level master read/write transaction.
514	*/	514	*/
515	static int omap_i2c_xfer_msg(struct i2c_adapter *adap,	515	static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
516	struct i2c_msg *msg, int stop)	516	struct i2c_msg *msg, int stop)
517	{	517	{
518	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);	518	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
519	unsigned long timeout;	519	unsigned long timeout;
520	u16 w;	520	u16 w;
521		521
522	dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",	522	dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
523	msg->addr, msg->len, msg->flags, stop);	523	msg->addr, msg->len, msg->flags, stop);
524		524
525	if (msg->len == 0)	525	if (msg->len == 0)
526	return -EINVAL;	526	return -EINVAL;
527		527
528	dev->receiver = !!(msg->flags & I2C_M_RD);	528	dev->receiver = !!(msg->flags & I2C_M_RD);
529	omap_i2c_resize_fifo(dev, msg->len, dev->receiver);	529	omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
530		530
531	omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);	531	omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
532		532
533	/* REVISIT: Could the STB bit of I2C_CON be used with probing? */	533	/* REVISIT: Could the STB bit of I2C_CON be used with probing? */
534	dev->buf = msg->buf;	534	dev->buf = msg->buf;
535	dev->buf_len = msg->len;	535	dev->buf_len = msg->len;
536		536
537	/* make sure writes to dev->buf_len are ordered */	537	/* make sure writes to dev->buf_len are ordered */
538	barrier();	538	barrier();
539		539
540	omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);	540	omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
541		541
542	/* Clear the FIFO Buffers */	542	/* Clear the FIFO Buffers */
543	w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);	543	w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
544	w \|= OMAP_I2C_BUF_RXFIF_CLR \| OMAP_I2C_BUF_TXFIF_CLR;	544	w \|= OMAP_I2C_BUF_RXFIF_CLR \| OMAP_I2C_BUF_TXFIF_CLR;
545	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);	545	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
546		546
547	INIT_COMPLETION(dev->cmd_complete);	547	INIT_COMPLETION(dev->cmd_complete);
548	dev->cmd_err = 0;	548	dev->cmd_err = 0;
549		549
550	w = OMAP_I2C_CON_EN \| OMAP_I2C_CON_MST \| OMAP_I2C_CON_STT;	550	w = OMAP_I2C_CON_EN \| OMAP_I2C_CON_MST \| OMAP_I2C_CON_STT;
551		551
552	/* High speed configuration */	552	/* High speed configuration */
553	if (dev->speed > 400)	553	if (dev->speed > 400)
554	w \|= OMAP_I2C_CON_OPMODE_HS;	554	w \|= OMAP_I2C_CON_OPMODE_HS;
555		555
556	if (msg->flags & I2C_M_STOP)	556	if (msg->flags & I2C_M_STOP)
557	stop = 1;	557	stop = 1;
558	if (msg->flags & I2C_M_TEN)	558	if (msg->flags & I2C_M_TEN)
559	w \|= OMAP_I2C_CON_XA;	559	w \|= OMAP_I2C_CON_XA;
560	if (!(msg->flags & I2C_M_RD))	560	if (!(msg->flags & I2C_M_RD))
561	w \|= OMAP_I2C_CON_TRX;	561	w \|= OMAP_I2C_CON_TRX;
562		562
563	if (!dev->b_hw && stop)	563	if (!dev->b_hw && stop)
564	w \|= OMAP_I2C_CON_STP;	564	w \|= OMAP_I2C_CON_STP;
565		565
566	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);	566	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
567		567
568	/*	568	/*
569	* Don't write stt and stp together on some hardware.	569	* Don't write stt and stp together on some hardware.
570	*/	570	*/
571	if (dev->b_hw && stop) {	571	if (dev->b_hw && stop) {
572	unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;	572	unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
573	u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);	573	u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
574	while (con & OMAP_I2C_CON_STT) {	574	while (con & OMAP_I2C_CON_STT) {
575	con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);	575	con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
576		576
577	/* Let the user know if i2c is in a bad state */	577	/* Let the user know if i2c is in a bad state */
578	if (time_after(jiffies, delay)) {	578	if (time_after(jiffies, delay)) {
579	dev_err(dev->dev, "controller timed out "	579	dev_err(dev->dev, "controller timed out "
580	"waiting for start condition to finish\n");	580	"waiting for start condition to finish\n");
581	return -ETIMEDOUT;	581	return -ETIMEDOUT;
582	}	582	}
583	cpu_relax();	583	cpu_relax();
584	}	584	}
585		585
586	w \|= OMAP_I2C_CON_STP;	586	w \|= OMAP_I2C_CON_STP;
587	w &= ~OMAP_I2C_CON_STT;	587	w &= ~OMAP_I2C_CON_STT;
588	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);	588	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
589	}	589	}
590		590
591	/*	591	/*
592	* REVISIT: We should abort the transfer on signals, but the bus goes	592	* REVISIT: We should abort the transfer on signals, but the bus goes
593	* into arbitration and we're currently unable to recover from it.	593	* into arbitration and we're currently unable to recover from it.
594	*/	594	*/
595	timeout = wait_for_completion_timeout(&dev->cmd_complete,	595	timeout = wait_for_completion_timeout(&dev->cmd_complete,
596	OMAP_I2C_TIMEOUT);	596	OMAP_I2C_TIMEOUT);
597	if (timeout == 0) {	597	if (timeout == 0) {
598	dev_err(dev->dev, "controller timed out\n");	598	dev_err(dev->dev, "controller timed out\n");
599	omap_i2c_reset(dev);	599	omap_i2c_reset(dev);
600	__omap_i2c_init(dev);	600	__omap_i2c_init(dev);
601	return -ETIMEDOUT;	601	return -ETIMEDOUT;
602	}	602	}
603		603
604	if (likely(!dev->cmd_err))	604	if (likely(!dev->cmd_err))
605	return 0;	605	return 0;
606		606
607	/* We have an error */	607	/* We have an error */
608	if (dev->cmd_err & (OMAP_I2C_STAT_AL \| OMAP_I2C_STAT_ROVR \|	608	if (dev->cmd_err & (OMAP_I2C_STAT_AL \| OMAP_I2C_STAT_ROVR \|
609	OMAP_I2C_STAT_XUDF)) {	609	OMAP_I2C_STAT_XUDF)) {
610	omap_i2c_reset(dev);	610	omap_i2c_reset(dev);
611	__omap_i2c_init(dev);	611	__omap_i2c_init(dev);
612	return -EIO;	612	return -EIO;
613	}	613	}
614		614
615	if (dev->cmd_err & OMAP_I2C_STAT_NACK) {	615	if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
616	if (msg->flags & I2C_M_IGNORE_NAK)	616	if (msg->flags & I2C_M_IGNORE_NAK)
617	return 0;	617	return 0;
618	if (stop) {	618
619	w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);	619	w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
620	w \|= OMAP_I2C_CON_STP;	620	w \|= OMAP_I2C_CON_STP;
621	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);	621	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
622	}
623	return -EREMOTEIO;	622	return -EREMOTEIO;
624	}	623	}
625	return -EIO;	624	return -EIO;
626	}	625	}
627		626
628		627
629	/*	628	/*
630	* Prepare controller for a transaction and call omap_i2c_xfer_msg	629	* Prepare controller for a transaction and call omap_i2c_xfer_msg
631	* to do the work during IRQ processing.	630	* to do the work during IRQ processing.
632	*/	631	*/
633	static int	632	static int
634	omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)	633	omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
635	{	634	{
636	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);	635	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
637	int i;	636	int i;
638	int r;	637	int r;
639		638
640	r = pm_runtime_get_sync(dev->dev);	639	r = pm_runtime_get_sync(dev->dev);
641	if (IS_ERR_VALUE(r))	640	if (IS_ERR_VALUE(r))
642	goto out;	641	goto out;
643		642
644	r = omap_i2c_wait_for_bb(dev);	643	r = omap_i2c_wait_for_bb(dev);
645	if (r < 0)	644	if (r < 0)
646	goto out;	645	goto out;
647		646
648	if (dev->set_mpu_wkup_lat != NULL)	647	if (dev->set_mpu_wkup_lat != NULL)
649	dev->set_mpu_wkup_lat(dev->dev, dev->latency);	648	dev->set_mpu_wkup_lat(dev->dev, dev->latency);
650		649
651	for (i = 0; i < num; i++) {	650	for (i = 0; i < num; i++) {
652	r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));	651	r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
653	if (r != 0)	652	if (r != 0)
654	break;	653	break;
655	}	654	}
656		655
657	if (r == 0)	656	if (r == 0)
658	r = num;	657	r = num;
659		658
660	omap_i2c_wait_for_bb(dev);	659	omap_i2c_wait_for_bb(dev);
661		660
662	if (dev->set_mpu_wkup_lat != NULL)	661	if (dev->set_mpu_wkup_lat != NULL)
663	dev->set_mpu_wkup_lat(dev->dev, -1);	662	dev->set_mpu_wkup_lat(dev->dev, -1);
664		663
665	out:	664	out:
666	pm_runtime_mark_last_busy(dev->dev);	665	pm_runtime_mark_last_busy(dev->dev);
667	pm_runtime_put_autosuspend(dev->dev);	666	pm_runtime_put_autosuspend(dev->dev);
668	return r;	667	return r;
669	}	668	}
670		669
671	static u32	670	static u32
672	omap_i2c_func(struct i2c_adapter *adap)	671	omap_i2c_func(struct i2c_adapter *adap)
673	{	672	{
674	return I2C_FUNC_I2C \| (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) \|	673	return I2C_FUNC_I2C \| (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) \|
675	I2C_FUNC_PROTOCOL_MANGLING;	674	I2C_FUNC_PROTOCOL_MANGLING;
676	}	675	}
677		676
678	static inline void	677	static inline void
679	omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)	678	omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
680	{	679	{
681	dev->cmd_err \|= err;	680	dev->cmd_err \|= err;
682	complete(&dev->cmd_complete);	681	complete(&dev->cmd_complete);
683	}	682	}
684		683
685	static inline void	684	static inline void
686	omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)	685	omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
687	{	686	{
688	omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);	687	omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
689	}	688	}
690		689
691	static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)	690	static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
692	{	691	{
693	/*	692	/*
694	* I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)	693	* I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
695	* Not applicable for OMAP4.	694	* Not applicable for OMAP4.
696	* Under certain rare conditions, RDR could be set again	695	* Under certain rare conditions, RDR could be set again
697	* when the bus is busy, then ignore the interrupt and	696	* when the bus is busy, then ignore the interrupt and
698	* clear the interrupt.	697	* clear the interrupt.
699	*/	698	*/
700	if (stat & OMAP_I2C_STAT_RDR) {	699	if (stat & OMAP_I2C_STAT_RDR) {
701	/* Step 1: If RDR is set, clear it */	700	/* Step 1: If RDR is set, clear it */
702	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);	701	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
703		702
704	/* Step 2: */	703	/* Step 2: */
705	if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)	704	if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
706	& OMAP_I2C_STAT_BB)) {	705	& OMAP_I2C_STAT_BB)) {
707		706
708	/* Step 3: */	707	/* Step 3: */
709	if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)	708	if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
710	& OMAP_I2C_STAT_RDR) {	709	& OMAP_I2C_STAT_RDR) {
711	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);	710	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
712	dev_dbg(dev->dev, "RDR when bus is busy.\n");	711	dev_dbg(dev->dev, "RDR when bus is busy.\n");
713	}	712	}
714		713
715	}	714	}
716	}	715	}
717	}	716	}
718		717
719	/* rev1 devices are apparently only on some 15xx */	718	/* rev1 devices are apparently only on some 15xx */
720	#ifdef CONFIG_ARCH_OMAP15XX	719	#ifdef CONFIG_ARCH_OMAP15XX
721		720
722	static irqreturn_t	721	static irqreturn_t
723	omap_i2c_omap1_isr(int this_irq, void *dev_id)	722	omap_i2c_omap1_isr(int this_irq, void *dev_id)
724	{	723	{
725	struct omap_i2c_dev *dev = dev_id;	724	struct omap_i2c_dev *dev = dev_id;
726	u16 iv, w;	725	u16 iv, w;
727		726
728	if (pm_runtime_suspended(dev->dev))	727	if (pm_runtime_suspended(dev->dev))
729	return IRQ_NONE;	728	return IRQ_NONE;
730		729
731	iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);	730	iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
732	switch (iv) {	731	switch (iv) {
733	case 0x00: /* None */	732	case 0x00: /* None */
734	break;	733	break;
735	case 0x01: /* Arbitration lost */	734	case 0x01: /* Arbitration lost */
736	dev_err(dev->dev, "Arbitration lost\n");	735	dev_err(dev->dev, "Arbitration lost\n");
737	omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);	736	omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
738	break;	737	break;
739	case 0x02: /* No acknowledgement */	738	case 0x02: /* No acknowledgement */
740	omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);	739	omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
741	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);	740	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
742	break;	741	break;
743	case 0x03: /* Register access ready */	742	case 0x03: /* Register access ready */
744	omap_i2c_complete_cmd(dev, 0);	743	omap_i2c_complete_cmd(dev, 0);
745	break;	744	break;
746	case 0x04: /* Receive data ready */	745	case 0x04: /* Receive data ready */
747	if (dev->buf_len) {	746	if (dev->buf_len) {
748	w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);	747	w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
749	*dev->buf++ = w;	748	*dev->buf++ = w;
750	dev->buf_len--;	749	dev->buf_len--;
751	if (dev->buf_len) {	750	if (dev->buf_len) {
752	*dev->buf++ = w >> 8;	751	*dev->buf++ = w >> 8;
753	dev->buf_len--;	752	dev->buf_len--;
754	}	753	}
755	} else	754	} else
756	dev_err(dev->dev, "RRDY IRQ while no data requested\n");	755	dev_err(dev->dev, "RRDY IRQ while no data requested\n");
757	break;	756	break;
758	case 0x05: /* Transmit data ready */	757	case 0x05: /* Transmit data ready */
759	if (dev->buf_len) {	758	if (dev->buf_len) {
760	w = *dev->buf++;	759	w = *dev->buf++;
761	dev->buf_len--;	760	dev->buf_len--;
762	if (dev->buf_len) {	761	if (dev->buf_len) {
763	w \|= *dev->buf++ << 8;	762	w \|= *dev->buf++ << 8;
764	dev->buf_len--;	763	dev->buf_len--;
765	}	764	}
766	omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);	765	omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
767	} else	766	} else
768	dev_err(dev->dev, "XRDY IRQ while no data to send\n");	767	dev_err(dev->dev, "XRDY IRQ while no data to send\n");
769	break;	768	break;
770	default:	769	default:
771	return IRQ_NONE;	770	return IRQ_NONE;
772	}	771	}
773		772
774	return IRQ_HANDLED;	773	return IRQ_HANDLED;
775	}	774	}
776	#else	775	#else
777	#define omap_i2c_omap1_isr NULL	776	#define omap_i2c_omap1_isr NULL
778	#endif	777	#endif
779		778
780	/*	779	/*
781	* OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing	780	* OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
782	* data to DATA_REG. Otherwise some data bytes can be lost while transferring	781	* data to DATA_REG. Otherwise some data bytes can be lost while transferring
783	* them from the memory to the I2C interface.	782	* them from the memory to the I2C interface.
784	*/	783	*/
785	static int errata_omap3_i462(struct omap_i2c_dev *dev)	784	static int errata_omap3_i462(struct omap_i2c_dev *dev)
786	{	785	{
787	unsigned long timeout = 10000;	786	unsigned long timeout = 10000;
788	u16 stat;	787	u16 stat;
789		788
790	do {	789	do {
791	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);	790	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
792	if (stat & OMAP_I2C_STAT_XUDF)	791	if (stat & OMAP_I2C_STAT_XUDF)
793	break;	792	break;
794		793
795	if (stat & (OMAP_I2C_STAT_NACK \| OMAP_I2C_STAT_AL)) {	794	if (stat & (OMAP_I2C_STAT_NACK \| OMAP_I2C_STAT_AL)) {
796	omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY \|	795	omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY \|
797	OMAP_I2C_STAT_XDR));	796	OMAP_I2C_STAT_XDR));
798	if (stat & OMAP_I2C_STAT_NACK) {	797	if (stat & OMAP_I2C_STAT_NACK) {
799	dev->cmd_err \|= OMAP_I2C_STAT_NACK;	798	dev->cmd_err \|= OMAP_I2C_STAT_NACK;
800	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);	799	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
801	}	800	}
802		801
803	if (stat & OMAP_I2C_STAT_AL) {	802	if (stat & OMAP_I2C_STAT_AL) {
804	dev_err(dev->dev, "Arbitration lost\n");	803	dev_err(dev->dev, "Arbitration lost\n");
805	dev->cmd_err \|= OMAP_I2C_STAT_AL;	804	dev->cmd_err \|= OMAP_I2C_STAT_AL;
806	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);	805	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
807	}	806	}
808		807
809	return -EIO;	808	return -EIO;
810	}	809	}
811		810
812	cpu_relax();	811	cpu_relax();
813	} while (--timeout);	812	} while (--timeout);
814		813
815	if (!timeout) {	814	if (!timeout) {
816	dev_err(dev->dev, "timeout waiting on XUDF bit\n");	815	dev_err(dev->dev, "timeout waiting on XUDF bit\n");
817	return 0;	816	return 0;
818	}	817	}
819		818
820	return 0;	819	return 0;
821	}	820	}
822		821
823	static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,	822	static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
824	bool is_rdr)	823	bool is_rdr)
825	{	824	{
826	u16 w;	825	u16 w;
827		826
828	while (num_bytes--) {	827	while (num_bytes--) {
829	w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);	828	w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
830	*dev->buf++ = w;	829	*dev->buf++ = w;
831	dev->buf_len--;	830	dev->buf_len--;
832		831
833	/*	832	/*
834	* Data reg in 2430, omap3 and	833	* Data reg in 2430, omap3 and
835	* omap4 is 8 bit wide	834	* omap4 is 8 bit wide
836	*/	835	*/
837	if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {	836	if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
838	*dev->buf++ = w >> 8;	837	*dev->buf++ = w >> 8;
839	dev->buf_len--;	838	dev->buf_len--;
840	}	839	}
841	}	840	}
842	}	841	}
843		842
844	static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,	843	static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
845	bool is_xdr)	844	bool is_xdr)
846	{	845	{
847	u16 w;	846	u16 w;
848		847
849	while (num_bytes--) {	848	while (num_bytes--) {
850	w = *dev->buf++;	849	w = *dev->buf++;
851	dev->buf_len--;	850	dev->buf_len--;
852		851
853	/*	852	/*
854	* Data reg in 2430, omap3 and	853	* Data reg in 2430, omap3 and
855	* omap4 is 8 bit wide	854	* omap4 is 8 bit wide
856	*/	855	*/
857	if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {	856	if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
858	w \|= *dev->buf++ << 8;	857	w \|= *dev->buf++ << 8;
859	dev->buf_len--;	858	dev->buf_len--;
860	}	859	}
861		860
862	if (dev->errata & I2C_OMAP_ERRATA_I462) {	861	if (dev->errata & I2C_OMAP_ERRATA_I462) {
863	int ret;	862	int ret;
864		863
865	ret = errata_omap3_i462(dev);	864	ret = errata_omap3_i462(dev);
866	if (ret < 0)	865	if (ret < 0)
867	return ret;	866	return ret;
868	}	867	}
869		868
870	omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);	869	omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
871	}	870	}
872		871
873	return 0;	872	return 0;
874	}	873	}
875		874
876	static irqreturn_t	875	static irqreturn_t
877	omap_i2c_isr(int irq, void *dev_id)	876	omap_i2c_isr(int irq, void *dev_id)
878	{	877	{
879	struct omap_i2c_dev *dev = dev_id;	878	struct omap_i2c_dev *dev = dev_id;
880	irqreturn_t ret = IRQ_HANDLED;	879	irqreturn_t ret = IRQ_HANDLED;
881	u16 mask;	880	u16 mask;
882	u16 stat;	881	u16 stat;
883		882
884	spin_lock(&dev->lock);	883	spin_lock(&dev->lock);
885	mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);	884	mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
886	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);	885	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
887		886
888	if (stat & mask)	887	if (stat & mask)
889	ret = IRQ_WAKE_THREAD;	888	ret = IRQ_WAKE_THREAD;
890		889
891	spin_unlock(&dev->lock);	890	spin_unlock(&dev->lock);
892		891
893	return ret;	892	return ret;
894	}	893	}
895		894
896	static irqreturn_t	895	static irqreturn_t
897	omap_i2c_isr_thread(int this_irq, void *dev_id)	896	omap_i2c_isr_thread(int this_irq, void *dev_id)
898	{	897	{
899	struct omap_i2c_dev *dev = dev_id;	898	struct omap_i2c_dev *dev = dev_id;
900	unsigned long flags;	899	unsigned long flags;
901	u16 bits;	900	u16 bits;
902	u16 stat;	901	u16 stat;
903	int err = 0, count = 0;	902	int err = 0, count = 0;
904		903
905	spin_lock_irqsave(&dev->lock, flags);	904	spin_lock_irqsave(&dev->lock, flags);
906	do {	905	do {
907	bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);	906	bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
908	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);	907	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
909	stat &= bits;	908	stat &= bits;
910		909
911	/* If we're in receiver mode, ignore XDR/XRDY */	910	/* If we're in receiver mode, ignore XDR/XRDY */
912	if (dev->receiver)	911	if (dev->receiver)
913	stat &= ~(OMAP_I2C_STAT_XDR \| OMAP_I2C_STAT_XRDY);	912	stat &= ~(OMAP_I2C_STAT_XDR \| OMAP_I2C_STAT_XRDY);
914	else	913	else
915	stat &= ~(OMAP_I2C_STAT_RDR \| OMAP_I2C_STAT_RRDY);	914	stat &= ~(OMAP_I2C_STAT_RDR \| OMAP_I2C_STAT_RRDY);
916		915
917	if (!stat) {	916	if (!stat) {
918	/* my work here is done */	917	/* my work here is done */
919	goto out;	918	goto out;
920	}	919	}
921		920
922	dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);	921	dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
923	if (count++ == 100) {	922	if (count++ == 100) {
924	dev_warn(dev->dev, "Too much work in one IRQ\n");	923	dev_warn(dev->dev, "Too much work in one IRQ\n");
925	break;	924	break;
926	}	925	}
927		926
928	if (stat & OMAP_I2C_STAT_NACK) {	927	if (stat & OMAP_I2C_STAT_NACK) {
929	err \|= OMAP_I2C_STAT_NACK;	928	err \|= OMAP_I2C_STAT_NACK;
930	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);	929	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
931	break;	930	break;
932	}	931	}
933		932
934	if (stat & OMAP_I2C_STAT_AL) {	933	if (stat & OMAP_I2C_STAT_AL) {
935	dev_err(dev->dev, "Arbitration lost\n");	934	dev_err(dev->dev, "Arbitration lost\n");
936	err \|= OMAP_I2C_STAT_AL;	935	err \|= OMAP_I2C_STAT_AL;
937	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);	936	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
938	break;	937	break;
939	}	938	}
940		939
941	/*	940	/*
942	* ProDB0017052: Clear ARDY bit twice	941	* ProDB0017052: Clear ARDY bit twice
943	*/	942	*/
944	if (stat & (OMAP_I2C_STAT_ARDY \| OMAP_I2C_STAT_NACK \|	943	if (stat & (OMAP_I2C_STAT_ARDY \| OMAP_I2C_STAT_NACK \|
945	OMAP_I2C_STAT_AL)) {	944	OMAP_I2C_STAT_AL)) {
946	omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY \|	945	omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY \|
947	OMAP_I2C_STAT_RDR \|	946	OMAP_I2C_STAT_RDR \|
948	OMAP_I2C_STAT_XRDY \|	947	OMAP_I2C_STAT_XRDY \|
949	OMAP_I2C_STAT_XDR \|	948	OMAP_I2C_STAT_XDR \|
950	OMAP_I2C_STAT_ARDY));	949	OMAP_I2C_STAT_ARDY));
951	break;	950	break;
952	}	951	}
953		952
954	if (stat & OMAP_I2C_STAT_RDR) {	953	if (stat & OMAP_I2C_STAT_RDR) {
955	u8 num_bytes = 1;	954	u8 num_bytes = 1;
956		955
957	if (dev->fifo_size)	956	if (dev->fifo_size)
958	num_bytes = dev->buf_len;	957	num_bytes = dev->buf_len;
959		958
960	omap_i2c_receive_data(dev, num_bytes, true);	959	omap_i2c_receive_data(dev, num_bytes, true);
961		960
962	if (dev->errata & I2C_OMAP_ERRATA_I207)	961	if (dev->errata & I2C_OMAP_ERRATA_I207)
963	i2c_omap_errata_i207(dev, stat);	962	i2c_omap_errata_i207(dev, stat);
964		963
965	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);	964	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
966	continue;	965	continue;
967	}	966	}
968		967
969	if (stat & OMAP_I2C_STAT_RRDY) {	968	if (stat & OMAP_I2C_STAT_RRDY) {
970	u8 num_bytes = 1;	969	u8 num_bytes = 1;
971		970
972	if (dev->threshold)	971	if (dev->threshold)
973	num_bytes = dev->threshold;	972	num_bytes = dev->threshold;
974		973
975	omap_i2c_receive_data(dev, num_bytes, false);	974	omap_i2c_receive_data(dev, num_bytes, false);
976	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);	975	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
977	continue;	976	continue;
978	}	977	}
979		978
980	if (stat & OMAP_I2C_STAT_XDR) {	979	if (stat & OMAP_I2C_STAT_XDR) {
981	u8 num_bytes = 1;	980	u8 num_bytes = 1;
982	int ret;	981	int ret;
983		982
984	if (dev->fifo_size)	983	if (dev->fifo_size)
985	num_bytes = dev->buf_len;	984	num_bytes = dev->buf_len;
986		985
987	ret = omap_i2c_transmit_data(dev, num_bytes, true);	986	ret = omap_i2c_transmit_data(dev, num_bytes, true);
988	if (ret < 0)	987	if (ret < 0)
989	break;	988	break;
990		989
991	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);	990	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
992	continue;	991	continue;
993	}	992	}
994		993
995	if (stat & OMAP_I2C_STAT_XRDY) {	994	if (stat & OMAP_I2C_STAT_XRDY) {
996	u8 num_bytes = 1;	995	u8 num_bytes = 1;
997	int ret;	996	int ret;
998		997
999	if (dev->threshold)	998	if (dev->threshold)
1000	num_bytes = dev->threshold;	999	num_bytes = dev->threshold;
1001		1000
1002	ret = omap_i2c_transmit_data(dev, num_bytes, false);	1001	ret = omap_i2c_transmit_data(dev, num_bytes, false);
1003	if (ret < 0)	1002	if (ret < 0)
1004	break;	1003	break;
1005		1004
1006	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);	1005	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
1007	continue;	1006	continue;
1008	}	1007	}
1009		1008
1010	if (stat & OMAP_I2C_STAT_ROVR) {	1009	if (stat & OMAP_I2C_STAT_ROVR) {
1011	dev_err(dev->dev, "Receive overrun\n");	1010	dev_err(dev->dev, "Receive overrun\n");
1012	err \|= OMAP_I2C_STAT_ROVR;	1011	err \|= OMAP_I2C_STAT_ROVR;
1013	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);	1012	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
1014	break;	1013	break;
1015	}	1014	}
1016		1015
1017	if (stat & OMAP_I2C_STAT_XUDF) {	1016	if (stat & OMAP_I2C_STAT_XUDF) {
1018	dev_err(dev->dev, "Transmit underflow\n");	1017	dev_err(dev->dev, "Transmit underflow\n");
1019	err \|= OMAP_I2C_STAT_XUDF;	1018	err \|= OMAP_I2C_STAT_XUDF;
1020	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);	1019	omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
1021	break;	1020	break;
1022	}	1021	}
1023	} while (stat);	1022	} while (stat);
1024		1023
1025	omap_i2c_complete_cmd(dev, err);	1024	omap_i2c_complete_cmd(dev, err);
1026		1025
1027	out:	1026	out:
1028	spin_unlock_irqrestore(&dev->lock, flags);	1027	spin_unlock_irqrestore(&dev->lock, flags);
1029		1028
1030	return IRQ_HANDLED;	1029	return IRQ_HANDLED;
1031	}	1030	}
1032		1031
1033	static const struct i2c_algorithm omap_i2c_algo = {	1032	static const struct i2c_algorithm omap_i2c_algo = {
1034	.master_xfer = omap_i2c_xfer,	1033	.master_xfer = omap_i2c_xfer,
1035	.functionality = omap_i2c_func,	1034	.functionality = omap_i2c_func,
1036	};	1035	};
1037		1036
1038	#ifdef CONFIG_OF	1037	#ifdef CONFIG_OF
1039	static struct omap_i2c_bus_platform_data omap3_pdata = {	1038	static struct omap_i2c_bus_platform_data omap3_pdata = {
1040	.rev = OMAP_I2C_IP_VERSION_1,	1039	.rev = OMAP_I2C_IP_VERSION_1,
1041	.flags = OMAP_I2C_FLAG_BUS_SHIFT_2,	1040	.flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1042	};	1041	};
1043		1042
1044	static struct omap_i2c_bus_platform_data omap4_pdata = {	1043	static struct omap_i2c_bus_platform_data omap4_pdata = {
1045	.rev = OMAP_I2C_IP_VERSION_2,	1044	.rev = OMAP_I2C_IP_VERSION_2,
1046	};	1045	};
1047		1046
1048	static const struct of_device_id omap_i2c_of_match[] = {	1047	static const struct of_device_id omap_i2c_of_match[] = {
1049	{	1048	{
1050	.compatible = "ti,omap4-i2c",	1049	.compatible = "ti,omap4-i2c",
1051	.data = &omap4_pdata,	1050	.data = &omap4_pdata,
1052	},	1051	},
1053	{	1052	{
1054	.compatible = "ti,omap3-i2c",	1053	.compatible = "ti,omap3-i2c",
1055	.data = &omap3_pdata,	1054	.data = &omap3_pdata,
1056	},	1055	},
1057	{ },	1056	{ },
1058	};	1057	};
1059	MODULE_DEVICE_TABLE(of, omap_i2c_of_match);	1058	MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1060	#endif	1059	#endif
1061		1060
1062	#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)	1061	#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1063		1062
1064	#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)	1063	#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1065	#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)	1064	#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1066		1065
1067	#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)	1066	#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1068	#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)	1067	#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1069	#define OMAP_I2C_SCHEME_0 0	1068	#define OMAP_I2C_SCHEME_0 0
1070	#define OMAP_I2C_SCHEME_1 1	1069	#define OMAP_I2C_SCHEME_1 1
1071		1070
1072	static int	1071	static int
1073	omap_i2c_probe(struct platform_device *pdev)	1072	omap_i2c_probe(struct platform_device *pdev)
1074	{	1073	{
1075	struct omap_i2c_dev *dev;	1074	struct omap_i2c_dev *dev;
1076	struct i2c_adapter *adap;	1075	struct i2c_adapter *adap;
1077	struct resource *mem;	1076	struct resource *mem;
1078	const struct omap_i2c_bus_platform_data *pdata =	1077	const struct omap_i2c_bus_platform_data *pdata =
1079	pdev->dev.platform_data;	1078	pdev->dev.platform_data;
1080	struct device_node *node = pdev->dev.of_node;	1079	struct device_node *node = pdev->dev.of_node;
1081	const struct of_device_id *match;	1080	const struct of_device_id *match;
1082	int irq;	1081	int irq;
1083	int r;	1082	int r;
1084	u32 rev;	1083	u32 rev;
1085	u16 minor, major;	1084	u16 minor, major;
1086		1085
1087	irq = platform_get_irq(pdev, 0);	1086	irq = platform_get_irq(pdev, 0);
1088	if (irq < 0) {	1087	if (irq < 0) {
1089	dev_err(&pdev->dev, "no irq resource?\n");	1088	dev_err(&pdev->dev, "no irq resource?\n");
1090	return irq;	1089	return irq;
1091	}	1090	}
1092		1091
1093	dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);	1092	dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1094	if (!dev) {	1093	if (!dev) {
1095	dev_err(&pdev->dev, "Menory allocation failed\n");	1094	dev_err(&pdev->dev, "Menory allocation failed\n");
1096	return -ENOMEM;	1095	return -ENOMEM;
1097	}	1096	}
1098		1097
1099	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);	1098	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1100	dev->base = devm_ioremap_resource(&pdev->dev, mem);	1099	dev->base = devm_ioremap_resource(&pdev->dev, mem);
1101	if (IS_ERR(dev->base))	1100	if (IS_ERR(dev->base))
1102	return PTR_ERR(dev->base);	1101	return PTR_ERR(dev->base);
1103		1102
1104	match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);	1103	match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1105	if (match) {	1104	if (match) {
1106	u32 freq = 100000; /* default to 100000 Hz */	1105	u32 freq = 100000; /* default to 100000 Hz */
1107		1106
1108	pdata = match->data;	1107	pdata = match->data;
1109	dev->flags = pdata->flags;	1108	dev->flags = pdata->flags;
1110		1109
1111	of_property_read_u32(node, "clock-frequency", &freq);	1110	of_property_read_u32(node, "clock-frequency", &freq);
1112	/* convert DT freq value in Hz into kHz for speed */	1111	/* convert DT freq value in Hz into kHz for speed */
1113	dev->speed = freq / 1000;	1112	dev->speed = freq / 1000;
1114	} else if (pdata != NULL) {	1113	} else if (pdata != NULL) {
1115	dev->speed = pdata->clkrate;	1114	dev->speed = pdata->clkrate;
1116	dev->flags = pdata->flags;	1115	dev->flags = pdata->flags;
1117	dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;	1116	dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1118	}	1117	}
1119		1118
1120	dev->dev = &pdev->dev;	1119	dev->dev = &pdev->dev;
1121	dev->irq = irq;	1120	dev->irq = irq;
1122		1121
1123	spin_lock_init(&dev->lock);	1122	spin_lock_init(&dev->lock);
1124		1123
1125	platform_set_drvdata(pdev, dev);	1124	platform_set_drvdata(pdev, dev);
1126	init_completion(&dev->cmd_complete);	1125	init_completion(&dev->cmd_complete);
1127		1126
1128	dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;	1127	dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1129		1128
1130	pm_runtime_enable(dev->dev);	1129	pm_runtime_enable(dev->dev);
1131	pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);	1130	pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1132	pm_runtime_use_autosuspend(dev->dev);	1131	pm_runtime_use_autosuspend(dev->dev);
1133		1132
1134	r = pm_runtime_get_sync(dev->dev);	1133	r = pm_runtime_get_sync(dev->dev);
1135	if (IS_ERR_VALUE(r))	1134	if (IS_ERR_VALUE(r))
1136	goto err_free_mem;	1135	goto err_free_mem;
1137		1136
1138	/*	1137	/*
1139	* Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.	1138	* Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1140	* On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.	1139	* On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1141	* Also since the omap_i2c_read_reg uses reg_map_ip_* a	1140	* Also since the omap_i2c_read_reg uses reg_map_ip_* a
1142	* raw_readw is done.	1141	* raw_readw is done.
1143	*/	1142	*/
1144	rev = __raw_readw(dev->base + 0x04);	1143	rev = __raw_readw(dev->base + 0x04);
1145		1144
1146	dev->scheme = OMAP_I2C_SCHEME(rev);	1145	dev->scheme = OMAP_I2C_SCHEME(rev);
1147	switch (dev->scheme) {	1146	switch (dev->scheme) {
1148	case OMAP_I2C_SCHEME_0:	1147	case OMAP_I2C_SCHEME_0:
1149	dev->regs = (u8 *)reg_map_ip_v1;	1148	dev->regs = (u8 *)reg_map_ip_v1;
1150	dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);	1149	dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1151	minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);	1150	minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1152	major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);	1151	major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1153	break;	1152	break;
1154	case OMAP_I2C_SCHEME_1:	1153	case OMAP_I2C_SCHEME_1:
1155	/* FALLTHROUGH */	1154	/* FALLTHROUGH */
1156	default:	1155	default:
1157	dev->regs = (u8 *)reg_map_ip_v2;	1156	dev->regs = (u8 *)reg_map_ip_v2;
1158	rev = (rev << 16) \|	1157	rev = (rev << 16) \|
1159	omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);	1158	omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1160	minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);	1159	minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1161	major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);	1160	major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1162	dev->rev = rev;	1161	dev->rev = rev;
1163	}	1162	}
1164		1163
1165	dev->errata = 0;	1164	dev->errata = 0;
1166		1165
1167	if (dev->rev >= OMAP_I2C_REV_ON_2430 &&	1166	if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1168	dev->rev < OMAP_I2C_REV_ON_4430_PLUS)	1167	dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
1169	dev->errata \|= I2C_OMAP_ERRATA_I207;	1168	dev->errata \|= I2C_OMAP_ERRATA_I207;
1170		1169
1171	if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)	1170	if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
1172	dev->errata \|= I2C_OMAP_ERRATA_I462;	1171	dev->errata \|= I2C_OMAP_ERRATA_I462;
1173		1172
1174	if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {	1173	if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1175	u16 s;	1174	u16 s;
1176		1175
1177	/* Set up the fifo size - Get total size */	1176	/* Set up the fifo size - Get total size */
1178	s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;	1177	s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1179	dev->fifo_size = 0x8 << s;	1178	dev->fifo_size = 0x8 << s;
1180		1179
1181	/*	1180	/*
1182	* Set up notification threshold as half the total available	1181	* Set up notification threshold as half the total available
1183	* size. This is to ensure that we can handle the status on int	1182	* size. This is to ensure that we can handle the status on int
1184	* call back latencies.	1183	* call back latencies.
1185	*/	1184	*/
1186		1185
1187	dev->fifo_size = (dev->fifo_size / 2);	1186	dev->fifo_size = (dev->fifo_size / 2);
1188		1187
1189	if (dev->rev < OMAP_I2C_REV_ON_3630)	1188	if (dev->rev < OMAP_I2C_REV_ON_3630)
1190	dev->b_hw = 1; /* Enable hardware fixes */	1189	dev->b_hw = 1; /* Enable hardware fixes */
1191		1190
1192	/* calculate wakeup latency constraint for MPU */	1191	/* calculate wakeup latency constraint for MPU */
1193	if (dev->set_mpu_wkup_lat != NULL)	1192	if (dev->set_mpu_wkup_lat != NULL)
1194	dev->latency = (1000000 * dev->fifo_size) /	1193	dev->latency = (1000000 * dev->fifo_size) /
1195	(1000 * dev->speed / 8);	1194	(1000 * dev->speed / 8);
1196	}	1195	}
1197		1196
1198	/* reset ASAP, clearing any IRQs */	1197	/* reset ASAP, clearing any IRQs */
1199	omap_i2c_init(dev);	1198	omap_i2c_init(dev);
1200		1199
1201	if (dev->rev < OMAP_I2C_OMAP1_REV_2)	1200	if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1202	r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,	1201	r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1203	IRQF_NO_SUSPEND, pdev->name, dev);	1202	IRQF_NO_SUSPEND, pdev->name, dev);
1204	else	1203	else
1205	r = devm_request_threaded_irq(&pdev->dev, dev->irq,	1204	r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1206	omap_i2c_isr, omap_i2c_isr_thread,	1205	omap_i2c_isr, omap_i2c_isr_thread,
1207	IRQF_NO_SUSPEND \| IRQF_ONESHOT,	1206	IRQF_NO_SUSPEND \| IRQF_ONESHOT,
1208	pdev->name, dev);	1207	pdev->name, dev);
1209		1208
1210	if (r) {	1209	if (r) {
1211	dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);	1210	dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1212	goto err_unuse_clocks;	1211	goto err_unuse_clocks;
1213	}	1212	}
1214		1213
1215	adap = &dev->adapter;	1214	adap = &dev->adapter;
1216	i2c_set_adapdata(adap, dev);	1215	i2c_set_adapdata(adap, dev);
1217	adap->owner = THIS_MODULE;	1216	adap->owner = THIS_MODULE;
1218	adap->class = I2C_CLASS_HWMON;	1217	adap->class = I2C_CLASS_HWMON;
1219	strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));	1218	strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1220	adap->algo = &omap_i2c_algo;	1219	adap->algo = &omap_i2c_algo;
1221	adap->dev.parent = &pdev->dev;	1220	adap->dev.parent = &pdev->dev;
1222	adap->dev.of_node = pdev->dev.of_node;	1221	adap->dev.of_node = pdev->dev.of_node;
1223		1222
1224	/* i2c device drivers may be active on return from add_adapter() */	1223	/* i2c device drivers may be active on return from add_adapter() */
1225	adap->nr = pdev->id;	1224	adap->nr = pdev->id;
1226	r = i2c_add_numbered_adapter(adap);	1225	r = i2c_add_numbered_adapter(adap);
1227	if (r) {	1226	if (r) {
1228	dev_err(dev->dev, "failure adding adapter\n");	1227	dev_err(dev->dev, "failure adding adapter\n");
1229	goto err_unuse_clocks;	1228	goto err_unuse_clocks;
1230	}	1229	}
1231		1230
1232	dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,	1231	dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1233	major, minor, dev->speed);	1232	major, minor, dev->speed);
1234		1233
1235	of_i2c_register_devices(adap);	1234	of_i2c_register_devices(adap);
1236		1235
1237	pm_runtime_mark_last_busy(dev->dev);	1236	pm_runtime_mark_last_busy(dev->dev);
1238	pm_runtime_put_autosuspend(dev->dev);	1237	pm_runtime_put_autosuspend(dev->dev);
1239		1238
1240	return 0;	1239	return 0;
1241		1240
1242	err_unuse_clocks:	1241	err_unuse_clocks:
1243	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);	1242	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1244	pm_runtime_put(dev->dev);	1243	pm_runtime_put(dev->dev);
1245	pm_runtime_disable(&pdev->dev);	1244	pm_runtime_disable(&pdev->dev);
1246	err_free_mem:	1245	err_free_mem:
1247		1246
1248	return r;	1247	return r;
1249	}	1248	}
1250		1249
1251	static int omap_i2c_remove(struct platform_device *pdev)	1250	static int omap_i2c_remove(struct platform_device *pdev)
1252	{	1251	{
1253	struct omap_i2c_dev *dev = platform_get_drvdata(pdev);	1252	struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1254	int ret;	1253	int ret;
1255		1254
1256	i2c_del_adapter(&dev->adapter);	1255	i2c_del_adapter(&dev->adapter);
1257	ret = pm_runtime_get_sync(&pdev->dev);	1256	ret = pm_runtime_get_sync(&pdev->dev);
1258	if (IS_ERR_VALUE(ret))	1257	if (IS_ERR_VALUE(ret))
1259	return ret;	1258	return ret;
1260		1259
1261	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);	1260	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1262	pm_runtime_put(&pdev->dev);	1261	pm_runtime_put(&pdev->dev);
1263	pm_runtime_disable(&pdev->dev);	1262	pm_runtime_disable(&pdev->dev);
1264	return 0;	1263	return 0;
1265	}	1264	}
1266		1265
1267	#ifdef CONFIG_PM	1266	#ifdef CONFIG_PM
1268	#ifdef CONFIG_PM_RUNTIME	1267	#ifdef CONFIG_PM_RUNTIME
1269	static int omap_i2c_runtime_suspend(struct device *dev)	1268	static int omap_i2c_runtime_suspend(struct device *dev)
1270	{	1269	{
1271	struct platform_device *pdev = to_platform_device(dev);	1270	struct platform_device *pdev = to_platform_device(dev);
1272	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);	1271	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1273		1272
1274	_dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);	1273	_dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
1275		1274
1276	if (_dev->scheme == OMAP_I2C_SCHEME_0)	1275	if (_dev->scheme == OMAP_I2C_SCHEME_0)
1277	omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);	1276	omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1278	else	1277	else
1279	omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,	1278	omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1280	OMAP_I2C_IP_V2_INTERRUPTS_MASK);	1279	OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1281		1280
1282	if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {	1281	if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1283	omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */	1282	omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1284	} else {	1283	} else {
1285	omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);	1284	omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1286		1285
1287	/* Flush posted write */	1286	/* Flush posted write */
1288	omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);	1287	omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1289	}	1288	}
1290		1289
1291	return 0;	1290	return 0;
1292	}	1291	}
1293		1292
1294	static int omap_i2c_runtime_resume(struct device *dev)	1293	static int omap_i2c_runtime_resume(struct device *dev)
1295	{	1294	{
1296	struct platform_device *pdev = to_platform_device(dev);	1295	struct platform_device *pdev = to_platform_device(dev);
1297	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);	1296	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1298		1297
1299	if (!_dev->regs)	1298	if (!_dev->regs)
1300	return 0;	1299	return 0;
1301		1300
1302	__omap_i2c_init(_dev);	1301	__omap_i2c_init(_dev);
1303		1302
1304	return 0;	1303	return 0;
1305	}	1304	}
1306	#endif /* CONFIG_PM_RUNTIME */	1305	#endif /* CONFIG_PM_RUNTIME */
1307		1306
1308	static struct dev_pm_ops omap_i2c_pm_ops = {	1307	static struct dev_pm_ops omap_i2c_pm_ops = {
1309	SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,	1308	SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1310	omap_i2c_runtime_resume, NULL)	1309	omap_i2c_runtime_resume, NULL)
1311	};	1310	};
1312	#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)	1311	#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1313	#else	1312	#else
1314	#define OMAP_I2C_PM_OPS NULL	1313	#define OMAP_I2C_PM_OPS NULL
1315	#endif /* CONFIG_PM */	1314	#endif /* CONFIG_PM */
1316		1315
1317	static struct platform_driver omap_i2c_driver = {	1316	static struct platform_driver omap_i2c_driver = {
1318	.probe = omap_i2c_probe,	1317	.probe = omap_i2c_probe,
1319	.remove = omap_i2c_remove,	1318	.remove = omap_i2c_remove,
1320	.driver = {	1319	.driver = {
1321	.name = "omap_i2c",	1320	.name = "omap_i2c",
1322	.owner = THIS_MODULE,	1321	.owner = THIS_MODULE,
1323	.pm = OMAP_I2C_PM_OPS,	1322	.pm = OMAP_I2C_PM_OPS,
1324	.of_match_table = of_match_ptr(omap_i2c_of_match),	1323	.of_match_table = of_match_ptr(omap_i2c_of_match),
1325	},	1324	},
1326	};	1325	};
1327		1326
1328	/* I2C may be needed to bring up other drivers */	1327	/* I2C may be needed to bring up other drivers */
1329	static int __init	1328	static int __init
1330	omap_i2c_init_driver(void)	1329	omap_i2c_init_driver(void)
1331	{	1330	{
1332	return platform_driver_register(&omap_i2c_driver);	1331	return platform_driver_register(&omap_i2c_driver);
1333	}	1332	}
1334	subsys_initcall(omap_i2c_init_driver);	1333	subsys_initcall(omap_i2c_init_driver);
1335		1334
1336	static void __exit omap_i2c_exit_driver(void)	1335	static void __exit omap_i2c_exit_driver(void)
1337	{	1336	{
1338	platform_driver_unregister(&omap_i2c_driver);	1337	platform_driver_unregister(&omap_i2c_driver);
1339	}	1338	}
1340	module_exit(omap_i2c_exit_driver);	1339	module_exit(omap_i2c_exit_driver);
1341		1340
1342	MODULE_AUTHOR("MontaVista Software, Inc. (and others)");	1341	MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1343	MODULE_DESCRIPTION("TI OMAP I2C bus adapter");	1342	MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1344	MODULE_LICENSE("GPL");	1343	MODULE_LICENSE("GPL");
1345	MODULE_ALIAS("platform:omap_i2c");	1344	MODULE_ALIAS("platform:omap_i2c");
1346		1345

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