Eric Lee / smarc-ti-linux-kernel

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Commit d4ef9dd33d0f513777409710fd99e016d46c3a85

Authored by Ralf Baechle
1 parent fbd0ed37c8
Exists in master and in 20 other branches dlt-processor-sdk-linux-03.00.00.04, newt-ti-linux-3.12.y, processor-sdk-linux-01.00.00, processor-sdk-linux-02.00.01, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y, smarc-ti-linux-3.14.y, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.12.y, ti-linux-3.14.y, ti-linux-3.15.y, ti-lsk-linux-4.1.y

[MIPS] PCI: Set need_domain_info if controller domain index is non-zero. 

This fixes this little funny:

bigsur:/proc/bus/pci# ls -l
total 0
dr-xr-xr-x    2 root     root            0 Aug 28 19:31 00
dr-xr-xr-x    2 root     root            0 Aug 28 19:31 00
dr-xr-xr-x    2 root     root            0 Aug 28 19:31 01
dr-xr-xr-x    2 root     root            0 Aug 28 19:31 03
-r--r--r--    1 root     root            0 Aug 28 19:31 devices

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 1 changed file with 1 additions and 0 deletions Inline Diff

1 /* 1 /*
2 * This program is free software; you can redistribute it and/or modify it 2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the 3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your 4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version. 5 * option) any later version.
6 * 6 *
7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
8 */ 8 */
9 #include <linux/kernel.h> 9 #include <linux/kernel.h>
10 #include <linux/mm.h> 10 #include <linux/mm.h>
11 #include <linux/bootmem.h> 11 #include <linux/bootmem.h>
12 #include <linux/init.h> 12 #include <linux/init.h>
13 #include <linux/types.h> 13 #include <linux/types.h>
14 #include <linux/pci.h> 14 #include <linux/pci.h>
15 15
16 /* 16 /*
17 * Indicate whether we respect the PCI setup left by the firmware. 17 * Indicate whether we respect the PCI setup left by the firmware.
18 * 18 *
19 * Make this long-lived so that we know when shutting down 19 * Make this long-lived so that we know when shutting down
20 * whether we probed only or not. 20 * whether we probed only or not.
21 */ 21 */
22 int pci_probe_only; 22 int pci_probe_only;
23 23
24 #define PCI_ASSIGN_ALL_BUSSES 1 24 #define PCI_ASSIGN_ALL_BUSSES 1
25 25
26 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; 26 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
27 27
28 /* 28 /*
29 * The PCI controller list. 29 * The PCI controller list.
30 */ 30 */
31 31
32 struct pci_controller *hose_head, **hose_tail = &hose_head; 32 struct pci_controller *hose_head, **hose_tail = &hose_head;
33 struct pci_controller *pci_isa_hose; 33 struct pci_controller *pci_isa_hose;
34 34
35 unsigned long PCIBIOS_MIN_IO = 0x0000; 35 unsigned long PCIBIOS_MIN_IO = 0x0000;
36 unsigned long PCIBIOS_MIN_MEM = 0; 36 unsigned long PCIBIOS_MIN_MEM = 0;
37 37
38 /* 38 /*
39 * We need to avoid collisions with `mirrored' VGA ports 39 * We need to avoid collisions with `mirrored' VGA ports
40 * and other strange ISA hardware, so we always want the 40 * and other strange ISA hardware, so we always want the
41 * addresses to be allocated in the 0x000-0x0ff region 41 * addresses to be allocated in the 0x000-0x0ff region
42 * modulo 0x400. 42 * modulo 0x400.
43 * 43 *
44 * Why? Because some silly external IO cards only decode 44 * Why? Because some silly external IO cards only decode
45 * the low 10 bits of the IO address. The 0x00-0xff region 45 * the low 10 bits of the IO address. The 0x00-0xff region
46 * is reserved for motherboard devices that decode all 16 46 * is reserved for motherboard devices that decode all 16
47 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 47 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
48 * but we want to try to avoid allocating at 0x2900-0x2bff 48 * but we want to try to avoid allocating at 0x2900-0x2bff
49 * which might have be mirrored at 0x0100-0x03ff.. 49 * which might have be mirrored at 0x0100-0x03ff..
50 */ 50 */
51 void 51 void
52 pcibios_align_resource(void *data, struct resource *res, 52 pcibios_align_resource(void *data, struct resource *res,
53 resource_size_t size, resource_size_t align) 53 resource_size_t size, resource_size_t align)
54 { 54 {
55 struct pci_dev *dev = data; 55 struct pci_dev *dev = data;
56 struct pci_controller *hose = dev->sysdata; 56 struct pci_controller *hose = dev->sysdata;
57 resource_size_t start = res->start; 57 resource_size_t start = res->start;
58 58
59 if (res->flags & IORESOURCE_IO) { 59 if (res->flags & IORESOURCE_IO) {
60 /* Make sure we start at our min on all hoses */ 60 /* Make sure we start at our min on all hoses */
61 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 61 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
62 start = PCIBIOS_MIN_IO + hose->io_resource->start; 62 start = PCIBIOS_MIN_IO + hose->io_resource->start;
63 63
64 /* 64 /*
65 * Put everything into 0x00-0xff region modulo 0x400 65 * Put everything into 0x00-0xff region modulo 0x400
66 */ 66 */
67 if (start & 0x300) 67 if (start & 0x300)
68 start = (start + 0x3ff) & ~0x3ff; 68 start = (start + 0x3ff) & ~0x3ff;
69 } else if (res->flags & IORESOURCE_MEM) { 69 } else if (res->flags & IORESOURCE_MEM) {
70 /* Make sure we start at our min on all hoses */ 70 /* Make sure we start at our min on all hoses */
71 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 71 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
72 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 72 start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
73 } 73 }
74 74
75 res->start = start; 75 res->start = start;
76 } 76 }
77 77
78 void __devinit register_pci_controller(struct pci_controller *hose) 78 void __devinit register_pci_controller(struct pci_controller *hose)
79 { 79 {
80 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 80 if (request_resource(&iomem_resource, hose->mem_resource) < 0)
81 goto out; 81 goto out;
82 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 82 if (request_resource(&ioport_resource, hose->io_resource) < 0) {
83 release_resource(hose->mem_resource); 83 release_resource(hose->mem_resource);
84 goto out; 84 goto out;
85 } 85 }
86 86
87 *hose_tail = hose; 87 *hose_tail = hose;
88 hose_tail = &hose->next; 88 hose_tail = &hose->next;
89 89
90 /* 90 /*
91 * Do not panic here but later - this might hapen before console init. 91 * Do not panic here but later - this might hapen before console init.
92 */ 92 */
93 if (!hose->io_map_base) { 93 if (!hose->io_map_base) {
94 printk(KERN_WARNING 94 printk(KERN_WARNING
95 "registering PCI controller with io_map_base unset\n"); 95 "registering PCI controller with io_map_base unset\n");
96 } 96 }
97 return; 97 return;
98 98
99 out: 99 out:
100 printk(KERN_WARNING 100 printk(KERN_WARNING
101 "Skipping PCI bus scan due to resource conflict\n"); 101 "Skipping PCI bus scan due to resource conflict\n");
102 } 102 }
103 103
104 /* Most MIPS systems have straight-forward swizzling needs. */ 104 /* Most MIPS systems have straight-forward swizzling needs. */
105 105
106 static inline u8 bridge_swizzle(u8 pin, u8 slot) 106 static inline u8 bridge_swizzle(u8 pin, u8 slot)
107 { 107 {
108 return (((pin - 1) + slot) % 4) + 1; 108 return (((pin - 1) + slot) % 4) + 1;
109 } 109 }
110 110
111 static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp) 111 static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
112 { 112 {
113 u8 pin = *pinp; 113 u8 pin = *pinp;
114 114
115 while (dev->bus->parent) { 115 while (dev->bus->parent) {
116 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); 116 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
117 /* Move up the chain of bridges. */ 117 /* Move up the chain of bridges. */
118 dev = dev->bus->self; 118 dev = dev->bus->self;
119 } 119 }
120 *pinp = pin; 120 *pinp = pin;
121 121
122 /* The slot is the slot of the last bridge. */ 122 /* The slot is the slot of the last bridge. */
123 return PCI_SLOT(dev->devfn); 123 return PCI_SLOT(dev->devfn);
124 } 124 }
125 125
126 static int __init pcibios_init(void) 126 static int __init pcibios_init(void)
127 { 127 {
128 struct pci_controller *hose; 128 struct pci_controller *hose;
129 struct pci_bus *bus; 129 struct pci_bus *bus;
130 int next_busno; 130 int next_busno;
131 int need_domain_info = 0; 131 int need_domain_info = 0;
132 132
133 /* Scan all of the recorded PCI controllers. */ 133 /* Scan all of the recorded PCI controllers. */
134 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { 134 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
135 135
136 if (!hose->iommu) 136 if (!hose->iommu)
137 PCI_DMA_BUS_IS_PHYS = 1; 137 PCI_DMA_BUS_IS_PHYS = 1;
138 138
139 if (hose->get_busno && pci_probe_only) 139 if (hose->get_busno && pci_probe_only)
140 next_busno = (*hose->get_busno)(); 140 next_busno = (*hose->get_busno)();
141 141
142 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 142 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
143 hose->bus = bus; 143 hose->bus = bus;
144 need_domain_info = need_domain_info || hose->index;
144 hose->need_domain_info = need_domain_info; 145 hose->need_domain_info = need_domain_info;
145 if (bus) { 146 if (bus) {
146 next_busno = bus->subordinate + 1; 147 next_busno = bus->subordinate + 1;
147 /* Don't allow 8-bit bus number overflow inside the hose - 148 /* Don't allow 8-bit bus number overflow inside the hose -
148 reserve some space for bridges. */ 149 reserve some space for bridges. */
149 if (next_busno > 224) { 150 if (next_busno > 224) {
150 next_busno = 0; 151 next_busno = 0;
151 need_domain_info = 1; 152 need_domain_info = 1;
152 } 153 }
153 } 154 }
154 } 155 }
155 156
156 if (!pci_probe_only) 157 if (!pci_probe_only)
157 pci_assign_unassigned_resources(); 158 pci_assign_unassigned_resources();
158 pci_fixup_irqs(common_swizzle, pcibios_map_irq); 159 pci_fixup_irqs(common_swizzle, pcibios_map_irq);
159 160
160 return 0; 161 return 0;
161 } 162 }
162 163
163 subsys_initcall(pcibios_init); 164 subsys_initcall(pcibios_init);
164 165
165 static int pcibios_enable_resources(struct pci_dev *dev, int mask) 166 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
166 { 167 {
167 u16 cmd, old_cmd; 168 u16 cmd, old_cmd;
168 int idx; 169 int idx;
169 struct resource *r; 170 struct resource *r;
170 171
171 pci_read_config_word(dev, PCI_COMMAND, &cmd); 172 pci_read_config_word(dev, PCI_COMMAND, &cmd);
172 old_cmd = cmd; 173 old_cmd = cmd;
173 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 174 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
174 /* Only set up the requested stuff */ 175 /* Only set up the requested stuff */
175 if (!(mask & (1<<idx))) 176 if (!(mask & (1<<idx)))
176 continue; 177 continue;
177 178
178 r = &dev->resource[idx]; 179 r = &dev->resource[idx];
179 if (!r->start && r->end) { 180 if (!r->start && r->end) {
180 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); 181 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
181 return -EINVAL; 182 return -EINVAL;
182 } 183 }
183 if (r->flags & IORESOURCE_IO) 184 if (r->flags & IORESOURCE_IO)
184 cmd |= PCI_COMMAND_IO; 185 cmd |= PCI_COMMAND_IO;
185 if (r->flags & IORESOURCE_MEM) 186 if (r->flags & IORESOURCE_MEM)
186 cmd |= PCI_COMMAND_MEMORY; 187 cmd |= PCI_COMMAND_MEMORY;
187 } 188 }
188 if (dev->resource[PCI_ROM_RESOURCE].start) 189 if (dev->resource[PCI_ROM_RESOURCE].start)
189 cmd |= PCI_COMMAND_MEMORY; 190 cmd |= PCI_COMMAND_MEMORY;
190 if (cmd != old_cmd) { 191 if (cmd != old_cmd) {
191 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); 192 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
192 pci_write_config_word(dev, PCI_COMMAND, cmd); 193 pci_write_config_word(dev, PCI_COMMAND, cmd);
193 } 194 }
194 return 0; 195 return 0;
195 } 196 }
196 197
197 /* 198 /*
198 * If we set up a device for bus mastering, we need to check the latency 199 * If we set up a device for bus mastering, we need to check the latency
199 * timer as certain crappy BIOSes forget to set it properly. 200 * timer as certain crappy BIOSes forget to set it properly.
200 */ 201 */
201 unsigned int pcibios_max_latency = 255; 202 unsigned int pcibios_max_latency = 255;
202 203
203 void pcibios_set_master(struct pci_dev *dev) 204 void pcibios_set_master(struct pci_dev *dev)
204 { 205 {
205 u8 lat; 206 u8 lat;
206 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 207 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
207 if (lat < 16) 208 if (lat < 16)
208 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 209 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
209 else if (lat > pcibios_max_latency) 210 else if (lat > pcibios_max_latency)
210 lat = pcibios_max_latency; 211 lat = pcibios_max_latency;
211 else 212 else
212 return; 213 return;
213 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", 214 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
214 pci_name(dev), lat); 215 pci_name(dev), lat);
215 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 216 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
216 } 217 }
217 218
218 unsigned int pcibios_assign_all_busses(void) 219 unsigned int pcibios_assign_all_busses(void)
219 { 220 {
220 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; 221 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
221 } 222 }
222 223
223 int pcibios_enable_device(struct pci_dev *dev, int mask) 224 int pcibios_enable_device(struct pci_dev *dev, int mask)
224 { 225 {
225 int err; 226 int err;
226 227
227 if ((err = pcibios_enable_resources(dev, mask)) < 0) 228 if ((err = pcibios_enable_resources(dev, mask)) < 0)
228 return err; 229 return err;
229 230
230 return pcibios_plat_dev_init(dev); 231 return pcibios_plat_dev_init(dev);
231 } 232 }
232 233
233 static void pcibios_fixup_device_resources(struct pci_dev *dev, 234 static void pcibios_fixup_device_resources(struct pci_dev *dev,
234 struct pci_bus *bus) 235 struct pci_bus *bus)
235 { 236 {
236 /* Update device resources. */ 237 /* Update device resources. */
237 struct pci_controller *hose = (struct pci_controller *)bus->sysdata; 238 struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
238 unsigned long offset = 0; 239 unsigned long offset = 0;
239 int i; 240 int i;
240 241
241 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 242 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
242 if (!dev->resource[i].start) 243 if (!dev->resource[i].start)
243 continue; 244 continue;
244 if (dev->resource[i].flags & IORESOURCE_IO) 245 if (dev->resource[i].flags & IORESOURCE_IO)
245 offset = hose->io_offset; 246 offset = hose->io_offset;
246 else if (dev->resource[i].flags & IORESOURCE_MEM) 247 else if (dev->resource[i].flags & IORESOURCE_MEM)
247 offset = hose->mem_offset; 248 offset = hose->mem_offset;
248 249
249 dev->resource[i].start += offset; 250 dev->resource[i].start += offset;
250 dev->resource[i].end += offset; 251 dev->resource[i].end += offset;
251 } 252 }
252 } 253 }
253 254
254 void pcibios_fixup_bus(struct pci_bus *bus) 255 void pcibios_fixup_bus(struct pci_bus *bus)
255 { 256 {
256 /* Propagate hose info into the subordinate devices. */ 257 /* Propagate hose info into the subordinate devices. */
257 258
258 struct pci_controller *hose = bus->sysdata; 259 struct pci_controller *hose = bus->sysdata;
259 struct list_head *ln; 260 struct list_head *ln;
260 struct pci_dev *dev = bus->self; 261 struct pci_dev *dev = bus->self;
261 262
262 if (!dev) { 263 if (!dev) {
263 bus->resource[0] = hose->io_resource; 264 bus->resource[0] = hose->io_resource;
264 bus->resource[1] = hose->mem_resource; 265 bus->resource[1] = hose->mem_resource;
265 } else if (pci_probe_only && 266 } else if (pci_probe_only &&
266 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 267 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
267 pci_read_bridge_bases(bus); 268 pci_read_bridge_bases(bus);
268 pcibios_fixup_device_resources(dev, bus); 269 pcibios_fixup_device_resources(dev, bus);
269 } 270 }
270 271
271 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 272 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
272 dev = pci_dev_b(ln); 273 dev = pci_dev_b(ln);
273 274
274 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 275 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
275 pcibios_fixup_device_resources(dev, bus); 276 pcibios_fixup_device_resources(dev, bus);
276 } 277 }
277 } 278 }
278 279
279 void __init 280 void __init
280 pcibios_update_irq(struct pci_dev *dev, int irq) 281 pcibios_update_irq(struct pci_dev *dev, int irq)
281 { 282 {
282 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 283 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
283 } 284 }
284 285
285 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 286 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
286 struct resource *res) 287 struct resource *res)
287 { 288 {
288 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 289 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
289 unsigned long offset = 0; 290 unsigned long offset = 0;
290 291
291 if (res->flags & IORESOURCE_IO) 292 if (res->flags & IORESOURCE_IO)
292 offset = hose->io_offset; 293 offset = hose->io_offset;
293 else if (res->flags & IORESOURCE_MEM) 294 else if (res->flags & IORESOURCE_MEM)
294 offset = hose->mem_offset; 295 offset = hose->mem_offset;
295 296
296 region->start = res->start - offset; 297 region->start = res->start - offset;
297 region->end = res->end - offset; 298 region->end = res->end - offset;
298 } 299 }
299 300
300 void __devinit 301 void __devinit
301 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 302 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
302 struct pci_bus_region *region) 303 struct pci_bus_region *region)
303 { 304 {
304 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 305 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
305 unsigned long offset = 0; 306 unsigned long offset = 0;
306 307
307 if (res->flags & IORESOURCE_IO) 308 if (res->flags & IORESOURCE_IO)
308 offset = hose->io_offset; 309 offset = hose->io_offset;
309 else if (res->flags & IORESOURCE_MEM) 310 else if (res->flags & IORESOURCE_MEM)
310 offset = hose->mem_offset; 311 offset = hose->mem_offset;
311 312
312 res->start = region->start + offset; 313 res->start = region->start + offset;
313 res->end = region->end + offset; 314 res->end = region->end + offset;
314 } 315 }
315 316
316 #ifdef CONFIG_HOTPLUG 317 #ifdef CONFIG_HOTPLUG
317 EXPORT_SYMBOL(pcibios_resource_to_bus); 318 EXPORT_SYMBOL(pcibios_resource_to_bus);
318 EXPORT_SYMBOL(pcibios_bus_to_resource); 319 EXPORT_SYMBOL(pcibios_bus_to_resource);
319 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 320 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
320 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 321 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
321 #endif 322 #endif
322 323
323 char *pcibios_setup(char *str) 324 char *pcibios_setup(char *str)
324 { 325 {
325 return str; 326 return str;
326 } 327 }
327 328