Eric Lee / smarc-ti-linux-kernel

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Commit dfc0a9d3a24cdccf7a07ec74712419089558d770

Authored by Eric Lee
1 parent 087edfb40a
Exists in smarc-ti-linux-3.12.10

Add LCD panel pixel clock polarity parameter in device tree

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arch/arm/boot/dts/am335x-smarc-common.dtsi
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1 /* 1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9 /* state the resources this carrier uses for audio function*/ 9 /* state the resources this carrier uses for audio function*/
10 /* the pin header uses for Audio*/ 10 /* the pin header uses for Audio*/
11 /* 11 /*
12 "S.39", mcasp1: mcasp0_fsr.mcasp1_fsx mode3 12 "S.39", mcasp1: mcasp0_fsr.mcasp1_fsx mode3
13 "S.40", mcasp1: mcasp0_axr1.mcasp1_axr0 mode3 13 "S.40", mcasp1: mcasp0_axr1.mcasp1_axr0 mode3
14 "S.41", mcasp1: mcasp0_ahclkx.mcasp1_axr1 mode3 14 "S.41", mcasp1: mcasp0_ahclkx.mcasp1_axr1 mode3
15 "S.42", mcasp1: mcasp0_aclkr.mcasp1_aclkx mode3 15 "S.42", mcasp1: mcasp0_aclkr.mcasp1_aclkx mode3
16 */ 16 */
17 /* the pin header uses for SPI1*/ 17 /* the pin header uses for SPI1*/
18 /* 18 /*
19 "P.54", spi1: mcasp0_ahclkr.spi1_cs0n mode3 19 "P.54", spi1: mcasp0_ahclkr.spi1_cs0n mode3
20 "P.55", spi1: xdma_event_intro0.spi1_cs1n mode4 20 "P.55", spi1: xdma_event_intro0.spi1_cs1n mode4
21 "P.56", spi1: mcasp0_aclkx.spi1_sclk mode3 21 "P.56", spi1: mcasp0_aclkx.spi1_sclk mode3
22 "P.57", spi1: mcasp0_fsx.spi1_d0 mode3 22 "P.57", spi1: mcasp0_fsx.spi1_d0 mode3
23 "P.58", spi1: mcasp0_axr0.spi1_d1 mode3 23 "P.58", spi1: mcasp0_axr0.spi1_d1 mode3
24 */ 24 */
25 /* the pin header uses for LCD*/ 25 /* the pin header uses for LCD*/
26 /* 26 /*
27 "S.114", lcd: lcd_data0.lcd_data0 mode0 27 "S.114", lcd: lcd_data0.lcd_data0 mode0
28 "S.115", lcd: lcd_data1.lcd_data1 mode0 28 "S.115", lcd: lcd_data1.lcd_data1 mode0
29 "S.116", lcd: lcd_data2.lcd_data2 mode0 29 "S.116", lcd: lcd_data2.lcd_data2 mode0
30 "S.117", lcd: lcd_data3.lcd_data3 mode0 30 "S.117", lcd: lcd_data3.lcd_data3 mode0
31 "S.118", lcd: lcd_data4.lcd_data4 mode0 31 "S.118", lcd: lcd_data4.lcd_data4 mode0
32 "S.104", lcd: lcd_data5.lcd_data5 mode0 32 "S.104", lcd: lcd_data5.lcd_data5 mode0
33 "S.105", lcd: lcd_data6.lcd_data6 mode0 33 "S.105", lcd: lcd_data6.lcd_data6 mode0
34 "S.106", lcd: lcd_data7.lcd_data7 mode0 34 "S.106", lcd: lcd_data7.lcd_data7 mode0
35 "S.107", lcd: lcd_data8.lcd_data8 mode0 35 "S.107", lcd: lcd_data8.lcd_data8 mode0
36 "S.108", lcd: lcd_data9.lcd_data9 mode0 36 "S.108", lcd: lcd_data9.lcd_data9 mode0
37 "S.109", lcd: lcd_data10.lcd_data10 mode0 37 "S.109", lcd: lcd_data10.lcd_data10 mode0
38 "S.96", lcd: lcd_data11.lcd_data11 mode0 38 "S.96", lcd: lcd_data11.lcd_data11 mode0
39 "S.97", lcd: lcd_data12.lcd_data12 mode0 39 "S.97", lcd: lcd_data12.lcd_data12 mode0
40 "S.98", lcd: lcd_data13.lcd_data13 mode0 40 "S.98", lcd: lcd_data13.lcd_data13 mode0
41 "S.99", lcd: lcd_data14.lcd_data14 mode0 41 "S.99", lcd: lcd_data14.lcd_data14 mode0
42 "S.100", lcd: lcd_data15.lcd_data15 mode0 42 "S.100", lcd: lcd_data15.lcd_data15 mode0
43 "S.113", lcd: lcd_data16.gpmc_ad15 mode0 43 "S.113", lcd: lcd_data16.gpmc_ad15 mode0
44 "S.95", lcd: lcd_data17.gpmc_ad14 mode0 44 "S.95", lcd: lcd_data17.gpmc_ad14 mode0
45 "S.112", lcd: lcd_data18.gpmc_ad13 mode0 45 "S.112", lcd: lcd_data18.gpmc_ad13 mode0
46 "S.103", lcd: lcd_data19.gpmc_ad12 mode0 46 "S.103", lcd: lcd_data19.gpmc_ad12 mode0
47 "S.94", lcd: lcd_data20.gpmc_ad11 mode0 47 "S.94", lcd: lcd_data20.gpmc_ad11 mode0
48 "S.111", lcd: lcd_data21.gpmc_ad10 mode0 48 "S.111", lcd: lcd_data21.gpmc_ad10 mode0
49 "S.102", lcd: lcd_data22.gpmc_ad9 mode0 49 "S.102", lcd: lcd_data22.gpmc_ad9 mode0
50 "S.93", lcd: lcd_data23.gpmc_ad8 mode0 50 "S.93", lcd: lcd_data23.gpmc_ad8 mode0
51 "S.121", lcd: lcd_vsync.lcd_vsync mode0 51 "S.121", lcd: lcd_vsync.lcd_vsync mode0
52 "S.122", lcd: lcd_hsync.lcd_hsync mode0 52 "S.122", lcd: lcd_hsync.lcd_hsync mode0
53 "S.123", lcd: lcd_pclk.lcd_pclk mode0 53 "S.123", lcd: lcd_pclk.lcd_pclk mode0
54 "S.120", lcd_de: lcd_ac_bias_en.lcd_ac_bias_en mode0 54 "S.120", lcd_de: lcd_ac_bias_en.lcd_ac_bias_en mode0
55 "S.133", lcd_vdd_en: gpmc_a7.gpio1_23 mode7 55 "S.133", lcd_vdd_en: gpmc_a7.gpio1_23 mode7
56 "S.127", lcd_bklt_en: gpmc_a6.gpio1_22 mode7 56 "S.127", lcd_bklt_en: gpmc_a6.gpio1_22 mode7
57 ` */ 57 ` */
58 /* the pin header uses for DCAN0*/ 58 /* the pin header uses for DCAN0*/
59 /* 59 /*
60 "P.143", dcan0_tx: gmii1_txd3.dcan0_tx mode1 60 "P.143", dcan0_tx: gmii1_txd3.dcan0_tx mode1
61 "P.144", dcan0_rx: gmii1_txd2.dcan0_rx mode1 61 "P.144", dcan0_rx: gmii1_txd2.dcan0_rx mode1
62 */ 62 */
63 /* the hardware ip uses */ 63 /* the hardware ip uses */
64 /* 64 /*
65 "mcasp1", 65 "mcasp1",
66 "i2c0", 66 "i2c0",
67 "i2c1", 67 "i2c1",
68 "i2c2", 68 "i2c2",
69 "uart0", 69 "uart0",
70 "uart2", 70 "uart2",
71 "uart3", 71 "uart3",
72 "touch", 72 "touch",
73 "mmc0/SD", 73 "mmc0/SD",
74 "emmc", 74 "emmc",
75 "ecap0/backlight", 75 "ecap0/backlight",
76 "emac0", 76 "emac0",
77 "emac1", 77 "emac1",
78 "gpio1_22", 78 "gpio1_22",
79 "gpio1_23", 79 "gpio1_23",
80 "gpio1_19", 80 "gpio1_19",
81 "lcd", 81 "lcd",
82 "dcan0", 82 "dcan0",
83 "spi0", 83 "spi0",
84 "spi1"; 84 "spi1";
85 */ 85 */
86 86
87 / { 87 / {
88 model = "TI AM335x SMARCT335X"; 88 model = "TI AM335x SMARCT335X";
89 compatible = "ti,am335x-smarct335x", "ti,am33xx"; 89 compatible = "ti,am335x-smarct335x", "ti,am33xx";
90 90
91 cpus { 91 cpus {
92 cpu@0 { 92 cpu@0 {
93 cpu0-supply = <&dcdc2_reg>; 93 cpu0-supply = <&dcdc2_reg>;
94 /* 94 /*
95 * To consider voltage drop between PMIC and SoC, 95 * To consider voltage drop between PMIC and SoC,
96 * tolerance value is reduced to 2% from 4% and 96 * tolerance value is reduced to 2% from 4% and
97 * voltage value is increased as a precaution. 97 * voltage value is increased as a precaution.
98 */ 98 */
99 operating-points = < 99 operating-points = <
100 /* kHz uV */ 100 /* kHz uV */
101 1000000 1325000 101 1000000 1325000
102 800000 1300000 102 800000 1300000
103 600000 1112000 103 600000 1112000
104 300000 969000 104 300000 969000
105 >; 105 >;
106 compatible = "arm,cortex-a8"; 106 compatible = "arm,cortex-a8";
107 voltage-tolerance = <0x2>; 107 voltage-tolerance = <0x2>;
108 clock-latency = <0x493e0>; 108 clock-latency = <0x493e0>;
109 cpu0-supply = <0x2>; 109 cpu0-supply = <0x2>;
110 }; 110 };
111 }; 111 };
112 112
113 memory { 113 memory {
114 device_type = "memory"; 114 device_type = "memory";
115 reg = <0x80000000 0x20000000>; /* 512 MB */ 115 reg = <0x80000000 0x20000000>; /* 512 MB */
116 }; 116 };
117 117
118 am33xx_pinmux: pinmux@44e10800 { 118 am33xx_pinmux: pinmux@44e10800 {
119 pinctrl-names = "default"; 119 pinctrl-names = "default";
120 pinctrl-0 = <&clkout2_pin &gpio_pins_default>; 120 pinctrl-0 = <&clkout2_pin &gpio_pins_default>;
121 121
122 i2c0_pins: pinmux_i2c0_pins { 122 i2c0_pins: pinmux_i2c0_pins {
123 pinctrl-single,pins = < 123 pinctrl-single,pins = <
124 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 124 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
125 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 125 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
126 >; 126 >;
127 }; 127 };
128 128
129 i2c1_pins: pinmux_i2c1_pins { 129 i2c1_pins: pinmux_i2c1_pins {
130 pinctrl-single,pins = < 130 pinctrl-single,pins = <
131 0x180 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rxd.i2c1_sda */ 131 0x180 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rxd.i2c1_sda */
132 0x184 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_txd.i2c1_scl */ 132 0x184 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_txd.i2c1_scl */
133 >; 133 >;
134 }; 134 };
135 135
136 i2c2_pins: pinmux_i2c2_pins { 136 i2c2_pins: pinmux_i2c2_pins {
137 pinctrl-single,pins = < 137 pinctrl-single,pins = <
138 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ 138 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
139 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ 139 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
140 >; 140 >;
141 }; 141 };
142 142
143 uart0_pins: pinmux_uart0_pins { 143 uart0_pins: pinmux_uart0_pins {
144 pinctrl-single,pins = < 144 pinctrl-single,pins = <
145 0x168 (PIN_INPUT_PULLUP | MUX_MODE6) /* uart0_ctsn.uart0_ctsn */ 145 0x168 (PIN_INPUT_PULLUP | MUX_MODE6) /* uart0_ctsn.uart0_ctsn */
146 0x16c (PIN_OUTPUT | MUX_MODE6) /* uart0_rtsn.uart0_rtsn */ 146 0x16c (PIN_OUTPUT | MUX_MODE6) /* uart0_rtsn.uart0_rtsn */
147 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 147 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
148 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 148 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
149 >; 149 >;
150 }; 150 };
151 151
152 uart2_pins: pinmux_uart2_pins { 152 uart2_pins: pinmux_uart2_pins {
153 pinctrl-single,pins = < 153 pinctrl-single,pins = <
154 0x12c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_txclk.uart2_rxd */ 154 0x12c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_txclk.uart2_rxd */
155 0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxclk.uart2_txd */ 155 0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxclk.uart2_txd */
156 >; 156 >;
157 }; 157 };
158 158
159 uart3_pins: pinmux_uart3_pins { 159 uart3_pins: pinmux_uart3_pins {
160 pinctrl-single,pins = < 160 pinctrl-single,pins = <
161 0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */ 161 0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */
162 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */ 162 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */
163 >; 163 >;
164 }; 164 };
165 165
166 clkout2_pin: pinmux_clkout2_pin { 166 clkout2_pin: pinmux_clkout2_pin {
167 pinctrl-single,pins = < 167 pinctrl-single,pins = <
168 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 168 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
169 >; 169 >;
170 }; 170 };
171 171
172 /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/ 172 /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/
173 gpio_pins_default: pinmux_gpio_pin { 173 gpio_pins_default: pinmux_gpio_pin {
174 pinctrl-single,pins = < 174 pinctrl-single,pins = <
175 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gmii1_rx_dv.gpio3_4 */ 175 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gmii1_rx_dv.gpio3_4 */
176 0x09c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ 176 0x09c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
177 0x064 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ 177 0x064 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
178 0x060 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.gpio1_24 */ 178 0x060 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.gpio1_24 */
179 0x098 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wen.gpio2_4 */ 179 0x098 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wen.gpio2_4 */
180 0x094 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oenren.gpio2_3 */ 180 0x094 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oenren.gpio2_3 */
181 0x078 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben1.gpio1_28 */ 181 0x078 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben1.gpio1_28 */
182 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ 182 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
183 0x088 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */ 183 0x088 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
184 0x08c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.gpio2_1 */ 184 0x08c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.gpio2_1 */
185 0x1e4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* emu0.gpio3_7 */ 185 0x1e4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* emu0.gpio3_7 */
186 0x1e8 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* emu1.gpio3_8 */ 186 0x1e8 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* emu1.gpio3_8 */
187 >; 187 >;
188 }; 188 };
189 189
190 ecap0_pins_default: backlight_pins { 190 ecap0_pins_default: backlight_pins {
191 pinctrl-single,pins = < 191 pinctrl-single,pins = <
192 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 192 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
193 >; 193 >;
194 }; 194 };
195 195
196 ecap0_pins_sleep: ecap0_pins_sleep { 196 ecap0_pins_sleep: ecap0_pins_sleep {
197 pinctrl-single,pins = < 197 pinctrl-single,pins = <
198 0x164 (PULL_DISABLE | MUX_MODE7) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ 198 0x164 (PULL_DISABLE | MUX_MODE7) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
199 >; 199 >;
200 }; 200 };
201 201
202 cpsw_default: cpsw_default { 202 cpsw_default: cpsw_default {
203 pinctrl-single,pins = < 203 pinctrl-single,pins = <
204 /* Slave 1 */ 204 /* Slave 1 */
205 0x10c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ 205 0x10c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
206 0x110 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 206 0x110 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
207 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ 207 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
208 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 208 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
209 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 209 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
210 0x13c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 210 0x13c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
211 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 211 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
212 0x144 (PIN_INPUT_PULLUP | MUX_MODE0) /* rmii1_ref_clk.rmii1_ref_clk */ 212 0x144 (PIN_INPUT_PULLUP | MUX_MODE0) /* rmii1_ref_clk.rmii1_ref_clk */
213 213
214 /* Slave 2 */ 214 /* Slave 2 */
215 0x070 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ 215 0x070 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */
216 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ 216 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */
217 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */ 217 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */
218 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ 218 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */
219 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ 219 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */
220 0x068 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ 220 0x068 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */
221 0x06c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ 221 0x06c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */
222 0x108 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_col.rmii2_ref_clk */ 222 0x108 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_col.rmii2_ref_clk */
223 >; 223 >;
224 }; 224 };
225 225
226 cpsw_sleep: cpsw_sleep { 226 cpsw_sleep: cpsw_sleep {
227 pinctrl-single,pins = < 227 pinctrl-single,pins = <
228 /* Slave 1 reset value */ 228 /* Slave 1 reset value */
229 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) 229 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
230 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) 230 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
231 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 231 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
232 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 232 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
233 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 233 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
234 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 234 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
235 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 235 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
236 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) 236 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
237 237
238 /* Slave 2 reset value */ 238 /* Slave 2 reset value */
239 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) 239 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7)
240 0x074 (PIN_INPUT_PULLDOWN | MUX_MODE7) 240 0x074 (PIN_INPUT_PULLDOWN | MUX_MODE7)
241 0x040 (PIN_INPUT_PULLDOWN | MUX_MODE7) 241 0x040 (PIN_INPUT_PULLDOWN | MUX_MODE7)
242 0x050 (PIN_INPUT_PULLDOWN | MUX_MODE7) 242 0x050 (PIN_INPUT_PULLDOWN | MUX_MODE7)
243 0x054 (PIN_INPUT_PULLDOWN | MUX_MODE7) 243 0x054 (PIN_INPUT_PULLDOWN | MUX_MODE7)
244 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE7) 244 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE7)
245 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE7) 245 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE7)
246 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) 246 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
247 >; 247 >;
248 }; 248 };
249 249
250 davinci_mdio_default: davinci_mdio_default { 250 davinci_mdio_default: davinci_mdio_default {
251 pinctrl-single,pins = < 251 pinctrl-single,pins = <
252 /* MDIO */ 252 /* MDIO */
253 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 253 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
254 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 254 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
255 >; 255 >;
256 }; 256 };
257 257
258 davinci_mdio_sleep: davinci_mdio_sleep { 258 davinci_mdio_sleep: davinci_mdio_sleep {
259 pinctrl-single,pins = < 259 pinctrl-single,pins = <
260 /* MDIO reset value */ 260 /* MDIO reset value */
261 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 261 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
262 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 262 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
263 >; 263 >;
264 }; 264 };
265 265
266 mmc1_pins: pinmux_mmc1_pins { 266 mmc1_pins: pinmux_mmc1_pins {
267 pinctrl-single,pins = < 267 pinctrl-single,pins = <
268 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ 268 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
269 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ 269 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
270 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ 270 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
271 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ 271 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
272 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ 272 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
273 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ 273 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
274 0x048 (PIN_INPUT | MUX_MODE7) /* GPIO1_18, MMC1_CD */ 274 0x048 (PIN_INPUT | MUX_MODE7) /* GPIO1_18, MMC1_CD */
275 0x044 (PIN_INPUT | MUX_MODE7) /* GPIO1_17, MMC1_WP */ 275 0x044 (PIN_INPUT | MUX_MODE7) /* GPIO1_17, MMC1_WP */
276 >; 276 >;
277 }; 277 };
278 278
279 mmc1_pins_sleep: pinmux_mmc1_pins_sleep { 279 mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
280 pinctrl-single,pins = < 280 pinctrl-single,pins = <
281 0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7) 281 0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
282 0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7) 282 0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
283 0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7) 283 0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
284 0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7) 284 0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7)
285 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7) 285 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
286 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7) 286 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
287 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7) 287 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
288 0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7) 288 0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7)
289 >; 289 >;
290 }; 290 };
291 291
292 emmc_pins: pinmux_emmc_pins { 292 emmc_pins: pinmux_emmc_pins {
293 pinctrl-single,pins = < 293 pinctrl-single,pins = <
294 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 294 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
295 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 295 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
296 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 296 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
297 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 297 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
298 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 298 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
299 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 299 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
300 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ 300 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
301 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ 301 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
302 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ 302 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
303 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ 303 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
304 >; 304 >;
305 }; 305 };
306 306
307 lcd_pins_default: lcd_pins_default { 307 lcd_pins_default: lcd_pins_default {
308 pinctrl-single,pins = < 308 pinctrl-single,pins = <
309 0x3c 0x01 /* gpmc_ad15.lcd_data16, OUTPUT | MODE1 */ 309 0x3c 0x01 /* gpmc_ad15.lcd_data16, OUTPUT | MODE1 */
310 0x38 0x01 /* gpmc_ad14.lcd_data17, OUTPUT | MODE1 */ 310 0x38 0x01 /* gpmc_ad14.lcd_data17, OUTPUT | MODE1 */
311 0x34 0x01 /* gpmc_ad13.lcd_data18, OUTPUT | MODE1 */ 311 0x34 0x01 /* gpmc_ad13.lcd_data18, OUTPUT | MODE1 */
312 0x30 0x01 /* gpmc_ad12.lcd_data19, OUTPUT | MODE1 */ 312 0x30 0x01 /* gpmc_ad12.lcd_data19, OUTPUT | MODE1 */
313 0x2c 0x01 /* gpmc_ad11.lcd_data20, OUTPUT | MODE1 */ 313 0x2c 0x01 /* gpmc_ad11.lcd_data20, OUTPUT | MODE1 */
314 0x28 0x01 /* gpmc_ad10.lcd_data21, OUTPUT | MODE1 */ 314 0x28 0x01 /* gpmc_ad10.lcd_data21, OUTPUT | MODE1 */
315 0x24 0x01 /* gpmc_ad9.lcd_data22, OUTPUT | MODE1 */ 315 0x24 0x01 /* gpmc_ad9.lcd_data22, OUTPUT | MODE1 */
316 0x20 0x01 /* gpmc_ad8.lcd_data23, OUTPUT | MODE1 */ 316 0x20 0x01 /* gpmc_ad8.lcd_data23, OUTPUT | MODE1 */
317 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ 317 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
318 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ 318 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
319 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ 319 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
320 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ 320 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
321 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ 321 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
322 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ 322 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
323 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ 323 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
324 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ 324 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
325 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ 325 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
326 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ 326 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
327 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ 327 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
328 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ 328 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
329 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ 329 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
330 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ 330 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
331 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ 331 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
332 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ 332 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
333 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ 333 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
334 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ 334 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
335 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ 335 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
336 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ 336 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
337 0x5c 0x17 /* gpmc_a7.gpio1_23, MODE7 - LCD_VDD_EN */ 337 0x5c 0x17 /* gpmc_a7.gpio1_23, MODE7 - LCD_VDD_EN */
338 >; 338 >;
339 }; 339 };
340 340
341 341
342 lcd_pins_sleep: lcd_pins_sleep { 342 lcd_pins_sleep: lcd_pins_sleep {
343 pinctrl-single,pins = < 343 pinctrl-single,pins = <
344 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16, OUTPUT | MODE1 */ 344 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16, OUTPUT | MODE1 */
345 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17, OUTPUT | MODE1 */ 345 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17, OUTPUT | MODE1 */
346 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18, OUTPUT | MODE1 */ 346 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18, OUTPUT | MODE1 */
347 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19, OUTPUT | MODE1 */ 347 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19, OUTPUT | MODE1 */
348 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20, OUTPUT | MODE1 */ 348 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20, OUTPUT | MODE1 */
349 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21, OUTPUT | MODE1 */ 349 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21, OUTPUT | MODE1 */
350 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22, OUTPUT | MODE1 */ 350 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22, OUTPUT | MODE1 */
351 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23, OUTPUT | MODE1 */ 351 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23, OUTPUT | MODE1 */
352 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ 352 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
353 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ 353 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
354 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ 354 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
355 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ 355 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
356 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ 356 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
357 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ 357 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
358 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ 358 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
359 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ 359 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
360 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ 360 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
361 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ 361 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
362 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ 362 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
363 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ 363 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
364 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ 364 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
365 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ 365 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
366 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ 366 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
367 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ 367 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
368 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ 368 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
369 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ 369 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
370 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ 370 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
371 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ 371 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
372 >; 372 >;
373 }; 373 };
374 374
375 mcasp1_pins: mcasp1_pins { 375 mcasp1_pins: mcasp1_pins {
376 pinctrl-single,pins = < 376 pinctrl-single,pins = <
377 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkr.mcasp1_aclkx */ 377 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkr.mcasp1_aclkx */
378 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_fsr.mcasp1_fsx */ 378 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_fsr.mcasp1_fsx */
379 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */ 379 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */
380 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_ahclkx.mcasp1_axr1 */ 380 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_ahclkx.mcasp1_axr1 */
381 >; 381 >;
382 }; 382 };
383 383
384 mcasp1_sleep_pins: mcasp1_sleep_pins { 384 mcasp1_sleep_pins: mcasp1_sleep_pins {
385 pinctrl-single,pins = < 385 pinctrl-single,pins = <
386 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) 386 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
387 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) 387 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
388 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) 388 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
389 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) 389 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7)
390 >; 390 >;
391 }; 391 };
392 392
393 spi0_pins: pinmux_spi0_pins { 393 spi0_pins: pinmux_spi0_pins {
394 pinctrl-single,pins = < 394 pinctrl-single,pins = <
395 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ 395 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
396 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ 396 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
397 0x158 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ 397 0x158 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
398 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ 398 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
399 0x160 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs1.spi0_cs1 */ 399 0x160 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs1.spi0_cs1 */
400 >; 400 >;
401 }; 401 };
402 402
403 spi1_pins: pinmux_spi1_pins { 403 spi1_pins: pinmux_spi1_pins {
404 pinctrl-single,pins = < 404 pinctrl-single,pins = <
405 0x190 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ 405 0x190 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
406 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ 406 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
407 0x198 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ 407 0x198 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
408 0x19c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ 408 0x19c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
409 0x1b0 (PIN_OUTPUT_PULLUP | MUX_MODE4) /* xdma_event_intr0.spi1_cs1 */ 409 0x1b0 (PIN_OUTPUT_PULLUP | MUX_MODE4) /* xdma_event_intr0.spi1_cs1 */
410 >; 410 >;
411 }; 411 };
412 412
413 dcan0_default: dcan0_default_pins { 413 dcan0_default: dcan0_default_pins {
414 pinctrl-single,pins = < 414 pinctrl-single,pins = <
415 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gmii1_txd3.dcan0_tx */ 415 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gmii1_txd3.dcan0_tx */
416 0x120 (PIN_INPUT_PULLUP | MUX_MODE1) /* gmii1_txd2.dcan0_rx */ 416 0x120 (PIN_INPUT_PULLUP | MUX_MODE1) /* gmii1_txd2.dcan0_rx */
417 >; 417 >;
418 }; 418 };
419 419
420 }; 420 };
421 421
422 ocp { 422 ocp {
423 uart0: serial@44e09000 { 423 uart0: serial@44e09000 {
424 pinctrl-names = "default"; 424 pinctrl-names = "default";
425 pinctrl-0 = <&uart0_pins>; 425 pinctrl-0 = <&uart0_pins>;
426 426
427 status = "okay"; 427 status = "okay";
428 }; 428 };
429 429
430 uart2: serial@48024000 { 430 uart2: serial@48024000 {
431 pinctrl-names = "default"; 431 pinctrl-names = "default";
432 pinctrl-0 = <&uart2_pins>; 432 pinctrl-0 = <&uart2_pins>;
433 433
434 status = "okay"; 434 status = "okay";
435 }; 435 };
436 436
437 uart3: serial@481a6000 { 437 uart3: serial@481a6000 {
438 pinctrl-names = "default"; 438 pinctrl-names = "default";
439 pinctrl-0 = <&uart3_pins>; 439 pinctrl-0 = <&uart3_pins>;
440 440
441 status = "okay"; 441 status = "okay";
442 }; 442 };
443 443
444 i2c0: i2c@44e0b000 { 444 i2c0: i2c@44e0b000 {
445 pinctrl-names = "default"; 445 pinctrl-names = "default";
446 pinctrl-0 = <&i2c0_pins>; 446 pinctrl-0 = <&i2c0_pins>;
447 447
448 status = "okay"; 448 status = "okay";
449 clock-frequency = <100000>; 449 clock-frequency = <100000>;
450 450
451 /* Set OPP50 (0.95V) for VDD core */ 451 /* Set OPP50 (0.95V) for VDD core */
452 sleep-sequence = /bits/ 8 < 452 sleep-sequence = /bits/ 8 <
453 0x02 0x24 0x0b 0x6d /* Password unlock 1 */ 453 0x02 0x24 0x0b 0x6d /* Password unlock 1 */
454 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */ 454 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */
455 0x02 0x24 0x0b 0x6d /* Password unlock 2 */ 455 0x02 0x24 0x0b 0x6d /* Password unlock 2 */
456 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */ 456 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */
457 0x02 0x24 0x0b 0x6c /* Password unlock 1 */ 457 0x02 0x24 0x0b 0x6c /* Password unlock 1 */
458 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ 458 0x02 0x24 0x11 0x86 /* Apply DCDC changes */
459 0x02 0x24 0x0b 0x6c /* Password unlock 2 */ 459 0x02 0x24 0x0b 0x6c /* Password unlock 2 */
460 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ 460 0x02 0x24 0x11 0x86 /* Apply DCDC changes */
461 >; 461 >;
462 462
463 /* Set OPP100 (1.10V) for VDD core */ 463 /* Set OPP100 (1.10V) for VDD core */
464 wake-sequence = /bits/ 8 < 464 wake-sequence = /bits/ 8 <
465 0x02 0x24 0x0b 0x6d /* Password unlock 1 */ 465 0x02 0x24 0x0b 0x6d /* Password unlock 1 */
466 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */ 466 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */
467 0x02 0x24 0x0b 0x6d /* Password unlock 2 */ 467 0x02 0x24 0x0b 0x6d /* Password unlock 2 */
468 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */ 468 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */
469 0x02 0x24 0x0b 0x6c /* Password unlock 1 */ 469 0x02 0x24 0x0b 0x6c /* Password unlock 1 */
470 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ 470 0x02 0x24 0x11 0x86 /* Apply DCDC changes */
471 0x02 0x24 0x0b 0x6c /* Password unlock 2 */ 471 0x02 0x24 0x0b 0x6c /* Password unlock 2 */
472 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ 472 0x02 0x24 0x11 0x86 /* Apply DCDC changes */
473 >; 473 >;
474 474
475 tps: tps@24 { 475 tps: tps@24 {
476 reg = <0x24>; 476 reg = <0x24>;
477 }; 477 };
478 478
479 baseboard_eeprom: baseboard_eeprom@50 { 479 baseboard_eeprom: baseboard_eeprom@50 {
480 compatible = "at,24c256"; 480 compatible = "at,24c256";
481 reg = <0x50>; 481 reg = <0x50>;
482 }; 482 };
483 483
484 tlv320aic3106: tlv320aic3106@1b { 484 tlv320aic3106: tlv320aic3106@1b {
485 compatible = "ti,tlv320aic3106"; 485 compatible = "ti,tlv320aic3106";
486 reg = <0x1b>; 486 reg = <0x1b>;
487 status = "okay"; 487 status = "okay";
488 488
489 /* Regulators */ 489 /* Regulators */
490 AVDD-supply = <&vmmcsd_fixed>; 490 AVDD-supply = <&vmmcsd_fixed>;
491 IOVDD-supply = <&vmmcsd_fixed>; 491 IOVDD-supply = <&vmmcsd_fixed>;
492 DRVDD-supply = <&vmmcsd_fixed>; 492 DRVDD-supply = <&vmmcsd_fixed>;
493 DVDD-supply = <&vdd1v8_fixed>; 493 DVDD-supply = <&vdd1v8_fixed>;
494 }; 494 };
495 495
496 s35390a: s35390a@30 { 496 s35390a: s35390a@30 {
497 compatible = "s35390a"; 497 compatible = "s35390a";
498 reg = <0x30>; 498 reg = <0x30>;
499 }; 499 };
500 500
501 cape_eeprom0: cape_eeprom@57 { 501 cape_eeprom0: cape_eeprom@57 {
502 compatible = "at,24c256"; 502 compatible = "at,24c256";
503 reg = <0x57>; 503 reg = <0x57>;
504 }; 504 };
505 505
506 }; 506 };
507 507
508 i2c1: i2c@4802a000 { 508 i2c1: i2c@4802a000 {
509 pinctrl-names = "default"; 509 pinctrl-names = "default";
510 pinctrl-0 = <&i2c1_pins>; 510 pinctrl-0 = <&i2c1_pins>;
511 status = "okay"; 511 status = "okay";
512 clock-frequency = <100000>; 512 clock-frequency = <100000>;
513 }; 513 };
514 514
515 i2c2: i2c@4819c000 { 515 i2c2: i2c@4819c000 {
516 pinctrl-names = "default"; 516 pinctrl-names = "default";
517 pinctrl-0 = <&i2c2_pins>; 517 pinctrl-0 = <&i2c2_pins>;
518 status = "okay"; 518 status = "okay";
519 clock-frequency = <100000>; 519 clock-frequency = <100000>;
520 }; 520 };
521 521
522 spi0: spi@48030000 { 522 spi0: spi@48030000 {
523 pinctrl-names = "default"; 523 pinctrl-names = "default";
524 pinctrl-0 = <&spi0_pins>; 524 pinctrl-0 = <&spi0_pins>;
525 status = "okay"; 525 status = "okay";
526 526
527 spidev0: spi@0 { 527 spidev0: spi@0 {
528 compatible = "spidev"; 528 compatible = "spidev";
529 reg = <0>; 529 reg = <0>;
530 spi-max-frequency = <16000000>; 530 spi-max-frequency = <16000000>;
531 spi-cpha; 531 spi-cpha;
532 }; 532 };
533 533
534 spidev2: spi@1 { 534 spidev2: spi@1 {
535 compatible = "spidev"; 535 compatible = "spidev";
536 reg = <1>; 536 reg = <1>;
537 spi-max-frequency = <16000000>; 537 spi-max-frequency = <16000000>;
538 }; 538 };
539 }; 539 };
540 540
541 spi1: spi@481a0000 { 541 spi1: spi@481a0000 {
542 pinctrl-names = "default"; 542 pinctrl-names = "default";
543 pinctrl-0 = <&spi1_pins>; 543 pinctrl-0 = <&spi1_pins>;
544 status = "okay"; 544 status = "okay";
545 545
546 spidev1: spi@0 { 546 spidev1: spi@0 {
547 compatible = "spidev"; 547 compatible = "spidev";
548 reg = <0>; 548 reg = <0>;
549 spi-max-frequency = <16000000>; 549 spi-max-frequency = <16000000>;
550 spi-cpha; 550 spi-cpha;
551 }; 551 };
552 552
553 spidev3: spi@1 { 553 spidev3: spi@1 {
554 compatible = "spidev"; 554 compatible = "spidev";
555 reg = <1>; 555 reg = <1>;
556 spi-max-frequency = <16000000>; 556 spi-max-frequency = <16000000>;
557 }; 557 };
558 }; 558 };
559 559
560 rtc@44e3e000 { 560 rtc@44e3e000 {
561 status = "disabled"; 561 status = "disabled";
562 }; 562 };
563 563
564 musb: usb@47400000 { 564 musb: usb@47400000 {
565 status = "okay"; 565 status = "okay";
566 566
567 control@44e10000 { 567 control@44e10000 {
568 status = "okay"; 568 status = "okay";
569 }; 569 };
570 570
571 usb-phy@47401300 { 571 usb-phy@47401300 {
572 status = "okay"; 572 status = "okay";
573 }; 573 };
574 574
575 usb@47401000 { 575 usb@47401000 {
576 status = "okay"; 576 status = "okay";
577 dr_mode = "host"; 577 dr_mode = "host";
578 }; 578 };
579 579
580 usb-phy@47401b00 { 580 usb-phy@47401b00 {
581 status = "okay"; 581 status = "okay";
582 }; 582 };
583 583
584 usb@47401800 { 584 usb@47401800 {
585 status = "okay"; 585 status = "okay";
586 dr_mode = "host"; 586 dr_mode = "host";
587 }; 587 };
588 588
589 dma-controller@07402000 { 589 dma-controller@07402000 {
590 status = "okay"; 590 status = "okay";
591 }; 591 };
592 }; 592 };
593 593
594 epwmss0: epwmss@48300000 { 594 epwmss0: epwmss@48300000 {
595 status = "okay"; 595 status = "okay";
596 596
597 ecap0: ecap@48300100 { 597 ecap0: ecap@48300100 {
598 status = "okay"; 598 status = "okay";
599 pinctrl-names = "default", "sleep"; 599 pinctrl-names = "default", "sleep";
600 pinctrl-0 = <&ecap0_pins_default>; 600 pinctrl-0 = <&ecap0_pins_default>;
601 pinctrl-1 = <&ecap0_pins_sleep>; 601 pinctrl-1 = <&ecap0_pins_sleep>;
602 }; 602 };
603 }; 603 };
604 604
605 lcdc: lcdc@0x4830e000 { 605 lcdc: lcdc@0x4830e000 {
606 pinctrl-names = "default", "sleep"; 606 pinctrl-names = "default", "sleep";
607 pinctrl-0 = <&lcd_pins_default>; 607 pinctrl-0 = <&lcd_pins_default>;
608 pinctrl-1 = <&lcd_pins_sleep>; 608 pinctrl-1 = <&lcd_pins_sleep>;
609 status = "okay"; 609 status = "okay";
610 display-timings { 610 display-timings {
611 800x480p60 { 611 800x480p60 {
612 clock-frequency = <32000000>; 612 clock-frequency = <32000000>;
613 hactive = <800>; 613 hactive = <800>;
614 vactive = <480>; 614 vactive = <480>;
615 hfront-porch = <42>; 615 hfront-porch = <42>;
616 hback-porch = <84>; 616 hback-porch = <84>;
617 hsync-len = <128>; 617 hsync-len = <128>;
618 vback-porch = <33>; 618 vback-porch = <33>;
619 vfront-porch = <10>; 619 vfront-porch = <10>;
620 vsync-len = <2>; 620 vsync-len = <2>;
621 hsync-active = <0>; 621 hsync-active = <0>;
622 vsync-active = <0>; 622 vsync-active = <0>;
623 }; 623 };
624 }; 624 };
625 }; 625 };
626 626
627 sound { 627 sound {
628 compatible = "ti,da830-evm-audio"; 628 compatible = "ti,da830-evm-audio";
629 ti,model = "TLV320AIC3106 SOUND CARD"; 629 ti,model = "TLV320AIC3106 SOUND CARD";
630 ti,audio-codec = <&tlv320aic3106>; 630 ti,audio-codec = <&tlv320aic3106>;
631 ti,mcasp-controller = <&mcasp1>; 631 ti,mcasp-controller = <&mcasp1>;
632 ti,codec-clock-rate = <24576000>; 632 ti,codec-clock-rate = <24576000>;
633 ti,audio-routing = 633 ti,audio-routing =
634 "Headphone Jack", "HPLOUT", 634 "Headphone Jack", "HPLOUT",
635 "Headphone Jack", "HPROUT", 635 "Headphone Jack", "HPROUT",
636 "LINE1L", "Line In", 636 "LINE1L", "Line In",
637 "LINE1R", "Line In"; 637 "LINE1R", "Line In";
638 }; 638 };
639 }; 639 };
640 640
641 backlight { 641 backlight {
642 compatible = "pwm-backlight"; 642 compatible = "pwm-backlight";
643 gpios = <&gpio1 22 1>; /* Backlight Enable Pin*/ 643 gpios = <&gpio1 22 1>; /* Backlight Enable Pin*/
644 pwms = <&ecap0 0 50000 0>; 644 pwms = <&ecap0 0 50000 0>;
645 brightness-levels = <0 51 53 56 62 75 101 152 255>; 645 brightness-levels = <0 51 53 56 62 75 101 152 255>;
646 default-brightness-level = <8>; 646 default-brightness-level = <8>;
647 }; 647 };
648 648
649 /* Settings for PVI PM070WL4 800x480 panel*/ 649 /* Settings for PVI PM070WL4 800x480 panel*/
650 panel { 650 panel {
651 compatible = "ti,tilcdc,panel"; 651 compatible = "ti,tilcdc,panel";
652 status = "okay"; 652 status = "okay";
653 pinctrl-names = "default"; 653 pinctrl-names = "default";
654 pinctrl-0 = <&lcd_pins_default>; 654 pinctrl-0 = <&lcd_pins_default>;
655 panel-info { 655 panel-info {
656 ac-bias = <255>; 656 ac-bias = <255>;
657 ac-bias-intrpt = <0>; 657 ac-bias-intrpt = <0>;
658 dma-burst-sz = <16>; 658 dma-burst-sz = <16>;
659 bpp = <32>; 659 bpp = <32>;
660 fdd = <0x80>; 660 fdd = <0x80>;
661 sync-edge = <0>; 661 sync-edge = <0>;
662 sync-ctrl = <1>; 662 sync-ctrl = <1>;
663 raster-order = <0>; 663 raster-order = <0>;
664 fifo-th = <0>; 664 fifo-th = <0>;
665 /*invert-pxl-clk;*/ /*pixel clock polarity*/
665 }; 666 };
666 667
667 display-timings { 668 display-timings {
668 800x480p60 { 669 800x480p60 {
669 clock-frequency = <32000000>; 670 clock-frequency = <32000000>;
670 hactive = <800>; 671 hactive = <800>;
671 vactive = <480>; 672 vactive = <480>;
672 hfront-porch = <42>; 673 hfront-porch = <42>;
673 hback-porch = <84>; 674 hback-porch = <84>;
674 hsync-len = <128>; 675 hsync-len = <128>;
675 vback-porch = <33>; 676 vback-porch = <33>;
676 vfront-porch = <10>; 677 vfront-porch = <10>;
677 vsync-len = <2>; 678 vsync-len = <2>;
678 hsync-active = <0>; 679 hsync-active = <0>;
679 vsync-active = <0>; 680 vsync-active = <0>;
680 }; 681 };
681 }; 682 };
682 }; 683 };
683 684
684 vmmcsd_fixed: fixedregulator@0 { 685 vmmcsd_fixed: fixedregulator@0 {
685 compatible = "regulator-fixed"; 686 compatible = "regulator-fixed";
686 regulator-name = "vmmcsd_fixed"; 687 regulator-name = "vmmcsd_fixed";
687 regulator-min-microvolt = <3300000>; 688 regulator-min-microvolt = <3300000>;
688 regulator-max-microvolt = <3300000>; 689 regulator-max-microvolt = <3300000>;
689 }; 690 };
690 691
691 vdd1v8_fixed: fixedregulator@1 { 692 vdd1v8_fixed: fixedregulator@1 {
692 compatible = "regulator-fixed"; 693 compatible = "regulator-fixed";
693 regulator-name = "vdd1v8_fixed"; 694 regulator-name = "vdd1v8_fixed";
694 regulator-min-microvolt = <1800000>; 695 regulator-min-microvolt = <1800000>;
695 regulator-max-microvolt = <1800000>; 696 regulator-max-microvolt = <1800000>;
696 }; 697 };
697 }; 698 };
698 699
699 /include/ "tps65217.dtsi" 700 /include/ "tps65217.dtsi"
700 701
701 &tps { 702 &tps {
702 regulators { 703 regulators {
703 dcdc1_reg: regulator@0 { 704 dcdc1_reg: regulator@0 {
704 regulator-always-on; 705 regulator-always-on;
705 }; 706 };
706 707
707 dcdc2_reg: regulator@1 { 708 dcdc2_reg: regulator@1 {
708 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 709 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
709 regulator-name = "vdd_mpu"; 710 regulator-name = "vdd_mpu";
710 regulator-min-microvolt = <925000>; 711 regulator-min-microvolt = <925000>;
711 regulator-max-microvolt = <1325000>; 712 regulator-max-microvolt = <1325000>;
712 regulator-boot-on; 713 regulator-boot-on;
713 regulator-always-on; 714 regulator-always-on;
714 }; 715 };
715 716
716 dcdc3_reg: regulator@2 { 717 dcdc3_reg: regulator@2 {
717 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 718 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
718 regulator-name = "vdd_core"; 719 regulator-name = "vdd_core";
719 regulator-min-microvolt = <925000>; 720 regulator-min-microvolt = <925000>;
720 regulator-max-microvolt = <1150000>; 721 regulator-max-microvolt = <1150000>;
721 regulator-boot-on; 722 regulator-boot-on;
722 regulator-always-on; 723 regulator-always-on;
723 }; 724 };
724 725
725 ldo1_reg: regulator@3 { 726 ldo1_reg: regulator@3 {
726 regulator-always-on; 727 regulator-always-on;
727 }; 728 };
728 729
729 ldo2_reg: regulator@4 { 730 ldo2_reg: regulator@4 {
730 regulator-always-on; 731 regulator-always-on;
731 }; 732 };
732 733
733 ldo3_reg: regulator@5 { 734 ldo3_reg: regulator@5 {
734 regulator-always-on; 735 regulator-always-on;
735 }; 736 };
736 737
737 ldo4_reg: regulator@6 { 738 ldo4_reg: regulator@6 {
738 regulator-always-on; 739 regulator-always-on;
739 }; 740 };
740 }; 741 };
741 }; 742 };
742 743
743 &edma { 744 &edma {
744 ti,edma-xbar-event-map = <1 12 745 ti,edma-xbar-event-map = <1 12
745 2 13>; 746 2 13>;
746 }; 747 };
747 748
748 &mmc1 { 749 &mmc1 {
749 status = "okay"; 750 status = "okay";
750 bus-width = <0x4>; 751 bus-width = <0x4>;
751 pinctrl-names = "default"; 752 pinctrl-names = "default";
752 pinctrl-0 = <&mmc1_pins>; 753 pinctrl-0 = <&mmc1_pins>;
753 gpios = <&gpio1 19 1>; /* mmc0 power enable*/ 754 gpios = <&gpio1 19 1>; /* mmc0 power enable*/
754 cd-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; 755 cd-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
755 cd-inverted; 756 cd-inverted;
756 wp-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; 757 wp-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
757 }; 758 };
758 759
759 &mcasp1 { 760 &mcasp1 {
760 pinctrl-names = "default", "sleep"; 761 pinctrl-names = "default", "sleep";
761 pinctrl-0 = <&mcasp1_pins>; 762 pinctrl-0 = <&mcasp1_pins>;
762 pinctrl-1 = <&mcasp1_sleep_pins>; 763 pinctrl-1 = <&mcasp1_sleep_pins>;
763 764
764 status = "okay"; 765 status = "okay";
765 766
766 op-mode = <0>; /* MCASP_IIS_MODE */ 767 op-mode = <0>; /* MCASP_IIS_MODE */
767 tdm-slots = <2>; 768 tdm-slots = <2>;
768 /* 4 serializers */ 769 /* 4 serializers */
769 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 770 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
770 1 2 0 0 771 1 2 0 0
771 >; 772 >;
772 tx-num-evt = <1>; 773 tx-num-evt = <1>;
773 rx-num-evt = <1>; 774 rx-num-evt = <1>;
774 }; 775 };
775 776
776 &mac { 777 &mac {
777 pinctrl-names = "default", "sleep"; 778 pinctrl-names = "default", "sleep";
778 pinctrl-0 = <&cpsw_default>; 779 pinctrl-0 = <&cpsw_default>;
779 pinctrl-1 = <&cpsw_sleep>; 780 pinctrl-1 = <&cpsw_sleep>;
780 dual_emac; 781 dual_emac;
781 }; 782 };
782 783
783 &davinci_mdio { 784 &davinci_mdio {
784 pinctrl-names = "default", "sleep"; 785 pinctrl-names = "default", "sleep";
785 pinctrl-0 = <&davinci_mdio_default>; 786 pinctrl-0 = <&davinci_mdio_default>;
786 pinctrl-1 = <&davinci_mdio_sleep>; 787 pinctrl-1 = <&davinci_mdio_sleep>;
787 }; 788 };
788 789
789 &cpsw_emac0 { 790 &cpsw_emac0 {
790 phy_id = <&davinci_mdio>, <0>; 791 phy_id = <&davinci_mdio>, <0>;
791 phy-mode = "rmii"; 792 phy-mode = "rmii";
792 dual_emac_res_vlan = <1>; 793 dual_emac_res_vlan = <1>;
793 }; 794 };
794 795
795 &cpsw_emac1 { 796 &cpsw_emac1 {
796 phy_id = <&davinci_mdio>, <1>; 797 phy_id = <&davinci_mdio>, <1>;
797 phy-mode = "rmii"; 798 phy-mode = "rmii";
798 dual_emac_res_vlan = <2>; 799 dual_emac_res_vlan = <2>;
799 }; 800 };
800 801
801 &phy_sel { 802 &phy_sel {
802 reg= <0x44e10650 0xf5>; 803 reg= <0x44e10650 0xf5>;
803 rmii-clock-ext; 804 rmii-clock-ext;
804 }; 805 };
805 806
806 &tscadc { 807 &tscadc {
807 status = "okay"; 808 status = "okay";
808 tsc { 809 tsc {
809 ti,wires = <4>; 810 ti,wires = <4>;
810 ti,x-plate-resistance = <200>; 811 ti,x-plate-resistance = <200>;
811 ti,coordinate-readouts = <5>; 812 ti,coordinate-readouts = <5>;
812 ti,wire-config = <0x00 0x11 0x22 0x33>; 813 ti,wire-config = <0x00 0x11 0x22 0x33>;
813 }; 814 };
814 815
815 adc { 816 adc {
816 ti,adc-channels = <0 1 2 3>; 817 ti,adc-channels = <0 1 2 3>;
817 }; 818 };
818 }; 819 };
819 820
820 &dcan0 { 821 &dcan0 {
821 pinctrl-names = "default"; 822 pinctrl-names = "default";
822 pinctrl-0 = <&dcan0_default>; 823 pinctrl-0 = <&dcan0_default>;
823 status = "okay"; 824 status = "okay";
824 }; 825 };
825 826
826 &sham { 827 &sham {
827 status = "okay"; 828 status = "okay";
828 }; 829 };
829 830
830 &aes { 831 &aes {
831 status = "okay"; 832 status = "okay";
832 }; 833 };
833 834