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Commit e4daa9efa2c4c1f1aa0aa6850e49b163fa2b6cc3

Authored by Franklin S. Cooper Jr
Committed by Jacob Stiffler
1 parent e19ba3d996
Exists in smarc-ti-linux-3.14.y and in 1 other branch processor-sdk-linux-01.00.00

opp33xx_data: Enabled 1 GHz for 2.0 Silicon 

* For AM335x, PG 2.0 silicon was a very short lived revision mainly used
  for internal board development and Beaglebone Black.
* For versions of the Beaglebone Black that were sold the 2.0 silicon used
  was binned to insure that they supported 1 GHz.
* Therefore, enable 1 GHz since the only real users of 1 GHz on 2.0 silicon
  are 1 GHz users.

Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

arch/arm/mach-omap2/opp33xx_data.c
Diff comments   View file @ e4daa9e
1 /* 1 /*
2 * AM33XX OPP table definitions. 2 * AM33XX OPP table definitions.
3 * 3 *
4 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty 11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 #include <linux/io.h> 15 #include <linux/io.h>
16 #include <linux/module.h> 16 #include <linux/module.h>
17 17
18 #include "control.h" 18 #include "control.h"
19 #include "omap_opp_data.h" 19 #include "omap_opp_data.h"
20 #include "pm.h" 20 #include "pm.h"
21 #include "soc.h" 21 #include "soc.h"
22 22
23 /* 23 /*
24 * Errata 1.0.15: OPP50 Operation on MPU Domain is Not Supported. 24 * Errata 1.0.15: OPP50 Operation on MPU Domain is Not Supported.
25 * 25 *
26 * To minimize power consumption, the ARM Cortex-A8 may be operated at 26 * To minimize power consumption, the ARM Cortex-A8 may be operated at
27 * the lower frequency defined by OPP50, but the respective voltage 27 * the lower frequency defined by OPP50, but the respective voltage
28 * domain VDD_MPU must be operated as defined by OPP100. So MPU OPP50 28 * domain VDD_MPU must be operated as defined by OPP100. So MPU OPP50
29 * definition is modified to 275MHz, 1.1V. 29 * definition is modified to 275MHz, 1.1V.
30 */ 30 */
31 static struct omap_opp_def am33xx_es1_0_opp_list[] __initdata = { 31 static struct omap_opp_def am33xx_es1_0_opp_list[] __initdata = {
32 /* MPU OPP1 - OPP50 */ 32 /* MPU OPP1 - OPP50 */
33 OPP_INITIALIZER("mpu", true, 275000000, 1100000), 33 OPP_INITIALIZER("mpu", true, 275000000, 1100000),
34 /* MPU OPP2 - OPP100 */ 34 /* MPU OPP2 - OPP100 */
35 OPP_INITIALIZER("mpu", true, 500000000, 1100000), 35 OPP_INITIALIZER("mpu", true, 500000000, 1100000),
36 /* MPU OPP3 - OPP120 */ 36 /* MPU OPP3 - OPP120 */
37 OPP_INITIALIZER("mpu", true, 600000000, 1200000), 37 OPP_INITIALIZER("mpu", true, 600000000, 1200000),
38 /* MPU OPP4 - OPPTurbo */ 38 /* MPU OPP4 - OPPTurbo */
39 OPP_INITIALIZER("mpu", true, 720000000, 1260000), 39 OPP_INITIALIZER("mpu", true, 720000000, 1260000),
40 }; 40 };
41 41
42 static struct omap_opp_def am33xx_es2_x_opp_list[] __initdata = { 42 static struct omap_opp_def am33xx_es2_x_opp_list[] __initdata = {
43 /* MPU OPP1 - OPP50 or OPP100 */ 43 /* MPU OPP1 - OPP50 or OPP100 */
44 OPP_INITIALIZER("mpu", true, 300000000, 950000), 44 OPP_INITIALIZER("mpu", true, 300000000, 950000),
45 /* MPU OPP2 - OPP100 */ 45 /* MPU OPP2 - OPP100 */
46 OPP_INITIALIZER("mpu", true, 600000000, 1100000), 46 OPP_INITIALIZER("mpu", true, 600000000, 1100000),
47 /* MPU OPP3 - OPP120 */ 47 /* MPU OPP3 - OPP120 */
48 OPP_INITIALIZER("mpu", true, 720000000, 1200000), 48 OPP_INITIALIZER("mpu", true, 720000000, 1200000),
49 /* MPU OPP4 - OPPTurbo */ 49 /* MPU OPP4 - OPPTurbo */
50 OPP_INITIALIZER("mpu", true, 800000000, 1260000), 50 OPP_INITIALIZER("mpu", true, 800000000, 1260000),
51 /* MPU OPP5 - OPPNitro */ 51 /* MPU OPP5 - OPPNitro */
52 OPP_INITIALIZER("mpu", false, 1000000000, 1325000), 52 OPP_INITIALIZER("mpu", true, 1000000000, 1325000),
53 }; 53 };
54 54
55 /* From AM335x TRM, SPRUH73H, Section 9.3.50 */ 55 /* From AM335x TRM, SPRUH73H, Section 9.3.50 */
56 #define AM33XX_EFUSE_SMA_OFFSET 0x7fc 56 #define AM33XX_EFUSE_SMA_OFFSET 0x7fc
57 57
58 /* 58 /*
59 * Bits [12:0] are OPP Disabled bits, 59 * Bits [12:0] are OPP Disabled bits,
60 * 1 = OPP is disabled and not available, 60 * 1 = OPP is disabled and not available,
61 * 0 = OPP available. 61 * 0 = OPP available.
62 */ 62 */
63 #define MAX_FREQ_MASK 0x1fff 63 #define MAX_FREQ_MASK 0x1fff
64 #define MAX_FREQ_SHFT 0 64 #define MAX_FREQ_SHFT 0
65 65
66 /* ES 2.1 eFuse Values for enabling/diasbling specific OPPs */ 66 /* ES 2.1 eFuse Values for enabling/diasbling specific OPPs */
67 #define EFUSE_OPP_50_300MHZ_BIT (0x1 << 4) 67 #define EFUSE_OPP_50_300MHZ_BIT (0x1 << 4)
68 #define EFUSE_OPP_100_300MHZ_BIT (0x1 << 5) 68 #define EFUSE_OPP_100_300MHZ_BIT (0x1 << 5)
69 #define EFUSE_OPP_100_600MHZ_BIT (0x1 << 6) 69 #define EFUSE_OPP_100_600MHZ_BIT (0x1 << 6)
70 #define EFUSE_OPP_120_720MHZ_BIT (0x1 << 7) 70 #define EFUSE_OPP_120_720MHZ_BIT (0x1 << 7)
71 #define EFUSE_OPP_TURBO_800MHZ_BIT (0x1 << 8) 71 #define EFUSE_OPP_TURBO_800MHZ_BIT (0x1 << 8)
72 #define EFUSE_OPP_NITRO_1GHZ_BIT (0x1 << 9) 72 #define EFUSE_OPP_NITRO_1GHZ_BIT (0x1 << 9)
73 73
74 /** 74 /**
75 * am33xx_opp_init() - initialize am33xx opp table 75 * am33xx_opp_init() - initialize am33xx opp table
76 */ 76 */
77 int __init am33xx_opp_init(void) 77 int __init am33xx_opp_init(void)
78 { 78 {
79 int r = -ENODEV; 79 int r = -ENODEV;
80 u32 rev, val, max_freq; 80 u32 rev, val, max_freq;
81 81
82 if (WARN(!soc_is_am33xx(), "Cannot init OPPs: unsupported SoC.\n")) 82 if (WARN(!soc_is_am33xx(), "Cannot init OPPs: unsupported SoC.\n"))
83 return r; 83 return r;
84 84
85 rev = omap_rev(); 85 rev = omap_rev();
86 86
87 switch (rev) { 87 switch (rev) {
88 case AM335X_REV_ES1_0: 88 case AM335X_REV_ES1_0:
89 r = omap_init_opp_table(am33xx_es1_0_opp_list, 89 r = omap_init_opp_table(am33xx_es1_0_opp_list,
90 ARRAY_SIZE(am33xx_es1_0_opp_list)); 90 ARRAY_SIZE(am33xx_es1_0_opp_list));
91 break; 91 break;
92 92
93 case AM335X_REV_ES2_1: 93 case AM335X_REV_ES2_1:
94 /* 94 /*
95 * First read efuse sma reg to detect package type and 95 * First read efuse sma reg to detect package type and
96 * supported frequency 96 * supported frequency
97 */ 97 */
98 val = omap_ctrl_readl(AM33XX_EFUSE_SMA_OFFSET); 98 val = omap_ctrl_readl(AM33XX_EFUSE_SMA_OFFSET);
99 99
100 if (!(val & MAX_FREQ_MASK)) { 100 if (!(val & MAX_FREQ_MASK)) {
101 /* 101 /*
102 * if mpu max freq is not populated, fall back to 102 * if mpu max freq is not populated, fall back to
103 * PG 2.0 OPP settings. 103 * PG 2.0 OPP settings.
104 */ 104 */
105 r = 105 r =
106 omap_init_opp_table(am33xx_es2_x_opp_list, 106 omap_init_opp_table(am33xx_es2_x_opp_list,
107 ARRAY_SIZE(am33xx_es2_x_opp_list)); 107 ARRAY_SIZE(am33xx_es2_x_opp_list));
108 break; 108 break;
109 } 109 }
110 110
111 /* 111 /*
112 * 1 = OPP is disabled and not available, 112 * 1 = OPP is disabled and not available,
113 * 0 = OPP available. 113 * 0 = OPP available.
114 */ 114 */
115 max_freq = ~val & MAX_FREQ_MASK; 115 max_freq = ~val & MAX_FREQ_MASK;
116 116
117 /* 117 /*
118 * 300 MHz OPP is special because one of two different u_volt 118 * 300 MHz OPP is special because one of two different u_volt
119 * values so check and update voltage value to OPP 100 level 119 * values so check and update voltage value to OPP 100 level
120 * if efuse is set. 120 * if efuse is set.
121 */ 121 */
122 if (max_freq & EFUSE_OPP_100_300MHZ_BIT) { 122 if (max_freq & EFUSE_OPP_100_300MHZ_BIT) {
123 opp_def_list_update_opp_voltage(am33xx_es2_x_opp_list, 123 opp_def_list_update_opp_voltage(am33xx_es2_x_opp_list,
124 ARRAY_SIZE(am33xx_es2_x_opp_list), 124 ARRAY_SIZE(am33xx_es2_x_opp_list),
125 "mpu", 300000000, 1100000); 125 "mpu", 300000000, 1100000);
126 opp_def_list_enable_opp(am33xx_es2_x_opp_list, 126 opp_def_list_enable_opp(am33xx_es2_x_opp_list,
127 ARRAY_SIZE(am33xx_es2_x_opp_list), 127 ARRAY_SIZE(am33xx_es2_x_opp_list),
128 "mpu", 300000000, true); 128 "mpu", 300000000, true);
129 } else if (max_freq & EFUSE_OPP_50_300MHZ_BIT) { 129 } else if (max_freq & EFUSE_OPP_50_300MHZ_BIT) {
130 opp_def_list_enable_opp(am33xx_es2_x_opp_list, 130 opp_def_list_enable_opp(am33xx_es2_x_opp_list,
131 ARRAY_SIZE(am33xx_es2_x_opp_list), 131 ARRAY_SIZE(am33xx_es2_x_opp_list),
132 "mpu", 300000000, true); 132 "mpu", 300000000, true);
133 } else { 133 } else {
134 opp_def_list_enable_opp(am33xx_es2_x_opp_list, 134 opp_def_list_enable_opp(am33xx_es2_x_opp_list,
135 ARRAY_SIZE(am33xx_es2_x_opp_list), 135 ARRAY_SIZE(am33xx_es2_x_opp_list),
136 "mpu", 300000000, false); 136 "mpu", 300000000, false);
137 } 137 }
138 138
139 opp_def_list_enable_opp(am33xx_es2_x_opp_list, 139 opp_def_list_enable_opp(am33xx_es2_x_opp_list,
140 ARRAY_SIZE(am33xx_es2_x_opp_list), 140 ARRAY_SIZE(am33xx_es2_x_opp_list),
141 "mpu", 600000000, 141 "mpu", 600000000,
142 (max_freq & EFUSE_OPP_100_600MHZ_BIT) ? true : false); 142 (max_freq & EFUSE_OPP_100_600MHZ_BIT) ? true : false);
143 143
144 opp_def_list_enable_opp(am33xx_es2_x_opp_list, 144 opp_def_list_enable_opp(am33xx_es2_x_opp_list,
145 ARRAY_SIZE(am33xx_es2_x_opp_list), 145 ARRAY_SIZE(am33xx_es2_x_opp_list),
146 "mpu", 720000000, 146 "mpu", 720000000,
147 (max_freq & EFUSE_OPP_120_720MHZ_BIT) ? true : false); 147 (max_freq & EFUSE_OPP_120_720MHZ_BIT) ? true : false);
148 148
149 opp_def_list_enable_opp(am33xx_es2_x_opp_list, 149 opp_def_list_enable_opp(am33xx_es2_x_opp_list,
150 ARRAY_SIZE(am33xx_es2_x_opp_list), 150 ARRAY_SIZE(am33xx_es2_x_opp_list),
151 "mpu", 800000000, 151 "mpu", 800000000,
152 (max_freq & EFUSE_OPP_TURBO_800MHZ_BIT) ? true : false); 152 (max_freq & EFUSE_OPP_TURBO_800MHZ_BIT) ? true : false);
153 153
154 opp_def_list_enable_opp(am33xx_es2_x_opp_list, 154 opp_def_list_enable_opp(am33xx_es2_x_opp_list,
155 ARRAY_SIZE(am33xx_es2_x_opp_list), 155 ARRAY_SIZE(am33xx_es2_x_opp_list),
156 "mpu", 1000000000, 156 "mpu", 1000000000,
157 (max_freq & EFUSE_OPP_NITRO_1GHZ_BIT) ? true : false); 157 (max_freq & EFUSE_OPP_NITRO_1GHZ_BIT) ? true : false);
158 158
159 r = omap_init_opp_table(am33xx_es2_x_opp_list, 159 r = omap_init_opp_table(am33xx_es2_x_opp_list,
160 ARRAY_SIZE(am33xx_es2_x_opp_list)); 160 ARRAY_SIZE(am33xx_es2_x_opp_list));
161 break; 161 break;
162 162
163 case AM335X_REV_ES2_0: 163 case AM335X_REV_ES2_0:
164 /* FALLTHROUGH */ 164 /* FALLTHROUGH */
165 default: 165 default:
166 r = omap_init_opp_table(am33xx_es2_x_opp_list, 166 r = omap_init_opp_table(am33xx_es2_x_opp_list,
167 ARRAY_SIZE(am33xx_es2_x_opp_list)); 167 ARRAY_SIZE(am33xx_es2_x_opp_list));
168 } 168 }
169 169
170 return r; 170 return r;
171 } 171 }
172 172