Eric Lee / smarc-ti-linux-kernel

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/*

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/*

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* Texas Instruments Ethernet Switch Driver

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* Texas Instruments Ethernet Switch Driver

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*

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*

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*

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*

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* This program is free software; you can redistribute it and/or

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* This program is free software; you can redistribute it and/or

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* modify it under the terms of the GNU General Public License as

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* modify it under the terms of the GNU General Public License as

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* published by the Free Software Foundation version 2.

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* published by the Free Software Foundation version 2.

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*

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*

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* This program is distributed "as is" WITHOUT ANY WARRANTY of any

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* This program is distributed "as is" WITHOUT ANY WARRANTY of any

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* kind, whether express or implied; without even the implied warranty

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* kind, whether express or implied; without even the implied warranty

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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*/

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*/

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/io.h>

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#include <linux/io.h>

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#include <linux/clk.h>

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#include <linux/clk.h>

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#include <linux/timer.h>

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#include <linux/timer.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/platform_device.h>

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#include <linux/platform_device.h>

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#include <linux/irqreturn.h>

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#include <linux/irqreturn.h>

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#include <linux/interrupt.h>

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#include <linux/interrupt.h>

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#include <linux/if_ether.h>

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#include <linux/if_ether.h>

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#include <linux/etherdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/netdevice.h>

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#include <linux/netdevice.h>

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#include <linux/net_tstamp.h>

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#include <linux/net_tstamp.h>

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#include <linux/phy.h>

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#include <linux/phy.h>

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#include <linux/workqueue.h>

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#include <linux/workqueue.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/pm_runtime.h>

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#include <linux/pm_runtime.h>

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#include <linux/of.h>

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#include <linux/of.h>

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#include <linux/of_net.h>

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#include <linux/of_net.h>

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#include <linux/of_device.h>

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#include <linux/of_device.h>

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#include <linux/if_vlan.h>

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#include <linux/if_vlan.h>

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#include <linux/mfd/syscon.h>

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#include <linux/mfd/syscon.h>

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#include <linux/regmap.h>

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#include <linux/regmap.h>

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#include <linux/pinctrl/consumer.h>

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#include <linux/pinctrl/consumer.h>

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#include "cpsw.h"

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#include "cpsw.h"

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#include "cpsw_ale.h"

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#include "cpsw_ale.h"

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#include "cpts.h"

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#include "cpts.h"

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#include "davinci_cpdma.h"

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#include "davinci_cpdma.h"

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#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \

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#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \

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NETIF_MSG_DRV | NETIF_MSG_LINK | \

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NETIF_MSG_DRV | NETIF_MSG_LINK | \

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NETIF_MSG_IFUP | NETIF_MSG_INTR | \

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NETIF_MSG_IFUP | NETIF_MSG_INTR | \

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NETIF_MSG_PROBE | NETIF_MSG_TIMER | \

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NETIF_MSG_PROBE | NETIF_MSG_TIMER | \

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NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \

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NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \

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NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \

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NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \

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NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \

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NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \

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NETIF_MSG_RX_STATUS)

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NETIF_MSG_RX_STATUS)

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#define cpsw_info(priv, type, format, ...) \

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#define cpsw_info(priv, type, format, ...) \

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do { \

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do { \

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if (netif_msg_##type(priv) && net_ratelimit()) \

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if (netif_msg_##type(priv) && net_ratelimit()) \

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dev_info(priv->dev, format, ## __VA_ARGS__); \

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dev_info(priv->dev, format, ## __VA_ARGS__); \

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} while (0)

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} while (0)

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#define cpsw_err(priv, type, format, ...) \

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#define cpsw_err(priv, type, format, ...) \

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do { \

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do { \

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if (netif_msg_##type(priv) && net_ratelimit()) \

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if (netif_msg_##type(priv) && net_ratelimit()) \

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dev_err(priv->dev, format, ## __VA_ARGS__); \

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dev_err(priv->dev, format, ## __VA_ARGS__); \

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} while (0)

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} while (0)

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#define cpsw_dbg(priv, type, format, ...) \

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#define cpsw_dbg(priv, type, format, ...) \

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do { \

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do { \

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if (netif_msg_##type(priv) && net_ratelimit()) \

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if (netif_msg_##type(priv) && net_ratelimit()) \

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dev_dbg(priv->dev, format, ## __VA_ARGS__); \

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dev_dbg(priv->dev, format, ## __VA_ARGS__); \

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} while (0)

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} while (0)

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#define cpsw_notice(priv, type, format, ...) \

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#define cpsw_notice(priv, type, format, ...) \

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do { \

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do { \

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if (netif_msg_##type(priv) && net_ratelimit()) \

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if (netif_msg_##type(priv) && net_ratelimit()) \

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dev_notice(priv->dev, format, ## __VA_ARGS__); \

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dev_notice(priv->dev, format, ## __VA_ARGS__); \

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} while (0)

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} while (0)

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#define ALE_ALL_PORTS 0x7

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#define ALE_ALL_PORTS 0x7

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#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)

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#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)

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#define CPSW_MINOR_VERSION(reg) (reg & 0xff)

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#define CPSW_MINOR_VERSION(reg) (reg & 0xff)

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#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)

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#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)

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#define CPSW_VERSION_1 0x19010a

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#define CPSW_VERSION_1 0x19010a

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#define CPSW_VERSION_2 0x19010c

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#define CPSW_VERSION_2 0x19010c

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#define CPSW_VERSION_3 0x19010f

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#define CPSW_VERSION_3 0x19010f

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#define CPSW_VERSION_4 0x190112

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#define CPSW_VERSION_4 0x190112

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#define HOST_PORT_NUM 0

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#define HOST_PORT_NUM 0

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#define SLIVER_SIZE 0x40

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#define SLIVER_SIZE 0x40

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#define CPSW1_HOST_PORT_OFFSET 0x028

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#define CPSW1_HOST_PORT_OFFSET 0x028

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#define CPSW1_SLAVE_OFFSET 0x050

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#define CPSW1_SLAVE_OFFSET 0x050

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#define CPSW1_SLAVE_SIZE 0x040

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#define CPSW1_SLAVE_SIZE 0x040

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#define CPSW1_CPDMA_OFFSET 0x100

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#define CPSW1_CPDMA_OFFSET 0x100

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#define CPSW1_STATERAM_OFFSET 0x200

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#define CPSW1_STATERAM_OFFSET 0x200

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#define CPSW1_HW_STATS 0x400

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#define CPSW1_HW_STATS 0x400

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#define CPSW1_CPTS_OFFSET 0x500

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#define CPSW1_CPTS_OFFSET 0x500

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#define CPSW1_ALE_OFFSET 0x600

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#define CPSW1_ALE_OFFSET 0x600

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#define CPSW1_SLIVER_OFFSET 0x700

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#define CPSW1_SLIVER_OFFSET 0x700

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#define CPSW2_HOST_PORT_OFFSET 0x108

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#define CPSW2_HOST_PORT_OFFSET 0x108

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#define CPSW2_SLAVE_OFFSET 0x200

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#define CPSW2_SLAVE_OFFSET 0x200

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#define CPSW2_SLAVE_SIZE 0x100

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#define CPSW2_SLAVE_SIZE 0x100

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#define CPSW2_CPDMA_OFFSET 0x800

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#define CPSW2_CPDMA_OFFSET 0x800

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#define CPSW2_HW_STATS 0x900

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#define CPSW2_HW_STATS 0x900

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#define CPSW2_STATERAM_OFFSET 0xa00

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#define CPSW2_STATERAM_OFFSET 0xa00

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#define CPSW2_CPTS_OFFSET 0xc00

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#define CPSW2_CPTS_OFFSET 0xc00

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#define CPSW2_ALE_OFFSET 0xd00

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#define CPSW2_ALE_OFFSET 0xd00

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#define CPSW2_SLIVER_OFFSET 0xd80

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#define CPSW2_SLIVER_OFFSET 0xd80

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#define CPSW2_BD_OFFSET 0x2000

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#define CPSW2_BD_OFFSET 0x2000

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#define CPDMA_RXTHRESH 0x0c0

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#define CPDMA_RXTHRESH 0x0c0

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#define CPDMA_RXFREE 0x0e0

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#define CPDMA_RXFREE 0x0e0

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#define CPDMA_TXHDP 0x00

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#define CPDMA_TXHDP 0x00

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#define CPDMA_RXHDP 0x20

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#define CPDMA_RXHDP 0x20

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#define CPDMA_TXCP 0x40

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#define CPDMA_TXCP 0x40

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#define CPDMA_RXCP 0x60

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#define CPDMA_RXCP 0x60

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#define CPSW_POLL_WEIGHT 64

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#define CPSW_POLL_WEIGHT 64

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#define CPSW_MIN_PACKET_SIZE 60

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#define CPSW_MIN_PACKET_SIZE 60

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#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)

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#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)

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#define RX_PRIORITY_MAPPING 0x76543210

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#define RX_PRIORITY_MAPPING 0x76543210

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#define TX_PRIORITY_MAPPING 0x33221100

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#define TX_PRIORITY_MAPPING 0x33221100

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#define CPDMA_TX_PRIORITY_MAP 0x76543210

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#define CPDMA_TX_PRIORITY_MAP 0x76543210

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#define CPSW_VLAN_AWARE BIT(1)

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#define CPSW_VLAN_AWARE BIT(1)

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#define CPSW_ALE_VLAN_AWARE 1

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#define CPSW_ALE_VLAN_AWARE 1

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#define CPSW_FIFO_NORMAL_MODE (0 << 16)

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#define CPSW_FIFO_NORMAL_MODE (0 << 16)

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#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)

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#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)

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#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)

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#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)

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#define CPSW_INTPACEEN (0x3f << 16)

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#define CPSW_INTPACEEN (0x3f << 16)

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#define CPSW_INTPRESCALE_MASK (0x7FF << 0)

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#define CPSW_INTPRESCALE_MASK (0x7FF << 0)

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#define CPSW_CMINTMAX_CNT 63

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#define CPSW_CMINTMAX_CNT 63

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#define CPSW_CMINTMIN_CNT 2

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#define CPSW_CMINTMIN_CNT 2

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#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)

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#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)

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#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)

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#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)

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#define cpsw_enable_irq(priv) \

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#define cpsw_enable_irq(priv) \

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do { \

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do { \

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u32 i; \

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u32 i; \

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for (i = 0; i < priv->num_irqs; i++) \

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for (i = 0; i < priv->num_irqs; i++) \

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enable_irq(priv->irqs_table[i]); \

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enable_irq(priv->irqs_table[i]); \

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} while (0)

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} while (0)

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#define cpsw_disable_irq(priv) \

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#define cpsw_disable_irq(priv) \

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do { \

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do { \

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u32 i; \

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u32 i; \

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for (i = 0; i < priv->num_irqs; i++) \

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for (i = 0; i < priv->num_irqs; i++) \

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disable_irq_nosync(priv->irqs_table[i]); \

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disable_irq_nosync(priv->irqs_table[i]); \

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} while (0)

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} while (0)

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#define cpsw_slave_index(priv) \

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#define cpsw_slave_index(priv) \

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((priv->data.dual_emac) ? priv->emac_port : \

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((priv->data.dual_emac) ? priv->emac_port : \

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priv->data.active_slave)

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priv->data.active_slave)

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static int debug_level;

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static int debug_level;

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module_param(debug_level, int, 0);

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module_param(debug_level, int, 0);

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MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");

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MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");

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static int ale_ageout = 10;

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static int ale_ageout = 10;

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module_param(ale_ageout, int, 0);

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module_param(ale_ageout, int, 0);

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MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");

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MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");

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static int rx_packet_max = CPSW_MAX_PACKET_SIZE;

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static int rx_packet_max = CPSW_MAX_PACKET_SIZE;

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module_param(rx_packet_max, int, 0);

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module_param(rx_packet_max, int, 0);

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MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");

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MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");

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struct cpsw_wr_regs {

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struct cpsw_wr_regs {

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u32 id_ver;

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u32 id_ver;

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u32 soft_reset;

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u32 soft_reset;

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u32 control;

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u32 control;

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u32 int_control;

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u32 int_control;

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u32 rx_thresh_en;

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u32 rx_thresh_en;

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u32 rx_en;

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u32 rx_en;

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u32 tx_en;

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u32 tx_en;

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u32 misc_en;

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u32 misc_en;

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u32 mem_allign1[8];

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u32 mem_allign1[8];

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u32 rx_thresh_stat;

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u32 rx_thresh_stat;

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u32 rx_stat;

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u32 rx_stat;

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u32 tx_stat;

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u32 tx_stat;

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u32 misc_stat;

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u32 misc_stat;

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u32 mem_allign2[8];

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u32 mem_allign2[8];

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u32 rx_imax;

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u32 rx_imax;

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u32 tx_imax;

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u32 tx_imax;

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};

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};

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struct cpsw_ss_regs {

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struct cpsw_ss_regs {

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u32 id_ver;

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u32 id_ver;

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u32 control;

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u32 control;

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u32 soft_reset;

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u32 soft_reset;

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u32 stat_port_en;

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u32 stat_port_en;

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u32 ptype;

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u32 ptype;

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u32 soft_idle;

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u32 soft_idle;

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u32 thru_rate;

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u32 thru_rate;

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u32 gap_thresh;

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u32 gap_thresh;

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u32 tx_start_wds;

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u32 tx_start_wds;

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u32 flow_control;

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u32 flow_control;

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u32 vlan_ltype;

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u32 vlan_ltype;

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u32 ts_ltype;

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u32 ts_ltype;

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u32 dlr_ltype;

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u32 dlr_ltype;

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};

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};

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/* CPSW_PORT_V1 */

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/* CPSW_PORT_V1 */

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#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */

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#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */

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#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */

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#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */

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#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */

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#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */

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#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */

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#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */

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#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */

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#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */

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#define CPSW1_TS_CTL 0x14 /* Time Sync Control */

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#define CPSW1_TS_CTL 0x14 /* Time Sync Control */

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#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */

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#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */

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#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */

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#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */

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/* CPSW_PORT_V2 */

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/* CPSW_PORT_V2 */

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#define CPSW2_CONTROL 0x00 /* Control Register */

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#define CPSW2_CONTROL 0x00 /* Control Register */

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#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */

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#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */

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#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */

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#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */

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#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */

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#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */

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#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */

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#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */

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#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */

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#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */

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#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */

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#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */

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/* CPSW_PORT_V1 and V2 */

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/* CPSW_PORT_V1 and V2 */

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#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */

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#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */

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#define SA_HI 0x24 /* CPGMAC_SL Source Address High */

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#define SA_HI 0x24 /* CPGMAC_SL Source Address High */

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#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */

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#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */

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/* CPSW_PORT_V2 only */

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/* CPSW_PORT_V2 only */

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#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */

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#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */

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/* Bit definitions for the CPSW2_CONTROL register */

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/* Bit definitions for the CPSW2_CONTROL register */

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#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */

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#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */

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#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */

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#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */

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#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */

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#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */

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#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */

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#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */

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#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */

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#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */

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#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */

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#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */

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#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */

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#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */

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#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */

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#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */

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#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */

251

#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */

252

#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */

252

#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */

253

#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */

253

#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */

254

#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */

254

#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */

255

#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */

255

#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */

256

#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */

256

#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */

257

#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */

257

#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */

258

#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */

258

#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */

259

#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */

259

#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */

260

261

#define CTRL_V2_TS_BITS \

261

#define CTRL_V2_TS_BITS \

262

(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\

262

(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\

263

TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)

263

TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)

264

265

#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)

265

#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)

266

#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)

266

#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)

267

#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)

267

#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)

268

269

270

#define CTRL_V3_TS_BITS \

270

#define CTRL_V3_TS_BITS \

271

(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\

271

(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\

272

TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\

272

TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\

273

TS_LTYPE1_EN)

273

TS_LTYPE1_EN)

274

275

#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)

275

#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)

276

#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)

276

#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)

277

#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)

277

#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)

278

279

/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */

279

/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */

280

#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */

280

#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */

281

#define TS_SEQ_ID_OFFSET_MASK (0x3f)

281

#define TS_SEQ_ID_OFFSET_MASK (0x3f)

282

#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */

282

#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */

283

#define TS_MSG_TYPE_EN_MASK (0xffff)

283

#define TS_MSG_TYPE_EN_MASK (0xffff)

284

285

/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */

285

/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */

286

#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))

286

#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))

287

288

/* Bit definitions for the CPSW1_TS_CTL register */

288

/* Bit definitions for the CPSW1_TS_CTL register */

289

#define CPSW_V1_TS_RX_EN BIT(0)

289

#define CPSW_V1_TS_RX_EN BIT(0)

290

#define CPSW_V1_TS_TX_EN BIT(4)

290

#define CPSW_V1_TS_TX_EN BIT(4)

291

#define CPSW_V1_MSG_TYPE_OFS 16

291

#define CPSW_V1_MSG_TYPE_OFS 16

292

293

/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */

293

/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */

294

#define CPSW_V1_SEQ_ID_OFS_SHIFT 16

294

#define CPSW_V1_SEQ_ID_OFS_SHIFT 16

295

296

struct cpsw_host_regs {

296

struct cpsw_host_regs {

297

u32 max_blks;

297

u32 max_blks;

298

u32 blk_cnt;

298

u32 blk_cnt;

299

u32 tx_in_ctl;

299

u32 tx_in_ctl;

300

u32 port_vlan;

300

u32 port_vlan;

301

u32 tx_pri_map;

301

u32 tx_pri_map;

302

u32 cpdma_tx_pri_map;

302

u32 cpdma_tx_pri_map;

303

u32 cpdma_rx_chan_map;

303

u32 cpdma_rx_chan_map;

304

};

304

};

305

306

struct cpsw_sliver_regs {

306

struct cpsw_sliver_regs {

307

u32 id_ver;

307

u32 id_ver;

308

u32 mac_control;

308

u32 mac_control;

309

u32 mac_status;

309

u32 mac_status;

310

u32 soft_reset;

310

u32 soft_reset;

311

u32 rx_maxlen;

311

u32 rx_maxlen;

312

u32 __reserved_0;

312

u32 __reserved_0;

313

u32 rx_pause;

313

u32 rx_pause;

314

u32 tx_pause;

314

u32 tx_pause;

315

u32 __reserved_1;

315

u32 __reserved_1;

316

u32 rx_pri_map;

316

u32 rx_pri_map;

317

};

317

};

318

319

struct cpsw_hw_stats {

319

struct cpsw_hw_stats {

320

u32 rxgoodframes;

320

u32 rxgoodframes;

321

u32 rxbroadcastframes;

321

u32 rxbroadcastframes;

322

u32 rxmulticastframes;

322

u32 rxmulticastframes;

323

u32 rxpauseframes;

323

u32 rxpauseframes;

324

u32 rxcrcerrors;

324

u32 rxcrcerrors;

325

u32 rxaligncodeerrors;

325

u32 rxaligncodeerrors;

326

u32 rxoversizedframes;

326

u32 rxoversizedframes;

327

u32 rxjabberframes;

327

u32 rxjabberframes;

328

u32 rxundersizedframes;

328

u32 rxundersizedframes;

329

u32 rxfragments;

329

u32 rxfragments;

330

u32 __pad_0[2];

330

u32 __pad_0[2];

331

u32 rxoctets;

331

u32 rxoctets;

332

u32 txgoodframes;

332

u32 txgoodframes;

333

u32 txbroadcastframes;

333

u32 txbroadcastframes;

334

u32 txmulticastframes;

334

u32 txmulticastframes;

335

u32 txpauseframes;

335

u32 txpauseframes;

336

u32 txdeferredframes;

336

u32 txdeferredframes;

337

u32 txcollisionframes;

337

u32 txcollisionframes;

338

u32 txsinglecollframes;

338

u32 txsinglecollframes;

339

u32 txmultcollframes;

339

u32 txmultcollframes;

340

u32 txexcessivecollisions;

340

u32 txexcessivecollisions;

341

u32 txlatecollisions;

341

u32 txlatecollisions;

342

u32 txunderrun;

342

u32 txunderrun;

343

u32 txcarriersenseerrors;

343

u32 txcarriersenseerrors;

344

u32 txoctets;

344

u32 txoctets;

345

u32 octetframes64;

345

u32 octetframes64;

346

u32 octetframes65t127;

346

u32 octetframes65t127;

347

u32 octetframes128t255;

347

u32 octetframes128t255;

348

u32 octetframes256t511;

348

u32 octetframes256t511;

349

u32 octetframes512t1023;

349

u32 octetframes512t1023;

350

u32 octetframes1024tup;

350

u32 octetframes1024tup;

351

u32 netoctets;

351

u32 netoctets;

352

u32 rxsofoverruns;

352

u32 rxsofoverruns;

353

u32 rxmofoverruns;

353

u32 rxmofoverruns;

354

u32 rxdmaoverruns;

354

u32 rxdmaoverruns;

355

};

355

};

356

357

struct cpsw_slave {

357

struct cpsw_slave {

358

void __iomem *regs;

358

void __iomem *regs;

359

struct cpsw_sliver_regs __iomem *sliver;

359

struct cpsw_sliver_regs __iomem *sliver;

360

int slave_num;

360

int slave_num;

361

u32 mac_control;

361

u32 mac_control;

362

struct cpsw_slave_data *data;

362

struct cpsw_slave_data *data;

363

struct phy_device *phy;

363

struct phy_device *phy;

364

struct net_device *ndev;

364

struct net_device *ndev;

365

u32 port_vlan;

365

u32 port_vlan;

366

u32 open_stat;

366

u32 open_stat;

367

};

367

};

368

369

static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)

369

static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)

370

{

370

{

371

return __raw_readl(slave->regs + offset);

371

return __raw_readl(slave->regs + offset);

372

}

372

}

373

374

static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)

374

static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)

375

{

375

{

376

__raw_writel(val, slave->regs + offset);

376

__raw_writel(val, slave->regs + offset);

377

}

377

}

378

379

struct cpsw_priv {

379

struct cpsw_priv {

380

spinlock_t lock;

380

spinlock_t lock;

381

struct platform_device *pdev;

381

struct platform_device *pdev;

382

struct net_device *ndev;

382

struct net_device *ndev;

383

struct napi_struct napi;

383

struct napi_struct napi;

384

struct device *dev;

384

struct device *dev;

385

struct cpsw_platform_data data;

385

struct cpsw_platform_data data;

386

struct cpsw_ss_regs __iomem *regs;

386

struct cpsw_ss_regs __iomem *regs;

387

struct cpsw_wr_regs __iomem *wr_regs;

387

struct cpsw_wr_regs __iomem *wr_regs;

388

u8 __iomem *hw_stats;

388

u8 __iomem *hw_stats;

389

struct cpsw_host_regs __iomem *host_port_regs;

389

struct cpsw_host_regs __iomem *host_port_regs;

390

u32 msg_enable;

390

u32 msg_enable;

391

u32 version;

391

u32 version;

392

u32 coal_intvl;

392

u32 coal_intvl;

393

u32 bus_freq_mhz;

393

u32 bus_freq_mhz;

394

int rx_packet_max;

394

int rx_packet_max;

395

int host_port;

395

int host_port;

396

struct clk *clk;

396

struct clk *clk;

397

u8 mac_addr[ETH_ALEN];

397

u8 mac_addr[ETH_ALEN];

398

struct cpsw_slave *slaves;

398

struct cpsw_slave *slaves;

399

struct cpdma_ctlr *dma;

399

struct cpdma_ctlr *dma;

400

struct cpdma_chan *txch, *rxch;

400

struct cpdma_chan *txch, *rxch;

401

struct cpsw_ale *ale;

401

struct cpsw_ale *ale;

402

bool rx_pause;

402

bool rx_pause;

403

bool tx_pause;

403

bool tx_pause;

404

/* snapshot of IRQ numbers */

404

/* snapshot of IRQ numbers */

405

u32 irqs_table[4];

405

u32 irqs_table[4];

406

u32 num_irqs;

406

u32 num_irqs;

407

bool irq_enabled;

407

bool irq_enabled;

408

struct cpts *cpts;

408

struct cpts *cpts;

409

u32 emac_port;

409

u32 emac_port;

410

};

410

};

411

412

struct cpsw_stats {

412

struct cpsw_stats {

413

char stat_string[ETH_GSTRING_LEN];

413

char stat_string[ETH_GSTRING_LEN];

414

int type;

414

int type;

415

int sizeof_stat;

415

int sizeof_stat;

416

int stat_offset;

416

int stat_offset;

417

};

417

};

418

419

enum {

419

enum {

420

CPSW_STATS,

420

CPSW_STATS,

421

CPDMA_RX_STATS,

421

CPDMA_RX_STATS,

422

CPDMA_TX_STATS,

422

CPDMA_TX_STATS,

423

};

423

};

424

425

#define CPSW_STAT(m) CPSW_STATS, \

425

#define CPSW_STAT(m) CPSW_STATS, \

426

sizeof(((struct cpsw_hw_stats *)0)->m), \

426

sizeof(((struct cpsw_hw_stats *)0)->m), \

427

offsetof(struct cpsw_hw_stats, m)

427

offsetof(struct cpsw_hw_stats, m)

428

#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \

428

#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \

429

sizeof(((struct cpdma_chan_stats *)0)->m), \

429

sizeof(((struct cpdma_chan_stats *)0)->m), \

430

offsetof(struct cpdma_chan_stats, m)

430

offsetof(struct cpdma_chan_stats, m)

431

#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \

431

#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \

432

sizeof(((struct cpdma_chan_stats *)0)->m), \

432

sizeof(((struct cpdma_chan_stats *)0)->m), \

433

offsetof(struct cpdma_chan_stats, m)

433

offsetof(struct cpdma_chan_stats, m)

434

435

static const struct cpsw_stats cpsw_gstrings_stats[] = {

435

static const struct cpsw_stats cpsw_gstrings_stats[] = {

436

{ "Good Rx Frames", CPSW_STAT(rxgoodframes) },

436

{ "Good Rx Frames", CPSW_STAT(rxgoodframes) },

437

{ "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },

437

{ "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },

438

{ "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },

438

{ "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },

439

{ "Pause Rx Frames", CPSW_STAT(rxpauseframes) },

439

{ "Pause Rx Frames", CPSW_STAT(rxpauseframes) },

440

{ "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },

440

{ "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },

441

{ "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },

441

{ "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },

442

{ "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },

442

{ "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },

443

{ "Rx Jabbers", CPSW_STAT(rxjabberframes) },

443

{ "Rx Jabbers", CPSW_STAT(rxjabberframes) },

444

{ "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },

444

{ "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },

445

{ "Rx Fragments", CPSW_STAT(rxfragments) },

445

{ "Rx Fragments", CPSW_STAT(rxfragments) },

446

{ "Rx Octets", CPSW_STAT(rxoctets) },

446

{ "Rx Octets", CPSW_STAT(rxoctets) },

447

{ "Good Tx Frames", CPSW_STAT(txgoodframes) },

447

{ "Good Tx Frames", CPSW_STAT(txgoodframes) },

448

{ "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },

448

{ "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },

449

{ "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },

449

{ "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },

450

{ "Pause Tx Frames", CPSW_STAT(txpauseframes) },

450

{ "Pause Tx Frames", CPSW_STAT(txpauseframes) },

451

{ "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },

451

{ "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },

452

{ "Collisions", CPSW_STAT(txcollisionframes) },

452

{ "Collisions", CPSW_STAT(txcollisionframes) },

453

{ "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },

453

{ "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },

454

{ "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },

454

{ "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },

455

{ "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },

455

{ "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },

456

{ "Late Collisions", CPSW_STAT(txlatecollisions) },

456

{ "Late Collisions", CPSW_STAT(txlatecollisions) },

457

{ "Tx Underrun", CPSW_STAT(txunderrun) },

457

{ "Tx Underrun", CPSW_STAT(txunderrun) },

458

{ "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },

458

{ "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },

459

{ "Tx Octets", CPSW_STAT(txoctets) },

459

{ "Tx Octets", CPSW_STAT(txoctets) },

460

{ "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },

460

{ "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },

461

{ "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },

461

{ "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },

462

{ "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },

462

{ "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },

463

{ "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },

463

{ "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },

464

{ "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },

464

{ "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },

465

{ "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },

465

{ "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },

466

{ "Net Octets", CPSW_STAT(netoctets) },

466

{ "Net Octets", CPSW_STAT(netoctets) },

467

{ "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },

467

{ "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },

468

{ "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },

468

{ "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },

469

{ "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },

469

{ "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },

470

{ "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },

470

{ "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },

471

{ "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },

471

{ "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },

472

{ "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },

472

{ "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },

473

{ "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },

473

{ "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },

474

{ "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },

474

{ "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },

475

{ "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },

475

{ "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },

476

{ "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },

476

{ "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },

477

{ "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },

477

{ "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },

478

{ "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },

478

{ "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },

479

{ "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },

479

{ "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },

480

{ "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },

480

{ "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },

481

{ "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },

481

{ "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },

482

{ "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },

482

{ "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },

483

{ "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },

483

{ "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },

484

{ "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },

484

{ "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },

485

{ "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },

485

{ "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },

486

{ "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },

486

{ "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },

487

{ "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },

487

{ "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },

488

{ "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },

488

{ "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },

489

{ "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },

489

{ "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },

490

{ "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },

490

{ "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },

491

{ "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },

491

{ "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },

492

{ "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },

492

{ "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },

493

{ "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },

493

{ "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },

494

{ "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },

494

{ "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },

495

{ "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },

495

{ "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },

496

};

496

};

497

498

#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)

498

#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)

499

500

#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)

500

#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)

501

#define for_each_slave(priv, func, arg...) \

501

#define for_each_slave(priv, func, arg...) \

502

do { \

502

do { \

503

struct cpsw_slave *slave; \

503

struct cpsw_slave *slave; \

504

int n; \

504

int n; \

505

if (priv->data.dual_emac) \

505

if (priv->data.dual_emac) \

506

(func)((priv)->slaves + priv->emac_port, ##arg);\

506

(func)((priv)->slaves + priv->emac_port, ##arg);\

507

else \

507

else \

508

for (n = (priv)->data.slaves, \

508

for (n = (priv)->data.slaves, \

509

slave = (priv)->slaves; \

509

slave = (priv)->slaves; \

510

n; n--) \

510

n; n--) \

511

(func)(slave++, ##arg); \

511

(func)(slave++, ##arg); \

512

} while (0)

512

} while (0)

513

#define cpsw_get_slave_ndev(priv, __slave_no__) \

513

#define cpsw_get_slave_ndev(priv, __slave_no__) \

514

(priv->slaves[__slave_no__].ndev)

514

(priv->slaves[__slave_no__].ndev)

515

#define cpsw_get_slave_priv(priv, __slave_no__) \

515

#define cpsw_get_slave_priv(priv, __slave_no__) \

516

((priv->slaves[__slave_no__].ndev) ? \

516

((priv->slaves[__slave_no__].ndev) ? \

517

netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \

517

netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \

518

519

#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \

519

#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \

520

do { \

520

do { \

521

if (!priv->data.dual_emac) \

521

if (!priv->data.dual_emac) \

522

break; \

522

break; \

523

if (CPDMA_RX_SOURCE_PORT(status) == 1) { \

523

if (CPDMA_RX_SOURCE_PORT(status) == 1) { \

524

ndev = cpsw_get_slave_ndev(priv, 0); \

524

ndev = cpsw_get_slave_ndev(priv, 0); \

525

priv = netdev_priv(ndev); \

525

priv = netdev_priv(ndev); \

526

skb->dev = ndev; \

526

skb->dev = ndev; \

527

} else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \

527

} else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \

528

ndev = cpsw_get_slave_ndev(priv, 1); \

528

ndev = cpsw_get_slave_ndev(priv, 1); \

529

priv = netdev_priv(ndev); \

529

priv = netdev_priv(ndev); \

530

skb->dev = ndev; \

530

skb->dev = ndev; \

531

} \

531

} \

532

} while (0)

532

} while (0)

533

#define cpsw_add_mcast(priv, addr) \

533

#define cpsw_add_mcast(priv, addr) \

534

do { \

534

do { \

535

if (priv->data.dual_emac) { \

535

if (priv->data.dual_emac) { \

536

struct cpsw_slave *slave = priv->slaves + \

536

struct cpsw_slave *slave = priv->slaves + \

537

priv->emac_port; \

537

priv->emac_port; \

538

int slave_port = cpsw_get_slave_port(priv, \

538

int slave_port = cpsw_get_slave_port(priv, \

539

slave->slave_num); \

539

slave->slave_num); \

540

cpsw_ale_add_mcast(priv->ale, addr, \

540

cpsw_ale_add_mcast(priv->ale, addr, \

541

1 << slave_port | 1 << priv->host_port, \

541

1 << slave_port | 1 << priv->host_port, \

542

ALE_VLAN, slave->port_vlan, 0); \

542

ALE_VLAN, slave->port_vlan, 0); \

543

} else { \

543

} else { \

544

cpsw_ale_add_mcast(priv->ale, addr, \

544

cpsw_ale_add_mcast(priv->ale, addr, \

545

ALE_ALL_PORTS << priv->host_port, \

545

ALE_ALL_PORTS << priv->host_port, \

546

0, 0, 0); \

546

0, 0, 0); \

547

} \

547

} \

548

} while (0)

548

} while (0)

549

550

static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)

550

static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)

551

{

551

{

552

if (priv->host_port == 0)

552

if (priv->host_port == 0)

553

return slave_num + 1;

553

return slave_num + 1;

554

else

554

else

555

return slave_num;

555

return slave_num;

556

}

556

}

557

558

static void cpsw_set_promiscious(struct net_device *ndev, bool enable)

558

static void cpsw_set_promiscious(struct net_device *ndev, bool enable)

559

{

559

{

560

struct cpsw_priv *priv = netdev_priv(ndev);

560

struct cpsw_priv *priv = netdev_priv(ndev);

561

struct cpsw_ale *ale = priv->ale;

561

struct cpsw_ale *ale = priv->ale;

562

int i;

562

int i;

563

564

if (priv->data.dual_emac) {

564

if (priv->data.dual_emac) {

565

bool flag = false;

565

bool flag = false;

566

567

/* Enabling promiscuous mode for one interface will be

567

/* Enabling promiscuous mode for one interface will be

568

* common for both the interface as the interface shares

568

* common for both the interface as the interface shares

569

* the same hardware resource.

569

* the same hardware resource.

570

*/

570

*/

571

for (i = 0; i < priv->data.slaves; i++)

571

for (i = 0; i < priv->data.slaves; i++)

572

if (priv->slaves[i].ndev->flags & IFF_PROMISC)

572

if (priv->slaves[i].ndev->flags & IFF_PROMISC)

573

flag = true;

573

flag = true;

574

575

if (!enable && flag) {

575

if (!enable && flag) {

576

enable = true;

576

enable = true;

577

dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");

577

dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");

578

}

578

}

579

580

if (enable) {

580

if (enable) {

581

/* Enable Bypass */

581

/* Enable Bypass */

582

cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);

582

cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);

583

584

dev_dbg(&ndev->dev, "promiscuity enabled\n");

584

dev_dbg(&ndev->dev, "promiscuity enabled\n");

585

} else {

585

} else {

586

/* Disable Bypass */

586

/* Disable Bypass */

587

cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);

587

cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);

588

dev_dbg(&ndev->dev, "promiscuity disabled\n");

588

dev_dbg(&ndev->dev, "promiscuity disabled\n");

589

}

589

}

590

} else {

590

} else {

591

if (enable) {

591

if (enable) {

592

unsigned long timeout = jiffies + HZ;

592

unsigned long timeout = jiffies + HZ;

593

594

/* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */

594

/* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */

595

for (i = 0; i <= priv->data.slaves; i++) {

595

for (i = 0; i <= priv->data.slaves; i++) {

596

cpsw_ale_control_set(ale, i,

596

cpsw_ale_control_set(ale, i,

597

ALE_PORT_NOLEARN, 1);

597

ALE_PORT_NOLEARN, 1);

598

cpsw_ale_control_set(ale, i,

598

cpsw_ale_control_set(ale, i,

599

ALE_PORT_NO_SA_UPDATE, 1);

599

ALE_PORT_NO_SA_UPDATE, 1);

600

}

600

}

601

602

/* Clear All Untouched entries */

602

/* Clear All Untouched entries */

603

cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);

603

cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);

604

do {

604

do {

605

cpu_relax();

605

cpu_relax();

606

if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))

606

if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))

607

break;

607

break;

608

} while (time_after(timeout, jiffies));

608

} while (time_after(timeout, jiffies));

609

cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);

609

cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);

610

611

/* Clear all mcast from ALE */

611

/* Clear all mcast from ALE */

612

cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<

612

cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<

613

priv->host_port, -1);

613

priv->host_port, -1);

614

615

/* Flood All Unicast Packets to Host port */

615

/* Flood All Unicast Packets to Host port */

616

cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);

616

cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);

617

dev_dbg(&ndev->dev, "promiscuity enabled\n");

617

dev_dbg(&ndev->dev, "promiscuity enabled\n");

618

} else {

618

} else {

619

/* Don't Flood All Unicast Packets to Host port */

619

/* Don't Flood All Unicast Packets to Host port */

620

cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);

620

cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);

621

622

/* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */

622

/* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */

623

for (i = 0; i <= priv->data.slaves; i++) {

623

for (i = 0; i <= priv->data.slaves; i++) {

624

cpsw_ale_control_set(ale, i,

624

cpsw_ale_control_set(ale, i,

625

ALE_PORT_NOLEARN, 0);

625

ALE_PORT_NOLEARN, 0);

626

cpsw_ale_control_set(ale, i,

626

cpsw_ale_control_set(ale, i,

627

ALE_PORT_NO_SA_UPDATE, 0);

627

ALE_PORT_NO_SA_UPDATE, 0);

628

}

628

}

629

dev_dbg(&ndev->dev, "promiscuity disabled\n");

629

dev_dbg(&ndev->dev, "promiscuity disabled\n");

630

}

630

}

631

}

631

}

632

}

632

}

633

634

static void cpsw_ndo_set_rx_mode(struct net_device *ndev)

634

static void cpsw_ndo_set_rx_mode(struct net_device *ndev)

635

{

635

{

636

struct cpsw_priv *priv = netdev_priv(ndev);

636

struct cpsw_priv *priv = netdev_priv(ndev);

637

int vid;

637

int vid;

638

639

if (priv->data.dual_emac)

639

if (priv->data.dual_emac)

640

vid = priv->slaves[priv->emac_port].port_vlan;

640

vid = priv->slaves[priv->emac_port].port_vlan;

641

else

641

else

642

vid = priv->data.default_vlan;

642

vid = priv->data.default_vlan;

643

644

if (ndev->flags & IFF_PROMISC) {

644

if (ndev->flags & IFF_PROMISC) {

645

/* Enable promiscuous mode */

645

/* Enable promiscuous mode */

646

cpsw_set_promiscious(ndev, true);

646

cpsw_set_promiscious(ndev, true);

647

cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);

647

cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);

648

return;

648

return;

649

} else {

649

} else {

650

/* Disable promiscuous mode */

650

/* Disable promiscuous mode */

651

cpsw_set_promiscious(ndev, false);

651

cpsw_set_promiscious(ndev, false);

652

}

652

}

653

654

/* Restore allmulti on vlans if necessary */

654

/* Restore allmulti on vlans if necessary */

655

cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);

655

cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);

656

657

/* Clear all mcast from ALE */

657

/* Clear all mcast from ALE */

658

cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,

658

cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,

659

vid);

659

vid);

660

661

if (!netdev_mc_empty(ndev)) {

661

if (!netdev_mc_empty(ndev)) {

662

struct netdev_hw_addr *ha;

662

struct netdev_hw_addr *ha;

663

664

/* program multicast address list into ALE register */

664

/* program multicast address list into ALE register */

665

netdev_for_each_mc_addr(ha, ndev) {

665

netdev_for_each_mc_addr(ha, ndev) {

666

cpsw_add_mcast(priv, (u8 *)ha->addr);

666

cpsw_add_mcast(priv, (u8 *)ha->addr);

667

}

667

}

668

}

668

}

669

}

669

}

670

671

static void cpsw_intr_enable(struct cpsw_priv *priv)

671

static void cpsw_intr_enable(struct cpsw_priv *priv)

672

{

672

{

673

__raw_writel(0xFF, &priv->wr_regs->tx_en);

673

__raw_writel(0xFF, &priv->wr_regs->tx_en);

674

__raw_writel(0xFF, &priv->wr_regs->rx_en);

674

__raw_writel(0xFF, &priv->wr_regs->rx_en);

675

676

cpdma_ctlr_int_ctrl(priv->dma, true);

676

cpdma_ctlr_int_ctrl(priv->dma, true);

677

return;

677

return;

678

}

678

}

679

680

static void cpsw_intr_disable(struct cpsw_priv *priv)

680

static void cpsw_intr_disable(struct cpsw_priv *priv)

681

{

681

{

682

__raw_writel(0, &priv->wr_regs->tx_en);

682

__raw_writel(0, &priv->wr_regs->tx_en);

683

__raw_writel(0, &priv->wr_regs->rx_en);

683

__raw_writel(0, &priv->wr_regs->rx_en);

684

685

cpdma_ctlr_int_ctrl(priv->dma, false);

685

cpdma_ctlr_int_ctrl(priv->dma, false);

686

return;

686

return;

687

}

687

}

688

689

static void cpsw_tx_handler(void *token, int len, int status)

689

static void cpsw_tx_handler(void *token, int len, int status)

690

{

690

{

691

struct sk_buff *skb = token;

691

struct sk_buff *skb = token;

692

struct net_device *ndev = skb->dev;

692

struct net_device *ndev = skb->dev;

693

struct cpsw_priv *priv = netdev_priv(ndev);

693

struct cpsw_priv *priv = netdev_priv(ndev);

694

695

/* Check whether the queue is stopped due to stalled tx dma, if the

695

/* Check whether the queue is stopped due to stalled tx dma, if the

696

* queue is stopped then start the queue as we have free desc for tx

696

* queue is stopped then start the queue as we have free desc for tx

697

*/

697

*/

698

if (unlikely(netif_queue_stopped(ndev)))

698

if (unlikely(netif_queue_stopped(ndev)))

699

netif_wake_queue(ndev);

699

netif_wake_queue(ndev);

700

cpts_tx_timestamp(priv->cpts, skb);

700

cpts_tx_timestamp(priv->cpts, skb);

701

ndev->stats.tx_packets++;

701

ndev->stats.tx_packets++;

702

ndev->stats.tx_bytes += len;

702

ndev->stats.tx_bytes += len;

703

dev_kfree_skb_any(skb);

703

dev_kfree_skb_any(skb);

704

}

704

}

705

706

static void cpsw_rx_handler(void *token, int len, int status)

706

static void cpsw_rx_handler(void *token, int len, int status)

707

{

707

{

708

struct sk_buff *skb = token;

708

struct sk_buff *skb = token;

709

struct sk_buff *new_skb;

709

struct sk_buff *new_skb;

710

struct net_device *ndev = skb->dev;

710

struct net_device *ndev = skb->dev;

711

struct cpsw_priv *priv = netdev_priv(ndev);

711

struct cpsw_priv *priv = netdev_priv(ndev);

712

int ret = 0;

712

int ret = 0;

713

714

cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);

714

cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);

715

716

if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {

716

if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {

717

bool ndev_status = false;

717

bool ndev_status = false;

718

struct cpsw_slave *slave = priv->slaves;

718

struct cpsw_slave *slave = priv->slaves;

719

int n;

719

int n;

720

721

if (priv->data.dual_emac) {

721

if (priv->data.dual_emac) {

722

/* In dual emac mode check for all interfaces */

722

/* In dual emac mode check for all interfaces */

723

for (n = priv->data.slaves; n; n--, slave++)

723

for (n = priv->data.slaves; n; n--, slave++)

724

if (netif_running(slave->ndev))

724

if (netif_running(slave->ndev))

725

ndev_status = true;

725

ndev_status = true;

726

}

726

}

727

728

if (ndev_status && (status >= 0)) {

728

if (ndev_status && (status >= 0)) {

729

/* The packet received is for the interface which

729

/* The packet received is for the interface which

730

* is already down and the other interface is up

730

* is already down and the other interface is up

731

* and running, intead of freeing which results

731

* and running, intead of freeing which results

732

* in reducing of the number of rx descriptor in

732

* in reducing of the number of rx descriptor in

733

* DMA engine, requeue skb back to cpdma.

733

* DMA engine, requeue skb back to cpdma.

734

*/

734

*/

735

new_skb = skb;

735

new_skb = skb;

736

goto requeue;

736

goto requeue;

737

}

737

}

738

739

/* the interface is going down, skbs are purged */

739

/* the interface is going down, skbs are purged */

740

dev_kfree_skb_any(skb);

740

dev_kfree_skb_any(skb);

741

return;

741

return;

742

}

742

}

743

744

new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);

744

new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);

745

if (new_skb) {

745

if (new_skb) {

746

skb_put(skb, len);

746

skb_put(skb, len);

747

cpts_rx_timestamp(priv->cpts, skb);

747

cpts_rx_timestamp(priv->cpts, skb);

748

skb->protocol = eth_type_trans(skb, ndev);

748

skb->protocol = eth_type_trans(skb, ndev);

749

netif_receive_skb(skb);

749

netif_receive_skb(skb);

750

ndev->stats.rx_bytes += len;

750

ndev->stats.rx_bytes += len;

751

ndev->stats.rx_packets++;

751

ndev->stats.rx_packets++;

752

} else {

752

} else {

753

ndev->stats.rx_dropped++;

753

ndev->stats.rx_dropped++;

754

new_skb = skb;

754

new_skb = skb;

755

}

755

}

756

757

requeue:

757

requeue:

758

ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,

758

ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,

759

skb_tailroom(new_skb), 0);

759

skb_tailroom(new_skb), 0);

760

if (WARN_ON(ret < 0))

760

if (WARN_ON(ret < 0))

761

dev_kfree_skb_any(new_skb);

761

dev_kfree_skb_any(new_skb);

762

}

762

}

763

764

static irqreturn_t cpsw_interrupt(int irq, void *dev_id)

764

static irqreturn_t cpsw_interrupt(int irq, void *dev_id)

765

{

765

{

766

struct cpsw_priv *priv = dev_id;

766

struct cpsw_priv *priv = dev_id;

767

int value = irq - priv->irqs_table[0];

767

int value = irq - priv->irqs_table[0];

768

769

/* NOTICE: Ending IRQ here. The trick with the 'value' variable above

769

/* NOTICE: Ending IRQ here. The trick with the 'value' variable above

770

* is to make sure we will always write the correct value to the EOI

770

* is to make sure we will always write the correct value to the EOI

771

* register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2

771

* register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2

772

* for TX Interrupt and 3 for MISC Interrupt.

772

* for TX Interrupt and 3 for MISC Interrupt.

773

*/

773

*/

774

cpdma_ctlr_eoi(priv->dma, value);

774

cpdma_ctlr_eoi(priv->dma, value);

775

776

cpsw_intr_disable(priv);

776

cpsw_intr_disable(priv);

777

if (priv->irq_enabled == true) {

777

if (priv->irq_enabled == true) {

778

cpsw_disable_irq(priv);

778

cpsw_disable_irq(priv);

779

priv->irq_enabled = false;

779

priv->irq_enabled = false;

780

}

780

}

781

782

if (netif_running(priv->ndev)) {

782

if (netif_running(priv->ndev)) {

783

napi_schedule(&priv->napi);

783

napi_schedule(&priv->napi);

784

return IRQ_HANDLED;

784

return IRQ_HANDLED;

785

}

785

}

786

787

priv = cpsw_get_slave_priv(priv, 1);

787

priv = cpsw_get_slave_priv(priv, 1);

788

if (!priv)

788

if (!priv)

789

return IRQ_NONE;

789

return IRQ_NONE;

790

791

if (netif_running(priv->ndev)) {

791

if (netif_running(priv->ndev)) {

792

napi_schedule(&priv->napi);

792

napi_schedule(&priv->napi);

793

return IRQ_HANDLED;

793

return IRQ_HANDLED;

794

}

794

}

795

return IRQ_NONE;

795

return IRQ_NONE;

796

}

796

}

797

798

static int cpsw_poll(struct napi_struct *napi, int budget)

798

static int cpsw_poll(struct napi_struct *napi, int budget)

799

{

799

{

800

struct cpsw_priv *priv = napi_to_priv(napi);

800

struct cpsw_priv *priv = napi_to_priv(napi);

801

int num_tx, num_rx;

801

int num_tx, num_rx;

802

803

num_tx = cpdma_chan_process(priv->txch, 128);

803

num_tx = cpdma_chan_process(priv->txch, 128);

804

805

num_rx = cpdma_chan_process(priv->rxch, budget);

805

num_rx = cpdma_chan_process(priv->rxch, budget);

806

if (num_rx < budget) {

806

if (num_rx < budget) {

807

struct cpsw_priv *prim_cpsw;

807

struct cpsw_priv *prim_cpsw;

808

809

napi_complete(napi);

809

napi_complete(napi);

810

cpsw_intr_enable(priv);

810

cpsw_intr_enable(priv);

811

prim_cpsw = cpsw_get_slave_priv(priv, 0);

811

prim_cpsw = cpsw_get_slave_priv(priv, 0);

812

if (prim_cpsw->irq_enabled == false) {

812

if (prim_cpsw->irq_enabled == false) {

813

prim_cpsw->irq_enabled = true;

813

prim_cpsw->irq_enabled = true;

814

cpsw_enable_irq(priv);

814

cpsw_enable_irq(priv);

815

}

815

}

816

}

816

}

817

818

if (num_rx || num_tx)

818

if (num_rx || num_tx)

819

cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",

819

cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",

820

num_rx, num_tx);

820

num_rx, num_tx);

821

822

return num_rx;

822

return num_rx;

823

}

823

}

824

825

static inline void soft_reset(const char *module, void __iomem *reg)

825

static inline void soft_reset(const char *module, void __iomem *reg)

826

{

826

{

827

unsigned long timeout = jiffies + HZ;

827

unsigned long timeout = jiffies + HZ;

828

829

__raw_writel(1, reg);

829

__raw_writel(1, reg);

830

do {

830

do {

831

cpu_relax();

831

cpu_relax();

832

} while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));

832

} while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));

833

834

WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);

834

WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);

835

}

835

}

836

837

#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \

837

#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \

838

((mac)[2] << 16) | ((mac)[3] << 24))

838

((mac)[2] << 16) | ((mac)[3] << 24))

839

#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))

839

#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))

840

841

static void cpsw_set_slave_mac(struct cpsw_slave *slave,

841

static void cpsw_set_slave_mac(struct cpsw_slave *slave,

842

struct cpsw_priv *priv)

842

struct cpsw_priv *priv)

843

{

843

{

844

slave_write(slave, mac_hi(priv->mac_addr), SA_HI);

844

slave_write(slave, mac_hi(priv->mac_addr), SA_HI);

845

slave_write(slave, mac_lo(priv->mac_addr), SA_LO);

845

slave_write(slave, mac_lo(priv->mac_addr), SA_LO);

846

}

846

}

847

848

static void _cpsw_adjust_link(struct cpsw_slave *slave,

848

static void _cpsw_adjust_link(struct cpsw_slave *slave,

849

struct cpsw_priv *priv, bool *link)

849

struct cpsw_priv *priv, bool *link)

850

{

850

{

851

struct phy_device *phy = slave->phy;

851

struct phy_device *phy = slave->phy;

852

u32 mac_control = 0;

852

u32 mac_control = 0;

853

u32 slave_port;

853

u32 slave_port;

854

855

if (!phy)

855

if (!phy)

856

return;

856

return;

857

858

slave_port = cpsw_get_slave_port(priv, slave->slave_num);

858

slave_port = cpsw_get_slave_port(priv, slave->slave_num);

859

860

if (phy->link) {

860

if (phy->link) {

861

mac_control = priv->data.mac_control;

861

mac_control = priv->data.mac_control;

862

863

/* enable forwarding */

863

/* enable forwarding */

864

cpsw_ale_control_set(priv->ale, slave_port,

864

cpsw_ale_control_set(priv->ale, slave_port,

865

ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);

865

ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);

866

867

if (phy->speed == 1000)

867

if (phy->speed == 1000)

868

mac_control |= BIT(7); /* GIGABITEN */

868

mac_control |= BIT(7); /* GIGABITEN */

869

if (phy->duplex)

869

if (phy->duplex)

870

mac_control |= BIT(0); /* FULLDUPLEXEN */

870

mac_control |= BIT(0); /* FULLDUPLEXEN */

871

872

/* set speed_in input in case RMII mode is used in 100Mbps */

872

/* set speed_in input in case RMII mode is used in 100Mbps */

873

if (phy->speed == 100)

873

if (phy->speed == 100)

874

mac_control |= BIT(15);

874

mac_control |= BIT(15);

875

else if (phy->speed == 10)

875

else if (phy->speed == 10)

876

mac_control |= BIT(18); /* In Band mode */

876

mac_control |= BIT(18); /* In Band mode */

877

878

if (priv->rx_pause)

878

if (priv->rx_pause)

879

mac_control |= BIT(3);

879

mac_control |= BIT(3);

880

881

if (priv->tx_pause)

881

if (priv->tx_pause)

882

mac_control |= BIT(4);

882

mac_control |= BIT(4);

883

884

*link = true;

884

*link = true;

885

} else {

885

} else {

886

mac_control = 0;

886

mac_control = 0;

887

/* disable forwarding */

887

/* disable forwarding */

888

cpsw_ale_control_set(priv->ale, slave_port,

888

cpsw_ale_control_set(priv->ale, slave_port,

889

ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);

889

ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);

890

}

890

}

891

892

if (mac_control != slave->mac_control) {

892

if (mac_control != slave->mac_control) {

893

phy_print_status(phy);

893

phy_print_status(phy);

894

__raw_writel(mac_control, &slave->sliver->mac_control);

894

__raw_writel(mac_control, &slave->sliver->mac_control);

895

}

895

}

896

897

slave->mac_control = mac_control;

897

slave->mac_control = mac_control;

898

}

898

}

899

900

static void cpsw_adjust_link(struct net_device *ndev)

900

static void cpsw_adjust_link(struct net_device *ndev)

901

{

901

{

902

struct cpsw_priv *priv = netdev_priv(ndev);

902

struct cpsw_priv *priv = netdev_priv(ndev);

903

bool link = false;

903

bool link = false;

904

905

for_each_slave(priv, _cpsw_adjust_link, priv, &link);

905

for_each_slave(priv, _cpsw_adjust_link, priv, &link);

906

907

if (link) {

907

if (link) {

908

netif_carrier_on(ndev);

908

netif_carrier_on(ndev);

909

if (netif_running(ndev))

909

if (netif_running(ndev))

910

netif_wake_queue(ndev);

910

netif_wake_queue(ndev);

911

} else {

911

} else {

912

netif_carrier_off(ndev);

912

netif_carrier_off(ndev);

913

netif_stop_queue(ndev);

913

netif_stop_queue(ndev);

914

}

914

}

915

}

915

}

916

917

static int cpsw_get_coalesce(struct net_device *ndev,

917

static int cpsw_get_coalesce(struct net_device *ndev,

918

struct ethtool_coalesce *coal)

918

struct ethtool_coalesce *coal)

919

{

919

{

920

struct cpsw_priv *priv = netdev_priv(ndev);

920

struct cpsw_priv *priv = netdev_priv(ndev);

921

922

coal->rx_coalesce_usecs = priv->coal_intvl;

922

coal->rx_coalesce_usecs = priv->coal_intvl;

923

return 0;

923

return 0;

924

}

924

}

925

926

static int cpsw_set_coalesce(struct net_device *ndev,

926

static int cpsw_set_coalesce(struct net_device *ndev,

927

struct ethtool_coalesce *coal)

927

struct ethtool_coalesce *coal)

928

{

928

{

929

struct cpsw_priv *priv = netdev_priv(ndev);

929

struct cpsw_priv *priv = netdev_priv(ndev);

930

u32 int_ctrl;

930

u32 int_ctrl;

931

u32 num_interrupts = 0;

931

u32 num_interrupts = 0;

932

u32 prescale = 0;

932

u32 prescale = 0;

933

u32 addnl_dvdr = 1;

933

u32 addnl_dvdr = 1;

934

u32 coal_intvl = 0;

934

u32 coal_intvl = 0;

935

936

coal_intvl = coal->rx_coalesce_usecs;

936

coal_intvl = coal->rx_coalesce_usecs;

937

938

int_ctrl = readl(&priv->wr_regs->int_control);

938

int_ctrl = readl(&priv->wr_regs->int_control);

939

prescale = priv->bus_freq_mhz * 4;

939

prescale = priv->bus_freq_mhz * 4;

940

941

if (!coal->rx_coalesce_usecs) {

941

if (!coal->rx_coalesce_usecs) {

942

int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);

942

int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);

943

goto update_return;

943

goto update_return;

944

}

944

}

945

946

if (coal_intvl < CPSW_CMINTMIN_INTVL)

946

if (coal_intvl < CPSW_CMINTMIN_INTVL)

947

coal_intvl = CPSW_CMINTMIN_INTVL;

947

coal_intvl = CPSW_CMINTMIN_INTVL;

948

949

if (coal_intvl > CPSW_CMINTMAX_INTVL) {

949

if (coal_intvl > CPSW_CMINTMAX_INTVL) {

950

/* Interrupt pacer works with 4us Pulse, we can

950

/* Interrupt pacer works with 4us Pulse, we can

951

* throttle further by dilating the 4us pulse.

951

* throttle further by dilating the 4us pulse.

952

*/

952

*/

953

addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;

953

addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;

954

955

if (addnl_dvdr > 1) {

955

if (addnl_dvdr > 1) {

956

prescale *= addnl_dvdr;

956

prescale *= addnl_dvdr;

957

if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))

957

if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))

958

coal_intvl = (CPSW_CMINTMAX_INTVL

958

coal_intvl = (CPSW_CMINTMAX_INTVL

959

* addnl_dvdr);

959

* addnl_dvdr);

960

} else {

960

} else {

961

addnl_dvdr = 1;

961

addnl_dvdr = 1;

962

coal_intvl = CPSW_CMINTMAX_INTVL;

962

coal_intvl = CPSW_CMINTMAX_INTVL;

963

}

963

}

964

}

964

}

965

966

num_interrupts = (1000 * addnl_dvdr) / coal_intvl;

966

num_interrupts = (1000 * addnl_dvdr) / coal_intvl;

967

writel(num_interrupts, &priv->wr_regs->rx_imax);

967

writel(num_interrupts, &priv->wr_regs->rx_imax);

968

writel(num_interrupts, &priv->wr_regs->tx_imax);

968

writel(num_interrupts, &priv->wr_regs->tx_imax);

969

970

int_ctrl |= CPSW_INTPACEEN;

970

int_ctrl |= CPSW_INTPACEEN;

971

int_ctrl &= (~CPSW_INTPRESCALE_MASK);

971

int_ctrl &= (~CPSW_INTPRESCALE_MASK);

972

int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);

972

int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);

973

974

update_return:

974

update_return:

975

writel(int_ctrl, &priv->wr_regs->int_control);

975

writel(int_ctrl, &priv->wr_regs->int_control);

976

977

cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);

977

cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);

978

if (priv->data.dual_emac) {

978

if (priv->data.dual_emac) {

979

int i;

979

int i;

980

981

for (i = 0; i < priv->data.slaves; i++) {

981

for (i = 0; i < priv->data.slaves; i++) {

982

priv = netdev_priv(priv->slaves[i].ndev);

982

priv = netdev_priv(priv->slaves[i].ndev);

983

priv->coal_intvl = coal_intvl;

983

priv->coal_intvl = coal_intvl;

984

}

984

}

985

} else {

985

} else {

986

priv->coal_intvl = coal_intvl;

986

priv->coal_intvl = coal_intvl;

987

}

987

}

988

989

return 0;

989

return 0;

990

}

990

}

991

992

static int cpsw_get_sset_count(struct net_device *ndev, int sset)

992

static int cpsw_get_sset_count(struct net_device *ndev, int sset)

993

{

993

{

994

switch (sset) {

994

switch (sset) {

995

case ETH_SS_STATS:

995

case ETH_SS_STATS:

996

return CPSW_STATS_LEN;

996

return CPSW_STATS_LEN;

997

default:

997

default:

998

return -EOPNOTSUPP;

998

return -EOPNOTSUPP;

999

}

999

}

1000

}

1000

}

1001

1002

static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)

1002

static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)

1003

{

1003

{

1004

u8 *p = data;

1004

u8 *p = data;

1005

int i;

1005

int i;

1006

1007

switch (stringset) {

1007

switch (stringset) {

1008

case ETH_SS_STATS:

1008

case ETH_SS_STATS:

1009

for (i = 0; i < CPSW_STATS_LEN; i++) {

1009

for (i = 0; i < CPSW_STATS_LEN; i++) {

1010

memcpy(p, cpsw_gstrings_stats[i].stat_string,

1010

memcpy(p, cpsw_gstrings_stats[i].stat_string,

1011

ETH_GSTRING_LEN);

1011

ETH_GSTRING_LEN);

1012

p += ETH_GSTRING_LEN;

1012

p += ETH_GSTRING_LEN;

1013

}

1013

}

1014

break;

1014

break;

1015

}

1015

}

1016

}

1016

}

1017

1018

static void cpsw_get_ethtool_stats(struct net_device *ndev,

1018

static void cpsw_get_ethtool_stats(struct net_device *ndev,

1019

struct ethtool_stats *stats, u64 *data)

1019

struct ethtool_stats *stats, u64 *data)

1020

{

1020

{

1021

struct cpsw_priv *priv = netdev_priv(ndev);

1021

struct cpsw_priv *priv = netdev_priv(ndev);

1022

struct cpdma_chan_stats rx_stats;

1022

struct cpdma_chan_stats rx_stats;

1023

struct cpdma_chan_stats tx_stats;

1023

struct cpdma_chan_stats tx_stats;

1024

u32 val;

1024

u32 val;

1025

u8 *p;

1025

u8 *p;

1026

int i;

1026

int i;

1027

1028

/* Collect Davinci CPDMA stats for Rx and Tx Channel */

1028

/* Collect Davinci CPDMA stats for Rx and Tx Channel */

1029

cpdma_chan_get_stats(priv->rxch, &rx_stats);

1029

cpdma_chan_get_stats(priv->rxch, &rx_stats);

1030

cpdma_chan_get_stats(priv->txch, &tx_stats);

1030

cpdma_chan_get_stats(priv->txch, &tx_stats);

1031

1032

for (i = 0; i < CPSW_STATS_LEN; i++) {

1032

for (i = 0; i < CPSW_STATS_LEN; i++) {

1033

switch (cpsw_gstrings_stats[i].type) {

1033

switch (cpsw_gstrings_stats[i].type) {

1034

case CPSW_STATS:

1034

case CPSW_STATS:

1035

val = readl(priv->hw_stats +

1035

val = readl(priv->hw_stats +

1036

cpsw_gstrings_stats[i].stat_offset);

1036

cpsw_gstrings_stats[i].stat_offset);

1037

data[i] = val;

1037

data[i] = val;

1038

break;

1038

break;

1039

1040

case CPDMA_RX_STATS:

1040

case CPDMA_RX_STATS:

1041

p = (u8 *)&rx_stats +

1041

p = (u8 *)&rx_stats +

1042

cpsw_gstrings_stats[i].stat_offset;

1042

cpsw_gstrings_stats[i].stat_offset;

1043

data[i] = *(u32 *)p;

1043

data[i] = *(u32 *)p;

1044

break;

1044

break;

1045

1046

case CPDMA_TX_STATS:

1046

case CPDMA_TX_STATS:

1047

p = (u8 *)&tx_stats +

1047

p = (u8 *)&tx_stats +

1048

cpsw_gstrings_stats[i].stat_offset;

1048

cpsw_gstrings_stats[i].stat_offset;

1049

data[i] = *(u32 *)p;

1049

data[i] = *(u32 *)p;

1050

break;

1050

break;

1051

}

1051

}

1052

}

1052

}

1053

}

1053

}

1054

1055

static int cpsw_common_res_usage_state(struct cpsw_priv *priv)

1055

static int cpsw_common_res_usage_state(struct cpsw_priv *priv)

1056

{

1056

{

1057

u32 i;

1057

u32 i;

1058

u32 usage_count = 0;

1058

u32 usage_count = 0;

1059

1060

if (!priv->data.dual_emac)

1060

if (!priv->data.dual_emac)

1061

return 0;

1061

return 0;

1062

1063

for (i = 0; i < priv->data.slaves; i++)

1063

for (i = 0; i < priv->data.slaves; i++)

1064

if (priv->slaves[i].open_stat)

1064

if (priv->slaves[i].open_stat)

1065

usage_count++;

1065

usage_count++;

1066

1067

return usage_count;

1067

return usage_count;

1068

}

1068

}

1069

1070

static inline int cpsw_tx_packet_submit(struct net_device *ndev,

1070

static inline int cpsw_tx_packet_submit(struct net_device *ndev,

1071

struct cpsw_priv *priv, struct sk_buff *skb)

1071

struct cpsw_priv *priv, struct sk_buff *skb)

1072

{

1072

{

1073

if (!priv->data.dual_emac)

1073

if (!priv->data.dual_emac)

1074

return cpdma_chan_submit(priv->txch, skb, skb->data,

1074

return cpdma_chan_submit(priv->txch, skb, skb->data,

1075

skb->len, 0);

1075

skb->len, 0);

1076

1077

if (ndev == cpsw_get_slave_ndev(priv, 0))

1077

if (ndev == cpsw_get_slave_ndev(priv, 0))

1078

return cpdma_chan_submit(priv->txch, skb, skb->data,

1078

return cpdma_chan_submit(priv->txch, skb, skb->data,

1079

skb->len, 1);

1079

skb->len, 1);

1080

else

1080

else

1081

return cpdma_chan_submit(priv->txch, skb, skb->data,

1081

return cpdma_chan_submit(priv->txch, skb, skb->data,

1082

skb->len, 2);

1082

skb->len, 2);

1083

}

1083

}

1084

1085

static inline void cpsw_add_dual_emac_def_ale_entries(

1085

static inline void cpsw_add_dual_emac_def_ale_entries(

1086

struct cpsw_priv *priv, struct cpsw_slave *slave,

1086

struct cpsw_priv *priv, struct cpsw_slave *slave,

1087

u32 slave_port)

1087

u32 slave_port)

1088

{

1088

{

1089

u32 port_mask = 1 << slave_port | 1 << priv->host_port;

1089

u32 port_mask = 1 << slave_port | 1 << priv->host_port;

1090

1091

if (priv->version == CPSW_VERSION_1)

1091

if (priv->version == CPSW_VERSION_1)

1092

slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);

1092

slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);

1093

else

1093

else

1094

slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);

1094

slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);

1095

cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,

1095

cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,

1096

port_mask, port_mask, 0);

1096

port_mask, port_mask, 0);

1097

cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,

1097

cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,

1098

port_mask, ALE_VLAN, slave->port_vlan, 0);

1098

port_mask, ALE_VLAN, slave->port_vlan, 0);

1099

cpsw_ale_add_ucast(priv->ale, priv->mac_addr,

1099

cpsw_ale_add_ucast(priv->ale, priv->mac_addr,

1100

priv->host_port, ALE_VLAN, slave->port_vlan);

1100

priv->host_port, ALE_VLAN, slave->port_vlan);

1101

}

1101

}

1102

1103

static void soft_reset_slave(struct cpsw_slave *slave)

1103

static void soft_reset_slave(struct cpsw_slave *slave)

1104

{

1104

{

1105

char name[32];

1105

char name[32];

1106

1107

snprintf(name, sizeof(name), "slave-%d", slave->slave_num);

1107

snprintf(name, sizeof(name), "slave-%d", slave->slave_num);

1108

soft_reset(name, &slave->sliver->soft_reset);

1108

soft_reset(name, &slave->sliver->soft_reset);

1109

}

1109

}

1110

1111

static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)

1111

static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)

1112

{

1112

{

1113

u32 slave_port;

1113

u32 slave_port;

1114

1115

soft_reset_slave(slave);

1115

soft_reset_slave(slave);

1116

1117

/* setup priority mapping */

1117

/* setup priority mapping */

1118

__raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);

1118

__raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);

1119

1120

switch (priv->version) {

1120

switch (priv->version) {

1121

case CPSW_VERSION_1:

1121

case CPSW_VERSION_1:

1122

slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);

1122

slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);

1123

break;

1123

break;

1124

case CPSW_VERSION_2:

1124

case CPSW_VERSION_2:

1125

case CPSW_VERSION_3:

1125

case CPSW_VERSION_3:

1126

case CPSW_VERSION_4:

1126

case CPSW_VERSION_4:

1127

slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);

1127

slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);

1128

break;

1128

break;

1129

}

1129

}

1130

1131

/* setup max packet size, and mac address */

1131

/* setup max packet size, and mac address */

1132

__raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);

1132

__raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);

1133

cpsw_set_slave_mac(slave, priv);

1133

cpsw_set_slave_mac(slave, priv);

1134

1135

slave->mac_control = 0; /* no link yet */

1135

slave->mac_control = 0; /* no link yet */

1136

1137

slave_port = cpsw_get_slave_port(priv, slave->slave_num);

1137

slave_port = cpsw_get_slave_port(priv, slave->slave_num);

1138

1139

if (priv->data.dual_emac)

1139

if (priv->data.dual_emac)

1140

cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);

1140

cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);

1141

else

1141

else

1142

cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,

1142

cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,

1143

1 << slave_port, 0, 0, ALE_MCAST_FWD_2);

1143

1 << slave_port, 0, 0, ALE_MCAST_FWD_2);

1144

1145

slave->phy = phy_connect(priv->ndev, slave->data->phy_id,

1145

slave->phy = phy_connect(priv->ndev, slave->data->phy_id,

1146

&cpsw_adjust_link, slave->data->phy_if);

1146

&cpsw_adjust_link, slave->data->phy_if);

1147

if (IS_ERR(slave->phy)) {

1147

if (IS_ERR(slave->phy)) {

1148

dev_err(priv->dev, "phy %s not found on slave %d\n",

1148

dev_err(priv->dev, "phy %s not found on slave %d\n",

1149

slave->data->phy_id, slave->slave_num);

1149

slave->data->phy_id, slave->slave_num);

1150

slave->phy = NULL;

1150

slave->phy = NULL;

1151

} else {

1151

} else {

1152

dev_info(priv->dev, "phy found : id is : 0x%x\n",

1152

dev_info(priv->dev, "phy found : id is : 0x%x\n",

1153

slave->phy->phy_id);

1153

slave->phy->phy_id);

1154

phy_start(slave->phy);

1154

phy_start(slave->phy);

1155

1156

/* Configure GMII_SEL register */

1156

/* Configure GMII_SEL register */

1157

cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,

1157

cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,

1158

slave->slave_num);

1158

slave->slave_num);

1159

}

1159

}

1160

}

1160

}

1161

1162

static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)

1162

static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)

1163

{

1163

{

1164

const int vlan = priv->data.default_vlan;

1164

const int vlan = priv->data.default_vlan;

1165

const int port = priv->host_port;

1165

const int port = priv->host_port;

1166

u32 reg;

1166

u32 reg;

1167

int i;

1167

int i;

1168

int unreg_mcast_mask;

1168

int unreg_mcast_mask;

1169

1170

reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :

1170

reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :

1171

CPSW2_PORT_VLAN;

1171

CPSW2_PORT_VLAN;

1172

1173

writel(vlan, &priv->host_port_regs->port_vlan);

1173

writel(vlan, &priv->host_port_regs->port_vlan);

1174

1175

for (i = 0; i < priv->data.slaves; i++)

1175

for (i = 0; i < priv->data.slaves; i++)

1176

slave_write(priv->slaves + i, vlan, reg);

1176

slave_write(priv->slaves + i, vlan, reg);

1177

1178

if (priv->ndev->flags & IFF_ALLMULTI)

1178

if (priv->ndev->flags & IFF_ALLMULTI)

1179

unreg_mcast_mask = ALE_ALL_PORTS;

1179

unreg_mcast_mask = ALE_ALL_PORTS;

1180

else

1180

else

1181

unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;

1181

unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;

1182

1183

cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,

1183

cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,

1184

ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,

1184

ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,

1185

unreg_mcast_mask << port);

1185

unreg_mcast_mask << port);

1186

}

1186

}

1187

1188

static void cpsw_init_host_port(struct cpsw_priv *priv)

1188

static void cpsw_init_host_port(struct cpsw_priv *priv)

1189

{

1189

{

1190

u32 control_reg;

1190

u32 control_reg;

1191

u32 fifo_mode;

1191

u32 fifo_mode;

1192

1193

/* soft reset the controller and initialize ale */

1193

/* soft reset the controller and initialize ale */

1194

soft_reset("cpsw", &priv->regs->soft_reset);

1194

soft_reset("cpsw", &priv->regs->soft_reset);

1195

cpsw_ale_start(priv->ale);

1195

cpsw_ale_start(priv->ale);

1196

1197

/* switch to vlan unaware mode */

1197

/* switch to vlan unaware mode */

1198

cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,

1198

cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,

1199

CPSW_ALE_VLAN_AWARE);

1199

CPSW_ALE_VLAN_AWARE);

1200

control_reg = readl(&priv->regs->control);

1200

control_reg = readl(&priv->regs->control);

1201

control_reg |= CPSW_VLAN_AWARE;

1201

control_reg |= CPSW_VLAN_AWARE;

1202

writel(control_reg, &priv->regs->control);

1202

writel(control_reg, &priv->regs->control);

1203

fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :

1203

fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :

1204

CPSW_FIFO_NORMAL_MODE;

1204

CPSW_FIFO_NORMAL_MODE;

1205

writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);

1205

writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);

1206

1207

/* setup host port priority mapping */

1207

/* setup host port priority mapping */

1208

__raw_writel(CPDMA_TX_PRIORITY_MAP,

1208

__raw_writel(CPDMA_TX_PRIORITY_MAP,

1209

&priv->host_port_regs->cpdma_tx_pri_map);

1209

&priv->host_port_regs->cpdma_tx_pri_map);

1210

__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);

1210

__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);

1211

1212

cpsw_ale_control_set(priv->ale, priv->host_port,

1212

cpsw_ale_control_set(priv->ale, priv->host_port,

1213

ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);

1213

ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);

1214

1215

if (!priv->data.dual_emac) {

1215

if (!priv->data.dual_emac) {

1216

cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,

1216

cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,

1217

0, 0);

1217

0, 0);

1218

cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,

1218

cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,

1219

1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);

1219

1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);

1220

}

1220

}

1221

}

1221

}

1222

1223

static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)

1223

static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)

1224

{

1224

{

1225

u32 slave_port;

1225

u32 slave_port;

1226

1227

slave_port = cpsw_get_slave_port(priv, slave->slave_num);

1227

slave_port = cpsw_get_slave_port(priv, slave->slave_num);

1228

1229

if (!slave->phy)

1229

if (!slave->phy)

1230

return;

1230

return;

1231

phy_stop(slave->phy);

1231

phy_stop(slave->phy);

1232

phy_disconnect(slave->phy);

1232

phy_disconnect(slave->phy);

1233

slave->phy = NULL;

1233

slave->phy = NULL;

1234

cpsw_ale_control_set(priv->ale, slave_port,

1234

cpsw_ale_control_set(priv->ale, slave_port,

1235

ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);

1235

ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);

1236

}

1236

}

1237

1238

static int cpsw_ndo_open(struct net_device *ndev)

1238

static int cpsw_ndo_open(struct net_device *ndev)

1239

{

1239

{

1240

struct cpsw_priv *priv = netdev_priv(ndev);

1240

struct cpsw_priv *priv = netdev_priv(ndev);

1241

struct cpsw_priv *prim_cpsw;

1241

struct cpsw_priv *prim_cpsw;

1242

int i, ret;

1242

int i, ret;

1243

u32 reg;

1243

u32 reg;

1244

1245

if (!cpsw_common_res_usage_state(priv))

1245

if (!cpsw_common_res_usage_state(priv))

1246

cpsw_intr_disable(priv);

1246

cpsw_intr_disable(priv);

1247

netif_carrier_off(ndev);

1247

netif_carrier_off(ndev);

1248

1249

pm_runtime_get_sync(&priv->pdev->dev);

1249

pm_runtime_get_sync(&priv->pdev->dev);

1250

1251

reg = priv->version;

1251

reg = priv->version;

1252

1253

dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",

1253

dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",

1254

CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),

1254

CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),

1255

CPSW_RTL_VERSION(reg));

1255

CPSW_RTL_VERSION(reg));

1256

1257

/* initialize host and slave ports */

1257

/* initialize host and slave ports */

1258

if (!cpsw_common_res_usage_state(priv))

1258

if (!cpsw_common_res_usage_state(priv))

1259

cpsw_init_host_port(priv);

1259

cpsw_init_host_port(priv);

1260

for_each_slave(priv, cpsw_slave_open, priv);

1260

for_each_slave(priv, cpsw_slave_open, priv);

1261

1262

/* Add default VLAN */

1262

/* Add default VLAN */

1263

if (!priv->data.dual_emac)

1263

if (!priv->data.dual_emac)

1264

cpsw_add_default_vlan(priv);

1264

cpsw_add_default_vlan(priv);

1265

else

1265

else

1266

cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,

1266

cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,

1267

ALE_ALL_PORTS << priv->host_port,

1267

ALE_ALL_PORTS << priv->host_port,

1268

ALE_ALL_PORTS << priv->host_port, 0, 0);

1268

ALE_ALL_PORTS << priv->host_port, 0, 0);

1269

1270

if (!cpsw_common_res_usage_state(priv)) {

1270

if (!cpsw_common_res_usage_state(priv)) {

1271

/* setup tx dma to fixed prio and zero offset */

1271

/* setup tx dma to fixed prio and zero offset */

1272

cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);

1272

cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);

1273

cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);

1273

cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);

1274

1275

/* disable priority elevation */

1275

/* disable priority elevation */

1276

__raw_writel(0, &priv->regs->ptype);

1276

__raw_writel(0, &priv->regs->ptype);

1277

1278

/* enable statistics collection only on all ports */

1278

/* enable statistics collection only on all ports */

1279

__raw_writel(0x7, &priv->regs->stat_port_en);

1279

__raw_writel(0x7, &priv->regs->stat_port_en);

1280

1281

/* Enable internal fifo flow control */

1281

/* Enable internal fifo flow control */

1282

writel(0x7, &priv->regs->flow_control);

1282

writel(0x7, &priv->regs->flow_control);

1283

1284

if (WARN_ON(!priv->data.rx_descs))

1284

if (WARN_ON(!priv->data.rx_descs))

1285

priv->data.rx_descs = 128;

1285

priv->data.rx_descs = 128;

1286

1287

for (i = 0; i < priv->data.rx_descs; i++) {

1287

for (i = 0; i < priv->data.rx_descs; i++) {

1288

struct sk_buff *skb;

1288

struct sk_buff *skb;

1289

1290

ret = -ENOMEM;

1290

ret = -ENOMEM;

1291

skb = __netdev_alloc_skb_ip_align(priv->ndev,

1291

skb = __netdev_alloc_skb_ip_align(priv->ndev,

1292

priv->rx_packet_max, GFP_KERNEL);

1292

priv->rx_packet_max, GFP_KERNEL);

1293

if (!skb)

1293

if (!skb)

1294

goto err_cleanup;

1294

goto err_cleanup;

1295

ret = cpdma_chan_submit(priv->rxch, skb, skb->data,

1295

ret = cpdma_chan_submit(priv->rxch, skb, skb->data,

1296

skb_tailroom(skb), 0);

1296

skb_tailroom(skb), 0);

1297

if (ret < 0) {

1297

if (ret < 0) {

1298

kfree_skb(skb);

1298

kfree_skb(skb);

1299

goto err_cleanup;

1299

goto err_cleanup;

1300

}

1300

}

1301

}

1301

}

1302

/* continue even if we didn't manage to submit all

1302

/* continue even if we didn't manage to submit all

1303

* receive descs

1303

* receive descs

1304

*/

1304

*/

1305

cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);

1305

cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);

1306

1307

if (cpts_register(&priv->pdev->dev, priv->cpts,

1307

if (cpts_register(&priv->pdev->dev, priv->cpts,

1308

priv->data.cpts_clock_mult,

1308

priv->data.cpts_clock_mult,

1309

priv->data.cpts_clock_shift))

1309

priv->data.cpts_clock_shift))

1310

dev_err(priv->dev, "error registering cpts device\n");

1310

dev_err(priv->dev, "error registering cpts device\n");

1311

1312

}

1312

}

1313

1314

/* Enable Interrupt pacing if configured */

1314

/* Enable Interrupt pacing if configured */

1315

if (priv->coal_intvl != 0) {

1315

if (priv->coal_intvl != 0) {

1316

struct ethtool_coalesce coal;

1316

struct ethtool_coalesce coal;

1317

1318

coal.rx_coalesce_usecs = (priv->coal_intvl << 4);

1318

coal.rx_coalesce_usecs = (priv->coal_intvl << 4);

1319

cpsw_set_coalesce(ndev, &coal);

1319

cpsw_set_coalesce(ndev, &coal);

1320

}

1320

}

1321

1322

napi_enable(&priv->napi);

1322

napi_enable(&priv->napi);

1323

cpdma_ctlr_start(priv->dma);

1323

cpdma_ctlr_start(priv->dma);

1324

cpsw_intr_enable(priv);

1324

cpsw_intr_enable(priv);

1325

1326

prim_cpsw = cpsw_get_slave_priv(priv, 0);

1326

prim_cpsw = cpsw_get_slave_priv(priv, 0);

1327

if (prim_cpsw->irq_enabled == false) {

1327

if (prim_cpsw->irq_enabled == false) {

1328

if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {

1328

if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {

1329

prim_cpsw->irq_enabled = true;

1329

prim_cpsw->irq_enabled = true;

1330

cpsw_enable_irq(prim_cpsw);

1330

cpsw_enable_irq(prim_cpsw);

1331

}

1331

}

1332

}

1332

}

1333

1334

if (priv->data.dual_emac)

1334

if (priv->data.dual_emac)

1335

priv->slaves[priv->emac_port].open_stat = true;

1335

priv->slaves[priv->emac_port].open_stat = true;

1336

return 0;

1336

return 0;

1337

1338

err_cleanup:

1338

err_cleanup:

1339

cpdma_ctlr_stop(priv->dma);

1339

cpdma_ctlr_stop(priv->dma);

1340

for_each_slave(priv, cpsw_slave_stop, priv);

1340

for_each_slave(priv, cpsw_slave_stop, priv);

1341

pm_runtime_put_sync(&priv->pdev->dev);

1341

pm_runtime_put_sync(&priv->pdev->dev);

1342

netif_carrier_off(priv->ndev);

1342

netif_carrier_off(priv->ndev);

1343

return ret;

1343

return ret;

1344

}

1344

}

1345

1346

static int cpsw_ndo_stop(struct net_device *ndev)

1346

static int cpsw_ndo_stop(struct net_device *ndev)

1347

{

1347

{

1348

struct cpsw_priv *priv = netdev_priv(ndev);

1348

struct cpsw_priv *priv = netdev_priv(ndev);

1349

1350

cpsw_info(priv, ifdown, "shutting down cpsw device\n");

1350

cpsw_info(priv, ifdown, "shutting down cpsw device\n");

1351

netif_stop_queue(priv->ndev);

1351

netif_stop_queue(priv->ndev);

1352

napi_disable(&priv->napi);

1352

napi_disable(&priv->napi);

1353

netif_carrier_off(priv->ndev);

1353

netif_carrier_off(priv->ndev);

1354

1355

if (cpsw_common_res_usage_state(priv) <= 1) {

1355

if (cpsw_common_res_usage_state(priv) <= 1) {

1356

cpts_unregister(priv->cpts);

1356

cpts_unregister(priv->cpts);

1357

cpsw_intr_disable(priv);

1357

cpsw_intr_disable(priv);

1358

cpdma_ctlr_int_ctrl(priv->dma, false);

1358

cpdma_ctlr_int_ctrl(priv->dma, false);

1359

cpdma_ctlr_stop(priv->dma);

1359

cpdma_ctlr_stop(priv->dma);

1360

cpsw_ale_stop(priv->ale);

1360

cpsw_ale_stop(priv->ale);

1361

}

1361

}

1362

for_each_slave(priv, cpsw_slave_stop, priv);

1362

for_each_slave(priv, cpsw_slave_stop, priv);

1363

pm_runtime_put_sync(&priv->pdev->dev);

1363

pm_runtime_put_sync(&priv->pdev->dev);

1364

if (priv->data.dual_emac)

1364

if (priv->data.dual_emac)

1365

priv->slaves[priv->emac_port].open_stat = false;

1365

priv->slaves[priv->emac_port].open_stat = false;

1366

return 0;

1366

return 0;

1367

}

1367

}

1368

1369

static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,

1369

static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,

1370

struct net_device *ndev)

1370

struct net_device *ndev)

1371

{

1371

{

1372

struct cpsw_priv *priv = netdev_priv(ndev);

1372

struct cpsw_priv *priv = netdev_priv(ndev);

1373

int ret;

1373

int ret;

1374

1375

ndev->trans_start = jiffies;

1375

ndev->trans_start = jiffies;

1376

1377

if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {

1377

if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {

1378

cpsw_err(priv, tx_err, "packet pad failed\n");

1378

cpsw_err(priv, tx_err, "packet pad failed\n");

1379

ndev->stats.tx_dropped++;

1379

ndev->stats.tx_dropped++;

1380

return NETDEV_TX_OK;

1380

return NETDEV_TX_OK;

1381

}

1381

}

1382

1383

if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&

1383

if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&

1384

priv->cpts->tx_enable)

1384

priv->cpts->tx_enable)

1385

skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;

1385

skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;

1386

1387

skb_tx_timestamp(skb);

1387

skb_tx_timestamp(skb);

1388

1389

ret = cpsw_tx_packet_submit(ndev, priv, skb);

1389

ret = cpsw_tx_packet_submit(ndev, priv, skb);

1390

if (unlikely(ret != 0)) {

1390

if (unlikely(ret != 0)) {

1391

cpsw_err(priv, tx_err, "desc submit failed\n");

1391

cpsw_err(priv, tx_err, "desc submit failed\n");

1392

goto fail;

1392

goto fail;

1393

}

1393

}

1394

1395

/* If there is no more tx desc left free then we need to

1395

/* If there is no more tx desc left free then we need to

1396

* tell the kernel to stop sending us tx frames.

1396

* tell the kernel to stop sending us tx frames.

1397

*/

1397

*/

1398

if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))

1398

if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))

1399

netif_stop_queue(ndev);

1399

netif_stop_queue(ndev);

1400

1401

return NETDEV_TX_OK;

1401

return NETDEV_TX_OK;

1402

fail:

1402

fail:

1403

ndev->stats.tx_dropped++;

1403

ndev->stats.tx_dropped++;

1404

netif_stop_queue(ndev);

1404

netif_stop_queue(ndev);

1405

return NETDEV_TX_BUSY;

1405

return NETDEV_TX_BUSY;

1406

}

1406

}

1407

1408

#ifdef CONFIG_TI_CPTS

1408

#ifdef CONFIG_TI_CPTS

1409

1410

static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)

1410

static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)

1411

{

1411

{

1412

struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];

1412

struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];

1413

u32 ts_en, seq_id;

1413

u32 ts_en, seq_id;

1414

1415

if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {

1415

if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {

1416

slave_write(slave, 0, CPSW1_TS_CTL);

1416

slave_write(slave, 0, CPSW1_TS_CTL);

1417

return;

1417

return;

1418

}

1418

}

1419

1420

seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;

1420

seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;

1421

ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;

1421

ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;

1422

1423

if (priv->cpts->tx_enable)

1423

if (priv->cpts->tx_enable)

1424

ts_en |= CPSW_V1_TS_TX_EN;

1424

ts_en |= CPSW_V1_TS_TX_EN;

1425

1426

if (priv->cpts->rx_enable)

1426

if (priv->cpts->rx_enable)

1427

ts_en |= CPSW_V1_TS_RX_EN;

1427

ts_en |= CPSW_V1_TS_RX_EN;

1428

1429

slave_write(slave, ts_en, CPSW1_TS_CTL);

1429

slave_write(slave, ts_en, CPSW1_TS_CTL);

1430

slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);

1430

slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);

1431

}

1431

}

1432

1433

static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)

1433

static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)

1434

{

1434

{

1435

struct cpsw_slave *slave;

1435

struct cpsw_slave *slave;

1436

u32 ctrl, mtype;

1436

u32 ctrl, mtype;

1437

1438

if (priv->data.dual_emac)

1438

if (priv->data.dual_emac)

1439

slave = &priv->slaves[priv->emac_port];

1439

slave = &priv->slaves[priv->emac_port];

1440

else

1440

else

1441

slave = &priv->slaves[priv->data.active_slave];

1441

slave = &priv->slaves[priv->data.active_slave];

1442

1443

ctrl = slave_read(slave, CPSW2_CONTROL);

1443

ctrl = slave_read(slave, CPSW2_CONTROL);

1444

switch (priv->version) {

1444

switch (priv->version) {

1445

case CPSW_VERSION_2:

1445

case CPSW_VERSION_2:

1446

ctrl &= ~CTRL_V2_ALL_TS_MASK;

1446

ctrl &= ~CTRL_V2_ALL_TS_MASK;

1447

1448

if (priv->cpts->tx_enable)

1448

if (priv->cpts->tx_enable)

1449

ctrl |= CTRL_V2_TX_TS_BITS;

1449

ctrl |= CTRL_V2_TX_TS_BITS;

1450

1451

if (priv->cpts->rx_enable)

1451

if (priv->cpts->rx_enable)

1452

ctrl |= CTRL_V2_RX_TS_BITS;

1452

ctrl |= CTRL_V2_RX_TS_BITS;

1453

break;

1453

break;

1454

case CPSW_VERSION_3:

1454

case CPSW_VERSION_3:

1455

default:

1455

default:

1456

ctrl &= ~CTRL_V3_ALL_TS_MASK;

1456

ctrl &= ~CTRL_V3_ALL_TS_MASK;

1457

1458

if (priv->cpts->tx_enable)

1458

if (priv->cpts->tx_enable)

1459

ctrl |= CTRL_V3_TX_TS_BITS;

1459

ctrl |= CTRL_V3_TX_TS_BITS;

1460

1461

if (priv->cpts->rx_enable)

1461

if (priv->cpts->rx_enable)

1462

ctrl |= CTRL_V3_RX_TS_BITS;

1462

ctrl |= CTRL_V3_RX_TS_BITS;

1463

break;

1463

break;

1464

}

1464

}

1465

1466

mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;

1466

mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;

1467

1468

slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);

1468

slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);

1469

slave_write(slave, ctrl, CPSW2_CONTROL);

1469

slave_write(slave, ctrl, CPSW2_CONTROL);

1470

__raw_writel(ETH_P_1588, &priv->regs->ts_ltype);

1470

__raw_writel(ETH_P_1588, &priv->regs->ts_ltype);

1471

}

1471

}

1472

1473

static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)

1473

static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)

1474

{

1474

{

1475

struct cpsw_priv *priv = netdev_priv(dev);

1475

struct cpsw_priv *priv = netdev_priv(dev);

1476

struct cpts *cpts = priv->cpts;

1476

struct cpts *cpts = priv->cpts;

1477

struct hwtstamp_config cfg;

1477

struct hwtstamp_config cfg;

1478

1479

if (priv->version != CPSW_VERSION_1 &&

1479

if (priv->version != CPSW_VERSION_1 &&

1480

priv->version != CPSW_VERSION_2 &&

1480

priv->version != CPSW_VERSION_2 &&

1481

priv->version != CPSW_VERSION_3)

1481

priv->version != CPSW_VERSION_3)

1482

return -EOPNOTSUPP;

1482

return -EOPNOTSUPP;

1483

1484

if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))

1484

if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))

1485

return -EFAULT;

1485

return -EFAULT;

1486

1487

/* reserved for future extensions */

1487

/* reserved for future extensions */

1488

if (cfg.flags)

1488

if (cfg.flags)

1489

return -EINVAL;

1489

return -EINVAL;

1490

1491

if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)

1491

if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)

1492

return -ERANGE;

1492

return -ERANGE;

1493

1494

switch (cfg.rx_filter) {

1494

switch (cfg.rx_filter) {

1495

case HWTSTAMP_FILTER_NONE:

1495

case HWTSTAMP_FILTER_NONE:

1496

cpts->rx_enable = 0;

1496

cpts->rx_enable = 0;

1497

break;

1497

break;

1498

case HWTSTAMP_FILTER_ALL:

1498

case HWTSTAMP_FILTER_ALL:

1499

case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:

1499

case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:

1500

case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:

1500

case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:

1501

case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:

1501

case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:

1502

return -ERANGE;

1502

return -ERANGE;

1503

case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:

1503

case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:

1504

case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:

1504

case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:

1505

case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:

1505

case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:

1506

case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:

1506

case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:

1507

case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:

1507

case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:

1508

case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:

1508

case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:

1509

case HWTSTAMP_FILTER_PTP_V2_EVENT:

1509

case HWTSTAMP_FILTER_PTP_V2_EVENT:

1510

case HWTSTAMP_FILTER_PTP_V2_SYNC:

1510

case HWTSTAMP_FILTER_PTP_V2_SYNC:

1511

case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:

1511

case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:

1512

cpts->rx_enable = 1;

1512

cpts->rx_enable = 1;

1513

cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;

1513

cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;

1514

break;

1514

break;

1515

default:

1515

default:

1516

return -ERANGE;

1516

return -ERANGE;

1517

}

1517

}

1518

1519

cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;

1519

cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;

1520

1521

switch (priv->version) {

1521

switch (priv->version) {

1522

case CPSW_VERSION_1:

1522

case CPSW_VERSION_1:

1523

cpsw_hwtstamp_v1(priv);

1523

cpsw_hwtstamp_v1(priv);

1524

break;

1524

break;

1525

case CPSW_VERSION_2:

1525

case CPSW_VERSION_2:

1526

case CPSW_VERSION_3:

1526

case CPSW_VERSION_3:

1527

cpsw_hwtstamp_v2(priv);

1527

cpsw_hwtstamp_v2(priv);

1528

break;

1528

break;

1529

default:

1529

default:

1530

WARN_ON(1);

1530

WARN_ON(1);

1531

}

1531

}

1532

1533

return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;

1533

return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;

1534

}

1534

}

1535

1536

static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)

1536

static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)

1537

{

1537

{

1538

struct cpsw_priv *priv = netdev_priv(dev);

1538

struct cpsw_priv *priv = netdev_priv(dev);

1539

struct cpts *cpts = priv->cpts;

1539

struct cpts *cpts = priv->cpts;

1540

struct hwtstamp_config cfg;

1540

struct hwtstamp_config cfg;

1541

1542

if (priv->version != CPSW_VERSION_1 &&

1542

if (priv->version != CPSW_VERSION_1 &&

1543

priv->version != CPSW_VERSION_2 &&

1543

priv->version != CPSW_VERSION_2 &&

1544

priv->version != CPSW_VERSION_3)

1544

priv->version != CPSW_VERSION_3)

1545

return -EOPNOTSUPP;

1545

return -EOPNOTSUPP;

1546

1547

cfg.flags = 0;

1547

cfg.flags = 0;

1548

cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;

1548

cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;

1549

cfg.rx_filter = (cpts->rx_enable ?

1549

cfg.rx_filter = (cpts->rx_enable ?

1550

HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);

1550

HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);

1551

1552

return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;

1552

return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;

1553

}

1553

}

1554

1555

#endif /*CONFIG_TI_CPTS*/

1555

#endif /*CONFIG_TI_CPTS*/

1556

1557

static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)

1557

static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)

1558

{

1558

{

1559

struct cpsw_priv *priv = netdev_priv(dev);

1559

struct cpsw_priv *priv = netdev_priv(dev);

1560

int slave_no = cpsw_slave_index(priv);

1560

int slave_no = cpsw_slave_index(priv);

1561

1562

if (!netif_running(dev))

1562

if (!netif_running(dev))

1563

return -EINVAL;

1563

return -EINVAL;

1564

1565

switch (cmd) {

1565

switch (cmd) {

1566

#ifdef CONFIG_TI_CPTS

1566

#ifdef CONFIG_TI_CPTS

1567

case SIOCSHWTSTAMP:

1567

case SIOCSHWTSTAMP:

1568

return cpsw_hwtstamp_set(dev, req);

1568

return cpsw_hwtstamp_set(dev, req);

1569

case SIOCGHWTSTAMP:

1569

case SIOCGHWTSTAMP:

1570

return cpsw_hwtstamp_get(dev, req);

1570

return cpsw_hwtstamp_get(dev, req);

1571

#endif

1571

#endif

1572

}

1572

}

1573

1574

if (!priv->slaves[slave_no].phy)

1574

if (!priv->slaves[slave_no].phy)

1575

return -EOPNOTSUPP;

1575

return -EOPNOTSUPP;

1576

return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);

1576

return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);

1577

}

1577

}

1578

1579

static void cpsw_ndo_tx_timeout(struct net_device *ndev)

1579

static void cpsw_ndo_tx_timeout(struct net_device *ndev)

1580

{

1580

{

1581

struct cpsw_priv *priv = netdev_priv(ndev);

1581

struct cpsw_priv *priv = netdev_priv(ndev);

1582

1583

cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");

1583

cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");

1584

ndev->stats.tx_errors++;

1584

ndev->stats.tx_errors++;

1585

cpsw_intr_disable(priv);

1585

cpsw_intr_disable(priv);

1586

cpdma_ctlr_int_ctrl(priv->dma, false);

1586

cpdma_ctlr_int_ctrl(priv->dma, false);

1587

cpdma_chan_stop(priv->txch);

1587

cpdma_chan_stop(priv->txch);

1588

cpdma_chan_start(priv->txch);

1588

cpdma_chan_start(priv->txch);

1589

cpdma_ctlr_int_ctrl(priv->dma, true);

1589

cpdma_ctlr_int_ctrl(priv->dma, true);

1590

cpsw_intr_enable(priv);

1590

cpsw_intr_enable(priv);

1591

}

1591

}

1592

1593

static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)

1593

static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)

1594

{

1594

{

1595

struct cpsw_priv *priv = netdev_priv(ndev);

1595

struct cpsw_priv *priv = netdev_priv(ndev);

1596

struct sockaddr *addr = (struct sockaddr *)p;

1596

struct sockaddr *addr = (struct sockaddr *)p;

1597

int flags = 0;

1597

int flags = 0;

1598

u16 vid = 0;

1598

u16 vid = 0;

1599

1600

if (!is_valid_ether_addr(addr->sa_data))

1600

if (!is_valid_ether_addr(addr->sa_data))

1601

return -EADDRNOTAVAIL;

1601

return -EADDRNOTAVAIL;

1602

1603

if (priv->data.dual_emac) {

1603

if (priv->data.dual_emac) {

1604

vid = priv->slaves[priv->emac_port].port_vlan;

1604

vid = priv->slaves[priv->emac_port].port_vlan;

1605

flags = ALE_VLAN;

1605

flags = ALE_VLAN;

1606

}

1606

}

1607

1608

cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,

1608

cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,

1609

flags, vid);

1609

flags, vid);

1610

cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,

1610

cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,

1611

flags, vid);

1611

flags, vid);

1612

1613

memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);

1613

memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);

1614

memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);

1614

memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);

1615

for_each_slave(priv, cpsw_set_slave_mac, priv);

1615

for_each_slave(priv, cpsw_set_slave_mac, priv);

1616

1617

return 0;

1617

return 0;

1618

}

1618

}

1619

1620

#ifdef CONFIG_NET_POLL_CONTROLLER

1620

#ifdef CONFIG_NET_POLL_CONTROLLER

1621

static void cpsw_ndo_poll_controller(struct net_device *ndev)

1621

static void cpsw_ndo_poll_controller(struct net_device *ndev)

1622

{

1622

{

1623

struct cpsw_priv *priv = netdev_priv(ndev);

1623

struct cpsw_priv *priv = netdev_priv(ndev);

1624

1625

cpsw_intr_disable(priv);

1625

cpsw_intr_disable(priv);

1626

cpdma_ctlr_int_ctrl(priv->dma, false);

1626

cpdma_ctlr_int_ctrl(priv->dma, false);

1627

cpsw_interrupt(ndev->irq, priv);

1627

cpsw_interrupt(ndev->irq, priv);

1628

cpdma_ctlr_int_ctrl(priv->dma, true);

1628

cpdma_ctlr_int_ctrl(priv->dma, true);

1629

cpsw_intr_enable(priv);

1629

cpsw_intr_enable(priv);

1630

}

1630

}

1631

#endif

1631

#endif

1632

1633

static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,

1633

static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,

1634

unsigned short vid)

1634

unsigned short vid)

1635

{

1635

{

1636

int ret;

1636

int ret;

1637

int unreg_mcast_mask;

1637

int unreg_mcast_mask;

1638

1639

if (priv->ndev->flags & IFF_ALLMULTI)

1639

if (priv->ndev->flags & IFF_ALLMULTI)

1640

unreg_mcast_mask = ALE_ALL_PORTS;

1640

unreg_mcast_mask = ALE_ALL_PORTS;

1641

else

1641

else

1642

unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;

1642

unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;

1643

1644

ret = cpsw_ale_add_vlan(priv->ale, vid,

1644

ret = cpsw_ale_add_vlan(priv->ale, vid,

1645

ALE_ALL_PORTS << priv->host_port,

1645

ALE_ALL_PORTS << priv->host_port,

1646

0, ALE_ALL_PORTS << priv->host_port,

1646

0, ALE_ALL_PORTS << priv->host_port,

1647

unreg_mcast_mask << priv->host_port);

1647

unreg_mcast_mask << priv->host_port);

1648

if (ret != 0)

1648

if (ret != 0)

1649

return ret;

1649

return ret;

1650

1651

ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,

1651

ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,

1652

priv->host_port, ALE_VLAN, vid);

1652

priv->host_port, ALE_VLAN, vid);

1653

if (ret != 0)

1653

if (ret != 0)

1654

goto clean_vid;

1654

goto clean_vid;

1655

1656

ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,

1656

ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,

1657

ALE_ALL_PORTS << priv->host_port,

1657

ALE_ALL_PORTS << priv->host_port,

1658

ALE_VLAN, vid, 0);

1658

ALE_VLAN, vid, 0);

1659

if (ret != 0)

1659

if (ret != 0)

1660

goto clean_vlan_ucast;

1660

goto clean_vlan_ucast;

1661

return 0;

1661

return 0;

1662

1663

clean_vlan_ucast:

1663

clean_vlan_ucast:

1664

cpsw_ale_del_ucast(priv->ale, priv->mac_addr,

1664

cpsw_ale_del_ucast(priv->ale, priv->mac_addr,

1665

priv->host_port, ALE_VLAN, vid);

1665

priv->host_port, ALE_VLAN, vid);

1666

clean_vid:

1666

clean_vid:

1667

cpsw_ale_del_vlan(priv->ale, vid, 0);

1667

cpsw_ale_del_vlan(priv->ale, vid, 0);

1668

return ret;

1668

return ret;

1669

}

1669

}

1670

1671

static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,

1671

static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,

1672

__be16 proto, u16 vid)

1672

__be16 proto, u16 vid)

1673

{

1673

{

1674

struct cpsw_priv *priv = netdev_priv(ndev);

1674

struct cpsw_priv *priv = netdev_priv(ndev);

1675

1676

if (vid == priv->data.default_vlan)

1676

if (vid == priv->data.default_vlan)

1677

return 0;

1677

return 0;

1678

1679

if (priv->data.dual_emac) {

1680

/* In dual EMAC, reserved VLAN id should not be used for

1681

* creating VLAN interfaces as this can break the dual

1682

* EMAC port separation

1683

*/

1684

int i;

1685

1686

for (i = 0; i < priv->data.slaves; i++) {

1687

if (vid == priv->slaves[i].port_vlan)

1688

return -EINVAL;

1689

}

1690

}

1691

1679

dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);

1692

dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);

1680

return cpsw_add_vlan_ale_entry(priv, vid);

1693

return cpsw_add_vlan_ale_entry(priv, vid);

1681

}

1694

}

1682

1695

1683

static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,

1696

static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,

1684

__be16 proto, u16 vid)

1697

__be16 proto, u16 vid)

1685

{

1698

{

1686

struct cpsw_priv *priv = netdev_priv(ndev);

1699

struct cpsw_priv *priv = netdev_priv(ndev);

1687

int ret;

1700

int ret;

1688

1701

1689

if (vid == priv->data.default_vlan)

1702

if (vid == priv->data.default_vlan)

1690

return 0;

1703

return 0;

1704

1705

if (priv->data.dual_emac) {

1706

int i;

1707

1708

for (i = 0; i < priv->data.slaves; i++) {

1709

if (vid == priv->slaves[i].port_vlan)

1710

return -EINVAL;

1711

}

1712

}

1691

1713

1692

dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);

1714

dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);

1693

ret = cpsw_ale_del_vlan(priv->ale, vid, 0);

1715

ret = cpsw_ale_del_vlan(priv->ale, vid, 0);

1694

if (ret != 0)

1716

if (ret != 0)

1695

return ret;

1717

return ret;

1696

1718

1697

ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,

1719

ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,

1698

priv->host_port, ALE_VLAN, vid);

1720

priv->host_port, ALE_VLAN, vid);

1699

if (ret != 0)

1721

if (ret != 0)

1700

return ret;

1722

return ret;

1701

1723

1702

return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,

1724

return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,

1703

0, ALE_VLAN, vid);

1725

0, ALE_VLAN, vid);

1704

}

1726

}

1705

1727

1706

static const struct net_device_ops cpsw_netdev_ops = {

1728

static const struct net_device_ops cpsw_netdev_ops = {

1707

.ndo_open = cpsw_ndo_open,

1729

.ndo_open = cpsw_ndo_open,

1708

.ndo_stop = cpsw_ndo_stop,

1730

.ndo_stop = cpsw_ndo_stop,

1709

.ndo_start_xmit = cpsw_ndo_start_xmit,

1731

.ndo_start_xmit = cpsw_ndo_start_xmit,

1710

.ndo_set_mac_address = cpsw_ndo_set_mac_address,

1732

.ndo_set_mac_address = cpsw_ndo_set_mac_address,

1711

.ndo_do_ioctl = cpsw_ndo_ioctl,

1733

.ndo_do_ioctl = cpsw_ndo_ioctl,

1712

.ndo_validate_addr = eth_validate_addr,

1734

.ndo_validate_addr = eth_validate_addr,

1713

.ndo_change_mtu = eth_change_mtu,

1735

.ndo_change_mtu = eth_change_mtu,

1714

.ndo_tx_timeout = cpsw_ndo_tx_timeout,

1736

.ndo_tx_timeout = cpsw_ndo_tx_timeout,

1715

.ndo_set_rx_mode = cpsw_ndo_set_rx_mode,

1737

.ndo_set_rx_mode = cpsw_ndo_set_rx_mode,

1716

#ifdef CONFIG_NET_POLL_CONTROLLER

1738

#ifdef CONFIG_NET_POLL_CONTROLLER

1717

.ndo_poll_controller = cpsw_ndo_poll_controller,

1739

.ndo_poll_controller = cpsw_ndo_poll_controller,

1718

#endif

1740

#endif

1719

.ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,

1741

.ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,

1720

.ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,

1742

.ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,

1721

};

1743

};

1722

1744

1723

static int cpsw_get_regs_len(struct net_device *ndev)

1745

static int cpsw_get_regs_len(struct net_device *ndev)

1724

{

1746

{

1725

struct cpsw_priv *priv = netdev_priv(ndev);

1747

struct cpsw_priv *priv = netdev_priv(ndev);

1726

1748

1727

return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);

1749

return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);

1728

}

1750

}

1729

1751

1730

static void cpsw_get_regs(struct net_device *ndev,

1752

static void cpsw_get_regs(struct net_device *ndev,

1731

struct ethtool_regs *regs, void *p)

1753

struct ethtool_regs *regs, void *p)

1732

{

1754

{

1733

struct cpsw_priv *priv = netdev_priv(ndev);

1755

struct cpsw_priv *priv = netdev_priv(ndev);

1734

u32 *reg = p;

1756

u32 *reg = p;

1735

1757

1736

/* update CPSW IP version */

1758

/* update CPSW IP version */

1737

regs->version = priv->version;

1759

regs->version = priv->version;

1738

1760

1739

cpsw_ale_dump(priv->ale, reg);

1761

cpsw_ale_dump(priv->ale, reg);

1740

}

1762

}

1741

1763

1742

static void cpsw_get_drvinfo(struct net_device *ndev,

1764

static void cpsw_get_drvinfo(struct net_device *ndev,

1743

struct ethtool_drvinfo *info)

1765

struct ethtool_drvinfo *info)

1744

{

1766

{

1745

struct cpsw_priv *priv = netdev_priv(ndev);

1767

struct cpsw_priv *priv = netdev_priv(ndev);

1746

1768

1747

strlcpy(info->driver, "cpsw", sizeof(info->driver));

1769

strlcpy(info->driver, "cpsw", sizeof(info->driver));

1748

strlcpy(info->version, "1.0", sizeof(info->version));

1770

strlcpy(info->version, "1.0", sizeof(info->version));

1749

strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));

1771

strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));

1750

info->regdump_len = cpsw_get_regs_len(ndev);

1772

info->regdump_len = cpsw_get_regs_len(ndev);

1751

}

1773

}

1752

1774

1753

static u32 cpsw_get_msglevel(struct net_device *ndev)

1775

static u32 cpsw_get_msglevel(struct net_device *ndev)

1754

{

1776

{

1755

struct cpsw_priv *priv = netdev_priv(ndev);

1777

struct cpsw_priv *priv = netdev_priv(ndev);

1756

return priv->msg_enable;

1778

return priv->msg_enable;

1757

}

1779

}

1758

1780

1759

static void cpsw_set_msglevel(struct net_device *ndev, u32 value)

1781

static void cpsw_set_msglevel(struct net_device *ndev, u32 value)

1760

{

1782

{

1761

struct cpsw_priv *priv = netdev_priv(ndev);

1783

struct cpsw_priv *priv = netdev_priv(ndev);

1762

priv->msg_enable = value;

1784

priv->msg_enable = value;

1763

}

1785

}

1764

1786

1765

static int cpsw_get_ts_info(struct net_device *ndev,

1787

static int cpsw_get_ts_info(struct net_device *ndev,

1766

struct ethtool_ts_info *info)

1788

struct ethtool_ts_info *info)

1767

{

1789

{

1768

#ifdef CONFIG_TI_CPTS

1790

#ifdef CONFIG_TI_CPTS

1769

struct cpsw_priv *priv = netdev_priv(ndev);

1791

struct cpsw_priv *priv = netdev_priv(ndev);

1770

1792

1771

info->so_timestamping =

1793

info->so_timestamping =

1772

SOF_TIMESTAMPING_TX_HARDWARE |

1794

SOF_TIMESTAMPING_TX_HARDWARE |

1773

SOF_TIMESTAMPING_TX_SOFTWARE |

1795

SOF_TIMESTAMPING_TX_SOFTWARE |

1774

SOF_TIMESTAMPING_RX_HARDWARE |

1796

SOF_TIMESTAMPING_RX_HARDWARE |

1775

SOF_TIMESTAMPING_RX_SOFTWARE |

1797

SOF_TIMESTAMPING_RX_SOFTWARE |

1776

SOF_TIMESTAMPING_SOFTWARE |

1798

SOF_TIMESTAMPING_SOFTWARE |

1777

SOF_TIMESTAMPING_RAW_HARDWARE;

1799

SOF_TIMESTAMPING_RAW_HARDWARE;

1778

info->phc_index = priv->cpts->phc_index;

1800

info->phc_index = priv->cpts->phc_index;

1779

info->tx_types =

1801

info->tx_types =

1780

(1 << HWTSTAMP_TX_OFF) |

1802

(1 << HWTSTAMP_TX_OFF) |

1781

(1 << HWTSTAMP_TX_ON);

1803

(1 << HWTSTAMP_TX_ON);

1782

info->rx_filters =

1804

info->rx_filters =

1783

(1 << HWTSTAMP_FILTER_NONE) |

1805

(1 << HWTSTAMP_FILTER_NONE) |

1784

(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);

1806

(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);

1785

#else

1807

#else

1786

info->so_timestamping =

1808

info->so_timestamping =

1787

SOF_TIMESTAMPING_TX_SOFTWARE |

1809

SOF_TIMESTAMPING_TX_SOFTWARE |

1788

SOF_TIMESTAMPING_RX_SOFTWARE |

1810

SOF_TIMESTAMPING_RX_SOFTWARE |

1789

SOF_TIMESTAMPING_SOFTWARE;

1811

SOF_TIMESTAMPING_SOFTWARE;

1790

info->phc_index = -1;

1812

info->phc_index = -1;

1791

info->tx_types = 0;

1813

info->tx_types = 0;

1792

info->rx_filters = 0;

1814

info->rx_filters = 0;

1793

#endif

1815

#endif

1794

return 0;

1816

return 0;

1795

}

1817

}

1796

1818

1797

static int cpsw_get_settings(struct net_device *ndev,

1819

static int cpsw_get_settings(struct net_device *ndev,

1798

struct ethtool_cmd *ecmd)

1820

struct ethtool_cmd *ecmd)

1799

{

1821

{

1800

struct cpsw_priv *priv = netdev_priv(ndev);

1822

struct cpsw_priv *priv = netdev_priv(ndev);

1801

int slave_no = cpsw_slave_index(priv);

1823

int slave_no = cpsw_slave_index(priv);

1802

1824

1803

if (priv->slaves[slave_no].phy)

1825

if (priv->slaves[slave_no].phy)

1804

return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);

1826

return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);

1805

else

1827

else

1806

return -EOPNOTSUPP;

1828

return -EOPNOTSUPP;

1807

}

1829

}

1808

1830

1809

static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)

1831

static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)

1810

{

1832

{

1811

struct cpsw_priv *priv = netdev_priv(ndev);

1833

struct cpsw_priv *priv = netdev_priv(ndev);

1812

int slave_no = cpsw_slave_index(priv);

1834

int slave_no = cpsw_slave_index(priv);

1813

1835

1814

if (priv->slaves[slave_no].phy)

1836

if (priv->slaves[slave_no].phy)

1815

return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);

1837

return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);

1816

else

1838

else

1817

return -EOPNOTSUPP;

1839

return -EOPNOTSUPP;

1818

}

1840

}

1819

1841

1820

static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)

1842

static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)

1821

{

1843

{

1822

struct cpsw_priv *priv = netdev_priv(ndev);

1844

struct cpsw_priv *priv = netdev_priv(ndev);

1823

int slave_no = cpsw_slave_index(priv);

1845

int slave_no = cpsw_slave_index(priv);

1824

1846

1825

wol->supported = 0;

1847

wol->supported = 0;

1826

wol->wolopts = 0;

1848

wol->wolopts = 0;

1827

1849

1828

if (priv->slaves[slave_no].phy)

1850

if (priv->slaves[slave_no].phy)

1829

phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);

1851

phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);

1830

}

1852

}

1831

1853

1832

static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)

1854

static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)

1833

{

1855

{

1834

struct cpsw_priv *priv = netdev_priv(ndev);

1856

struct cpsw_priv *priv = netdev_priv(ndev);

1835

int slave_no = cpsw_slave_index(priv);

1857

int slave_no = cpsw_slave_index(priv);

1836

1858

1837

if (priv->slaves[slave_no].phy)

1859

if (priv->slaves[slave_no].phy)

1838

return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);

1860

return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);

1839

else

1861

else

1840

return -EOPNOTSUPP;

1862

return -EOPNOTSUPP;

1841

}

1863

}

1842

1864

1843

static void cpsw_get_pauseparam(struct net_device *ndev,

1865

static void cpsw_get_pauseparam(struct net_device *ndev,

1844

struct ethtool_pauseparam *pause)

1866

struct ethtool_pauseparam *pause)

1845

{

1867

{

1846

struct cpsw_priv *priv = netdev_priv(ndev);

1868

struct cpsw_priv *priv = netdev_priv(ndev);

1847

1869

1848

pause->autoneg = AUTONEG_DISABLE;

1870

pause->autoneg = AUTONEG_DISABLE;

1849

pause->rx_pause = priv->rx_pause ? true : false;

1871

pause->rx_pause = priv->rx_pause ? true : false;

1850

pause->tx_pause = priv->tx_pause ? true : false;

1872

pause->tx_pause = priv->tx_pause ? true : false;

1851

}

1873

}

1852

1874

1853

static int cpsw_set_pauseparam(struct net_device *ndev,

1875

static int cpsw_set_pauseparam(struct net_device *ndev,

1854

struct ethtool_pauseparam *pause)

1876

struct ethtool_pauseparam *pause)

1855

{

1877

{

1856

struct cpsw_priv *priv = netdev_priv(ndev);

1878

struct cpsw_priv *priv = netdev_priv(ndev);

1857

bool link;

1879

bool link;

1858

1880

1859

priv->rx_pause = pause->rx_pause ? true : false;

1881

priv->rx_pause = pause->rx_pause ? true : false;

1860

priv->tx_pause = pause->tx_pause ? true : false;

1882

priv->tx_pause = pause->tx_pause ? true : false;

1861

1883

1862

for_each_slave(priv, _cpsw_adjust_link, priv, &link);

1884

for_each_slave(priv, _cpsw_adjust_link, priv, &link);

1863

1885

1864

return 0;

1886

return 0;

1865

}

1887

}

1866

1888

1867

static const struct ethtool_ops cpsw_ethtool_ops = {

1889

static const struct ethtool_ops cpsw_ethtool_ops = {

1868

.get_drvinfo = cpsw_get_drvinfo,

1890

.get_drvinfo = cpsw_get_drvinfo,

1869

.get_msglevel = cpsw_get_msglevel,

1891

.get_msglevel = cpsw_get_msglevel,

1870

.set_msglevel = cpsw_set_msglevel,

1892

.set_msglevel = cpsw_set_msglevel,

1871

.get_link = ethtool_op_get_link,

1893

.get_link = ethtool_op_get_link,

1872

.get_ts_info = cpsw_get_ts_info,

1894

.get_ts_info = cpsw_get_ts_info,

1873

.get_settings = cpsw_get_settings,

1895

.get_settings = cpsw_get_settings,

1874

.set_settings = cpsw_set_settings,

1896

.set_settings = cpsw_set_settings,

1875

.get_coalesce = cpsw_get_coalesce,

1897

.get_coalesce = cpsw_get_coalesce,

1876

.set_coalesce = cpsw_set_coalesce,

1898

.set_coalesce = cpsw_set_coalesce,

1877

.get_sset_count = cpsw_get_sset_count,

1899

.get_sset_count = cpsw_get_sset_count,

1878

.get_strings = cpsw_get_strings,

1900

.get_strings = cpsw_get_strings,

1879

.get_ethtool_stats = cpsw_get_ethtool_stats,

1901

.get_ethtool_stats = cpsw_get_ethtool_stats,

1880

.get_pauseparam = cpsw_get_pauseparam,

1902

.get_pauseparam = cpsw_get_pauseparam,

1881

.set_pauseparam = cpsw_set_pauseparam,

1903

.set_pauseparam = cpsw_set_pauseparam,

1882

.get_wol = cpsw_get_wol,

1904

.get_wol = cpsw_get_wol,

1883

.set_wol = cpsw_set_wol,

1905

.set_wol = cpsw_set_wol,

1884

.get_regs_len = cpsw_get_regs_len,

1906

.get_regs_len = cpsw_get_regs_len,

1885

.get_regs = cpsw_get_regs,

1907

.get_regs = cpsw_get_regs,

1886

};

1908

};

1887

1909

1888

static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,

1910

static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,

1889

u32 slave_reg_ofs, u32 sliver_reg_ofs)

1911

u32 slave_reg_ofs, u32 sliver_reg_ofs)

1890

{

1912

{

1891

void __iomem *regs = priv->regs;

1913

void __iomem *regs = priv->regs;

1892

int slave_num = slave->slave_num;

1914

int slave_num = slave->slave_num;

1893

struct cpsw_slave_data *data = priv->data.slave_data + slave_num;

1915

struct cpsw_slave_data *data = priv->data.slave_data + slave_num;

1894

1916

1895

slave->data = data;

1917

slave->data = data;

1896

slave->regs = regs + slave_reg_ofs;

1918

slave->regs = regs + slave_reg_ofs;

1897

slave->sliver = regs + sliver_reg_ofs;

1919

slave->sliver = regs + sliver_reg_ofs;

1898

slave->port_vlan = data->dual_emac_res_vlan;

1920

slave->port_vlan = data->dual_emac_res_vlan;

1899

}

1921

}

1900

1922

1901

#define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)

1923

#define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)

1902

#define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)

1924

#define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)

1903

1925

1904

static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,

1926

static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,

1905

u8 *mac_addr)

1927

u8 *mac_addr)

1906

{

1928

{

1907

u32 macid_lo;

1929

u32 macid_lo;

1908

u32 macid_hi;

1930

u32 macid_hi;

1909

struct regmap *syscon;

1931

struct regmap *syscon;

1910

1932

1911

syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");

1933

syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");

1912

if (IS_ERR(syscon)) {

1934

if (IS_ERR(syscon)) {

1913

if (PTR_ERR(syscon) == -ENODEV)

1935

if (PTR_ERR(syscon) == -ENODEV)

1914

return 0;

1936

return 0;

1915

return PTR_ERR(syscon);

1937

return PTR_ERR(syscon);

1916

}

1938

}

1917

1939

1918

regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), &macid_lo);

1940

regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), &macid_lo);

1919

regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), &macid_hi);

1941

regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), &macid_hi);

1920

1942

1921

mac_addr[5] = (macid_lo >> 8) & 0xff;

1943

mac_addr[5] = (macid_lo >> 8) & 0xff;

1922

mac_addr[4] = macid_lo & 0xff;

1944

mac_addr[4] = macid_lo & 0xff;

1923

mac_addr[3] = (macid_hi >> 24) & 0xff;

1945

mac_addr[3] = (macid_hi >> 24) & 0xff;

1924

mac_addr[2] = (macid_hi >> 16) & 0xff;

1946

mac_addr[2] = (macid_hi >> 16) & 0xff;

1925

mac_addr[1] = (macid_hi >> 8) & 0xff;

1947

mac_addr[1] = (macid_hi >> 8) & 0xff;

1926

mac_addr[0] = macid_hi & 0xff;

1948

mac_addr[0] = macid_hi & 0xff;

1927

1949

1928

return 0;

1950

return 0;

1929

}

1951

}

1930

1952

1931

static int cpsw_probe_dt(struct cpsw_platform_data *data,

1953

static int cpsw_probe_dt(struct cpsw_platform_data *data,

1932

struct platform_device *pdev)

1954

struct platform_device *pdev)

1933

{

1955

{

1934

struct device_node *node = pdev->dev.of_node;

1956

struct device_node *node = pdev->dev.of_node;

1935

struct device_node *slave_node;

1957

struct device_node *slave_node;

1936

int i = 0, ret;

1958

int i = 0, ret;

1937

u32 prop;

1959

u32 prop;

1938

1960

1939

if (!node)

1961

if (!node)

1940

return -EINVAL;

1962

return -EINVAL;

1941

1963

1942

if (of_property_read_u32(node, "slaves", &prop)) {

1964

if (of_property_read_u32(node, "slaves", &prop)) {

1943

dev_err(&pdev->dev, "Missing slaves property in the DT.\n");

1965

dev_err(&pdev->dev, "Missing slaves property in the DT.\n");

1944

return -EINVAL;

1966

return -EINVAL;

1945

}

1967

}

1946

data->slaves = prop;

1968

data->slaves = prop;

1947

1969

1948

if (of_property_read_u32(node, "active_slave", &prop)) {

1970

if (of_property_read_u32(node, "active_slave", &prop)) {

1949

dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");

1971

dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");

1950

return -EINVAL;

1972

return -EINVAL;

1951

}

1973

}

1952

data->active_slave = prop;

1974

data->active_slave = prop;

1953

1975

1954

if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {

1976

if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {

1955

dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");

1977

dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");

1956

return -EINVAL;

1978

return -EINVAL;

1957

}

1979

}

1958

data->cpts_clock_mult = prop;

1980

data->cpts_clock_mult = prop;

1959

1981

1960

if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {

1982

if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {

1961

dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");

1983

dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");

1962

return -EINVAL;

1984

return -EINVAL;

1963

}

1985

}

1964

data->cpts_clock_shift = prop;

1986

data->cpts_clock_shift = prop;

1965

1987

1966

data->slave_data = devm_kzalloc(&pdev->dev, data->slaves

1988

data->slave_data = devm_kzalloc(&pdev->dev, data->slaves

1967

* sizeof(struct cpsw_slave_data),

1989

* sizeof(struct cpsw_slave_data),

1968

GFP_KERNEL);

1990

GFP_KERNEL);

1969

if (!data->slave_data)

1991

if (!data->slave_data)

1970

return -ENOMEM;

1992

return -ENOMEM;

1971

1993

1972

if (of_property_read_u32(node, "cpdma_channels", &prop)) {

1994

if (of_property_read_u32(node, "cpdma_channels", &prop)) {

1973

dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");

1995

dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");

1974

return -EINVAL;

1996

return -EINVAL;

1975

}

1997

}

1976

data->channels = prop;

1998

data->channels = prop;

1977

1999

1978

if (of_property_read_u32(node, "ale_entries", &prop)) {

2000

if (of_property_read_u32(node, "ale_entries", &prop)) {

1979

dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");

2001

dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");

1980

return -EINVAL;

2002

return -EINVAL;

1981

}

2003

}

1982

data->ale_entries = prop;

2004

data->ale_entries = prop;

1983

2005

1984

if (of_property_read_u32(node, "bd_ram_size", &prop)) {

2006

if (of_property_read_u32(node, "bd_ram_size", &prop)) {

1985

dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");

2007

dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");

1986

return -EINVAL;

2008

return -EINVAL;

1987

}

2009

}

1988

data->bd_ram_size = prop;

2010

data->bd_ram_size = prop;

1989

2011

1990

if (of_property_read_u32(node, "rx_descs", &prop)) {

2012

if (of_property_read_u32(node, "rx_descs", &prop)) {

1991

dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");

2013

dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");

1992

return -EINVAL;

2014

return -EINVAL;

1993

}

2015

}

1994

data->rx_descs = prop;

2016

data->rx_descs = prop;

1995

2017

1996

if (of_property_read_u32(node, "mac_control", &prop)) {

2018

if (of_property_read_u32(node, "mac_control", &prop)) {

1997

dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");

2019

dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");

1998

return -EINVAL;

2020

return -EINVAL;

1999

}

2021

}

2000

data->mac_control = prop;

2022

data->mac_control = prop;

2001

2023

2002

if (of_property_read_bool(node, "dual_emac"))

2024

if (of_property_read_bool(node, "dual_emac"))

2003

data->dual_emac = 1;

2025

data->dual_emac = 1;

2004

2026

2005

/*

2027

/*

2006

* Populate all the child nodes here...

2028

* Populate all the child nodes here...

2007

*/

2029

*/

2008

ret = of_platform_populate(node, NULL, NULL, &pdev->dev);

2030

ret = of_platform_populate(node, NULL, NULL, &pdev->dev);

2009

/* We do not want to force this, as in some cases may not have child */

2031

/* We do not want to force this, as in some cases may not have child */

2010

if (ret)

2032

if (ret)

2011

dev_warn(&pdev->dev, "Doesn't have any child node\n");

2033

dev_warn(&pdev->dev, "Doesn't have any child node\n");

2012

2034

2013

for_each_child_of_node(node, slave_node) {

2035

for_each_child_of_node(node, slave_node) {

2014

struct cpsw_slave_data *slave_data = data->slave_data + i;

2036

struct cpsw_slave_data *slave_data = data->slave_data + i;

2015

const void *mac_addr = NULL;

2037

const void *mac_addr = NULL;

2016

u32 phyid;

2038

u32 phyid;

2017

int lenp;

2039

int lenp;

2018

const __be32 *parp;

2040

const __be32 *parp;

2019

struct device_node *mdio_node;

2041

struct device_node *mdio_node;

2020

struct platform_device *mdio;

2042

struct platform_device *mdio;

2021

2043

2022

/* This is no slave child node, continue */

2044

/* This is no slave child node, continue */

2023

if (strcmp(slave_node->name, "slave"))

2045

if (strcmp(slave_node->name, "slave"))

2024

continue;

2046

continue;

2025

2047

2026

parp = of_get_property(slave_node, "phy_id", &lenp);

2048

parp = of_get_property(slave_node, "phy_id", &lenp);

2027

if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {

2049

if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {

2028

dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);

2050

dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);

2029

goto no_phy_slave;

2051

goto no_phy_slave;

2030

}

2052

}

2031

mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));

2053

mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));

2032

phyid = be32_to_cpup(parp+1);

2054

phyid = be32_to_cpup(parp+1);

2033

mdio = of_find_device_by_node(mdio_node);

2055

mdio = of_find_device_by_node(mdio_node);

2034

of_node_put(mdio_node);

2056

of_node_put(mdio_node);

2035

if (!mdio) {

2057

if (!mdio) {

2036

dev_err(&pdev->dev, "Missing mdio platform device\n");

2058

dev_err(&pdev->dev, "Missing mdio platform device\n");

2037

return -EINVAL;

2059

return -EINVAL;

2038

}

2060

}

2039

snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),

2061

snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),

2040

PHY_ID_FMT, mdio->name, phyid);

2062

PHY_ID_FMT, mdio->name, phyid);

2041

2063

2042

slave_data->phy_if = of_get_phy_mode(slave_node);

2064

slave_data->phy_if = of_get_phy_mode(slave_node);

2043

if (slave_data->phy_if < 0) {

2065

if (slave_data->phy_if < 0) {

2044

dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",

2066

dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",

2045

i);

2067

i);

2046

return slave_data->phy_if;

2068

return slave_data->phy_if;

2047

}

2069

}

2048

2070

2049

no_phy_slave:

2071

no_phy_slave:

2050

mac_addr = of_get_mac_address(slave_node);

2072

mac_addr = of_get_mac_address(slave_node);

2051

if (mac_addr) {

2073

if (mac_addr) {

2052

memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);

2074

memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);

2053

} else {

2075

} else {

2054

if (of_machine_is_compatible("ti,am33xx")) {

2076

if (of_machine_is_compatible("ti,am33xx")) {

2055

ret = cpsw_am33xx_cm_get_macid(&pdev->dev, i,

2077

ret = cpsw_am33xx_cm_get_macid(&pdev->dev, i,

2056

slave_data->mac_addr);

2078

slave_data->mac_addr);

2057

if (ret)

2079

if (ret)

2058

return ret;

2080

return ret;

2059

}

2081

}

2060

}

2082

}

2061

if (data->dual_emac) {

2083

if (data->dual_emac) {

2062

if (of_property_read_u32(slave_node, "dual_emac_res_vlan",

2084

if (of_property_read_u32(slave_node, "dual_emac_res_vlan",

2063

&prop)) {

2085

&prop)) {

2064

dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");

2086

dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");

2065

slave_data->dual_emac_res_vlan = i+1;

2087

slave_data->dual_emac_res_vlan = i+1;

2066

dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",

2088

dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",

2067

slave_data->dual_emac_res_vlan, i);

2089

slave_data->dual_emac_res_vlan, i);

2068

} else {

2090

} else {

2069

slave_data->dual_emac_res_vlan = prop;

2091

slave_data->dual_emac_res_vlan = prop;

2070

}

2092

}

2071

}

2093

}

2072

2094

2073

i++;

2095

i++;

2074

if (i == data->slaves)

2096

if (i == data->slaves)

2075

break;

2097

break;

2076

}

2098

}

2077

2099

2078

return 0;

2100

return 0;

2079

}

2101

}

2080

2102

2081

static int cpsw_probe_dual_emac(struct platform_device *pdev,

2103

static int cpsw_probe_dual_emac(struct platform_device *pdev,

2082

struct cpsw_priv *priv)

2104

struct cpsw_priv *priv)

2083

{

2105

{

2084

struct cpsw_platform_data *data = &priv->data;

2106

struct cpsw_platform_data *data = &priv->data;

2085

struct net_device *ndev;

2107

struct net_device *ndev;

2086

struct cpsw_priv *priv_sl2;

2108

struct cpsw_priv *priv_sl2;

2087

int ret = 0, i;

2109

int ret = 0, i;

2088

2110

2089

ndev = alloc_etherdev(sizeof(struct cpsw_priv));

2111

ndev = alloc_etherdev(sizeof(struct cpsw_priv));

2090

if (!ndev) {

2112

if (!ndev) {

2091

dev_err(&pdev->dev, "cpsw: error allocating net_device\n");

2113

dev_err(&pdev->dev, "cpsw: error allocating net_device\n");

2092

return -ENOMEM;

2114

return -ENOMEM;

2093

}

2115

}

2094

2116

2095

priv_sl2 = netdev_priv(ndev);

2117

priv_sl2 = netdev_priv(ndev);

2096

spin_lock_init(&priv_sl2->lock);

2118

spin_lock_init(&priv_sl2->lock);

2097

priv_sl2->data = *data;

2119

priv_sl2->data = *data;

2098

priv_sl2->pdev = pdev;

2120

priv_sl2->pdev = pdev;

2099

priv_sl2->ndev = ndev;

2121

priv_sl2->ndev = ndev;

2100

priv_sl2->dev = &ndev->dev;

2122

priv_sl2->dev = &ndev->dev;

2101

priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);

2123

priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);

2102

priv_sl2->rx_packet_max = max(rx_packet_max, 128);

2124

priv_sl2->rx_packet_max = max(rx_packet_max, 128);

2103

2125

2104

if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {

2126

if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {

2105

memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,

2127

memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,

2106

ETH_ALEN);

2128

ETH_ALEN);

2107

dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);

2129

dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);

2108

} else {

2130

} else {

2109

random_ether_addr(priv_sl2->mac_addr);

2131

random_ether_addr(priv_sl2->mac_addr);

2110

dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);

2132

dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);

2111

}

2133

}

2112

memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);

2134

memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);

2113

2135

2114

priv_sl2->slaves = priv->slaves;

2136

priv_sl2->slaves = priv->slaves;

2115

priv_sl2->clk = priv->clk;

2137

priv_sl2->clk = priv->clk;

2116

2138

2117

priv_sl2->coal_intvl = 0;

2139

priv_sl2->coal_intvl = 0;

2118

priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;

2140

priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;

2119

2141

2120

priv_sl2->regs = priv->regs;

2142

priv_sl2->regs = priv->regs;

2121

priv_sl2->host_port = priv->host_port;

2143

priv_sl2->host_port = priv->host_port;

2122

priv_sl2->host_port_regs = priv->host_port_regs;

2144

priv_sl2->host_port_regs = priv->host_port_regs;

2123

priv_sl2->wr_regs = priv->wr_regs;

2145

priv_sl2->wr_regs = priv->wr_regs;

2124

priv_sl2->hw_stats = priv->hw_stats;

2146

priv_sl2->hw_stats = priv->hw_stats;

2125

priv_sl2->dma = priv->dma;

2147

priv_sl2->dma = priv->dma;

2126

priv_sl2->txch = priv->txch;

2148

priv_sl2->txch = priv->txch;

2127

priv_sl2->rxch = priv->rxch;

2149

priv_sl2->rxch = priv->rxch;

2128

priv_sl2->ale = priv->ale;

2150

priv_sl2->ale = priv->ale;

2129

priv_sl2->emac_port = 1;

2151

priv_sl2->emac_port = 1;

2130

priv->slaves[1].ndev = ndev;

2152

priv->slaves[1].ndev = ndev;

2131

priv_sl2->cpts = priv->cpts;

2153

priv_sl2->cpts = priv->cpts;

2132

priv_sl2->version = priv->version;

2154

priv_sl2->version = priv->version;

2133

2155

2134

for (i = 0; i < priv->num_irqs; i++) {

2156

for (i = 0; i < priv->num_irqs; i++) {

2135

priv_sl2->irqs_table[i] = priv->irqs_table[i];

2157

priv_sl2->irqs_table[i] = priv->irqs_table[i];

2136

priv_sl2->num_irqs = priv->num_irqs;

2158

priv_sl2->num_irqs = priv->num_irqs;

2137

}

2159

}

2138

ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;

2160

ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;

2139

2161

2140

ndev->netdev_ops = &cpsw_netdev_ops;

2162

ndev->netdev_ops = &cpsw_netdev_ops;

2141

ndev->ethtool_ops = &cpsw_ethtool_ops;

2163

ndev->ethtool_ops = &cpsw_ethtool_ops;

2142

netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);

2164

netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);

2143

2165

2144

/* register the network device */

2166

/* register the network device */

2145

SET_NETDEV_DEV(ndev, &pdev->dev);

2167

SET_NETDEV_DEV(ndev, &pdev->dev);

2146

ret = register_netdev(ndev);

2168

ret = register_netdev(ndev);

2147

if (ret) {

2169

if (ret) {

2148

dev_err(&pdev->dev, "cpsw: error registering net device\n");

2170

dev_err(&pdev->dev, "cpsw: error registering net device\n");

2149

free_netdev(ndev);

2171

free_netdev(ndev);

2150

ret = -ENODEV;

2172

ret = -ENODEV;

2151

}

2173

}

2152

2174

2153

return ret;

2175

return ret;

2154

}

2176

}

2155

2177

2156

static int cpsw_probe(struct platform_device *pdev)

2178

static int cpsw_probe(struct platform_device *pdev)

2157

{

2179

{

2158

struct cpsw_platform_data *data;

2180

struct cpsw_platform_data *data;

2159

struct net_device *ndev;

2181

struct net_device *ndev;

2160

struct cpsw_priv *priv;

2182

struct cpsw_priv *priv;

2161

struct cpdma_params dma_params;

2183

struct cpdma_params dma_params;

2162

struct cpsw_ale_params ale_params;

2184

struct cpsw_ale_params ale_params;

2163

void __iomem *ss_regs;

2185

void __iomem *ss_regs;

2164

struct resource *res, *ss_res;

2186

struct resource *res, *ss_res;

2165

u32 slave_offset, sliver_offset, slave_size;

2187

u32 slave_offset, sliver_offset, slave_size;

2166

int ret = 0, i, k = 0;

2188

int ret = 0, i, k = 0;

2167

2189

2168

ndev = alloc_etherdev(sizeof(struct cpsw_priv));

2190

ndev = alloc_etherdev(sizeof(struct cpsw_priv));

2169

if (!ndev) {

2191

if (!ndev) {

2170

dev_err(&pdev->dev, "error allocating net_device\n");

2192

dev_err(&pdev->dev, "error allocating net_device\n");

2171

return -ENOMEM;

2193

return -ENOMEM;

2172

}

2194

}

2173

2195

2174

platform_set_drvdata(pdev, ndev);

2196

platform_set_drvdata(pdev, ndev);

2175

priv = netdev_priv(ndev);

2197

priv = netdev_priv(ndev);

2176

spin_lock_init(&priv->lock);

2198

spin_lock_init(&priv->lock);

2177

priv->pdev = pdev;

2199

priv->pdev = pdev;

2178

priv->ndev = ndev;

2200

priv->ndev = ndev;

2179

priv->dev = &ndev->dev;

2201

priv->dev = &ndev->dev;

2180

priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);

2202

priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);

2181

priv->rx_packet_max = max(rx_packet_max, 128);

2203

priv->rx_packet_max = max(rx_packet_max, 128);

2182

priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);

2204

priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);

2183

priv->irq_enabled = true;

2205

priv->irq_enabled = true;

2184

if (!priv->cpts) {

2206

if (!priv->cpts) {

2185

dev_err(&pdev->dev, "error allocating cpts\n");

2207

dev_err(&pdev->dev, "error allocating cpts\n");

2186

ret = -ENOMEM;

2208

ret = -ENOMEM;

2187

goto clean_ndev_ret;

2209

goto clean_ndev_ret;

2188

}

2210

}

2189

2211

2190

/*

2212

/*

2191

* This may be required here for child devices.

2213

* This may be required here for child devices.

2192

*/

2214

*/

2193

pm_runtime_enable(&pdev->dev);

2215

pm_runtime_enable(&pdev->dev);

2194

2216

2195

/* Select default pin state */

2217

/* Select default pin state */

2196

pinctrl_pm_select_default_state(&pdev->dev);

2218

pinctrl_pm_select_default_state(&pdev->dev);

2197

2219

2198

if (cpsw_probe_dt(&priv->data, pdev)) {

2220

if (cpsw_probe_dt(&priv->data, pdev)) {

2199

dev_err(&pdev->dev, "cpsw: platform data missing\n");

2221

dev_err(&pdev->dev, "cpsw: platform data missing\n");

2200

ret = -ENODEV;

2222

ret = -ENODEV;

2201

goto clean_runtime_disable_ret;

2223

goto clean_runtime_disable_ret;

2202

}

2224

}

2203

data = &priv->data;

2225

data = &priv->data;

2204

2226

2205

if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {

2227

if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {

2206

memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);

2228

memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);

2207

dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);

2229

dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);

2208

} else {

2230

} else {

2209

eth_random_addr(priv->mac_addr);

2231

eth_random_addr(priv->mac_addr);

2210

dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);

2232

dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);

2211

}

2233

}

2212

2234

2213

memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);

2235

memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);

2214

2236

2215

priv->slaves = devm_kzalloc(&pdev->dev,

2237

priv->slaves = devm_kzalloc(&pdev->dev,

2216

sizeof(struct cpsw_slave) * data->slaves,

2238

sizeof(struct cpsw_slave) * data->slaves,

2217

GFP_KERNEL);

2239

GFP_KERNEL);

2218

if (!priv->slaves) {

2240

if (!priv->slaves) {

2219

ret = -ENOMEM;

2241

ret = -ENOMEM;

2220

goto clean_runtime_disable_ret;

2242

goto clean_runtime_disable_ret;

2221

}

2243

}

2222

for (i = 0; i < data->slaves; i++)

2244

for (i = 0; i < data->slaves; i++)

2223

priv->slaves[i].slave_num = i;

2245

priv->slaves[i].slave_num = i;

2224

2246

2225

priv->slaves[0].ndev = ndev;

2247

priv->slaves[0].ndev = ndev;

2226

priv->emac_port = 0;

2248

priv->emac_port = 0;

2227

2249

2228

priv->clk = devm_clk_get(&pdev->dev, "fck");

2250

priv->clk = devm_clk_get(&pdev->dev, "fck");

2229

if (IS_ERR(priv->clk)) {

2251

if (IS_ERR(priv->clk)) {

2230

dev_err(priv->dev, "fck is not found\n");

2252

dev_err(priv->dev, "fck is not found\n");

2231

ret = -ENODEV;

2253

ret = -ENODEV;

2232

goto clean_runtime_disable_ret;

2254

goto clean_runtime_disable_ret;

2233

}

2255

}

2234

priv->coal_intvl = 0;

2256

priv->coal_intvl = 0;

2235

priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;

2257

priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;

2236

2258

2237

ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

2259

ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

2238

ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);

2260

ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);

2239

if (IS_ERR(ss_regs)) {

2261

if (IS_ERR(ss_regs)) {

2240

ret = PTR_ERR(ss_regs);

2262

ret = PTR_ERR(ss_regs);

2241

goto clean_runtime_disable_ret;

2263

goto clean_runtime_disable_ret;

2242

}

2264

}

2243

priv->regs = ss_regs;

2265

priv->regs = ss_regs;

2244

priv->host_port = HOST_PORT_NUM;

2266

priv->host_port = HOST_PORT_NUM;

2245

2267

2246

/* Need to enable clocks with runtime PM api to access module

2268

/* Need to enable clocks with runtime PM api to access module

2247

* registers

2269

* registers

2248

*/

2270

*/

2249

pm_runtime_get_sync(&pdev->dev);

2271

pm_runtime_get_sync(&pdev->dev);

2250

priv->version = readl(&priv->regs->id_ver);

2272

priv->version = readl(&priv->regs->id_ver);

2251

pm_runtime_put_sync(&pdev->dev);

2273

pm_runtime_put_sync(&pdev->dev);

2252

2274

2253

res = platform_get_resource(pdev, IORESOURCE_MEM, 1);

2275

res = platform_get_resource(pdev, IORESOURCE_MEM, 1);

2254

priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);

2276

priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);

2255

if (IS_ERR(priv->wr_regs)) {

2277

if (IS_ERR(priv->wr_regs)) {

2256

ret = PTR_ERR(priv->wr_regs);

2278

ret = PTR_ERR(priv->wr_regs);

2257

goto clean_runtime_disable_ret;

2279

goto clean_runtime_disable_ret;

2258

}

2280

}

2259

2281

2260

memset(&dma_params, 0, sizeof(dma_params));

2282

memset(&dma_params, 0, sizeof(dma_params));

2261

memset(&ale_params, 0, sizeof(ale_params));

2283

memset(&ale_params, 0, sizeof(ale_params));

2262

2284

2263

switch (priv->version) {

2285

switch (priv->version) {

2264

case CPSW_VERSION_1:

2286

case CPSW_VERSION_1:

2265

priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;

2287

priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;

2266

priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;

2288

priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;

2267

priv->hw_stats = ss_regs + CPSW1_HW_STATS;

2289

priv->hw_stats = ss_regs + CPSW1_HW_STATS;

2268

dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;

2290

dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;

2269

dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;

2291

dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;

2270

ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;

2292

ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;

2271

slave_offset = CPSW1_SLAVE_OFFSET;

2293

slave_offset = CPSW1_SLAVE_OFFSET;

2272

slave_size = CPSW1_SLAVE_SIZE;

2294

slave_size = CPSW1_SLAVE_SIZE;

2273

sliver_offset = CPSW1_SLIVER_OFFSET;

2295

sliver_offset = CPSW1_SLIVER_OFFSET;

2274

dma_params.desc_mem_phys = 0;

2296

dma_params.desc_mem_phys = 0;

2275

break;

2297

break;

2276

case CPSW_VERSION_2:

2298

case CPSW_VERSION_2:

2277

case CPSW_VERSION_3:

2299

case CPSW_VERSION_3:

2278

case CPSW_VERSION_4:

2300

case CPSW_VERSION_4:

2279

priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;

2301

priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;

2280

priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;

2302

priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;

2281

priv->hw_stats = ss_regs + CPSW2_HW_STATS;

2303

priv->hw_stats = ss_regs + CPSW2_HW_STATS;

2282

dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;

2304

dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;

2283

dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;

2305

dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;

2284

ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;

2306

ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;

2285

slave_offset = CPSW2_SLAVE_OFFSET;

2307

slave_offset = CPSW2_SLAVE_OFFSET;

2286

slave_size = CPSW2_SLAVE_SIZE;

2308

slave_size = CPSW2_SLAVE_SIZE;

2287

sliver_offset = CPSW2_SLIVER_OFFSET;

2309

sliver_offset = CPSW2_SLIVER_OFFSET;

2288

dma_params.desc_mem_phys =

2310

dma_params.desc_mem_phys =

2289

(u32 __force) ss_res->start + CPSW2_BD_OFFSET;

2311

(u32 __force) ss_res->start + CPSW2_BD_OFFSET;

2290

break;

2312

break;

2291

default:

2313

default:

2292

dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);

2314

dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);

2293

ret = -ENODEV;

2315

ret = -ENODEV;

2294

goto clean_runtime_disable_ret;

2316

goto clean_runtime_disable_ret;

2295

}

2317

}

2296

for (i = 0; i < priv->data.slaves; i++) {

2318

for (i = 0; i < priv->data.slaves; i++) {

2297

struct cpsw_slave *slave = &priv->slaves[i];

2319

struct cpsw_slave *slave = &priv->slaves[i];

2298

cpsw_slave_init(slave, priv, slave_offset, sliver_offset);

2320

cpsw_slave_init(slave, priv, slave_offset, sliver_offset);

2299

slave_offset += slave_size;

2321

slave_offset += slave_size;

2300

sliver_offset += SLIVER_SIZE;

2322

sliver_offset += SLIVER_SIZE;

2301

}

2323

}

2302

2324

2303

dma_params.dev = &pdev->dev;

2325

dma_params.dev = &pdev->dev;

2304

dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;

2326

dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;

2305

dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;

2327

dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;

2306

dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;

2328

dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;

2307

dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;

2329

dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;

2308

dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;

2330

dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;

2309

2331

2310

dma_params.num_chan = data->channels;

2332

dma_params.num_chan = data->channels;

2311

dma_params.has_soft_reset = true;

2333

dma_params.has_soft_reset = true;

2312

dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;

2334

dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;

2313

dma_params.desc_mem_size = data->bd_ram_size;

2335

dma_params.desc_mem_size = data->bd_ram_size;

2314

dma_params.desc_align = 16;

2336

dma_params.desc_align = 16;

2315

dma_params.has_ext_regs = true;

2337

dma_params.has_ext_regs = true;

2316

dma_params.desc_hw_addr = dma_params.desc_mem_phys;

2338

dma_params.desc_hw_addr = dma_params.desc_mem_phys;

2317

2339

2318

priv->dma = cpdma_ctlr_create(&dma_params);

2340

priv->dma = cpdma_ctlr_create(&dma_params);

2319

if (!priv->dma) {

2341

if (!priv->dma) {

2320

dev_err(priv->dev, "error initializing dma\n");

2342

dev_err(priv->dev, "error initializing dma\n");

2321

ret = -ENOMEM;

2343

ret = -ENOMEM;

2322

goto clean_runtime_disable_ret;

2344

goto clean_runtime_disable_ret;

2323

}

2345

}

2324

2346

2325

priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),

2347

priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),

2326

cpsw_tx_handler);

2348

cpsw_tx_handler);

2327

priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),

2349

priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),

2328

cpsw_rx_handler);

2350

cpsw_rx_handler);

2329

2351

2330

if (WARN_ON(!priv->txch || !priv->rxch)) {

2352

if (WARN_ON(!priv->txch || !priv->rxch)) {

2331

dev_err(priv->dev, "error initializing dma channels\n");

2353

dev_err(priv->dev, "error initializing dma channels\n");

2332

ret = -ENOMEM;

2354

ret = -ENOMEM;

2333

goto clean_dma_ret;

2355

goto clean_dma_ret;

2334

}

2356

}

2335

2357

2336

ale_params.dev = &ndev->dev;

2358

ale_params.dev = &ndev->dev;

2337

ale_params.ale_ageout = ale_ageout;

2359

ale_params.ale_ageout = ale_ageout;

2338

ale_params.ale_entries = data->ale_entries;

2360

ale_params.ale_entries = data->ale_entries;

2339

ale_params.ale_ports = data->slaves;

2361

ale_params.ale_ports = data->slaves;

2340

2362

2341

priv->ale = cpsw_ale_create(&ale_params);

2363

priv->ale = cpsw_ale_create(&ale_params);

2342

if (!priv->ale) {

2364

if (!priv->ale) {

2343

dev_err(priv->dev, "error initializing ale engine\n");

2365

dev_err(priv->dev, "error initializing ale engine\n");

2344

ret = -ENODEV;

2366

ret = -ENODEV;

2345

goto clean_dma_ret;

2367

goto clean_dma_ret;

2346

}

2368

}

2347

2369

2348

ndev->irq = platform_get_irq(pdev, 0);

2370

ndev->irq = platform_get_irq(pdev, 0);

2349

if (ndev->irq < 0) {

2371

if (ndev->irq < 0) {

2350

dev_err(priv->dev, "error getting irq resource\n");

2372

dev_err(priv->dev, "error getting irq resource\n");

2351

ret = -ENOENT;

2373

ret = -ENOENT;

2352

goto clean_ale_ret;

2374

goto clean_ale_ret;

2353

}

2375

}

2354

2376

2355

while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {

2377

while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {

2356

if (k >= ARRAY_SIZE(priv->irqs_table)) {

2378

if (k >= ARRAY_SIZE(priv->irqs_table)) {

2357

ret = -EINVAL;

2379

ret = -EINVAL;

2358

goto clean_ale_ret;

2380

goto clean_ale_ret;

2359

}

2381

}

2360

2382

2361

ret = devm_request_irq(&pdev->dev, res->start, cpsw_interrupt,

2383

ret = devm_request_irq(&pdev->dev, res->start, cpsw_interrupt,

2362

0, dev_name(&pdev->dev), priv);

2384

0, dev_name(&pdev->dev), priv);

2363

if (ret < 0) {

2385

if (ret < 0) {

2364

dev_err(priv->dev, "error attaching irq (%d)\n", ret);

2386

dev_err(priv->dev, "error attaching irq (%d)\n", ret);

2365

goto clean_ale_ret;

2387

goto clean_ale_ret;

2366

}

2388

}

2367

2389

2368

priv->irqs_table[k] = res->start;

2390

priv->irqs_table[k] = res->start;

2369

k++;

2391

k++;

2370

}

2392

}

2371

2393

2372

priv->num_irqs = k;

2394

priv->num_irqs = k;

2373

2395

2374

ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;

2396

ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;

2375

2397

2376

ndev->netdev_ops = &cpsw_netdev_ops;

2398

ndev->netdev_ops = &cpsw_netdev_ops;

2377

ndev->ethtool_ops = &cpsw_ethtool_ops;

2399

ndev->ethtool_ops = &cpsw_ethtool_ops;

2378

netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);

2400

netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);

2379

2401

2380

/* register the network device */

2402

/* register the network device */

2381

SET_NETDEV_DEV(ndev, &pdev->dev);

2403

SET_NETDEV_DEV(ndev, &pdev->dev);

2382

ret = register_netdev(ndev);

2404

ret = register_netdev(ndev);

2383

if (ret) {

2405

if (ret) {

2384

dev_err(priv->dev, "error registering net device\n");

2406

dev_err(priv->dev, "error registering net device\n");

2385

ret = -ENODEV;

2407

ret = -ENODEV;

2386

goto clean_ale_ret;

2408

goto clean_ale_ret;

2387

}

2409

}

2388

2410

2389

cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",

2411

cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",

2390

&ss_res->start, ndev->irq);

2412

&ss_res->start, ndev->irq);

2391

2413

2392

if (priv->data.dual_emac) {

2414

if (priv->data.dual_emac) {

2393

ret = cpsw_probe_dual_emac(pdev, priv);

2415

ret = cpsw_probe_dual_emac(pdev, priv);

2394

if (ret) {

2416

if (ret) {

2395

cpsw_err(priv, probe, "error probe slave 2 emac interface\n");

2417

cpsw_err(priv, probe, "error probe slave 2 emac interface\n");

2396

goto clean_ale_ret;

2418

goto clean_ale_ret;

2397

}

2419

}

2398

}

2420

}

2399

2421

2400

return 0;

2422

return 0;

2401

2423

2402

clean_ale_ret:

2424

clean_ale_ret:

2403

cpsw_ale_destroy(priv->ale);

2425

cpsw_ale_destroy(priv->ale);

2404

clean_dma_ret:

2426

clean_dma_ret:

2405

cpdma_chan_destroy(priv->txch);

2427

cpdma_chan_destroy(priv->txch);

2406

cpdma_chan_destroy(priv->rxch);

2428

cpdma_chan_destroy(priv->rxch);

2407

cpdma_ctlr_destroy(priv->dma);

2429

cpdma_ctlr_destroy(priv->dma);

2408

clean_runtime_disable_ret:

2430

clean_runtime_disable_ret:

2409

pm_runtime_disable(&pdev->dev);

2431

pm_runtime_disable(&pdev->dev);

2410

clean_ndev_ret:

2432

clean_ndev_ret:

2411

free_netdev(priv->ndev);

2433

free_netdev(priv->ndev);

2412

return ret;

2434

return ret;

2413

}

2435

}

2414

2436

2415

static int cpsw_remove_child_device(struct device *dev, void *c)

2437

static int cpsw_remove_child_device(struct device *dev, void *c)

2416

{

2438

{

2417

struct platform_device *pdev = to_platform_device(dev);

2439

struct platform_device *pdev = to_platform_device(dev);

2418

2440

2419

of_device_unregister(pdev);

2441

of_device_unregister(pdev);

2420

2442

2421

return 0;

2443

return 0;

2422

}

2444

}

2423

2445

2424

static int cpsw_remove(struct platform_device *pdev)

2446

static int cpsw_remove(struct platform_device *pdev)

2425

{

2447

{

2426

struct net_device *ndev = platform_get_drvdata(pdev);

2448

struct net_device *ndev = platform_get_drvdata(pdev);

2427

struct cpsw_priv *priv = netdev_priv(ndev);

2449

struct cpsw_priv *priv = netdev_priv(ndev);

2428

2450

2429

if (priv->data.dual_emac)

2451

if (priv->data.dual_emac)

2430

unregister_netdev(cpsw_get_slave_ndev(priv, 1));

2452

unregister_netdev(cpsw_get_slave_ndev(priv, 1));

2431

unregister_netdev(ndev);

2453

unregister_netdev(ndev);

2432

2454

2433

cpsw_ale_destroy(priv->ale);

2455

cpsw_ale_destroy(priv->ale);

2434

cpdma_chan_destroy(priv->txch);

2456

cpdma_chan_destroy(priv->txch);

2435

cpdma_chan_destroy(priv->rxch);

2457

cpdma_chan_destroy(priv->rxch);

2436

cpdma_ctlr_destroy(priv->dma);

2458

cpdma_ctlr_destroy(priv->dma);

2437

pm_runtime_disable(&pdev->dev);

2459

pm_runtime_disable(&pdev->dev);

2438

device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);

2460

device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);

2439

if (priv->data.dual_emac)

2461

if (priv->data.dual_emac)

2440

free_netdev(cpsw_get_slave_ndev(priv, 1));

2462

free_netdev(cpsw_get_slave_ndev(priv, 1));

2441

free_netdev(ndev);

2463

free_netdev(ndev);

2442

return 0;

2464

return 0;

2443

}

2465

}

2444

2466

2445

static int cpsw_suspend(struct device *dev)

2467

static int cpsw_suspend(struct device *dev)

2446

{

2468

{

2447

struct platform_device *pdev = to_platform_device(dev);

2469

struct platform_device *pdev = to_platform_device(dev);

2448

struct net_device *ndev = platform_get_drvdata(pdev);

2470

struct net_device *ndev = platform_get_drvdata(pdev);

2449

struct cpsw_priv *priv = netdev_priv(ndev);

2471

struct cpsw_priv *priv = netdev_priv(ndev);

2450

2472

2451

if (priv->data.dual_emac) {

2473

if (priv->data.dual_emac) {

2452

int i;

2474

int i;

2453

2475

2454

for (i = 0; i < priv->data.slaves; i++) {

2476

for (i = 0; i < priv->data.slaves; i++) {

2455

if (netif_running(priv->slaves[i].ndev))

2477

if (netif_running(priv->slaves[i].ndev))

2456

cpsw_ndo_stop(priv->slaves[i].ndev);

2478

cpsw_ndo_stop(priv->slaves[i].ndev);

2457

soft_reset_slave(priv->slaves + i);

2479

soft_reset_slave(priv->slaves + i);

2458

}

2480

}

2459

} else {

2481

} else {

2460

if (netif_running(ndev))

2482

if (netif_running(ndev))

2461

cpsw_ndo_stop(ndev);

2483

cpsw_ndo_stop(ndev);

2462

for_each_slave(priv, soft_reset_slave);

2484

for_each_slave(priv, soft_reset_slave);

2463

}

2485

}

2464

2486

2465

pm_runtime_put_sync(&pdev->dev);

2487

pm_runtime_put_sync(&pdev->dev);

2466

2488

2467

/* Select sleep pin state */

2489

/* Select sleep pin state */

2468

pinctrl_pm_select_sleep_state(&pdev->dev);

2490

pinctrl_pm_select_sleep_state(&pdev->dev);

2469

2491

2470

return 0;

2492

return 0;

2471

}

2493

}

2472

2494

2473

static int cpsw_resume(struct device *dev)

2495

static int cpsw_resume(struct device *dev)

2474

{

2496

{

2475

struct platform_device *pdev = to_platform_device(dev);

2497

struct platform_device *pdev = to_platform_device(dev);

2476

struct net_device *ndev = platform_get_drvdata(pdev);

2498

struct net_device *ndev = platform_get_drvdata(pdev);

2477

struct cpsw_priv *priv = netdev_priv(ndev);

2499

struct cpsw_priv *priv = netdev_priv(ndev);

2478

2500

2479

pm_runtime_get_sync(&pdev->dev);

2501

pm_runtime_get_sync(&pdev->dev);

2480

2502

2481

/* Select default pin state */

2503

/* Select default pin state */

2482

pinctrl_pm_select_default_state(&pdev->dev);

2504

pinctrl_pm_select_default_state(&pdev->dev);

2483

2505

2484

if (priv->data.dual_emac) {

2506

if (priv->data.dual_emac) {

2485

int i;

2507

int i;

2486

2508

2487

for (i = 0; i < priv->data.slaves; i++) {

2509

for (i = 0; i < priv->data.slaves; i++) {

2488

if (netif_running(priv->slaves[i].ndev))

2510

if (netif_running(priv->slaves[i].ndev))

2489

cpsw_ndo_open(priv->slaves[i].ndev);

2511

cpsw_ndo_open(priv->slaves[i].ndev);

2490

}

2512

}

2491

} else {

2513

} else {

2492

if (netif_running(ndev))

2514

if (netif_running(ndev))

2493

cpsw_ndo_open(ndev);

2515

cpsw_ndo_open(ndev);

2494

}

2516

}

2495

return 0;

2517

return 0;

2496

}

2518

}

2497

2519

2498

static const struct dev_pm_ops cpsw_pm_ops = {

2520

static const struct dev_pm_ops cpsw_pm_ops = {

2499

.suspend = cpsw_suspend,

2521

.suspend = cpsw_suspend,

2500

.resume = cpsw_resume,

2522

.resume = cpsw_resume,

2501

};

2523

};

2502

2524

2503

static const struct of_device_id cpsw_of_mtable[] = {

2525

static const struct of_device_id cpsw_of_mtable[] = {

2504

{ .compatible = "ti,cpsw", },

2526

{ .compatible = "ti,cpsw", },

2505

{ /* sentinel */ },

2527

{ /* sentinel */ },

2506

};

2528

};

2507

MODULE_DEVICE_TABLE(of, cpsw_of_mtable);

2529

MODULE_DEVICE_TABLE(of, cpsw_of_mtable);

2508

2530

2509

static struct platform_driver cpsw_driver = {

2531

static struct platform_driver cpsw_driver = {

2510

.driver = {

2532

.driver = {

2511

.name = "cpsw",

2533

.name = "cpsw",

2512

.pm = &cpsw_pm_ops,

2534

.pm = &cpsw_pm_ops,

2513

.of_match_table = cpsw_of_mtable,

2535

.of_match_table = cpsw_of_mtable,

2514

},

2536

},

2515

.probe = cpsw_probe,

2537

.probe = cpsw_probe,

2516

.remove = cpsw_remove,

2538

.remove = cpsw_remove,

2517

};

2539

};

2518

2540

2519

static int __init cpsw_init(void)

2541

static int __init cpsw_init(void)

2520

{

2542

{

2521

return platform_driver_register(&cpsw_driver);

2543

return platform_driver_register(&cpsw_driver);

2522

}

2544

}

2523

late_initcall(cpsw_init);

2545

late_initcall(cpsw_init);

2524

2546

2525

static void __exit cpsw_exit(void)

2547

static void __exit cpsw_exit(void)

2526

{

2548

{

2527

platform_driver_unregister(&cpsw_driver);

2549

platform_driver_unregister(&cpsw_driver);

2528

}

2550

}

2529

module_exit(cpsw_exit);

2551

module_exit(cpsw_exit);

2530

2552

2531

MODULE_LICENSE("GPL");

2553

MODULE_LICENSE("GPL");

2532

MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");

2554

MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");

2533

MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");

2555

MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");

2534

MODULE_DESCRIPTION("TI CPSW Ethernet driver");

2556

MODULE_DESCRIPTION("TI CPSW Ethernet driver");

2535

2557

GITLAB

drivers: net: cpsw: discard dual emac default vlan configuration

 /*
  * Texas Instruments Ethernet Switch Driver
  *
  * Copyright (C) 2012 Texas Instruments
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation version 2.
  *
  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  * kind, whether express or implied; without even the implied warranty
  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/timer.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/irqreturn.h>
 #include <linux/interrupt.h>
 #include <linux/if_ether.h>
 #include <linux/etherdevice.h>
 #include <linux/netdevice.h>
 #include <linux/net_tstamp.h>
 #include <linux/phy.h>
 #include <linux/workqueue.h>
 #include <linux/delay.h>
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_net.h>
 #include <linux/of_device.h>
 #include <linux/if_vlan.h>
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/pinctrl/consumer.h>
 #include "cpsw.h"
 #include "cpsw_ale.h"
 #include "cpts.h"
 #include "davinci_cpdma.h"
 #define CPSW_DEBUG	(NETIF_MSG_HW		| NETIF_MSG_WOL		| \
 			 NETIF_MSG_DRV		| NETIF_MSG_LINK	| \
 			 NETIF_MSG_IFUP		| NETIF_MSG_INTR	| \
 			 NETIF_MSG_PROBE	| NETIF_MSG_TIMER	| \
 			 NETIF_MSG_IFDOWN	| NETIF_MSG_RX_ERR	| \
 			 NETIF_MSG_TX_ERR	| NETIF_MSG_TX_DONE	| \
 			 NETIF_MSG_PKTDATA	| NETIF_MSG_TX_QUEUED	| \
 			 NETIF_MSG_RX_STATUS)
 #define cpsw_info(priv, type, format, ...)		\
 do {								\
 	if (netif_msg_##type(priv) && net_ratelimit())		\
 		dev_info(priv->dev, format, ## __VA_ARGS__);	\
 } while (0)
 #define cpsw_err(priv, type, format, ...)		\
 do {								\
 	if (netif_msg_##type(priv) && net_ratelimit())		\
 		dev_err(priv->dev, format, ## __VA_ARGS__);	\
 } while (0)
 #define cpsw_dbg(priv, type, format, ...)		\
 do {								\
 	if (netif_msg_##type(priv) && net_ratelimit())		\
 		dev_dbg(priv->dev, format, ## __VA_ARGS__);	\
 } while (0)
 #define cpsw_notice(priv, type, format, ...)		\
 do {								\
 	if (netif_msg_##type(priv) && net_ratelimit())		\
 		dev_notice(priv->dev, format, ## __VA_ARGS__);	\
 } while (0)
 #define ALE_ALL_PORTS		0x7
 #define CPSW_MAJOR_VERSION(reg)		(reg >> 8 & 0x7)
 #define CPSW_MINOR_VERSION(reg)		(reg & 0xff)
 #define CPSW_RTL_VERSION(reg)		((reg >> 11) & 0x1f)
 #define CPSW_VERSION_1		0x19010a
 #define CPSW_VERSION_2		0x19010c
 #define CPSW_VERSION_3		0x19010f
 #define CPSW_VERSION_4		0x190112
 #define HOST_PORT_NUM		0
 #define SLIVER_SIZE		0x40
 #define CPSW1_HOST_PORT_OFFSET	0x028
 #define CPSW1_SLAVE_OFFSET	0x050
 #define CPSW1_SLAVE_SIZE	0x040
 #define CPSW1_CPDMA_OFFSET	0x100
 #define CPSW1_STATERAM_OFFSET	0x200
 #define CPSW1_HW_STATS		0x400
 #define CPSW1_CPTS_OFFSET	0x500
 #define CPSW1_ALE_OFFSET	0x600
 #define CPSW1_SLIVER_OFFSET	0x700
 #define CPSW2_HOST_PORT_OFFSET	0x108
 #define CPSW2_SLAVE_OFFSET	0x200
 #define CPSW2_SLAVE_SIZE	0x100
 #define CPSW2_CPDMA_OFFSET	0x800
 #define CPSW2_HW_STATS		0x900
 #define CPSW2_STATERAM_OFFSET	0xa00
 #define CPSW2_CPTS_OFFSET	0xc00
 #define CPSW2_ALE_OFFSET	0xd00
 #define CPSW2_SLIVER_OFFSET	0xd80
 #define CPSW2_BD_OFFSET		0x2000
 #define CPDMA_RXTHRESH		0x0c0
 #define CPDMA_RXFREE		0x0e0
 #define CPDMA_TXHDP		0x00
 #define CPDMA_RXHDP		0x20
 #define CPDMA_TXCP		0x40
 #define CPDMA_RXCP		0x60
 #define CPSW_POLL_WEIGHT	64
 #define CPSW_MIN_PACKET_SIZE	60
 #define CPSW_MAX_PACKET_SIZE	(1500 + 14 + 4 + 4)
 #define RX_PRIORITY_MAPPING	0x76543210
 #define TX_PRIORITY_MAPPING	0x33221100
 #define CPDMA_TX_PRIORITY_MAP	0x76543210
 #define CPSW_VLAN_AWARE		BIT(1)
 #define CPSW_ALE_VLAN_AWARE	1
 #define CPSW_FIFO_NORMAL_MODE		(0 << 16)
 #define CPSW_FIFO_DUAL_MAC_MODE		(1 << 16)
 #define CPSW_FIFO_RATE_LIMIT_MODE	(2 << 16)
 #define CPSW_INTPACEEN		(0x3f << 16)
 #define CPSW_INTPRESCALE_MASK	(0x7FF << 0)
 #define CPSW_CMINTMAX_CNT	63
 #define CPSW_CMINTMIN_CNT	2
 #define CPSW_CMINTMAX_INTVL	(1000 / CPSW_CMINTMIN_CNT)
 #define CPSW_CMINTMIN_INTVL	((1000 / CPSW_CMINTMAX_CNT) + 1)
 #define cpsw_enable_irq(priv)	\
 	do {			\
 		u32 i;		\
 		for (i = 0; i < priv->num_irqs; i++) \
 			enable_irq(priv->irqs_table[i]); \
 	} while (0)
 #define cpsw_disable_irq(priv)	\
 	do {			\
 		u32 i;		\
 		for (i = 0; i < priv->num_irqs; i++) \
 			disable_irq_nosync(priv->irqs_table[i]); \
 	} while (0)
 #define cpsw_slave_index(priv)				\
 		((priv->data.dual_emac) ? priv->emac_port :	\
 		priv->data.active_slave)
 static int debug_level;
 module_param(debug_level, int, 0);
 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 static int ale_ageout = 10;
 module_param(ale_ageout, int, 0);
 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 module_param(rx_packet_max, int, 0);
 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 struct cpsw_wr_regs {
 	u32	id_ver;
 	u32	soft_reset;
 	u32	control;
 	u32	int_control;
 	u32	rx_thresh_en;
 	u32	rx_en;
 	u32	tx_en;
 	u32	misc_en;
 	u32	mem_allign1[8];
 	u32	rx_thresh_stat;
 	u32	rx_stat;
 	u32	tx_stat;
 	u32	misc_stat;
 	u32	mem_allign2[8];
 	u32	rx_imax;
 	u32	tx_imax;
 };
 struct cpsw_ss_regs {
 	u32	id_ver;
 	u32	control;
 	u32	soft_reset;
 	u32	stat_port_en;
 	u32	ptype;
 	u32	soft_idle;
 	u32	thru_rate;
 	u32	gap_thresh;
 	u32	tx_start_wds;
 	u32	flow_control;
 	u32	vlan_ltype;
 	u32	ts_ltype;
 	u32	dlr_ltype;
 };
 /* CPSW_PORT_V1 */
 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 /* CPSW_PORT_V2 */
 #define CPSW2_CONTROL       0x00 /* Control Register */
 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 /* CPSW_PORT_V1 and V2 */
 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 /* CPSW_PORT_V2 only */
 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 /* Bit definitions for the CPSW2_CONTROL register */
 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 #define CTRL_V2_TS_BITS \
 	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 	 TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 #define CTRL_V3_TS_BITS \
 	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 	 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 	 TS_LTYPE1_EN)
 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 /* Bit definitions for the CPSW1_TS_CTL register */
 #define CPSW_V1_TS_RX_EN		BIT(0)
 #define CPSW_V1_TS_TX_EN		BIT(4)
 #define CPSW_V1_MSG_TYPE_OFS		16
 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 #define CPSW_V1_SEQ_ID_OFS_SHIFT	16
 struct cpsw_host_regs {
 	u32	max_blks;
 	u32	blk_cnt;
 	u32	tx_in_ctl;
 	u32	port_vlan;
 	u32	tx_pri_map;
 	u32	cpdma_tx_pri_map;
 	u32	cpdma_rx_chan_map;
 };
 struct cpsw_sliver_regs {
 	u32	id_ver;
 	u32	mac_control;
 	u32	mac_status;
 	u32	soft_reset;
 	u32	rx_maxlen;
 	u32	__reserved_0;
 	u32	rx_pause;
 	u32	tx_pause;
 	u32	__reserved_1;
 	u32	rx_pri_map;
 };
 struct cpsw_hw_stats {
 	u32	rxgoodframes;
 	u32	rxbroadcastframes;
 	u32	rxmulticastframes;
 	u32	rxpauseframes;
 	u32	rxcrcerrors;
 	u32	rxaligncodeerrors;
 	u32	rxoversizedframes;
 	u32	rxjabberframes;
 	u32	rxundersizedframes;
 	u32	rxfragments;
 	u32	__pad_0[2];
 	u32	rxoctets;
 	u32	txgoodframes;
 	u32	txbroadcastframes;
 	u32	txmulticastframes;
 	u32	txpauseframes;
 	u32	txdeferredframes;
 	u32	txcollisionframes;
 	u32	txsinglecollframes;
 	u32	txmultcollframes;
 	u32	txexcessivecollisions;
 	u32	txlatecollisions;
 	u32	txunderrun;
 	u32	txcarriersenseerrors;
 	u32	txoctets;
 	u32	octetframes64;
 	u32	octetframes65t127;
 	u32	octetframes128t255;
 	u32	octetframes256t511;
 	u32	octetframes512t1023;
 	u32	octetframes1024tup;
 	u32	netoctets;
 	u32	rxsofoverruns;
 	u32	rxmofoverruns;
 	u32	rxdmaoverruns;
 };
 struct cpsw_slave {
 	void __iomem			*regs;
 	struct cpsw_sliver_regs __iomem	*sliver;
 	int				slave_num;
 	u32				mac_control;
 	struct cpsw_slave_data		*data;
 	struct phy_device		*phy;
 	struct net_device		*ndev;
 	u32				port_vlan;
 	u32				open_stat;
 };
 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 {
 	return __raw_readl(slave->regs + offset);
 }
 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 {
 	__raw_writel(val, slave->regs + offset);
 }
 struct cpsw_priv {
 	spinlock_t			lock;
 	struct platform_device		*pdev;
 	struct net_device		*ndev;
 	struct napi_struct		napi;
 	struct device			*dev;
 	struct cpsw_platform_data	data;
 	struct cpsw_ss_regs __iomem	*regs;
 	struct cpsw_wr_regs __iomem	*wr_regs;
 	u8 __iomem			*hw_stats;
 	struct cpsw_host_regs __iomem	*host_port_regs;
 	u32				msg_enable;
 	u32				version;
 	u32				coal_intvl;
 	u32				bus_freq_mhz;
 	int				rx_packet_max;
 	int				host_port;
 	struct clk			*clk;
 	u8				mac_addr[ETH_ALEN];
 	struct cpsw_slave		*slaves;
 	struct cpdma_ctlr		*dma;
 	struct cpdma_chan		*txch, *rxch;
 	struct cpsw_ale			*ale;
 	bool				rx_pause;
 	bool				tx_pause;
 	/* snapshot of IRQ numbers */
 	u32 irqs_table[4];
 	u32 num_irqs;
 	bool irq_enabled;
 	struct cpts *cpts;
 	u32 emac_port;
 };
 struct cpsw_stats {
 	char stat_string[ETH_GSTRING_LEN];
 	int type;
 	int sizeof_stat;
 	int stat_offset;
 };
 enum {
 	CPSW_STATS,
 	CPDMA_RX_STATS,
 	CPDMA_TX_STATS,
 };
 #define CPSW_STAT(m)		CPSW_STATS,				\
 				sizeof(((struct cpsw_hw_stats *)0)->m), \
 				offsetof(struct cpsw_hw_stats, m)
 #define CPDMA_RX_STAT(m)	CPDMA_RX_STATS,				   \
 				sizeof(((struct cpdma_chan_stats *)0)->m), \
 				offsetof(struct cpdma_chan_stats, m)
 #define CPDMA_TX_STAT(m)	CPDMA_TX_STATS,				   \
 				sizeof(((struct cpdma_chan_stats *)0)->m), \
 				offsetof(struct cpdma_chan_stats, m)
 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 	{ "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 	{ "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 	{ "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 	{ "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 	{ "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 	{ "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 	{ "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 	{ "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 	{ "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 	{ "Rx Fragments", CPSW_STAT(rxfragments) },
 	{ "Rx Octets", CPSW_STAT(rxoctets) },
 	{ "Good Tx Frames", CPSW_STAT(txgoodframes) },
 	{ "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 	{ "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 	{ "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 	{ "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 	{ "Collisions", CPSW_STAT(txcollisionframes) },
 	{ "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 	{ "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 	{ "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 	{ "Late Collisions", CPSW_STAT(txlatecollisions) },
 	{ "Tx Underrun", CPSW_STAT(txunderrun) },
 	{ "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 	{ "Tx Octets", CPSW_STAT(txoctets) },
 	{ "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 	{ "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 	{ "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 	{ "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 	{ "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 	{ "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 	{ "Net Octets", CPSW_STAT(netoctets) },
 	{ "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 	{ "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 	{ "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 	{ "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 	{ "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 	{ "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 	{ "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 	{ "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 	{ "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 	{ "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 	{ "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 	{ "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 	{ "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 	{ "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 	{ "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 	{ "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 	{ "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 	{ "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 	{ "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 	{ "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 	{ "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 	{ "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 	{ "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 	{ "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 	{ "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 	{ "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 	{ "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 	{ "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 	{ "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 };
 #define CPSW_STATS_LEN	ARRAY_SIZE(cpsw_gstrings_stats)
 #define napi_to_priv(napi)	container_of(napi, struct cpsw_priv, napi)
 #define for_each_slave(priv, func, arg...)				\
 	do {								\
 		struct cpsw_slave *slave;				\
 		int n;							\
 		if (priv->data.dual_emac)				\
 			(func)((priv)->slaves + priv->emac_port, ##arg);\
 		else							\
 			for (n = (priv)->data.slaves,			\
 					slave = (priv)->slaves;		\
 					n; n--)				\
 				(func)(slave++, ##arg);			\
 	} while (0)
 #define cpsw_get_slave_ndev(priv, __slave_no__)				\
 	(priv->slaves[__slave_no__].ndev)
 #define cpsw_get_slave_priv(priv, __slave_no__)				\
 	((priv->slaves[__slave_no__].ndev) ?				\
 		netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)	\
 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)		\
 	do {								\
 		if (!priv->data.dual_emac)				\
 			break;						\
 		if (CPDMA_RX_SOURCE_PORT(status) == 1) {		\
 			ndev = cpsw_get_slave_ndev(priv, 0);		\
 			priv = netdev_priv(ndev);			\
 			skb->dev = ndev;				\
 		} else if (CPDMA_RX_SOURCE_PORT(status) == 2) {		\
 			ndev = cpsw_get_slave_ndev(priv, 1);		\
 			priv = netdev_priv(ndev);			\
 			skb->dev = ndev;				\
 		}							\
 	} while (0)
 #define cpsw_add_mcast(priv, addr)					\
 	do {								\
 		if (priv->data.dual_emac) {				\
 			struct cpsw_slave *slave = priv->slaves +	\
 						priv->emac_port;	\
 			int slave_port = cpsw_get_slave_port(priv,	\
 						slave->slave_num);	\
 			cpsw_ale_add_mcast(priv->ale, addr,		\
 				1 << slave_port | 1 << priv->host_port,	\
 				ALE_VLAN, slave->port_vlan, 0);		\
 		} else {						\
 			cpsw_ale_add_mcast(priv->ale, addr,		\
 				ALE_ALL_PORTS << priv->host_port,	\
 				0, 0, 0);				\
 		}							\
 	} while (0)
 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 {
 	if (priv->host_port == 0)
 		return slave_num + 1;
 	else
 		return slave_num;
 }
 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	struct cpsw_ale *ale = priv->ale;
 	int i;
 	if (priv->data.dual_emac) {
 		bool flag = false;
 		/* Enabling promiscuous mode for one interface will be
 		 * common for both the interface as the interface shares
 		 * the same hardware resource.
 		 */
 		for (i = 0; i < priv->data.slaves; i++)
 			if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 				flag = true;
 		if (!enable && flag) {
 			enable = true;
 			dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 		}
 		if (enable) {
 			/* Enable Bypass */
 			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 			dev_dbg(&ndev->dev, "promiscuity enabled\n");
 		} else {
 			/* Disable Bypass */
 			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 			dev_dbg(&ndev->dev, "promiscuity disabled\n");
 		}
 	} else {
 		if (enable) {
 			unsigned long timeout = jiffies + HZ;
 			/* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 			for (i = 0; i <= priv->data.slaves; i++) {
 				cpsw_ale_control_set(ale, i,
 						     ALE_PORT_NOLEARN, 1);
 				cpsw_ale_control_set(ale, i,
 						     ALE_PORT_NO_SA_UPDATE, 1);
 			}
 			/* Clear All Untouched entries */
 			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 			do {
 				cpu_relax();
 				if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 					break;
 			} while (time_after(timeout, jiffies));
 			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 			/* Clear all mcast from ALE */
 			cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 						 priv->host_port, -1);
 			/* Flood All Unicast Packets to Host port */
 			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 			dev_dbg(&ndev->dev, "promiscuity enabled\n");
 		} else {
 			/* Don't Flood All Unicast Packets to Host port */
 			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 			/* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 			for (i = 0; i <= priv->data.slaves; i++) {
 				cpsw_ale_control_set(ale, i,
 						     ALE_PORT_NOLEARN, 0);
 				cpsw_ale_control_set(ale, i,
 						     ALE_PORT_NO_SA_UPDATE, 0);
 			}
 			dev_dbg(&ndev->dev, "promiscuity disabled\n");
 		}
 	}
 }
 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	int vid;
 	if (priv->data.dual_emac)
 		vid = priv->slaves[priv->emac_port].port_vlan;
 	else
 		vid = priv->data.default_vlan;
 	if (ndev->flags & IFF_PROMISC) {
 		/* Enable promiscuous mode */
 		cpsw_set_promiscious(ndev, true);
 		cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 		return;
 	} else {
 		/* Disable promiscuous mode */
 		cpsw_set_promiscious(ndev, false);
 	}
 	/* Restore allmulti on vlans if necessary */
 	cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 	/* Clear all mcast from ALE */
 	cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
 				 vid);
 	if (!netdev_mc_empty(ndev)) {
 		struct netdev_hw_addr *ha;
 		/* program multicast address list into ALE register */
 		netdev_for_each_mc_addr(ha, ndev) {
 			cpsw_add_mcast(priv, (u8 *)ha->addr);
 		}
 	}
 }
 static void cpsw_intr_enable(struct cpsw_priv *priv)
 {
 	__raw_writel(0xFF, &priv->wr_regs->tx_en);
 	__raw_writel(0xFF, &priv->wr_regs->rx_en);
 	cpdma_ctlr_int_ctrl(priv->dma, true);
 	return;
 }
 static void cpsw_intr_disable(struct cpsw_priv *priv)
 {
 	__raw_writel(0, &priv->wr_regs->tx_en);
 	__raw_writel(0, &priv->wr_regs->rx_en);
 	cpdma_ctlr_int_ctrl(priv->dma, false);
 	return;
 }
 static void cpsw_tx_handler(void *token, int len, int status)
 {
 	struct sk_buff		*skb = token;
 	struct net_device	*ndev = skb->dev;
 	struct cpsw_priv	*priv = netdev_priv(ndev);
 	/* Check whether the queue is stopped due to stalled tx dma, if the
 	 * queue is stopped then start the queue as we have free desc for tx
 	 */
 	if (unlikely(netif_queue_stopped(ndev)))
 		netif_wake_queue(ndev);
 	cpts_tx_timestamp(priv->cpts, skb);
 	ndev->stats.tx_packets++;
 	ndev->stats.tx_bytes += len;
 	dev_kfree_skb_any(skb);
 }
 static void cpsw_rx_handler(void *token, int len, int status)
 {
 	struct sk_buff		*skb = token;
 	struct sk_buff		*new_skb;
 	struct net_device	*ndev = skb->dev;
 	struct cpsw_priv	*priv = netdev_priv(ndev);
 	int			ret = 0;
 	cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 	if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 		bool ndev_status = false;
 		struct cpsw_slave *slave = priv->slaves;
 		int n;
 		if (priv->data.dual_emac) {
 			/* In dual emac mode check for all interfaces */
 			for (n = priv->data.slaves; n; n--, slave++)
 				if (netif_running(slave->ndev))
 					ndev_status = true;
 		}
 		if (ndev_status && (status >= 0)) {
 			/* The packet received is for the interface which
 			 * is already down and the other interface is up
 			 * and running, intead of freeing which results
 			 * in reducing of the number of rx descriptor in
 			 * DMA engine, requeue skb back to cpdma.
 			 */
 			new_skb = skb;
 			goto requeue;
 		}
 		/* the interface is going down, skbs are purged */
 		dev_kfree_skb_any(skb);
 		return;
 	}
 	new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 	if (new_skb) {
 		skb_put(skb, len);
 		cpts_rx_timestamp(priv->cpts, skb);
 		skb->protocol = eth_type_trans(skb, ndev);
 		netif_receive_skb(skb);
 		ndev->stats.rx_bytes += len;
 		ndev->stats.rx_packets++;
 	} else {
 		ndev->stats.rx_dropped++;
 		new_skb = skb;
 	}
 requeue:
 	ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 			skb_tailroom(new_skb), 0);
 	if (WARN_ON(ret < 0))
 		dev_kfree_skb_any(new_skb);
 }
 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 {
 	struct cpsw_priv *priv = dev_id;
 	int value = irq - priv->irqs_table[0];
 	/* NOTICE: Ending IRQ here. The trick with the 'value' variable above
 	 * is to make sure we will always write the correct value to the EOI
 	 * register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2
 	 * for TX Interrupt and 3 for MISC Interrupt.
 	 */
 	cpdma_ctlr_eoi(priv->dma, value);
 	cpsw_intr_disable(priv);
 	if (priv->irq_enabled == true) {
 		cpsw_disable_irq(priv);
 		priv->irq_enabled = false;
 	}
 	if (netif_running(priv->ndev)) {
 		napi_schedule(&priv->napi);
 		return IRQ_HANDLED;
 	}
 	priv = cpsw_get_slave_priv(priv, 1);
 	if (!priv)
 		return IRQ_NONE;
 	if (netif_running(priv->ndev)) {
 		napi_schedule(&priv->napi);
 		return IRQ_HANDLED;
 	}
 	return IRQ_NONE;
 }
 static int cpsw_poll(struct napi_struct *napi, int budget)
 {
 	struct cpsw_priv	*priv = napi_to_priv(napi);
 	int			num_tx, num_rx;
 	num_tx = cpdma_chan_process(priv->txch, 128);
 	num_rx = cpdma_chan_process(priv->rxch, budget);
 	if (num_rx < budget) {
 		struct cpsw_priv *prim_cpsw;
 		napi_complete(napi);
 		cpsw_intr_enable(priv);
 		prim_cpsw = cpsw_get_slave_priv(priv, 0);
 		if (prim_cpsw->irq_enabled == false) {
 			prim_cpsw->irq_enabled = true;
 			cpsw_enable_irq(priv);
 		}
 	}
 	if (num_rx || num_tx)
 		cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 			 num_rx, num_tx);
 	return num_rx;
 }
 static inline void soft_reset(const char *module, void __iomem *reg)
 {
 	unsigned long timeout = jiffies + HZ;
 	__raw_writel(1, reg);
 	do {
 		cpu_relax();
 	} while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 	WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 }
 #define mac_hi(mac)	(((mac)[0] << 0) | ((mac)[1] << 8) |	\
 			 ((mac)[2] << 16) | ((mac)[3] << 24))
 #define mac_lo(mac)	(((mac)[4] << 0) | ((mac)[5] << 8))
 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 			       struct cpsw_priv *priv)
 {
 	slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 	slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 }
 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 			      struct cpsw_priv *priv, bool *link)
 {
 	struct phy_device	*phy = slave->phy;
 	u32			mac_control = 0;
 	u32			slave_port;
 	if (!phy)
 		return;
 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 	if (phy->link) {
 		mac_control = priv->data.mac_control;
 		/* enable forwarding */
 		cpsw_ale_control_set(priv->ale, slave_port,
 				     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 		if (phy->speed == 1000)
 			mac_control |= BIT(7);	/* GIGABITEN	*/
 		if (phy->duplex)
 			mac_control |= BIT(0);	/* FULLDUPLEXEN	*/
 		/* set speed_in input in case RMII mode is used in 100Mbps */
 		if (phy->speed == 100)
 			mac_control |= BIT(15);
 		else if (phy->speed == 10)
 			mac_control |= BIT(18); /* In Band mode */
 		if (priv->rx_pause)
 			mac_control |= BIT(3);
 		if (priv->tx_pause)
 			mac_control |= BIT(4);
 		*link = true;
 	} else {
 		mac_control = 0;
 		/* disable forwarding */
 		cpsw_ale_control_set(priv->ale, slave_port,
 				     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 	}
 	if (mac_control != slave->mac_control) {
 		phy_print_status(phy);
 		__raw_writel(mac_control, &slave->sliver->mac_control);
 	}
 	slave->mac_control = mac_control;
 }
 static void cpsw_adjust_link(struct net_device *ndev)
 {
 	struct cpsw_priv	*priv = netdev_priv(ndev);
 	bool			link = false;
 	for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 	if (link) {
 		netif_carrier_on(ndev);
 		if (netif_running(ndev))
 			netif_wake_queue(ndev);
 	} else {
 		netif_carrier_off(ndev);
 		netif_stop_queue(ndev);
 	}
 }
 static int cpsw_get_coalesce(struct net_device *ndev,
 				struct ethtool_coalesce *coal)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	coal->rx_coalesce_usecs = priv->coal_intvl;
 	return 0;
 }
 static int cpsw_set_coalesce(struct net_device *ndev,
 				struct ethtool_coalesce *coal)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	u32 int_ctrl;
 	u32 num_interrupts = 0;
 	u32 prescale = 0;
 	u32 addnl_dvdr = 1;
 	u32 coal_intvl = 0;
 	coal_intvl = coal->rx_coalesce_usecs;
 	int_ctrl =  readl(&priv->wr_regs->int_control);
 	prescale = priv->bus_freq_mhz * 4;
 	if (!coal->rx_coalesce_usecs) {
 		int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 		goto update_return;
 	}
 	if (coal_intvl < CPSW_CMINTMIN_INTVL)
 		coal_intvl = CPSW_CMINTMIN_INTVL;
 	if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 		/* Interrupt pacer works with 4us Pulse, we can
 		 * throttle further by dilating the 4us pulse.
 		 */
 		addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 		if (addnl_dvdr > 1) {
 			prescale *= addnl_dvdr;
 			if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 				coal_intvl = (CPSW_CMINTMAX_INTVL
 						* addnl_dvdr);
 		} else {
 			addnl_dvdr = 1;
 			coal_intvl = CPSW_CMINTMAX_INTVL;
 		}
 	}
 	num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 	writel(num_interrupts, &priv->wr_regs->rx_imax);
 	writel(num_interrupts, &priv->wr_regs->tx_imax);
 	int_ctrl |= CPSW_INTPACEEN;
 	int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 	int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 update_return:
 	writel(int_ctrl, &priv->wr_regs->int_control);
 	cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 	if (priv->data.dual_emac) {
 		int i;
 		for (i = 0; i < priv->data.slaves; i++) {
 			priv = netdev_priv(priv->slaves[i].ndev);
 			priv->coal_intvl = coal_intvl;
 		}
 	} else {
 		priv->coal_intvl = coal_intvl;
 	}
 	return 0;
 }
 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 {
 	switch (sset) {
 	case ETH_SS_STATS:
 		return CPSW_STATS_LEN;
 	default:
 		return -EOPNOTSUPP;
 	}
 }
 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
 {
 	u8 *p = data;
 	int i;
 	switch (stringset) {
 	case ETH_SS_STATS:
 		for (i = 0; i < CPSW_STATS_LEN; i++) {
 			memcpy(p, cpsw_gstrings_stats[i].stat_string,
 			       ETH_GSTRING_LEN);
 			p += ETH_GSTRING_LEN;
 		}
 		break;
 	}
 }
 static void cpsw_get_ethtool_stats(struct net_device *ndev,
 				    struct ethtool_stats *stats, u64 *data)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	struct cpdma_chan_stats rx_stats;
 	struct cpdma_chan_stats tx_stats;
 	u32 val;
 	u8 *p;
 	int i;
 	/* Collect Davinci CPDMA stats for Rx and Tx Channel */
 	cpdma_chan_get_stats(priv->rxch, &rx_stats);
 	cpdma_chan_get_stats(priv->txch, &tx_stats);
 	for (i = 0; i < CPSW_STATS_LEN; i++) {
 		switch (cpsw_gstrings_stats[i].type) {
 		case CPSW_STATS:
 			val = readl(priv->hw_stats +
 				    cpsw_gstrings_stats[i].stat_offset);
 			data[i] = val;
 			break;
 		case CPDMA_RX_STATS:
 			p = (u8 *)&rx_stats +
 				cpsw_gstrings_stats[i].stat_offset;
 			data[i] = *(u32 *)p;
 			break;
 		case CPDMA_TX_STATS:
 			p = (u8 *)&tx_stats +
 				cpsw_gstrings_stats[i].stat_offset;
 			data[i] = *(u32 *)p;
 			break;
 		}
 	}
 }
 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
 {
 	u32 i;
 	u32 usage_count = 0;
 	if (!priv->data.dual_emac)
 		return 0;
 	for (i = 0; i < priv->data.slaves; i++)
 		if (priv->slaves[i].open_stat)
 			usage_count++;
 	return usage_count;
 }
 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
 			struct cpsw_priv *priv, struct sk_buff *skb)
 {
 	if (!priv->data.dual_emac)
 		return cpdma_chan_submit(priv->txch, skb, skb->data,
 				  skb->len, 0);
 	if (ndev == cpsw_get_slave_ndev(priv, 0))
 		return cpdma_chan_submit(priv->txch, skb, skb->data,
 				  skb->len, 1);
 	else
 		return cpdma_chan_submit(priv->txch, skb, skb->data,
 				  skb->len, 2);
 }
 static inline void cpsw_add_dual_emac_def_ale_entries(
 		struct cpsw_priv *priv, struct cpsw_slave *slave,
 		u32 slave_port)
 {
 	u32 port_mask = 1 << slave_port | 1 << priv->host_port;
 	if (priv->version == CPSW_VERSION_1)
 		slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
 	else
 		slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
 	cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
 			  port_mask, port_mask, 0);
 	cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 			   port_mask, ALE_VLAN, slave->port_vlan, 0);
 	cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
 		priv->host_port, ALE_VLAN, slave->port_vlan);
 }
 static void soft_reset_slave(struct cpsw_slave *slave)
 {
 	char name[32];
 	snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
 	soft_reset(name, &slave->sliver->soft_reset);
 }
 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
 {
 	u32 slave_port;
 	soft_reset_slave(slave);
 	/* setup priority mapping */
 	__raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
 	switch (priv->version) {
 	case CPSW_VERSION_1:
 		slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
 		break;
 	case CPSW_VERSION_2:
 	case CPSW_VERSION_3:
 	case CPSW_VERSION_4:
 		slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
 		break;
 	}
 	/* setup max packet size, and mac address */
 	__raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
 	cpsw_set_slave_mac(slave, priv);
 	slave->mac_control = 0;	/* no link yet */
 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 	if (priv->data.dual_emac)
 		cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
 	else
 		cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 				   1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
 	slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
 				 &cpsw_adjust_link, slave->data->phy_if);
 	if (IS_ERR(slave->phy)) {
 		dev_err(priv->dev, "phy %s not found on slave %d\n",
 			slave->data->phy_id, slave->slave_num);
 		slave->phy = NULL;
 	} else {
 		dev_info(priv->dev, "phy found : id is : 0x%x\n",
 			 slave->phy->phy_id);
 		phy_start(slave->phy);
 		/* Configure GMII_SEL register */
 		cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
 			     slave->slave_num);
 	}
 }
 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
 {
 	const int vlan = priv->data.default_vlan;
 	const int port = priv->host_port;
 	u32 reg;
 	int i;
 	int unreg_mcast_mask;
 	reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
 	       CPSW2_PORT_VLAN;
 	writel(vlan, &priv->host_port_regs->port_vlan);
 	for (i = 0; i < priv->data.slaves; i++)
 		slave_write(priv->slaves + i, vlan, reg);
 	if (priv->ndev->flags & IFF_ALLMULTI)
 		unreg_mcast_mask = ALE_ALL_PORTS;
 	else
 		unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
 	cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
 			  ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
 			  unreg_mcast_mask << port);
 }
 static void cpsw_init_host_port(struct cpsw_priv *priv)
 {
 	u32 control_reg;
 	u32 fifo_mode;
 	/* soft reset the controller and initialize ale */
 	soft_reset("cpsw", &priv->regs->soft_reset);
 	cpsw_ale_start(priv->ale);
 	/* switch to vlan unaware mode */
 	cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
 			     CPSW_ALE_VLAN_AWARE);
 	control_reg = readl(&priv->regs->control);
 	control_reg |= CPSW_VLAN_AWARE;
 	writel(control_reg, &priv->regs->control);
 	fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
 		     CPSW_FIFO_NORMAL_MODE;
 	writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
 	/* setup host port priority mapping */
 	__raw_writel(CPDMA_TX_PRIORITY_MAP,
 		     &priv->host_port_regs->cpdma_tx_pri_map);
 	__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 	cpsw_ale_control_set(priv->ale, priv->host_port,
 			     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 	if (!priv->data.dual_emac) {
 		cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
 				   0, 0);
 		cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 				   1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
 	}
 }
 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
 {
 	u32 slave_port;
 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 	if (!slave->phy)
 		return;
 	phy_stop(slave->phy);
 	phy_disconnect(slave->phy);
 	slave->phy = NULL;
 	cpsw_ale_control_set(priv->ale, slave_port,
 			     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 }
 static int cpsw_ndo_open(struct net_device *ndev)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	struct cpsw_priv *prim_cpsw;
 	int i, ret;
 	u32 reg;
 	if (!cpsw_common_res_usage_state(priv))
 		cpsw_intr_disable(priv);
 	netif_carrier_off(ndev);
 	pm_runtime_get_sync(&priv->pdev->dev);
 	reg = priv->version;
 	dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
 		 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
 		 CPSW_RTL_VERSION(reg));
 	/* initialize host and slave ports */
 	if (!cpsw_common_res_usage_state(priv))
 		cpsw_init_host_port(priv);
 	for_each_slave(priv, cpsw_slave_open, priv);
 	/* Add default VLAN */
 	if (!priv->data.dual_emac)
 		cpsw_add_default_vlan(priv);
 	else
 		cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
 				  ALE_ALL_PORTS << priv->host_port,
 				  ALE_ALL_PORTS << priv->host_port, 0, 0);
 	if (!cpsw_common_res_usage_state(priv)) {
 		/* setup tx dma to fixed prio and zero offset */
 		cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
 		cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
 		/* disable priority elevation */
 		__raw_writel(0, &priv->regs->ptype);
 		/* enable statistics collection only on all ports */
 		__raw_writel(0x7, &priv->regs->stat_port_en);
 		/* Enable internal fifo flow control */
 		writel(0x7, &priv->regs->flow_control);
 		if (WARN_ON(!priv->data.rx_descs))
 			priv->data.rx_descs = 128;
 		for (i = 0; i < priv->data.rx_descs; i++) {
 			struct sk_buff *skb;
 			ret = -ENOMEM;
 			skb = __netdev_alloc_skb_ip_align(priv->ndev,
 					priv->rx_packet_max, GFP_KERNEL);
 			if (!skb)
 				goto err_cleanup;
 			ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
 					skb_tailroom(skb), 0);
 			if (ret < 0) {
 				kfree_skb(skb);
 				goto err_cleanup;
 			}
 		}
 		/* continue even if we didn't manage to submit all
 		 * receive descs
 		 */
 		cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
 		if (cpts_register(&priv->pdev->dev, priv->cpts,
 				  priv->data.cpts_clock_mult,
 				  priv->data.cpts_clock_shift))
 			dev_err(priv->dev, "error registering cpts device\n");
 	}
 	/* Enable Interrupt pacing if configured */
 	if (priv->coal_intvl != 0) {
 		struct ethtool_coalesce coal;
 		coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
 		cpsw_set_coalesce(ndev, &coal);
 	}
 	napi_enable(&priv->napi);
 	cpdma_ctlr_start(priv->dma);
 	cpsw_intr_enable(priv);
 	prim_cpsw = cpsw_get_slave_priv(priv, 0);
 	if (prim_cpsw->irq_enabled == false) {
 		if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
 			prim_cpsw->irq_enabled = true;
 			cpsw_enable_irq(prim_cpsw);
 		}
 	}
 	if (priv->data.dual_emac)
 		priv->slaves[priv->emac_port].open_stat = true;
 	return 0;
 err_cleanup:
 	cpdma_ctlr_stop(priv->dma);
 	for_each_slave(priv, cpsw_slave_stop, priv);
 	pm_runtime_put_sync(&priv->pdev->dev);
 	netif_carrier_off(priv->ndev);
 	return ret;
 }
 static int cpsw_ndo_stop(struct net_device *ndev)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	cpsw_info(priv, ifdown, "shutting down cpsw device\n");
 	netif_stop_queue(priv->ndev);
 	napi_disable(&priv->napi);
 	netif_carrier_off(priv->ndev);
 	if (cpsw_common_res_usage_state(priv) <= 1) {
 		cpts_unregister(priv->cpts);
 		cpsw_intr_disable(priv);
 		cpdma_ctlr_int_ctrl(priv->dma, false);
 		cpdma_ctlr_stop(priv->dma);
 		cpsw_ale_stop(priv->ale);
 	}
 	for_each_slave(priv, cpsw_slave_stop, priv);
 	pm_runtime_put_sync(&priv->pdev->dev);
 	if (priv->data.dual_emac)
 		priv->slaves[priv->emac_port].open_stat = false;
 	return 0;
 }
 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
 				       struct net_device *ndev)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	int ret;
 	ndev->trans_start = jiffies;
 	if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
 		cpsw_err(priv, tx_err, "packet pad failed\n");
 		ndev->stats.tx_dropped++;
 		return NETDEV_TX_OK;
 	}
 	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
 				priv->cpts->tx_enable)
 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
 	skb_tx_timestamp(skb);
 	ret = cpsw_tx_packet_submit(ndev, priv, skb);
 	if (unlikely(ret != 0)) {
 		cpsw_err(priv, tx_err, "desc submit failed\n");
 		goto fail;
 	}
 	/* If there is no more tx desc left free then we need to
 	 * tell the kernel to stop sending us tx frames.
 	 */
 	if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
 		netif_stop_queue(ndev);
 	return NETDEV_TX_OK;
 fail:
 	ndev->stats.tx_dropped++;
 	netif_stop_queue(ndev);
 	return NETDEV_TX_BUSY;
 }
 #ifdef CONFIG_TI_CPTS
 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
 {
 	struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
 	u32 ts_en, seq_id;
 	if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
 		slave_write(slave, 0, CPSW1_TS_CTL);
 		return;
 	}
 	seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
 	ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
 	if (priv->cpts->tx_enable)
 		ts_en |= CPSW_V1_TS_TX_EN;
 	if (priv->cpts->rx_enable)
 		ts_en |= CPSW_V1_TS_RX_EN;
 	slave_write(slave, ts_en, CPSW1_TS_CTL);
 	slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
 }
 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
 {
 	struct cpsw_slave *slave;
 	u32 ctrl, mtype;
 	if (priv->data.dual_emac)
 		slave = &priv->slaves[priv->emac_port];
 	else
 		slave = &priv->slaves[priv->data.active_slave];
 	ctrl = slave_read(slave, CPSW2_CONTROL);
 	switch (priv->version) {
 	case CPSW_VERSION_2:
 		ctrl &= ~CTRL_V2_ALL_TS_MASK;
 		if (priv->cpts->tx_enable)
 			ctrl |= CTRL_V2_TX_TS_BITS;
 		if (priv->cpts->rx_enable)
 			ctrl |= CTRL_V2_RX_TS_BITS;
 	break;
 	case CPSW_VERSION_3:
 	default:
 		ctrl &= ~CTRL_V3_ALL_TS_MASK;
 		if (priv->cpts->tx_enable)
 			ctrl |= CTRL_V3_TX_TS_BITS;
 		if (priv->cpts->rx_enable)
 			ctrl |= CTRL_V3_RX_TS_BITS;
 	break;
 	}
 	mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
 	slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
 	slave_write(slave, ctrl, CPSW2_CONTROL);
 	__raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
 }
 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 {
 	struct cpsw_priv *priv = netdev_priv(dev);
 	struct cpts *cpts = priv->cpts;
 	struct hwtstamp_config cfg;
 	if (priv->version != CPSW_VERSION_1 &&
 	    priv->version != CPSW_VERSION_2 &&
 	    priv->version != CPSW_VERSION_3)
 		return -EOPNOTSUPP;
 	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 		return -EFAULT;
 	/* reserved for future extensions */
 	if (cfg.flags)
 		return -EINVAL;
 	if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
 		return -ERANGE;
 	switch (cfg.rx_filter) {
 	case HWTSTAMP_FILTER_NONE:
 		cpts->rx_enable = 0;
 		break;
 	case HWTSTAMP_FILTER_ALL:
 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 		return -ERANGE;
 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 		cpts->rx_enable = 1;
 		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 		break;
 	default:
 		return -ERANGE;
 	}
 	cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
 	switch (priv->version) {
 	case CPSW_VERSION_1:
 		cpsw_hwtstamp_v1(priv);
 		break;
 	case CPSW_VERSION_2:
 	case CPSW_VERSION_3:
 		cpsw_hwtstamp_v2(priv);
 		break;
 	default:
 		WARN_ON(1);
 	}
 	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 }
 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 {
 	struct cpsw_priv *priv = netdev_priv(dev);
 	struct cpts *cpts = priv->cpts;
 	struct hwtstamp_config cfg;
 	if (priv->version != CPSW_VERSION_1 &&
 	    priv->version != CPSW_VERSION_2 &&
 	    priv->version != CPSW_VERSION_3)
 		return -EOPNOTSUPP;
 	cfg.flags = 0;
 	cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 	cfg.rx_filter = (cpts->rx_enable ?
 			 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
 	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 }
 #endif /*CONFIG_TI_CPTS*/
 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 {
 	struct cpsw_priv *priv = netdev_priv(dev);
 	int slave_no = cpsw_slave_index(priv);
 	if (!netif_running(dev))
 		return -EINVAL;
 	switch (cmd) {
 #ifdef CONFIG_TI_CPTS
 	case SIOCSHWTSTAMP:
 		return cpsw_hwtstamp_set(dev, req);
 	case SIOCGHWTSTAMP:
 		return cpsw_hwtstamp_get(dev, req);
 #endif
 	}
 	if (!priv->slaves[slave_no].phy)
 		return -EOPNOTSUPP;
 	return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
 }
 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
 	ndev->stats.tx_errors++;
 	cpsw_intr_disable(priv);
 	cpdma_ctlr_int_ctrl(priv->dma, false);
 	cpdma_chan_stop(priv->txch);
 	cpdma_chan_start(priv->txch);
 	cpdma_ctlr_int_ctrl(priv->dma, true);
 	cpsw_intr_enable(priv);
 }
 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	struct sockaddr *addr = (struct sockaddr *)p;
 	int flags = 0;
 	u16 vid = 0;
 	if (!is_valid_ether_addr(addr->sa_data))
 		return -EADDRNOTAVAIL;
 	if (priv->data.dual_emac) {
 		vid = priv->slaves[priv->emac_port].port_vlan;
 		flags = ALE_VLAN;
 	}
 	cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
 			   flags, vid);
 	cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
 			   flags, vid);
 	memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
 	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
 	for_each_slave(priv, cpsw_set_slave_mac, priv);
 	return 0;
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void cpsw_ndo_poll_controller(struct net_device *ndev)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	cpsw_intr_disable(priv);
 	cpdma_ctlr_int_ctrl(priv->dma, false);
 	cpsw_interrupt(ndev->irq, priv);
 	cpdma_ctlr_int_ctrl(priv->dma, true);
 	cpsw_intr_enable(priv);
 }
 #endif
 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
 				unsigned short vid)
 {
 	int ret;
 	int unreg_mcast_mask;
 	if (priv->ndev->flags & IFF_ALLMULTI)
 		unreg_mcast_mask = ALE_ALL_PORTS;
 	else
 		unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
 	ret = cpsw_ale_add_vlan(priv->ale, vid,
 				ALE_ALL_PORTS << priv->host_port,
 				0, ALE_ALL_PORTS << priv->host_port,
 				unreg_mcast_mask << priv->host_port);
 	if (ret != 0)
 		return ret;
 	ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
 				 priv->host_port, ALE_VLAN, vid);
 	if (ret != 0)
 		goto clean_vid;
 	ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 				 ALE_ALL_PORTS << priv->host_port,
 				 ALE_VLAN, vid, 0);
 	if (ret != 0)
 		goto clean_vlan_ucast;
 	return 0;
 clean_vlan_ucast:
 	cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
 			    priv->host_port, ALE_VLAN, vid);
 clean_vid:
 	cpsw_ale_del_vlan(priv->ale, vid, 0);
 	return ret;
 }
 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
 				    __be16 proto, u16 vid)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	if (vid == priv->data.default_vlan)
 		return 0;
+	if (priv->data.dual_emac) {
+		/* In dual EMAC, reserved VLAN id should not be used for
+		 * creating VLAN interfaces as this can break the dual
+		 * EMAC port separation
+		 */
+		int i;
+		for (i = 0; i < priv->data.slaves; i++) {
+			if (vid == priv->slaves[i].port_vlan)
+				return -EINVAL;
+		}
+	}
 	dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
 	return cpsw_add_vlan_ale_entry(priv, vid);
 }
 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
 				     __be16 proto, u16 vid)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	int ret;
 	if (vid == priv->data.default_vlan)
 		return 0;
+	if (priv->data.dual_emac) {
+		int i;
+		for (i = 0; i < priv->data.slaves; i++) {
+			if (vid == priv->slaves[i].port_vlan)
+				return -EINVAL;
+		}
+	}
 	dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
 	ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
 	if (ret != 0)
 		return ret;
 	ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
 				 priv->host_port, ALE_VLAN, vid);
 	if (ret != 0)
 		return ret;
 	return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
 				  0, ALE_VLAN, vid);
 }
 static const struct net_device_ops cpsw_netdev_ops = {
 	.ndo_open		= cpsw_ndo_open,
 	.ndo_stop		= cpsw_ndo_stop,
 	.ndo_start_xmit		= cpsw_ndo_start_xmit,
 	.ndo_set_mac_address	= cpsw_ndo_set_mac_address,
 	.ndo_do_ioctl		= cpsw_ndo_ioctl,
 	.ndo_validate_addr	= eth_validate_addr,
 	.ndo_change_mtu		= eth_change_mtu,
 	.ndo_tx_timeout		= cpsw_ndo_tx_timeout,
 	.ndo_set_rx_mode	= cpsw_ndo_set_rx_mode,
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	.ndo_poll_controller	= cpsw_ndo_poll_controller,
 #endif
 	.ndo_vlan_rx_add_vid	= cpsw_ndo_vlan_rx_add_vid,
 	.ndo_vlan_rx_kill_vid	= cpsw_ndo_vlan_rx_kill_vid,
 };
 static int cpsw_get_regs_len(struct net_device *ndev)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
 }
 static void cpsw_get_regs(struct net_device *ndev,
 			  struct ethtool_regs *regs, void *p)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	u32 *reg = p;
 	/* update CPSW IP version */
 	regs->version = priv->version;
 	cpsw_ale_dump(priv->ale, reg);
 }
 static void cpsw_get_drvinfo(struct net_device *ndev,
 			     struct ethtool_drvinfo *info)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	strlcpy(info->driver, "cpsw", sizeof(info->driver));
 	strlcpy(info->version, "1.0", sizeof(info->version));
 	strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
 	info->regdump_len = cpsw_get_regs_len(ndev);
 }
 static u32 cpsw_get_msglevel(struct net_device *ndev)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	return priv->msg_enable;
 }
 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	priv->msg_enable = value;
 }
 static int cpsw_get_ts_info(struct net_device *ndev,
 			    struct ethtool_ts_info *info)
 {
 #ifdef CONFIG_TI_CPTS
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	info->so_timestamping =
 		SOF_TIMESTAMPING_TX_HARDWARE |
 		SOF_TIMESTAMPING_TX_SOFTWARE |
 		SOF_TIMESTAMPING_RX_HARDWARE |
 		SOF_TIMESTAMPING_RX_SOFTWARE |
 		SOF_TIMESTAMPING_SOFTWARE |
 		SOF_TIMESTAMPING_RAW_HARDWARE;
 	info->phc_index = priv->cpts->phc_index;
 	info->tx_types =
 		(1 << HWTSTAMP_TX_OFF) |
 		(1 << HWTSTAMP_TX_ON);
 	info->rx_filters =
 		(1 << HWTSTAMP_FILTER_NONE) |
 		(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
 #else
 	info->so_timestamping =
 		SOF_TIMESTAMPING_TX_SOFTWARE |
 		SOF_TIMESTAMPING_RX_SOFTWARE |
 		SOF_TIMESTAMPING_SOFTWARE;
 	info->phc_index = -1;
 	info->tx_types = 0;
 	info->rx_filters = 0;
 #endif
 	return 0;
 }
 static int cpsw_get_settings(struct net_device *ndev,
 			     struct ethtool_cmd *ecmd)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	int slave_no = cpsw_slave_index(priv);
 	if (priv->slaves[slave_no].phy)
 		return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
 	else
 		return -EOPNOTSUPP;
 }
 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	int slave_no = cpsw_slave_index(priv);
 	if (priv->slaves[slave_no].phy)
 		return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
 	else
 		return -EOPNOTSUPP;
 }
 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	int slave_no = cpsw_slave_index(priv);
 	wol->supported = 0;
 	wol->wolopts = 0;
 	if (priv->slaves[slave_no].phy)
 		phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
 }
 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	int slave_no = cpsw_slave_index(priv);
 	if (priv->slaves[slave_no].phy)
 		return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
 	else
 		return -EOPNOTSUPP;
 }
 static void cpsw_get_pauseparam(struct net_device *ndev,
 				struct ethtool_pauseparam *pause)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	pause->autoneg = AUTONEG_DISABLE;
 	pause->rx_pause = priv->rx_pause ? true : false;
 	pause->tx_pause = priv->tx_pause ? true : false;
 }
 static int cpsw_set_pauseparam(struct net_device *ndev,
 			       struct ethtool_pauseparam *pause)
 {
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	bool link;
 	priv->rx_pause = pause->rx_pause ? true : false;
 	priv->tx_pause = pause->tx_pause ? true : false;
 	for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 	return 0;
 }
 static const struct ethtool_ops cpsw_ethtool_ops = {
 	.get_drvinfo	= cpsw_get_drvinfo,
 	.get_msglevel	= cpsw_get_msglevel,
 	.set_msglevel	= cpsw_set_msglevel,
 	.get_link	= ethtool_op_get_link,
 	.get_ts_info	= cpsw_get_ts_info,
 	.get_settings	= cpsw_get_settings,
 	.set_settings	= cpsw_set_settings,
 	.get_coalesce	= cpsw_get_coalesce,
 	.set_coalesce	= cpsw_set_coalesce,
 	.get_sset_count		= cpsw_get_sset_count,
 	.get_strings		= cpsw_get_strings,
 	.get_ethtool_stats	= cpsw_get_ethtool_stats,
 	.get_pauseparam		= cpsw_get_pauseparam,
 	.set_pauseparam		= cpsw_set_pauseparam,
 	.get_wol	= cpsw_get_wol,
 	.set_wol	= cpsw_set_wol,
 	.get_regs_len	= cpsw_get_regs_len,
 	.get_regs	= cpsw_get_regs,
 };
 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
 			    u32 slave_reg_ofs, u32 sliver_reg_ofs)
 {
 	void __iomem		*regs = priv->regs;
 	int			slave_num = slave->slave_num;
 	struct cpsw_slave_data	*data = priv->data.slave_data + slave_num;
 	slave->data	= data;
 	slave->regs	= regs + slave_reg_ofs;
 	slave->sliver	= regs + sliver_reg_ofs;
 	slave->port_vlan = data->dual_emac_res_vlan;
 }
 #define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)
 #define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)
 static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,
 		u8 *mac_addr)
 {
 	u32 macid_lo;
 	u32 macid_hi;
 	struct regmap *syscon;
 	syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
 	if (IS_ERR(syscon)) {
 		if (PTR_ERR(syscon) == -ENODEV)
 			return 0;
 		return PTR_ERR(syscon);
 	}
 	regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), &macid_lo);
 	regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), &macid_hi);
 	mac_addr[5] = (macid_lo >> 8) & 0xff;
 	mac_addr[4] = macid_lo & 0xff;
 	mac_addr[3] = (macid_hi >> 24) & 0xff;
 	mac_addr[2] = (macid_hi >> 16) & 0xff;
 	mac_addr[1] = (macid_hi >> 8) & 0xff;
 	mac_addr[0] = macid_hi & 0xff;
 	return 0;
 }
 static int cpsw_probe_dt(struct cpsw_platform_data *data,
 			 struct platform_device *pdev)
 {
 	struct device_node *node = pdev->dev.of_node;
 	struct device_node *slave_node;
 	int i = 0, ret;
 	u32 prop;
 	if (!node)
 		return -EINVAL;
 	if (of_property_read_u32(node, "slaves", &prop)) {
 		dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
 		return -EINVAL;
 	}
 	data->slaves = prop;
 	if (of_property_read_u32(node, "active_slave", &prop)) {
 		dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
 		return -EINVAL;
 	}
 	data->active_slave = prop;
 	if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
 		dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
 		return -EINVAL;
 	}
 	data->cpts_clock_mult = prop;
 	if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
 		dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
 		return -EINVAL;
 	}
 	data->cpts_clock_shift = prop;
 	data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
 					* sizeof(struct cpsw_slave_data),
 					GFP_KERNEL);
 	if (!data->slave_data)
 		return -ENOMEM;
 	if (of_property_read_u32(node, "cpdma_channels", &prop)) {
 		dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
 		return -EINVAL;
 	}
 	data->channels = prop;
 	if (of_property_read_u32(node, "ale_entries", &prop)) {
 		dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
 		return -EINVAL;
 	}
 	data->ale_entries = prop;
 	if (of_property_read_u32(node, "bd_ram_size", &prop)) {
 		dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
 		return -EINVAL;
 	}
 	data->bd_ram_size = prop;
 	if (of_property_read_u32(node, "rx_descs", &prop)) {
 		dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
 		return -EINVAL;
 	}
 	data->rx_descs = prop;
 	if (of_property_read_u32(node, "mac_control", &prop)) {
 		dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
 		return -EINVAL;
 	}
 	data->mac_control = prop;
 	if (of_property_read_bool(node, "dual_emac"))
 		data->dual_emac = 1;
 	/*
 	 * Populate all the child nodes here...
 	 */
 	ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
 	/* We do not want to force this, as in some cases may not have child */
 	if (ret)
 		dev_warn(&pdev->dev, "Doesn't have any child node\n");
 	for_each_child_of_node(node, slave_node) {
 		struct cpsw_slave_data *slave_data = data->slave_data + i;
 		const void *mac_addr = NULL;
 		u32 phyid;
 		int lenp;
 		const __be32 *parp;
 		struct device_node *mdio_node;
 		struct platform_device *mdio;
 		/* This is no slave child node, continue */
 		if (strcmp(slave_node->name, "slave"))
 			continue;
 		parp = of_get_property(slave_node, "phy_id", &lenp);
 		if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
 			dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
 			goto no_phy_slave;
 		}
 		mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
 		phyid = be32_to_cpup(parp+1);
 		mdio = of_find_device_by_node(mdio_node);
 		of_node_put(mdio_node);
 		if (!mdio) {
 			dev_err(&pdev->dev, "Missing mdio platform device\n");
 			return -EINVAL;
 		}
 		snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
 			 PHY_ID_FMT, mdio->name, phyid);
 		slave_data->phy_if = of_get_phy_mode(slave_node);
 		if (slave_data->phy_if < 0) {
 			dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
 				i);
 			return slave_data->phy_if;
 		}
 no_phy_slave:
 		mac_addr = of_get_mac_address(slave_node);
 		if (mac_addr) {
 			memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
 		} else {
 			if (of_machine_is_compatible("ti,am33xx")) {
 				ret = cpsw_am33xx_cm_get_macid(&pdev->dev, i,
 							slave_data->mac_addr);
 				if (ret)
 					return ret;
 			}
 		}
 		if (data->dual_emac) {
 			if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
 						 &prop)) {
 				dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
 				slave_data->dual_emac_res_vlan = i+1;
 				dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
 					slave_data->dual_emac_res_vlan, i);
 			} else {
 				slave_data->dual_emac_res_vlan = prop;
 			}
 		}
 		i++;
 		if (i == data->slaves)
 			break;
 	}
 	return 0;
 }
 static int cpsw_probe_dual_emac(struct platform_device *pdev,
 				struct cpsw_priv *priv)
 {
 	struct cpsw_platform_data	*data = &priv->data;
 	struct net_device		*ndev;
 	struct cpsw_priv		*priv_sl2;
 	int ret = 0, i;
 	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
 	if (!ndev) {
 		dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
 		return -ENOMEM;
 	}
 	priv_sl2 = netdev_priv(ndev);
 	spin_lock_init(&priv_sl2->lock);
 	priv_sl2->data = *data;
 	priv_sl2->pdev = pdev;
 	priv_sl2->ndev = ndev;
 	priv_sl2->dev  = &ndev->dev;
 	priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
 	priv_sl2->rx_packet_max = max(rx_packet_max, 128);
 	if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
 		memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
 			ETH_ALEN);
 		dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
 	} else {
 		random_ether_addr(priv_sl2->mac_addr);
 		dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
 	}
 	memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
 	priv_sl2->slaves = priv->slaves;
 	priv_sl2->clk = priv->clk;
 	priv_sl2->coal_intvl = 0;
 	priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
 	priv_sl2->regs = priv->regs;
 	priv_sl2->host_port = priv->host_port;
 	priv_sl2->host_port_regs = priv->host_port_regs;
 	priv_sl2->wr_regs = priv->wr_regs;
 	priv_sl2->hw_stats = priv->hw_stats;
 	priv_sl2->dma = priv->dma;
 	priv_sl2->txch = priv->txch;
 	priv_sl2->rxch = priv->rxch;
 	priv_sl2->ale = priv->ale;
 	priv_sl2->emac_port = 1;
 	priv->slaves[1].ndev = ndev;
 	priv_sl2->cpts = priv->cpts;
 	priv_sl2->version = priv->version;
 	for (i = 0; i < priv->num_irqs; i++) {
 		priv_sl2->irqs_table[i] = priv->irqs_table[i];
 		priv_sl2->num_irqs = priv->num_irqs;
 	}
 	ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
 	ndev->netdev_ops = &cpsw_netdev_ops;
 	ndev->ethtool_ops = &cpsw_ethtool_ops;
 	netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
 	/* register the network device */
 	SET_NETDEV_DEV(ndev, &pdev->dev);
 	ret = register_netdev(ndev);
 	if (ret) {
 		dev_err(&pdev->dev, "cpsw: error registering net device\n");
 		free_netdev(ndev);
 		ret = -ENODEV;
 	}
 	return ret;
 }
 static int cpsw_probe(struct platform_device *pdev)
 {
 	struct cpsw_platform_data	*data;
 	struct net_device		*ndev;
 	struct cpsw_priv		*priv;
 	struct cpdma_params		dma_params;
 	struct cpsw_ale_params		ale_params;
 	void __iomem			*ss_regs;
 	struct resource			*res, *ss_res;
 	u32 slave_offset, sliver_offset, slave_size;
 	int ret = 0, i, k = 0;
 	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
 	if (!ndev) {
 		dev_err(&pdev->dev, "error allocating net_device\n");
 		return -ENOMEM;
 	}
 	platform_set_drvdata(pdev, ndev);
 	priv = netdev_priv(ndev);
 	spin_lock_init(&priv->lock);
 	priv->pdev = pdev;
 	priv->ndev = ndev;
 	priv->dev  = &ndev->dev;
 	priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
 	priv->rx_packet_max = max(rx_packet_max, 128);
 	priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
 	priv->irq_enabled = true;
 	if (!priv->cpts) {
 		dev_err(&pdev->dev, "error allocating cpts\n");
 		ret = -ENOMEM;
 		goto clean_ndev_ret;
 	}
 	/*
 	 * This may be required here for child devices.
 	 */
 	pm_runtime_enable(&pdev->dev);
 	/* Select default pin state */
 	pinctrl_pm_select_default_state(&pdev->dev);
 	if (cpsw_probe_dt(&priv->data, pdev)) {
 		dev_err(&pdev->dev, "cpsw: platform data missing\n");
 		ret = -ENODEV;
 		goto clean_runtime_disable_ret;
 	}
 	data = &priv->data;
 	if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
 		memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
 		dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
 	} else {
 		eth_random_addr(priv->mac_addr);
 		dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
 	}
 	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
 	priv->slaves = devm_kzalloc(&pdev->dev,
 				    sizeof(struct cpsw_slave) * data->slaves,
 				    GFP_KERNEL);
 	if (!priv->slaves) {
 		ret = -ENOMEM;
 		goto clean_runtime_disable_ret;
 	}
 	for (i = 0; i < data->slaves; i++)
 		priv->slaves[i].slave_num = i;
 	priv->slaves[0].ndev = ndev;
 	priv->emac_port = 0;
 	priv->clk = devm_clk_get(&pdev->dev, "fck");
 	if (IS_ERR(priv->clk)) {
 		dev_err(priv->dev, "fck is not found\n");
 		ret = -ENODEV;
 		goto clean_runtime_disable_ret;
 	}
 	priv->coal_intvl = 0;
 	priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
 	ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
 	if (IS_ERR(ss_regs)) {
 		ret = PTR_ERR(ss_regs);
 		goto clean_runtime_disable_ret;
 	}
 	priv->regs = ss_regs;
 	priv->host_port = HOST_PORT_NUM;
 	/* Need to enable clocks with runtime PM api to access module
 	 * registers
 	 */
 	pm_runtime_get_sync(&pdev->dev);
 	priv->version = readl(&priv->regs->id_ver);
 	pm_runtime_put_sync(&pdev->dev);
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(priv->wr_regs)) {
 		ret = PTR_ERR(priv->wr_regs);
 		goto clean_runtime_disable_ret;
 	}
 	memset(&dma_params, 0, sizeof(dma_params));
 	memset(&ale_params, 0, sizeof(ale_params));
 	switch (priv->version) {
 	case CPSW_VERSION_1:
 		priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
 		priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
 		priv->hw_stats	     = ss_regs + CPSW1_HW_STATS;
 		dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
 		dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
 		ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
 		slave_offset         = CPSW1_SLAVE_OFFSET;
 		slave_size           = CPSW1_SLAVE_SIZE;
 		sliver_offset        = CPSW1_SLIVER_OFFSET;
 		dma_params.desc_mem_phys = 0;
 		break;
 	case CPSW_VERSION_2:
 	case CPSW_VERSION_3:
 	case CPSW_VERSION_4:
 		priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
 		priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
 		priv->hw_stats	     = ss_regs + CPSW2_HW_STATS;
 		dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
 		dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
 		ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
 		slave_offset         = CPSW2_SLAVE_OFFSET;
 		slave_size           = CPSW2_SLAVE_SIZE;
 		sliver_offset        = CPSW2_SLIVER_OFFSET;
 		dma_params.desc_mem_phys =
 			(u32 __force) ss_res->start + CPSW2_BD_OFFSET;
 		break;
 	default:
 		dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
 		ret = -ENODEV;
 		goto clean_runtime_disable_ret;
 	}
 	for (i = 0; i < priv->data.slaves; i++) {
 		struct cpsw_slave *slave = &priv->slaves[i];
 		cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
 		slave_offset  += slave_size;
 		sliver_offset += SLIVER_SIZE;
 	}
 	dma_params.dev		= &pdev->dev;
 	dma_params.rxthresh	= dma_params.dmaregs + CPDMA_RXTHRESH;
 	dma_params.rxfree	= dma_params.dmaregs + CPDMA_RXFREE;
 	dma_params.rxhdp	= dma_params.txhdp + CPDMA_RXHDP;
 	dma_params.txcp		= dma_params.txhdp + CPDMA_TXCP;
 	dma_params.rxcp		= dma_params.txhdp + CPDMA_RXCP;
 	dma_params.num_chan		= data->channels;
 	dma_params.has_soft_reset	= true;
 	dma_params.min_packet_size	= CPSW_MIN_PACKET_SIZE;
 	dma_params.desc_mem_size	= data->bd_ram_size;
 	dma_params.desc_align		= 16;
 	dma_params.has_ext_regs		= true;
 	dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
 	priv->dma = cpdma_ctlr_create(&dma_params);
 	if (!priv->dma) {
 		dev_err(priv->dev, "error initializing dma\n");
 		ret = -ENOMEM;
 		goto clean_runtime_disable_ret;
 	}
 	priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
 				       cpsw_tx_handler);
 	priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
 				       cpsw_rx_handler);
 	if (WARN_ON(!priv->txch || !priv->rxch)) {
 		dev_err(priv->dev, "error initializing dma channels\n");
 		ret = -ENOMEM;
 		goto clean_dma_ret;
 	}
 	ale_params.dev			= &ndev->dev;
 	ale_params.ale_ageout		= ale_ageout;
 	ale_params.ale_entries		= data->ale_entries;
 	ale_params.ale_ports		= data->slaves;
 	priv->ale = cpsw_ale_create(&ale_params);
 	if (!priv->ale) {
 		dev_err(priv->dev, "error initializing ale engine\n");
 		ret = -ENODEV;
 		goto clean_dma_ret;
 	}
 	ndev->irq = platform_get_irq(pdev, 0);
 	if (ndev->irq < 0) {
 		dev_err(priv->dev, "error getting irq resource\n");
 		ret = -ENOENT;
 		goto clean_ale_ret;
 	}
 	while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
 		if (k >= ARRAY_SIZE(priv->irqs_table)) {
 			ret = -EINVAL;
 			goto clean_ale_ret;
 		}
 		ret = devm_request_irq(&pdev->dev, res->start, cpsw_interrupt,
 				       0, dev_name(&pdev->dev), priv);
 		if (ret < 0) {
 			dev_err(priv->dev, "error attaching irq (%d)\n", ret);
 			goto clean_ale_ret;
 		}
 		priv->irqs_table[k] = res->start;
 		k++;
 	}
 	priv->num_irqs = k;
 	ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
 	ndev->netdev_ops = &cpsw_netdev_ops;
 	ndev->ethtool_ops = &cpsw_ethtool_ops;
 	netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
 	/* register the network device */
 	SET_NETDEV_DEV(ndev, &pdev->dev);
 	ret = register_netdev(ndev);
 	if (ret) {
 		dev_err(priv->dev, "error registering net device\n");
 		ret = -ENODEV;
 		goto clean_ale_ret;
 	}
 	cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
 		    &ss_res->start, ndev->irq);
 	if (priv->data.dual_emac) {
 		ret = cpsw_probe_dual_emac(pdev, priv);
 		if (ret) {
 			cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
 			goto clean_ale_ret;
 		}
 	}
 	return 0;
 clean_ale_ret:
 	cpsw_ale_destroy(priv->ale);
 clean_dma_ret:
 	cpdma_chan_destroy(priv->txch);
 	cpdma_chan_destroy(priv->rxch);
 	cpdma_ctlr_destroy(priv->dma);
 clean_runtime_disable_ret:
 	pm_runtime_disable(&pdev->dev);
 clean_ndev_ret:
 	free_netdev(priv->ndev);
 	return ret;
 }
 static int cpsw_remove_child_device(struct device *dev, void *c)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	of_device_unregister(pdev);
 	return 0;
 }
 static int cpsw_remove(struct platform_device *pdev)
 {
 	struct net_device *ndev = platform_get_drvdata(pdev);
 	struct cpsw_priv *priv = netdev_priv(ndev);
 	if (priv->data.dual_emac)
 		unregister_netdev(cpsw_get_slave_ndev(priv, 1));
 	unregister_netdev(ndev);
 	cpsw_ale_destroy(priv->ale);
 	cpdma_chan_destroy(priv->txch);
 	cpdma_chan_destroy(priv->rxch);
 	cpdma_ctlr_destroy(priv->dma);
 	pm_runtime_disable(&pdev->dev);
 	device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
 	if (priv->data.dual_emac)
 		free_netdev(cpsw_get_slave_ndev(priv, 1));
 	free_netdev(ndev);
 	return 0;
 }
 static int cpsw_suspend(struct device *dev)
 {
 	struct platform_device	*pdev = to_platform_device(dev);
 	struct net_device	*ndev = platform_get_drvdata(pdev);
 	struct cpsw_priv	*priv = netdev_priv(ndev);
 	if (priv->data.dual_emac) {
 		int i;
 		for (i = 0; i < priv->data.slaves; i++) {
 			if (netif_running(priv->slaves[i].ndev))
 				cpsw_ndo_stop(priv->slaves[i].ndev);
 			soft_reset_slave(priv->slaves + i);
 		}
 	} else {
 		if (netif_running(ndev))
 			cpsw_ndo_stop(ndev);
 		for_each_slave(priv, soft_reset_slave);
 	}
 	pm_runtime_put_sync(&pdev->dev);
 	/* Select sleep pin state */
 	pinctrl_pm_select_sleep_state(&pdev->dev);
 	return 0;
 }
 static int cpsw_resume(struct device *dev)
 {
 	struct platform_device	*pdev = to_platform_device(dev);
 	struct net_device	*ndev = platform_get_drvdata(pdev);
 	struct cpsw_priv	*priv = netdev_priv(ndev);
 	pm_runtime_get_sync(&pdev->dev);
 	/* Select default pin state */
 	pinctrl_pm_select_default_state(&pdev->dev);
 	if (priv->data.dual_emac) {
 		int i;
 		for (i = 0; i < priv->data.slaves; i++) {
 			if (netif_running(priv->slaves[i].ndev))
 				cpsw_ndo_open(priv->slaves[i].ndev);
 		}
 	} else {
 		if (netif_running(ndev))
 			cpsw_ndo_open(ndev);
 	}
 	return 0;
 }
 static const struct dev_pm_ops cpsw_pm_ops = {
 	.suspend	= cpsw_suspend,
 	.resume		= cpsw_resume,
 };
 static const struct of_device_id cpsw_of_mtable[] = {
 	{ .compatible = "ti,cpsw", },
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
 static struct platform_driver cpsw_driver = {
 	.driver = {
 		.name	 = "cpsw",
 		.pm	 = &cpsw_pm_ops,
 		.of_match_table = cpsw_of_mtable,
 	},
 	.probe = cpsw_probe,
 	.remove = cpsw_remove,
 };
 static int __init cpsw_init(void)
 {
 	return platform_driver_register(&cpsw_driver);
 }
 late_initcall(cpsw_init);
 static void __exit cpsw_exit(void)
 {
 	platform_driver_unregister(&cpsw_driver);
 }
 module_exit(cpsw_exit);
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
 MODULE_DESCRIPTION("TI CPSW Ethernet driver");