Commit f8b5992beea79b68f6695d301868b6a2a8f7e16f
Committed by
Sekhar Nori
1 parent
24b53d317d
Exists in
smarc-ti-linux-3.14.y
and in
1 other branch
ARM: DRA7: GMAC: Apply Errata i877
Errata ID: i877 Description: The RGMII Transmit timing is based on the output clock (rgmiin_txc) being driven relative to the rising edge of an internal clock and the output control/data (rgmiin_txctl/txd) being driven relative to the falling edge of an internal clock source. If the internal clock source is allowed to be static low (i.e., disabled) for an extended period of time then when the clock is actually enabled the timing delta between the rising edge and falling edge can change over the lifetime of the device. This can result in the device switching characteristics degrading over time, and eventually failing to meet the Data Manual Delay Time/Skew specs. To maintain RGMII IO Timings, SW should minimize the duration that the Ethernet internal clock source is disabled. Note that the device reset state for the Ethernet clock is "disabled". Workaround: If the SoC Ethernet interface(s) are used in RGMII mode, SW should minimize the time the Ethernet internal clock source is disabled to a maximum of 200 hours in a device life cycle. This is done by enabling the clock as early as possible in IPL (QNX) or SPL/u-boot (Linux/Android) by setting the register CM_GMAC_CLKSTCTRL[1:0]CLKTRCTRL = 0x2:SW_WKUP. In addition to programming SW_WKUP(0x2) on CM_GMAC_CLKSTCTRL, SW should also program modulemode field as ENABLED(0x2) on CM_GMAC_GMAC_CLKCTRL register. Note that this erratum applies only when device may need to be used for 1Gbit operation. Since the POR is to use 1GB mode, enabling this errata by hooking ti,no-idle flag to gmac node. Acked-by: Roger Quadros <rogerq@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Showing 3 changed files with 3 additions and 0 deletions Inline Diff
arch/arm/boot/dts/am57xx-beagle-x15.dts
1 | /* | 1 | /* |
2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
7 | */ | 7 | */ |
8 | /dts-v1/; | 8 | /dts-v1/; |
9 | 9 | ||
10 | #include "dra74x.dtsi" | 10 | #include "dra74x.dtsi" |
11 | #include <dt-bindings/gpio/gpio.h> | 11 | #include <dt-bindings/gpio/gpio.h> |
12 | #include <dt-bindings/interrupt-controller/irq.h> | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
13 | 13 | ||
14 | / { | 14 | / { |
15 | model = "TI AM5728 BeagleBoard-X15"; | 15 | model = "TI AM5728 BeagleBoard-X15"; |
16 | compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; | 16 | compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; |
17 | 17 | ||
18 | aliases { | 18 | aliases { |
19 | rtc0 = &mcp_rtc; | 19 | rtc0 = &mcp_rtc; |
20 | rtc1 = &rtc; | 20 | rtc1 = &rtc; |
21 | rtc2 = &tps659038_rtc; | 21 | rtc2 = &tps659038_rtc; |
22 | display0 = &hdmi0; | 22 | display0 = &hdmi0; |
23 | sound0 = &primary_sound; | 23 | sound0 = &primary_sound; |
24 | sound1 = &hdmi; | 24 | sound1 = &hdmi; |
25 | }; | 25 | }; |
26 | 26 | ||
27 | memory { | 27 | memory { |
28 | device_type = "memory"; | 28 | device_type = "memory"; |
29 | reg = <0x80000000 0x80000000>; | 29 | reg = <0x80000000 0x80000000>; |
30 | }; | 30 | }; |
31 | 31 | ||
32 | reserved-memory { | 32 | reserved-memory { |
33 | #address-cells = <1>; | 33 | #address-cells = <1>; |
34 | #size-cells = <1>; | 34 | #size-cells = <1>; |
35 | ranges; | 35 | ranges; |
36 | 36 | ||
37 | ipu2_cma_pool: ipu2_cma@95800000 { | 37 | ipu2_cma_pool: ipu2_cma@95800000 { |
38 | compatible = "shared-dma-pool"; | 38 | compatible = "shared-dma-pool"; |
39 | reg = <0x95800000 0x3800000>; | 39 | reg = <0x95800000 0x3800000>; |
40 | reusable; | 40 | reusable; |
41 | status = "okay"; | 41 | status = "okay"; |
42 | }; | 42 | }; |
43 | 43 | ||
44 | dsp1_cma_pool: dsp1_cma@99000000 { | 44 | dsp1_cma_pool: dsp1_cma@99000000 { |
45 | compatible = "shared-dma-pool"; | 45 | compatible = "shared-dma-pool"; |
46 | reg = <0x99000000 0x4000000>; | 46 | reg = <0x99000000 0x4000000>; |
47 | reusable; | 47 | reusable; |
48 | status = "okay"; | 48 | status = "okay"; |
49 | }; | 49 | }; |
50 | 50 | ||
51 | ipu1_cma_pool: ipu1_cma@9d000000 { | 51 | ipu1_cma_pool: ipu1_cma@9d000000 { |
52 | compatible = "shared-dma-pool"; | 52 | compatible = "shared-dma-pool"; |
53 | reg = <0x9d000000 0x2000000>; | 53 | reg = <0x9d000000 0x2000000>; |
54 | reusable; | 54 | reusable; |
55 | status = "okay"; | 55 | status = "okay"; |
56 | }; | 56 | }; |
57 | 57 | ||
58 | dsp2_cma_pool: dsp2_cma@9f000000 { | 58 | dsp2_cma_pool: dsp2_cma@9f000000 { |
59 | compatible = "shared-dma-pool"; | 59 | compatible = "shared-dma-pool"; |
60 | reg = <0x9f000000 0x800000>; | 60 | reg = <0x9f000000 0x800000>; |
61 | reusable; | 61 | reusable; |
62 | status = "okay"; | 62 | status = "okay"; |
63 | }; | 63 | }; |
64 | }; | 64 | }; |
65 | 65 | ||
66 | vdd_3v3: fixedregulator-vdd_3v3 { | 66 | vdd_3v3: fixedregulator-vdd_3v3 { |
67 | compatible = "regulator-fixed"; | 67 | compatible = "regulator-fixed"; |
68 | regulator-name = "vdd_3v3"; | 68 | regulator-name = "vdd_3v3"; |
69 | vin-supply = <®en1>; | 69 | vin-supply = <®en1>; |
70 | regulator-min-microvolt = <3300000>; | 70 | regulator-min-microvolt = <3300000>; |
71 | regulator-max-microvolt = <3300000>; | 71 | regulator-max-microvolt = <3300000>; |
72 | }; | 72 | }; |
73 | 73 | ||
74 | aic_dvdd: fixedregulator-aic_dvdd { | 74 | aic_dvdd: fixedregulator-aic_dvdd { |
75 | compatible = "regulator-fixed"; | 75 | compatible = "regulator-fixed"; |
76 | regulator-name = "aic_dvdd_fixed"; | 76 | regulator-name = "aic_dvdd_fixed"; |
77 | vin-supply = <&vdd_3v3>; | 77 | vin-supply = <&vdd_3v3>; |
78 | regulator-min-microvolt = <1800000>; | 78 | regulator-min-microvolt = <1800000>; |
79 | regulator-max-microvolt = <1800000>; | 79 | regulator-max-microvolt = <1800000>; |
80 | }; | 80 | }; |
81 | 81 | ||
82 | vtt_fixed: fixedregulator-vtt { | 82 | vtt_fixed: fixedregulator-vtt { |
83 | /* TPS51200 */ | 83 | /* TPS51200 */ |
84 | compatible = "regulator-fixed"; | 84 | compatible = "regulator-fixed"; |
85 | regulator-name = "vtt_fixed"; | 85 | regulator-name = "vtt_fixed"; |
86 | vin-supply = <&smps3_reg>; | 86 | vin-supply = <&smps3_reg>; |
87 | regulator-min-microvolt = <3300000>; | 87 | regulator-min-microvolt = <3300000>; |
88 | regulator-max-microvolt = <3300000>; | 88 | regulator-max-microvolt = <3300000>; |
89 | regulator-always-on; | 89 | regulator-always-on; |
90 | regulator-boot-on; | 90 | regulator-boot-on; |
91 | enable-active-high; | 91 | enable-active-high; |
92 | gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; | 92 | gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; |
93 | }; | 93 | }; |
94 | 94 | ||
95 | hdmi0: connector@1 { | 95 | hdmi0: connector@1 { |
96 | compatible = "hdmi-connector"; | 96 | compatible = "hdmi-connector"; |
97 | label = "hdmi"; | 97 | label = "hdmi"; |
98 | 98 | ||
99 | type = "a"; | 99 | type = "a"; |
100 | 100 | ||
101 | port { | 101 | port { |
102 | hdmi_connector_in: endpoint { | 102 | hdmi_connector_in: endpoint { |
103 | remote-endpoint = <&tpd12s015_out>; | 103 | remote-endpoint = <&tpd12s015_out>; |
104 | }; | 104 | }; |
105 | }; | 105 | }; |
106 | }; | 106 | }; |
107 | 107 | ||
108 | tpd12s015: encoder@1 { | 108 | tpd12s015: encoder@1 { |
109 | compatible = "ti,tpd12s015"; | 109 | compatible = "ti,tpd12s015"; |
110 | 110 | ||
111 | gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ | 111 | gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ |
112 | <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ | 112 | <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ |
113 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ | 113 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ |
114 | 114 | ||
115 | ports { | 115 | ports { |
116 | #address-cells = <1>; | 116 | #address-cells = <1>; |
117 | #size-cells = <0>; | 117 | #size-cells = <0>; |
118 | 118 | ||
119 | port@0 { | 119 | port@0 { |
120 | reg = <0>; | 120 | reg = <0>; |
121 | 121 | ||
122 | tpd12s015_in: endpoint@0 { | 122 | tpd12s015_in: endpoint@0 { |
123 | remote-endpoint = <&hdmi_out>; | 123 | remote-endpoint = <&hdmi_out>; |
124 | }; | 124 | }; |
125 | }; | 125 | }; |
126 | 126 | ||
127 | port@1 { | 127 | port@1 { |
128 | reg = <1>; | 128 | reg = <1>; |
129 | 129 | ||
130 | tpd12s015_out: endpoint@0 { | 130 | tpd12s015_out: endpoint@0 { |
131 | remote-endpoint = <&hdmi_connector_in>; | 131 | remote-endpoint = <&hdmi_connector_in>; |
132 | }; | 132 | }; |
133 | }; | 133 | }; |
134 | }; | 134 | }; |
135 | }; | 135 | }; |
136 | 136 | ||
137 | leds { | 137 | leds { |
138 | compatible = "gpio-leds"; | 138 | compatible = "gpio-leds"; |
139 | 139 | ||
140 | led@0 { | 140 | led@0 { |
141 | label = "beagle-x15:usr0"; | 141 | label = "beagle-x15:usr0"; |
142 | gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; | 142 | gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; |
143 | linux,default-trigger = "heartbeat"; | 143 | linux,default-trigger = "heartbeat"; |
144 | default-state = "off"; | 144 | default-state = "off"; |
145 | }; | 145 | }; |
146 | 146 | ||
147 | led@1 { | 147 | led@1 { |
148 | label = "beagle-x15:usr1"; | 148 | label = "beagle-x15:usr1"; |
149 | gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; | 149 | gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; |
150 | linux,default-trigger = "cpu0"; | 150 | linux,default-trigger = "cpu0"; |
151 | default-state = "off"; | 151 | default-state = "off"; |
152 | }; | 152 | }; |
153 | 153 | ||
154 | led@2 { | 154 | led@2 { |
155 | label = "beagle-x15:usr2"; | 155 | label = "beagle-x15:usr2"; |
156 | gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; | 156 | gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; |
157 | linux,default-trigger = "mmc0"; | 157 | linux,default-trigger = "mmc0"; |
158 | default-state = "off"; | 158 | default-state = "off"; |
159 | }; | 159 | }; |
160 | 160 | ||
161 | led@3 { | 161 | led@3 { |
162 | label = "beagle-x15:usr3"; | 162 | label = "beagle-x15:usr3"; |
163 | gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; | 163 | gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; |
164 | linux,default-trigger = "ide-disk"; | 164 | linux,default-trigger = "ide-disk"; |
165 | default-state = "off"; | 165 | default-state = "off"; |
166 | }; | 166 | }; |
167 | }; | 167 | }; |
168 | 168 | ||
169 | gpio_fan: gpio_fan { | 169 | gpio_fan: gpio_fan { |
170 | /* Based on 5v 500mA AFB02505HHB */ | 170 | /* Based on 5v 500mA AFB02505HHB */ |
171 | compatible = "gpio-fan"; | 171 | compatible = "gpio-fan"; |
172 | gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; | 172 | gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; |
173 | gpio-fan,speed-map = <0 0 | 173 | gpio-fan,speed-map = <0 0 |
174 | 13000 1>; | 174 | 13000 1>; |
175 | #cooling-cells = <2>; | 175 | #cooling-cells = <2>; |
176 | }; | 176 | }; |
177 | 177 | ||
178 | primary_sound: primary_sound { | 178 | primary_sound: primary_sound { |
179 | compatible = "ti,da830-evm-audio"; | 179 | compatible = "ti,da830-evm-audio"; |
180 | ti,model = "BeagleBoard-X15"; | 180 | ti,model = "BeagleBoard-X15"; |
181 | ti,audio-codec = <&tlv320aic3104>; | 181 | ti,audio-codec = <&tlv320aic3104>; |
182 | ti,mcasp-controller = <&mcasp3>; | 182 | ti,mcasp-controller = <&mcasp3>; |
183 | clocks = <&clkout2_clk>; | 183 | clocks = <&clkout2_clk>; |
184 | clock-names = "mclk"; | 184 | clock-names = "mclk"; |
185 | ti,audio-routing = | 185 | ti,audio-routing = |
186 | "Line Out", "LLOUT", | 186 | "Line Out", "LLOUT", |
187 | "Line Out", "RLOUT", | 187 | "Line Out", "RLOUT", |
188 | "MIC2L", "Line In", | 188 | "MIC2L", "Line In", |
189 | "MIC2R", "Line In"; | 189 | "MIC2R", "Line In"; |
190 | }; | 190 | }; |
191 | }; | 191 | }; |
192 | 192 | ||
193 | &dra7_pmx_core { | 193 | &dra7_pmx_core { |
194 | mmc1_pins_default: mmc1_pins_default { | 194 | mmc1_pins_default: mmc1_pins_default { |
195 | pinctrl-single,pins = < | 195 | pinctrl-single,pins = < |
196 | 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ | 196 | 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ |
197 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | 197 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ |
198 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | 198 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ |
199 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | 199 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ |
200 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | 200 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ |
201 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | 201 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ |
202 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | 202 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ |
203 | >; | 203 | >; |
204 | }; | 204 | }; |
205 | 205 | ||
206 | mmc1_pins_hs: mmc1_pins_hs { | 206 | mmc1_pins_hs: mmc1_pins_hs { |
207 | pinctrl-single,pins = < | 207 | pinctrl-single,pins = < |
208 | 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ | 208 | 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ |
209 | 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ | 209 | 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ |
210 | 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ | 210 | 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ |
211 | 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ | 211 | 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ |
212 | 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ | 212 | 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ |
213 | 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ | 213 | 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ |
214 | >; | 214 | >; |
215 | }; | 215 | }; |
216 | 216 | ||
217 | mmc2_pins_default: mmc2_pins_default { | 217 | mmc2_pins_default: mmc2_pins_default { |
218 | pinctrl-single,pins = < | 218 | pinctrl-single,pins = < |
219 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | 219 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ |
220 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | 220 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ |
221 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | 221 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ |
222 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | 222 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ |
223 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | 223 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ |
224 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | 224 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ |
225 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | 225 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ |
226 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | 226 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ |
227 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | 227 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ |
228 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | 228 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ |
229 | >; | 229 | >; |
230 | }; | 230 | }; |
231 | 231 | ||
232 | mmc2_pins_hs: mmc2_pins_hs { | 232 | mmc2_pins_hs: mmc2_pins_hs { |
233 | pinctrl-single,pins = < | 233 | pinctrl-single,pins = < |
234 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | 234 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ |
235 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | 235 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ |
236 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | 236 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ |
237 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | 237 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ |
238 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | 238 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ |
239 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | 239 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ |
240 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | 240 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ |
241 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | 241 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ |
242 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | 242 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ |
243 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | 243 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ |
244 | >; | 244 | >; |
245 | }; | 245 | }; |
246 | }; | 246 | }; |
247 | 247 | ||
248 | &i2c1 { | 248 | &i2c1 { |
249 | status = "okay"; | 249 | status = "okay"; |
250 | clock-frequency = <400000>; | 250 | clock-frequency = <400000>; |
251 | 251 | ||
252 | tps659038: tps659038@58 { | 252 | tps659038: tps659038@58 { |
253 | compatible = "ti,tps659038"; | 253 | compatible = "ti,tps659038"; |
254 | reg = <0x58>; | 254 | reg = <0x58>; |
255 | interrupts-extended = <&gpio1 0 IRQ_TYPE_LEVEL_HIGH | 255 | interrupts-extended = <&gpio1 0 IRQ_TYPE_LEVEL_HIGH |
256 | &dra7_pmx_core 0x418>; | 256 | &dra7_pmx_core 0x418>; |
257 | 257 | ||
258 | #interrupt-cells = <2>; | 258 | #interrupt-cells = <2>; |
259 | interrupt-controller; | 259 | interrupt-controller; |
260 | 260 | ||
261 | ti,system-power-controller; | 261 | ti,system-power-controller; |
262 | 262 | ||
263 | tps659038_pmic { | 263 | tps659038_pmic { |
264 | compatible = "ti,tps659038-pmic"; | 264 | compatible = "ti,tps659038-pmic"; |
265 | 265 | ||
266 | regulators { | 266 | regulators { |
267 | smps12_reg: smps12 { | 267 | smps12_reg: smps12 { |
268 | /* VDD_MPU */ | 268 | /* VDD_MPU */ |
269 | regulator-name = "smps12"; | 269 | regulator-name = "smps12"; |
270 | regulator-min-microvolt = < 850000>; | 270 | regulator-min-microvolt = < 850000>; |
271 | regulator-max-microvolt = <1250000>; | 271 | regulator-max-microvolt = <1250000>; |
272 | regulator-always-on; | 272 | regulator-always-on; |
273 | regulator-boot-on; | 273 | regulator-boot-on; |
274 | }; | 274 | }; |
275 | 275 | ||
276 | smps3_reg: smps3 { | 276 | smps3_reg: smps3 { |
277 | /* VDD_DDR */ | 277 | /* VDD_DDR */ |
278 | regulator-name = "smps3"; | 278 | regulator-name = "smps3"; |
279 | regulator-min-microvolt = <1350000>; | 279 | regulator-min-microvolt = <1350000>; |
280 | regulator-max-microvolt = <1350000>; | 280 | regulator-max-microvolt = <1350000>; |
281 | regulator-always-on; | 281 | regulator-always-on; |
282 | regulator-boot-on; | 282 | regulator-boot-on; |
283 | }; | 283 | }; |
284 | 284 | ||
285 | smps45_reg: smps45 { | 285 | smps45_reg: smps45 { |
286 | /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ | 286 | /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ |
287 | regulator-name = "smps45"; | 287 | regulator-name = "smps45"; |
288 | regulator-min-microvolt = < 850000>; | 288 | regulator-min-microvolt = < 850000>; |
289 | regulator-max-microvolt = <1150000>; | 289 | regulator-max-microvolt = <1150000>; |
290 | regulator-always-on; | 290 | regulator-always-on; |
291 | regulator-boot-on; | 291 | regulator-boot-on; |
292 | }; | 292 | }; |
293 | 293 | ||
294 | smps6_reg: smps6 { | 294 | smps6_reg: smps6 { |
295 | /* VDD_CORE */ | 295 | /* VDD_CORE */ |
296 | regulator-name = "smps6"; | 296 | regulator-name = "smps6"; |
297 | regulator-min-microvolt = <850000>; | 297 | regulator-min-microvolt = <850000>; |
298 | regulator-max-microvolt = <1030000>; | 298 | regulator-max-microvolt = <1030000>; |
299 | regulator-always-on; | 299 | regulator-always-on; |
300 | regulator-boot-on; | 300 | regulator-boot-on; |
301 | }; | 301 | }; |
302 | 302 | ||
303 | /* SMPS7 unused */ | 303 | /* SMPS7 unused */ |
304 | 304 | ||
305 | smps8_reg: smps8 { | 305 | smps8_reg: smps8 { |
306 | /* VDD_1V8 */ | 306 | /* VDD_1V8 */ |
307 | regulator-name = "smps8"; | 307 | regulator-name = "smps8"; |
308 | regulator-min-microvolt = <1800000>; | 308 | regulator-min-microvolt = <1800000>; |
309 | regulator-max-microvolt = <1800000>; | 309 | regulator-max-microvolt = <1800000>; |
310 | regulator-always-on; | 310 | regulator-always-on; |
311 | regulator-boot-on; | 311 | regulator-boot-on; |
312 | }; | 312 | }; |
313 | 313 | ||
314 | /* SMPS9 unused */ | 314 | /* SMPS9 unused */ |
315 | 315 | ||
316 | ldo1_reg: ldo1 { | 316 | ldo1_reg: ldo1 { |
317 | /* VDD_SD */ | 317 | /* VDD_SD */ |
318 | regulator-name = "ldo1"; | 318 | regulator-name = "ldo1"; |
319 | regulator-min-microvolt = <1800000>; | 319 | regulator-min-microvolt = <1800000>; |
320 | regulator-max-microvolt = <3300000>; | 320 | regulator-max-microvolt = <3300000>; |
321 | regulator-boot-on; | 321 | regulator-boot-on; |
322 | }; | 322 | }; |
323 | 323 | ||
324 | ldo2_reg: ldo2 { | 324 | ldo2_reg: ldo2 { |
325 | /* VDD_SHV5 */ | 325 | /* VDD_SHV5 */ |
326 | regulator-name = "ldo2"; | 326 | regulator-name = "ldo2"; |
327 | regulator-min-microvolt = <3300000>; | 327 | regulator-min-microvolt = <3300000>; |
328 | regulator-max-microvolt = <3300000>; | 328 | regulator-max-microvolt = <3300000>; |
329 | regulator-always-on; | 329 | regulator-always-on; |
330 | regulator-boot-on; | 330 | regulator-boot-on; |
331 | }; | 331 | }; |
332 | 332 | ||
333 | ldo3_reg: ldo3 { | 333 | ldo3_reg: ldo3 { |
334 | /* VDDA_1V8_PHY */ | 334 | /* VDDA_1V8_PHY */ |
335 | regulator-name = "ldo3"; | 335 | regulator-name = "ldo3"; |
336 | regulator-min-microvolt = <1800000>; | 336 | regulator-min-microvolt = <1800000>; |
337 | regulator-max-microvolt = <1800000>; | 337 | regulator-max-microvolt = <1800000>; |
338 | regulator-always-on; | 338 | regulator-always-on; |
339 | regulator-boot-on; | 339 | regulator-boot-on; |
340 | }; | 340 | }; |
341 | 341 | ||
342 | ldo9_reg: ldo9 { | 342 | ldo9_reg: ldo9 { |
343 | /* VDD_RTC */ | 343 | /* VDD_RTC */ |
344 | regulator-name = "ldo9"; | 344 | regulator-name = "ldo9"; |
345 | regulator-min-microvolt = <1050000>; | 345 | regulator-min-microvolt = <1050000>; |
346 | regulator-max-microvolt = <1050000>; | 346 | regulator-max-microvolt = <1050000>; |
347 | regulator-always-on; | 347 | regulator-always-on; |
348 | regulator-boot-on; | 348 | regulator-boot-on; |
349 | }; | 349 | }; |
350 | 350 | ||
351 | ldoln_reg: ldoln { | 351 | ldoln_reg: ldoln { |
352 | /* VDDA_1V8_PLL */ | 352 | /* VDDA_1V8_PLL */ |
353 | regulator-name = "ldoln"; | 353 | regulator-name = "ldoln"; |
354 | regulator-min-microvolt = <1800000>; | 354 | regulator-min-microvolt = <1800000>; |
355 | regulator-max-microvolt = <1800000>; | 355 | regulator-max-microvolt = <1800000>; |
356 | regulator-always-on; | 356 | regulator-always-on; |
357 | regulator-boot-on; | 357 | regulator-boot-on; |
358 | }; | 358 | }; |
359 | 359 | ||
360 | ldousb_reg: ldousb { | 360 | ldousb_reg: ldousb { |
361 | /* VDDA_3V_USB: VDDA_USBHS33 */ | 361 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
362 | regulator-name = "ldousb"; | 362 | regulator-name = "ldousb"; |
363 | regulator-min-microvolt = <3300000>; | 363 | regulator-min-microvolt = <3300000>; |
364 | regulator-max-microvolt = <3300000>; | 364 | regulator-max-microvolt = <3300000>; |
365 | regulator-boot-on; | 365 | regulator-boot-on; |
366 | }; | 366 | }; |
367 | 367 | ||
368 | regen1: regen1 { | 368 | regen1: regen1 { |
369 | /* VDD_3V3_ON */ | 369 | /* VDD_3V3_ON */ |
370 | regulator-name = "regen1"; | 370 | regulator-name = "regen1"; |
371 | regulator-boot-on; | 371 | regulator-boot-on; |
372 | regulator-always-on; | 372 | regulator-always-on; |
373 | }; | 373 | }; |
374 | 374 | ||
375 | regen2: regen2 { | 375 | regen2: regen2 { |
376 | /* Needed for PMIC internal resource */ | 376 | /* Needed for PMIC internal resource */ |
377 | regulator-name = "regen2"; | 377 | regulator-name = "regen2"; |
378 | regulator-boot-on; | 378 | regulator-boot-on; |
379 | regulator-always-on; | 379 | regulator-always-on; |
380 | }; | 380 | }; |
381 | }; | 381 | }; |
382 | }; | 382 | }; |
383 | 383 | ||
384 | tps659038_rtc: tps659038_rtc { | 384 | tps659038_rtc: tps659038_rtc { |
385 | compatible = "ti,palmas-rtc"; | 385 | compatible = "ti,palmas-rtc"; |
386 | interrupt-parent = <&tps659038>; | 386 | interrupt-parent = <&tps659038>; |
387 | interrupts = <8 IRQ_TYPE_NONE>; | 387 | interrupts = <8 IRQ_TYPE_NONE>; |
388 | wakeup-source; | 388 | wakeup-source; |
389 | }; | 389 | }; |
390 | 390 | ||
391 | tps659038_pwr_button: tps659038_pwr_button { | 391 | tps659038_pwr_button: tps659038_pwr_button { |
392 | compatible = "ti,palmas-pwrbutton"; | 392 | compatible = "ti,palmas-pwrbutton"; |
393 | interrupt-parent = <&tps659038>; | 393 | interrupt-parent = <&tps659038>; |
394 | interrupts = <1 IRQ_TYPE_NONE>; | 394 | interrupts = <1 IRQ_TYPE_NONE>; |
395 | wakeup-source; | 395 | wakeup-source; |
396 | ti,palmas-long-press-seconds = <13>; | 396 | ti,palmas-long-press-seconds = <13>; |
397 | }; | 397 | }; |
398 | 398 | ||
399 | tps659038_gpio: tps659038_gpio { | 399 | tps659038_gpio: tps659038_gpio { |
400 | compatible = "ti,palmas-gpio"; | 400 | compatible = "ti,palmas-gpio"; |
401 | gpio-controller; | 401 | gpio-controller; |
402 | #gpio-cells = <2>; | 402 | #gpio-cells = <2>; |
403 | }; | 403 | }; |
404 | 404 | ||
405 | extcon_usb2: tps659038_usb { | 405 | extcon_usb2: tps659038_usb { |
406 | compatible = "ti,palmas-usb-vid"; | 406 | compatible = "ti,palmas-usb-vid"; |
407 | ti,enable-vbus-detection; | 407 | ti,enable-vbus-detection; |
408 | ti,enable-gpio-id-detection; | 408 | ti,enable-gpio-id-detection; |
409 | id-gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>; | 409 | id-gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>; |
410 | }; | 410 | }; |
411 | 411 | ||
412 | }; | 412 | }; |
413 | 413 | ||
414 | tmp102: tmp102@48 { | 414 | tmp102: tmp102@48 { |
415 | compatible = "ti,tmp102"; | 415 | compatible = "ti,tmp102"; |
416 | reg = <0x48>; | 416 | reg = <0x48>; |
417 | interrupt-parent = <&gpio7>; | 417 | interrupt-parent = <&gpio7>; |
418 | interrupts = <16 IRQ_TYPE_LEVEL_LOW>; | 418 | interrupts = <16 IRQ_TYPE_LEVEL_LOW>; |
419 | #thermal-sensor-cells = <1>; | 419 | #thermal-sensor-cells = <1>; |
420 | }; | 420 | }; |
421 | 421 | ||
422 | tlv320aic3104: tlv320aic3104@18 { | 422 | tlv320aic3104: tlv320aic3104@18 { |
423 | compatible = "ti,tlv320aic3104"; | 423 | compatible = "ti,tlv320aic3104"; |
424 | reg = <0x18>; | 424 | reg = <0x18>; |
425 | status = "okay"; | 425 | status = "okay"; |
426 | adc-settle-ms = <40>; | 426 | adc-settle-ms = <40>; |
427 | 427 | ||
428 | AVDD-supply = <&vdd_3v3>; | 428 | AVDD-supply = <&vdd_3v3>; |
429 | IOVDD-supply = <&vdd_3v3>; | 429 | IOVDD-supply = <&vdd_3v3>; |
430 | DRVDD-supply = <&vdd_3v3>; | 430 | DRVDD-supply = <&vdd_3v3>; |
431 | DVDD-supply = <&aic_dvdd>; | 431 | DVDD-supply = <&aic_dvdd>; |
432 | }; | 432 | }; |
433 | }; | 433 | }; |
434 | 434 | ||
435 | &i2c3 { | 435 | &i2c3 { |
436 | status = "okay"; | 436 | status = "okay"; |
437 | clock-frequency = <400000>; | 437 | clock-frequency = <400000>; |
438 | 438 | ||
439 | mcp_rtc: rtc@6f { | 439 | mcp_rtc: rtc@6f { |
440 | compatible = "microchip,mcp7941x"; | 440 | compatible = "microchip,mcp7941x"; |
441 | reg = <0x6f>; | 441 | reg = <0x6f>; |
442 | vcc-supply = <&vdd_3v3>; | 442 | vcc-supply = <&vdd_3v3>; |
443 | 443 | ||
444 | /* Rev A1 */ | 444 | /* Rev A1 */ |
445 | interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_EDGE_RISING | 445 | interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_EDGE_RISING |
446 | &dra7_pmx_core 0x424>; | 446 | &dra7_pmx_core 0x424>; |
447 | wakeup-source; | 447 | wakeup-source; |
448 | }; | 448 | }; |
449 | }; | 449 | }; |
450 | 450 | ||
451 | &gpio7 { | 451 | &gpio7 { |
452 | ti,no-reset-on-init; | 452 | ti,no-reset-on-init; |
453 | ti,no-idle-on-init; | 453 | ti,no-idle-on-init; |
454 | }; | 454 | }; |
455 | 455 | ||
456 | &uart3 { | 456 | &uart3 { |
457 | status = "okay"; | 457 | status = "okay"; |
458 | interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH | 458 | interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH |
459 | &dra7_pmx_core 0x3f8>; | 459 | &dra7_pmx_core 0x3f8>; |
460 | }; | 460 | }; |
461 | 461 | ||
462 | &voltdm_mpu { | 462 | &voltdm_mpu { |
463 | vdd-supply = <&smps12_reg>; | 463 | vdd-supply = <&smps12_reg>; |
464 | }; | 464 | }; |
465 | 465 | ||
466 | &voltdm_dspeve { | 466 | &voltdm_dspeve { |
467 | vdd-supply = <&smps45_reg>; | 467 | vdd-supply = <&smps45_reg>; |
468 | }; | 468 | }; |
469 | 469 | ||
470 | &voltdm_gpu { | 470 | &voltdm_gpu { |
471 | vdd-supply = <&smps45_reg>; | 471 | vdd-supply = <&smps45_reg>; |
472 | }; | 472 | }; |
473 | 473 | ||
474 | &voltdm_ivahd { | 474 | &voltdm_ivahd { |
475 | vdd-supply = <&smps45_reg>; | 475 | vdd-supply = <&smps45_reg>; |
476 | }; | 476 | }; |
477 | 477 | ||
478 | &voltdm_core { | 478 | &voltdm_core { |
479 | vdd-supply = <&smps6_reg>; | 479 | vdd-supply = <&smps6_reg>; |
480 | }; | 480 | }; |
481 | 481 | ||
482 | &cpu0 { | 482 | &cpu0 { |
483 | cpu0-voltdm = <&voltdm_mpu>; | 483 | cpu0-voltdm = <&voltdm_mpu>; |
484 | voltage-tolerance = <1>; | 484 | voltage-tolerance = <1>; |
485 | }; | 485 | }; |
486 | 486 | ||
487 | &mac { | 487 | &mac { |
488 | status = "okay"; | 488 | status = "okay"; |
489 | dual_emac; | 489 | dual_emac; |
490 | ti,no-idle; | ||
490 | }; | 491 | }; |
491 | 492 | ||
492 | &cpsw_emac0 { | 493 | &cpsw_emac0 { |
493 | phy_id = <&davinci_mdio>, <1>; | 494 | phy_id = <&davinci_mdio>, <1>; |
494 | phy-mode = "rgmii"; | 495 | phy-mode = "rgmii"; |
495 | dual_emac_res_vlan = <1>; | 496 | dual_emac_res_vlan = <1>; |
496 | }; | 497 | }; |
497 | 498 | ||
498 | &cpsw_emac1 { | 499 | &cpsw_emac1 { |
499 | phy_id = <&davinci_mdio>, <2>; | 500 | phy_id = <&davinci_mdio>, <2>; |
500 | phy-mode = "rgmii"; | 501 | phy-mode = "rgmii"; |
501 | dual_emac_res_vlan = <2>; | 502 | dual_emac_res_vlan = <2>; |
502 | }; | 503 | }; |
503 | 504 | ||
504 | &mmc1 { | 505 | &mmc1 { |
505 | status = "okay"; | 506 | status = "okay"; |
506 | pinctrl-names = "default", "hs"; | 507 | pinctrl-names = "default", "hs"; |
507 | pinctrl-0 = <&mmc1_pins_default>; | 508 | pinctrl-0 = <&mmc1_pins_default>; |
508 | pinctrl-1 = <&mmc1_pins_hs>; | 509 | pinctrl-1 = <&mmc1_pins_hs>; |
509 | vmmc-supply = <&ldo1_reg>; | 510 | vmmc-supply = <&ldo1_reg>; |
510 | vmmc_aux-supply = <&vdd_3v3>; | 511 | vmmc_aux-supply = <&vdd_3v3>; |
511 | pbias-supply = <&pbias_mmc_reg>; | 512 | pbias-supply = <&pbias_mmc_reg>; |
512 | bus-width = <4>; | 513 | bus-width = <4>; |
513 | cd-gpios = <&gpio6 27 0>; /* gpio 219 */ | 514 | cd-gpios = <&gpio6 27 0>; /* gpio 219 */ |
514 | }; | 515 | }; |
515 | 516 | ||
516 | &mmc2 { | 517 | &mmc2 { |
517 | status = "okay"; | 518 | status = "okay"; |
518 | pinctrl-names = "default", "hs"; | 519 | pinctrl-names = "default", "hs"; |
519 | pinctrl-0 = <&mmc2_pins_default>; | 520 | pinctrl-0 = <&mmc2_pins_default>; |
520 | pinctrl-1 = <&mmc2_pins_hs>; | 521 | pinctrl-1 = <&mmc2_pins_hs>; |
521 | vmmc-supply = <&vdd_3v3>; | 522 | vmmc-supply = <&vdd_3v3>; |
522 | bus-width = <8>; | 523 | bus-width = <8>; |
523 | ti,non-removable; | 524 | ti,non-removable; |
524 | cap-mmc-dual-data-rate; | 525 | cap-mmc-dual-data-rate; |
525 | }; | 526 | }; |
526 | 527 | ||
527 | &dss { | 528 | &dss { |
528 | status = "ok"; | 529 | status = "ok"; |
529 | 530 | ||
530 | vdda_video-supply = <&ldoln_reg>; | 531 | vdda_video-supply = <&ldoln_reg>; |
531 | }; | 532 | }; |
532 | 533 | ||
533 | &hdmi { | 534 | &hdmi { |
534 | status = "ok"; | 535 | status = "ok"; |
535 | vdda-supply = <&ldo3_reg>; | 536 | vdda-supply = <&ldo3_reg>; |
536 | 537 | ||
537 | port { | 538 | port { |
538 | hdmi_out: endpoint { | 539 | hdmi_out: endpoint { |
539 | remote-endpoint = <&tpd12s015_in>; | 540 | remote-endpoint = <&tpd12s015_in>; |
540 | }; | 541 | }; |
541 | }; | 542 | }; |
542 | }; | 543 | }; |
543 | 544 | ||
544 | &mailbox3 { | 545 | &mailbox3 { |
545 | status = "okay"; | 546 | status = "okay"; |
546 | mbox_pru1_0: mbox_pru1_0 { | 547 | mbox_pru1_0: mbox_pru1_0 { |
547 | status = "okay"; | 548 | status = "okay"; |
548 | }; | 549 | }; |
549 | mbox_pru1_1: mbox_pru1_1 { | 550 | mbox_pru1_1: mbox_pru1_1 { |
550 | status = "okay"; | 551 | status = "okay"; |
551 | }; | 552 | }; |
552 | }; | 553 | }; |
553 | 554 | ||
554 | &mailbox4 { | 555 | &mailbox4 { |
555 | status = "okay"; | 556 | status = "okay"; |
556 | mbox_pru2_0: mbox_pru2_0 { | 557 | mbox_pru2_0: mbox_pru2_0 { |
557 | status = "okay"; | 558 | status = "okay"; |
558 | }; | 559 | }; |
559 | mbox_pru2_1: mbox_pru2_1 { | 560 | mbox_pru2_1: mbox_pru2_1 { |
560 | status = "okay"; | 561 | status = "okay"; |
561 | }; | 562 | }; |
562 | }; | 563 | }; |
563 | 564 | ||
564 | &mailbox5 { | 565 | &mailbox5 { |
565 | status = "okay"; | 566 | status = "okay"; |
566 | mbox_ipu1_legacy: mbox_ipu1_legacy { | 567 | mbox_ipu1_legacy: mbox_ipu1_legacy { |
567 | status = "okay"; | 568 | status = "okay"; |
568 | }; | 569 | }; |
569 | mbox_dsp1_legacy: mbox_dsp1_legacy { | 570 | mbox_dsp1_legacy: mbox_dsp1_legacy { |
570 | status = "okay"; | 571 | status = "okay"; |
571 | }; | 572 | }; |
572 | }; | 573 | }; |
573 | 574 | ||
574 | &mailbox6 { | 575 | &mailbox6 { |
575 | status = "okay"; | 576 | status = "okay"; |
576 | mbox_ipu2_legacy: mbox_ipu2_legacy { | 577 | mbox_ipu2_legacy: mbox_ipu2_legacy { |
577 | status = "okay"; | 578 | status = "okay"; |
578 | }; | 579 | }; |
579 | mbox_dsp2_legacy: mbox_dsp2_legacy { | 580 | mbox_dsp2_legacy: mbox_dsp2_legacy { |
580 | status = "okay"; | 581 | status = "okay"; |
581 | }; | 582 | }; |
582 | }; | 583 | }; |
583 | 584 | ||
584 | &mmu0_dsp1 { | 585 | &mmu0_dsp1 { |
585 | status = "okay"; | 586 | status = "okay"; |
586 | }; | 587 | }; |
587 | 588 | ||
588 | &mmu1_dsp1 { | 589 | &mmu1_dsp1 { |
589 | status = "okay"; | 590 | status = "okay"; |
590 | }; | 591 | }; |
591 | 592 | ||
592 | &mmu0_dsp2 { | 593 | &mmu0_dsp2 { |
593 | status = "okay"; | 594 | status = "okay"; |
594 | }; | 595 | }; |
595 | 596 | ||
596 | &mmu1_dsp2 { | 597 | &mmu1_dsp2 { |
597 | status = "okay"; | 598 | status = "okay"; |
598 | }; | 599 | }; |
599 | 600 | ||
600 | &mmu_ipu1 { | 601 | &mmu_ipu1 { |
601 | status = "okay"; | 602 | status = "okay"; |
602 | }; | 603 | }; |
603 | 604 | ||
604 | &mmu_ipu2 { | 605 | &mmu_ipu2 { |
605 | status = "okay"; | 606 | status = "okay"; |
606 | }; | 607 | }; |
607 | 608 | ||
608 | &ipu2 { | 609 | &ipu2 { |
609 | status = "okay"; | 610 | status = "okay"; |
610 | memory-region = <&ipu2_cma_pool>; | 611 | memory-region = <&ipu2_cma_pool>; |
611 | mboxes = <&mailbox6 &mbox_ipu2_legacy>; | 612 | mboxes = <&mailbox6 &mbox_ipu2_legacy>; |
612 | timers = <&timer3>; | 613 | timers = <&timer3>; |
613 | watchdog-timers = <&timer4>, <&timer9>; | 614 | watchdog-timers = <&timer4>, <&timer9>; |
614 | }; | 615 | }; |
615 | 616 | ||
616 | &ipu1 { | 617 | &ipu1 { |
617 | status = "okay"; | 618 | status = "okay"; |
618 | memory-region = <&ipu1_cma_pool>; | 619 | memory-region = <&ipu1_cma_pool>; |
619 | mboxes = <&mailbox5 &mbox_ipu1_legacy>; | 620 | mboxes = <&mailbox5 &mbox_ipu1_legacy>; |
620 | timers = <&timer11>; | 621 | timers = <&timer11>; |
621 | }; | 622 | }; |
622 | 623 | ||
623 | &dsp1 { | 624 | &dsp1 { |
624 | status = "okay"; | 625 | status = "okay"; |
625 | memory-region = <&dsp1_cma_pool>; | 626 | memory-region = <&dsp1_cma_pool>; |
626 | mboxes = <&mailbox5 &mbox_dsp1_legacy>; | 627 | mboxes = <&mailbox5 &mbox_dsp1_legacy>; |
627 | timers = <&timer5>; | 628 | timers = <&timer5>; |
628 | }; | 629 | }; |
629 | 630 | ||
630 | &dsp2 { | 631 | &dsp2 { |
631 | status = "okay"; | 632 | status = "okay"; |
632 | memory-region = <&dsp2_cma_pool>; | 633 | memory-region = <&dsp2_cma_pool>; |
633 | mboxes = <&mailbox6 &mbox_dsp2_legacy>; | 634 | mboxes = <&mailbox6 &mbox_dsp2_legacy>; |
634 | timers = <&timer6>; | 635 | timers = <&timer6>; |
635 | }; | 636 | }; |
636 | 637 | ||
637 | &usb2_phy1 { | 638 | &usb2_phy1 { |
638 | phy-supply = <&ldousb_reg>; | 639 | phy-supply = <&ldousb_reg>; |
639 | }; | 640 | }; |
640 | 641 | ||
641 | &usb2_phy2 { | 642 | &usb2_phy2 { |
642 | phy-supply = <&ldousb_reg>; | 643 | phy-supply = <&ldousb_reg>; |
643 | }; | 644 | }; |
644 | 645 | ||
645 | &usb1 { | 646 | &usb1 { |
646 | dr_mode = "host"; | 647 | dr_mode = "host"; |
647 | }; | 648 | }; |
648 | 649 | ||
649 | &omap_dwc3_2 { | 650 | &omap_dwc3_2 { |
650 | extcon = <&extcon_usb2>; | 651 | extcon = <&extcon_usb2>; |
651 | }; | 652 | }; |
652 | 653 | ||
653 | &usb2 { | 654 | &usb2 { |
654 | /* | 655 | /* |
655 | * Stand alone usage is peripheral only. | 656 | * Stand alone usage is peripheral only. |
656 | * However, with some resistor modifications | 657 | * However, with some resistor modifications |
657 | * this port can be used via expansion connectors | 658 | * this port can be used via expansion connectors |
658 | * as "host" or "dual-role". If so, provide | 659 | * as "host" or "dual-role". If so, provide |
659 | * the necessary dr_mode override in the expansion | 660 | * the necessary dr_mode override in the expansion |
660 | * board's DT. | 661 | * board's DT. |
661 | */ | 662 | */ |
662 | dr_mode = "peripheral"; | 663 | dr_mode = "peripheral"; |
663 | }; | 664 | }; |
664 | 665 | ||
665 | &mcasp3 { | 666 | &mcasp3 { |
666 | status = "okay"; | 667 | status = "okay"; |
667 | 668 | ||
668 | op-mode = <0>; /* MCASP_IIS_MODE */ | 669 | op-mode = <0>; /* MCASP_IIS_MODE */ |
669 | tdm-slots = <2>; | 670 | tdm-slots = <2>; |
670 | /* 4 serializers */ | 671 | /* 4 serializers */ |
671 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | 672 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
672 | 1 2 0 0 | 673 | 1 2 0 0 |
673 | >; | 674 | >; |
674 | }; | 675 | }; |
675 | 676 | ||
676 | &pruss1 { | 677 | &pruss1 { |
677 | status = "okay"; | 678 | status = "okay"; |
678 | pru1_0: pru@4b234000 { | 679 | pru1_0: pru@4b234000 { |
679 | mboxes = <&mailbox3 &mbox_pru1_0>; | 680 | mboxes = <&mailbox3 &mbox_pru1_0>; |
680 | status = "okay"; | 681 | status = "okay"; |
681 | }; | 682 | }; |
682 | 683 | ||
683 | pru1_1: pru@4b238000 { | 684 | pru1_1: pru@4b238000 { |
684 | mboxes = <&mailbox3 &mbox_pru1_1>; | 685 | mboxes = <&mailbox3 &mbox_pru1_1>; |
685 | status = "okay"; | 686 | status = "okay"; |
686 | }; | 687 | }; |
687 | }; | 688 | }; |
688 | 689 | ||
689 | &pruss2 { | 690 | &pruss2 { |
690 | status = "okay"; | 691 | status = "okay"; |
691 | pru2_0: pru@4b2b4000 { | 692 | pru2_0: pru@4b2b4000 { |
692 | mboxes = <&mailbox4 &mbox_pru2_0>; | 693 | mboxes = <&mailbox4 &mbox_pru2_0>; |
693 | status = "okay"; | 694 | status = "okay"; |
694 | }; | 695 | }; |
695 | 696 | ||
696 | pru2_1: pru@4b2b8000 { | 697 | pru2_1: pru@4b2b8000 { |
697 | mboxes = <&mailbox4 &mbox_pru2_1>; | 698 | mboxes = <&mailbox4 &mbox_pru2_1>; |
698 | status = "okay"; | 699 | status = "okay"; |
699 | }; | 700 | }; |
700 | }; | 701 | }; |
701 | 702 | ||
702 | &cpu_trips { | 703 | &cpu_trips { |
703 | cpu_alert1: cpu_alert1 { | 704 | cpu_alert1: cpu_alert1 { |
704 | temperature = <50000>; /* millicelsius */ | 705 | temperature = <50000>; /* millicelsius */ |
705 | hysteresis = <2000>; /* millicelsius */ | 706 | hysteresis = <2000>; /* millicelsius */ |
706 | type = "active"; | 707 | type = "active"; |
707 | }; | 708 | }; |
708 | }; | 709 | }; |
709 | 710 | ||
710 | &cpu_cooling_maps { | 711 | &cpu_cooling_maps { |
711 | map1 { | 712 | map1 { |
712 | trip = <&cpu_alert1>; | 713 | trip = <&cpu_alert1>; |
713 | cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | 714 | cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
714 | }; | 715 | }; |
715 | }; | 716 | }; |
716 | 717 | ||
717 | &thermal_zones { | 718 | &thermal_zones { |
718 | board_thermal: board_thermal { | 719 | board_thermal: board_thermal { |
719 | polling-delay-passive = <1250>; /* milliseconds */ | 720 | polling-delay-passive = <1250>; /* milliseconds */ |
720 | polling-delay = <1500>; /* milliseconds */ | 721 | polling-delay = <1500>; /* milliseconds */ |
721 | 722 | ||
722 | /* sensor ID */ | 723 | /* sensor ID */ |
723 | thermal-sensors = <&tmp102 0>; | 724 | thermal-sensors = <&tmp102 0>; |
724 | 725 | ||
725 | board_trips: trips { | 726 | board_trips: trips { |
726 | board_alert0: board_alert { | 727 | board_alert0: board_alert { |
727 | temperature = <40000>; /* millicelsius */ | 728 | temperature = <40000>; /* millicelsius */ |
728 | hysteresis = <2000>; /* millicelsius */ | 729 | hysteresis = <2000>; /* millicelsius */ |
729 | type = "active"; | 730 | type = "active"; |
730 | }; | 731 | }; |
731 | 732 | ||
732 | board_crit: board_crit { | 733 | board_crit: board_crit { |
733 | temperature = <105000>; /* millicelsius */ | 734 | temperature = <105000>; /* millicelsius */ |
734 | hysteresis = <0>; /* millicelsius */ | 735 | hysteresis = <0>; /* millicelsius */ |
735 | type = "critical"; | 736 | type = "critical"; |
736 | }; | 737 | }; |
737 | }; | 738 | }; |
738 | 739 | ||
739 | board_cooling_maps: cooling-maps { | 740 | board_cooling_maps: cooling-maps { |
740 | map0 { | 741 | map0 { |
741 | trip = <&board_alert0>; | 742 | trip = <&board_alert0>; |
742 | cooling-device = | 743 | cooling-device = |
743 | <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | 744 | <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
744 | }; | 745 | }; |
745 | }; | 746 | }; |
746 | }; | 747 | }; |
747 | }; | 748 | }; |
748 | 749 |
arch/arm/boot/dts/dra7-evm.dts
1 | /* | 1 | /* |
2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
7 | */ | 7 | */ |
8 | /dts-v1/; | 8 | /dts-v1/; |
9 | 9 | ||
10 | #include "dra74x.dtsi" | 10 | #include "dra74x.dtsi" |
11 | #include <dt-bindings/interrupt-controller/irq.h> | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
12 | #include <dt-bindings/gpio/gpio.h> | 12 | #include <dt-bindings/gpio/gpio.h> |
13 | #include <dt-bindings/clk/ti-dra7-atl.h> | 13 | #include <dt-bindings/clk/ti-dra7-atl.h> |
14 | 14 | ||
15 | / { | 15 | / { |
16 | model = "TI DRA742"; | 16 | model = "TI DRA742"; |
17 | compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; | 17 | compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; |
18 | 18 | ||
19 | memory { | 19 | memory { |
20 | device_type = "memory"; | 20 | device_type = "memory"; |
21 | reg = <0x80000000 0x60000000>; /* 1536 MB */ | 21 | reg = <0x80000000 0x60000000>; /* 1536 MB */ |
22 | }; | 22 | }; |
23 | 23 | ||
24 | reserved-memory { | 24 | reserved-memory { |
25 | #address-cells = <1>; | 25 | #address-cells = <1>; |
26 | #size-cells = <1>; | 26 | #size-cells = <1>; |
27 | ranges; | 27 | ranges; |
28 | 28 | ||
29 | ipu2_cma_pool: ipu2_cma@95800000 { | 29 | ipu2_cma_pool: ipu2_cma@95800000 { |
30 | compatible = "shared-dma-pool"; | 30 | compatible = "shared-dma-pool"; |
31 | reg = <0x95800000 0x3800000>; | 31 | reg = <0x95800000 0x3800000>; |
32 | reusable; | 32 | reusable; |
33 | status = "okay"; | 33 | status = "okay"; |
34 | }; | 34 | }; |
35 | 35 | ||
36 | dsp1_cma_pool: dsp1_cma@99000000 { | 36 | dsp1_cma_pool: dsp1_cma@99000000 { |
37 | compatible = "shared-dma-pool"; | 37 | compatible = "shared-dma-pool"; |
38 | reg = <0x99000000 0x4000000>; | 38 | reg = <0x99000000 0x4000000>; |
39 | reusable; | 39 | reusable; |
40 | status = "okay"; | 40 | status = "okay"; |
41 | }; | 41 | }; |
42 | 42 | ||
43 | ipu1_cma_pool: ipu1_cma@9d000000 { | 43 | ipu1_cma_pool: ipu1_cma@9d000000 { |
44 | compatible = "shared-dma-pool"; | 44 | compatible = "shared-dma-pool"; |
45 | reg = <0x9d000000 0x2000000>; | 45 | reg = <0x9d000000 0x2000000>; |
46 | reusable; | 46 | reusable; |
47 | status = "okay"; | 47 | status = "okay"; |
48 | }; | 48 | }; |
49 | 49 | ||
50 | dsp2_cma_pool: dsp2_cma@9f000000 { | 50 | dsp2_cma_pool: dsp2_cma@9f000000 { |
51 | compatible = "shared-dma-pool"; | 51 | compatible = "shared-dma-pool"; |
52 | reg = <0x9f000000 0x800000>; | 52 | reg = <0x9f000000 0x800000>; |
53 | reusable; | 53 | reusable; |
54 | status = "okay"; | 54 | status = "okay"; |
55 | }; | 55 | }; |
56 | }; | 56 | }; |
57 | 57 | ||
58 | extcon_usb1: extcon_usb1 { | 58 | extcon_usb1: extcon_usb1 { |
59 | compatible = "linux,extcon-usb-gpio"; | 59 | compatible = "linux,extcon-usb-gpio"; |
60 | id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; | 60 | id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; |
61 | }; | 61 | }; |
62 | 62 | ||
63 | extcon_usb2: extcon_usb2 { | 63 | extcon_usb2: extcon_usb2 { |
64 | compatible = "linux,extcon-usb-gpio"; | 64 | compatible = "linux,extcon-usb-gpio"; |
65 | id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; | 65 | id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; |
66 | }; | 66 | }; |
67 | 67 | ||
68 | evm_3v3_sd: fixedregulator-sd { | 68 | evm_3v3_sd: fixedregulator-sd { |
69 | compatible = "regulator-fixed"; | 69 | compatible = "regulator-fixed"; |
70 | regulator-name = "evm_3v3_sd"; | 70 | regulator-name = "evm_3v3_sd"; |
71 | regulator-min-microvolt = <3300000>; | 71 | regulator-min-microvolt = <3300000>; |
72 | regulator-max-microvolt = <3300000>; | 72 | regulator-max-microvolt = <3300000>; |
73 | enable-active-high; | 73 | enable-active-high; |
74 | gpio = <&pcf_gpio_21 5 0>; | 74 | gpio = <&pcf_gpio_21 5 0>; |
75 | }; | 75 | }; |
76 | 76 | ||
77 | evm_3v3_sw: fixedregulator-evm_3v3_sw { | 77 | evm_3v3_sw: fixedregulator-evm_3v3_sw { |
78 | compatible = "regulator-fixed"; | 78 | compatible = "regulator-fixed"; |
79 | regulator-name = "evm_3v3_sw"; | 79 | regulator-name = "evm_3v3_sw"; |
80 | vin-supply = <&sysen1>; | 80 | vin-supply = <&sysen1>; |
81 | regulator-min-microvolt = <3300000>; | 81 | regulator-min-microvolt = <3300000>; |
82 | regulator-max-microvolt = <3300000>; | 82 | regulator-max-microvolt = <3300000>; |
83 | }; | 83 | }; |
84 | 84 | ||
85 | aic_dvdd: fixedregulator-aic_dvdd { | 85 | aic_dvdd: fixedregulator-aic_dvdd { |
86 | /* TPS77018DBVT */ | 86 | /* TPS77018DBVT */ |
87 | compatible = "regulator-fixed"; | 87 | compatible = "regulator-fixed"; |
88 | regulator-name = "aic_dvdd"; | 88 | regulator-name = "aic_dvdd"; |
89 | vin-supply = <&evm_3v3_sw>; | 89 | vin-supply = <&evm_3v3_sw>; |
90 | regulator-min-microvolt = <1800000>; | 90 | regulator-min-microvolt = <1800000>; |
91 | regulator-max-microvolt = <1800000>; | 91 | regulator-max-microvolt = <1800000>; |
92 | }; | 92 | }; |
93 | 93 | ||
94 | vmmcwl_fixed: fixedregulator-mmcwl { | 94 | vmmcwl_fixed: fixedregulator-mmcwl { |
95 | compatible = "regulator-fixed"; | 95 | compatible = "regulator-fixed"; |
96 | regulator-name = "vmmcwl_fixed"; | 96 | regulator-name = "vmmcwl_fixed"; |
97 | regulator-min-microvolt = <1800000>; | 97 | regulator-min-microvolt = <1800000>; |
98 | regulator-max-microvolt = <1800000>; | 98 | regulator-max-microvolt = <1800000>; |
99 | gpio = <&gpio5 8 0>; /* gpio5_8 */ | 99 | gpio = <&gpio5 8 0>; /* gpio5_8 */ |
100 | startup-delay-us = <70000>; | 100 | startup-delay-us = <70000>; |
101 | enable-active-high; | 101 | enable-active-high; |
102 | }; | 102 | }; |
103 | 103 | ||
104 | kim { | 104 | kim { |
105 | compatible = "kim"; | 105 | compatible = "kim"; |
106 | nshutdown_gpio = <132>; | 106 | nshutdown_gpio = <132>; |
107 | dev_name = "/dev/ttyS2"; | 107 | dev_name = "/dev/ttyS2"; |
108 | flow_cntrl = <1>; | 108 | flow_cntrl = <1>; |
109 | baud_rate = <3686400>; | 109 | baud_rate = <3686400>; |
110 | }; | 110 | }; |
111 | 111 | ||
112 | btwilink { | 112 | btwilink { |
113 | compatible = "btwilink"; | 113 | compatible = "btwilink"; |
114 | }; | 114 | }; |
115 | 115 | ||
116 | vtt_fixed: fixedregulator-vtt { | 116 | vtt_fixed: fixedregulator-vtt { |
117 | compatible = "regulator-fixed"; | 117 | compatible = "regulator-fixed"; |
118 | regulator-name = "vtt_fixed"; | 118 | regulator-name = "vtt_fixed"; |
119 | regulator-min-microvolt = <1350000>; | 119 | regulator-min-microvolt = <1350000>; |
120 | regulator-max-microvolt = <1350000>; | 120 | regulator-max-microvolt = <1350000>; |
121 | regulator-always-on; | 121 | regulator-always-on; |
122 | regulator-boot-on; | 122 | regulator-boot-on; |
123 | enable-active-high; | 123 | enable-active-high; |
124 | vin-supply = <&sysen2>; | 124 | vin-supply = <&sysen2>; |
125 | gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; | 125 | gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; |
126 | }; | 126 | }; |
127 | 127 | ||
128 | aliases { | 128 | aliases { |
129 | display0 = &hdmi0; | 129 | display0 = &hdmi0; |
130 | sound0 = &primary_sound; | 130 | sound0 = &primary_sound; |
131 | sound1 = &hdmi; | 131 | sound1 = &hdmi; |
132 | }; | 132 | }; |
133 | 133 | ||
134 | hdmi0: connector@1 { | 134 | hdmi0: connector@1 { |
135 | compatible = "hdmi-connector"; | 135 | compatible = "hdmi-connector"; |
136 | label = "hdmi"; | 136 | label = "hdmi"; |
137 | 137 | ||
138 | type = "a"; | 138 | type = "a"; |
139 | 139 | ||
140 | port { | 140 | port { |
141 | hdmi_connector_in: endpoint { | 141 | hdmi_connector_in: endpoint { |
142 | remote-endpoint = <&tpd12s015_out>; | 142 | remote-endpoint = <&tpd12s015_out>; |
143 | }; | 143 | }; |
144 | }; | 144 | }; |
145 | }; | 145 | }; |
146 | 146 | ||
147 | tpd12s015: encoder@1 { | 147 | tpd12s015: encoder@1 { |
148 | compatible = "ti,dra7evm-tpd12s015"; | 148 | compatible = "ti,dra7evm-tpd12s015"; |
149 | 149 | ||
150 | gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */ | 150 | gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */ |
151 | <&pcf_hdmi 5 0>, /* P5, LS OE */ | 151 | <&pcf_hdmi 5 0>, /* P5, LS OE */ |
152 | <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */ | 152 | <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */ |
153 | 153 | ||
154 | ports { | 154 | ports { |
155 | #address-cells = <1>; | 155 | #address-cells = <1>; |
156 | #size-cells = <0>; | 156 | #size-cells = <0>; |
157 | 157 | ||
158 | port@0 { | 158 | port@0 { |
159 | reg = <0>; | 159 | reg = <0>; |
160 | 160 | ||
161 | tpd12s015_in: endpoint@0 { | 161 | tpd12s015_in: endpoint@0 { |
162 | remote-endpoint = <&hdmi_out>; | 162 | remote-endpoint = <&hdmi_out>; |
163 | }; | 163 | }; |
164 | }; | 164 | }; |
165 | 165 | ||
166 | port@1 { | 166 | port@1 { |
167 | reg = <1>; | 167 | reg = <1>; |
168 | 168 | ||
169 | tpd12s015_out: endpoint@0 { | 169 | tpd12s015_out: endpoint@0 { |
170 | remote-endpoint = <&hdmi_connector_in>; | 170 | remote-endpoint = <&hdmi_connector_in>; |
171 | }; | 171 | }; |
172 | }; | 172 | }; |
173 | }; | 173 | }; |
174 | }; | 174 | }; |
175 | 175 | ||
176 | primary_sound: primary_sound { | 176 | primary_sound: primary_sound { |
177 | compatible = "ti,dra7xx-evm-audio"; | 177 | compatible = "ti,dra7xx-evm-audio"; |
178 | ti,model = "DRA7xx-EVM"; | 178 | ti,model = "DRA7xx-EVM"; |
179 | ti,audio-codec = <&tlv320aic3106>; | 179 | ti,audio-codec = <&tlv320aic3106>; |
180 | ti,mcasp-controller = <&mcasp3>; | 180 | ti,mcasp-controller = <&mcasp3>; |
181 | ti,codec-clock-rate = <5644800>; | 181 | ti,codec-clock-rate = <5644800>; |
182 | clocks = <&atl_clkin2_ck>; | 182 | clocks = <&atl_clkin2_ck>; |
183 | clock-names = "mclk"; | 183 | clock-names = "mclk"; |
184 | ti,audio-routing = | 184 | ti,audio-routing = |
185 | "Headphone Jack", "HPLOUT", | 185 | "Headphone Jack", "HPLOUT", |
186 | "Headphone Jack", "HPROUT", | 186 | "Headphone Jack", "HPROUT", |
187 | "Line Out", "LLOUT", | 187 | "Line Out", "LLOUT", |
188 | "Line Out", "RLOUT", | 188 | "Line Out", "RLOUT", |
189 | "MIC3L", "Mic Jack", | 189 | "MIC3L", "Mic Jack", |
190 | "MIC3R", "Mic Jack", | 190 | "MIC3R", "Mic Jack", |
191 | "Mic Jack", "Mic Bias", | 191 | "Mic Jack", "Mic Bias", |
192 | "LINE1L", "Line In", | 192 | "LINE1L", "Line In", |
193 | "LINE1R", "Line In"; | 193 | "LINE1R", "Line In"; |
194 | }; | 194 | }; |
195 | }; | 195 | }; |
196 | 196 | ||
197 | &dra7_pmx_core { | 197 | &dra7_pmx_core { |
198 | wlan_pins: pinmux_wlan_pins { | 198 | wlan_pins: pinmux_wlan_pins { |
199 | pinctrl-single,pins = < | 199 | pinctrl-single,pins = < |
200 | 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ | 200 | 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ |
201 | 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ | 201 | 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ |
202 | 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ | 202 | 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ |
203 | 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ | 203 | 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ |
204 | 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ | 204 | 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ |
205 | 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ | 205 | 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ |
206 | 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */ | 206 | 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */ |
207 | >; | 207 | >; |
208 | }; | 208 | }; |
209 | 209 | ||
210 | wlirq_pins: pinmux_wlirq_pins { | 210 | wlirq_pins: pinmux_wlirq_pins { |
211 | pinctrl-single,pins = < | 211 | pinctrl-single,pins = < |
212 | 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */ | 212 | 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */ |
213 | >; | 213 | >; |
214 | }; | 214 | }; |
215 | 215 | ||
216 | dcan1_pins_default: dcan1_pins_default { | 216 | dcan1_pins_default: dcan1_pins_default { |
217 | pinctrl-single,pins = < | 217 | pinctrl-single,pins = < |
218 | 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ | 218 | 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ |
219 | 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ | 219 | 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ |
220 | >; | 220 | >; |
221 | }; | 221 | }; |
222 | 222 | ||
223 | dcan1_pins_sleep: dcan1_pins_sleep { | 223 | dcan1_pins_sleep: dcan1_pins_sleep { |
224 | pinctrl-single,pins = < | 224 | pinctrl-single,pins = < |
225 | 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ | 225 | 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ |
226 | 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ | 226 | 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ |
227 | >; | 227 | >; |
228 | }; | 228 | }; |
229 | 229 | ||
230 | mmc1_pins_default: pinmux_mmc1_default_pins { | 230 | mmc1_pins_default: pinmux_mmc1_default_pins { |
231 | pinctrl-single,pins = < | 231 | pinctrl-single,pins = < |
232 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | 232 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ |
233 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | 233 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ |
234 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | 234 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ |
235 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | 235 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ |
236 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | 236 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ |
237 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | 237 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ |
238 | 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */ | 238 | 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */ |
239 | >; | 239 | >; |
240 | }; | 240 | }; |
241 | 241 | ||
242 | mmc1_pins_hs: pinmux_mmc1_hs_pins { | 242 | mmc1_pins_hs: pinmux_mmc1_hs_pins { |
243 | pinctrl-single,pins = < | 243 | pinctrl-single,pins = < |
244 | 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ | 244 | 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ |
245 | 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ | 245 | 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ |
246 | 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ | 246 | 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ |
247 | 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ | 247 | 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ |
248 | 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ | 248 | 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ |
249 | 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ | 249 | 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ |
250 | >; | 250 | >; |
251 | }; | 251 | }; |
252 | 252 | ||
253 | mmc2_pins_default: mmc2_pins_default { | 253 | mmc2_pins_default: mmc2_pins_default { |
254 | pinctrl-single,pins = < | 254 | pinctrl-single,pins = < |
255 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | 255 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ |
256 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | 256 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ |
257 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | 257 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ |
258 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | 258 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ |
259 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | 259 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ |
260 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | 260 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ |
261 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | 261 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ |
262 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | 262 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ |
263 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | 263 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ |
264 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | 264 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ |
265 | >; | 265 | >; |
266 | }; | 266 | }; |
267 | 267 | ||
268 | mmc2_pins_hs: pinmux_mmc2_hs_pins { | 268 | mmc2_pins_hs: pinmux_mmc2_hs_pins { |
269 | pinctrl-single,pins = < | 269 | pinctrl-single,pins = < |
270 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | 270 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ |
271 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | 271 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ |
272 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | 272 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ |
273 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | 273 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ |
274 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | 274 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ |
275 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | 275 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ |
276 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | 276 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ |
277 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | 277 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ |
278 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | 278 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ |
279 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | 279 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ |
280 | >; | 280 | >; |
281 | }; | 281 | }; |
282 | }; | 282 | }; |
283 | 283 | ||
284 | &i2c1 { | 284 | &i2c1 { |
285 | status = "okay"; | 285 | status = "okay"; |
286 | clock-frequency = <400000>; | 286 | clock-frequency = <400000>; |
287 | 287 | ||
288 | tps659038: tps659038@58 { | 288 | tps659038: tps659038@58 { |
289 | compatible = "ti,tps659038"; | 289 | compatible = "ti,tps659038"; |
290 | reg = <0x58>; | 290 | reg = <0x58>; |
291 | 291 | ||
292 | tps659038_pmic { | 292 | tps659038_pmic { |
293 | compatible = "ti,tps659038-pmic"; | 293 | compatible = "ti,tps659038-pmic"; |
294 | 294 | ||
295 | regulators { | 295 | regulators { |
296 | smps123_reg: smps123 { | 296 | smps123_reg: smps123 { |
297 | /* VDD_MPU */ | 297 | /* VDD_MPU */ |
298 | regulator-name = "smps123"; | 298 | regulator-name = "smps123"; |
299 | regulator-min-microvolt = < 850000>; | 299 | regulator-min-microvolt = < 850000>; |
300 | regulator-max-microvolt = <1250000>; | 300 | regulator-max-microvolt = <1250000>; |
301 | regulator-always-on; | 301 | regulator-always-on; |
302 | regulator-boot-on; | 302 | regulator-boot-on; |
303 | }; | 303 | }; |
304 | 304 | ||
305 | smps45_reg: smps45 { | 305 | smps45_reg: smps45 { |
306 | /* VDD_DSPEVE */ | 306 | /* VDD_DSPEVE */ |
307 | regulator-name = "smps45"; | 307 | regulator-name = "smps45"; |
308 | regulator-min-microvolt = < 850000>; | 308 | regulator-min-microvolt = < 850000>; |
309 | regulator-max-microvolt = <1150000>; | 309 | regulator-max-microvolt = <1150000>; |
310 | regulator-boot-on; | 310 | regulator-boot-on; |
311 | regulator-always-on; | 311 | regulator-always-on; |
312 | }; | 312 | }; |
313 | 313 | ||
314 | smps6_reg: smps6 { | 314 | smps6_reg: smps6 { |
315 | /* VDD_GPU - over VDD_SMPS6 */ | 315 | /* VDD_GPU - over VDD_SMPS6 */ |
316 | regulator-name = "smps6"; | 316 | regulator-name = "smps6"; |
317 | regulator-min-microvolt = <850000>; | 317 | regulator-min-microvolt = <850000>; |
318 | regulator-max-microvolt = <1250000>; | 318 | regulator-max-microvolt = <1250000>; |
319 | regulator-boot-on; | 319 | regulator-boot-on; |
320 | regulator-always-on; | 320 | regulator-always-on; |
321 | }; | 321 | }; |
322 | 322 | ||
323 | smps7_reg: smps7 { | 323 | smps7_reg: smps7 { |
324 | /* CORE_VDD */ | 324 | /* CORE_VDD */ |
325 | regulator-name = "smps7"; | 325 | regulator-name = "smps7"; |
326 | regulator-min-microvolt = <850000>; | 326 | regulator-min-microvolt = <850000>; |
327 | regulator-max-microvolt = <1060000>; | 327 | regulator-max-microvolt = <1060000>; |
328 | regulator-always-on; | 328 | regulator-always-on; |
329 | regulator-boot-on; | 329 | regulator-boot-on; |
330 | }; | 330 | }; |
331 | 331 | ||
332 | smps8_reg: smps8 { | 332 | smps8_reg: smps8 { |
333 | /* VDD_IVAHD */ | 333 | /* VDD_IVAHD */ |
334 | regulator-name = "smps8"; | 334 | regulator-name = "smps8"; |
335 | regulator-min-microvolt = < 850000>; | 335 | regulator-min-microvolt = < 850000>; |
336 | regulator-max-microvolt = <1250000>; | 336 | regulator-max-microvolt = <1250000>; |
337 | regulator-boot-on; | 337 | regulator-boot-on; |
338 | regulator-always-on; | 338 | regulator-always-on; |
339 | }; | 339 | }; |
340 | 340 | ||
341 | smps9_reg: smps9 { | 341 | smps9_reg: smps9 { |
342 | /* VDDS1V8 */ | 342 | /* VDDS1V8 */ |
343 | regulator-name = "smps9"; | 343 | regulator-name = "smps9"; |
344 | regulator-min-microvolt = <1800000>; | 344 | regulator-min-microvolt = <1800000>; |
345 | regulator-max-microvolt = <1800000>; | 345 | regulator-max-microvolt = <1800000>; |
346 | regulator-always-on; | 346 | regulator-always-on; |
347 | regulator-boot-on; | 347 | regulator-boot-on; |
348 | }; | 348 | }; |
349 | 349 | ||
350 | ldo1_reg: ldo1 { | 350 | ldo1_reg: ldo1 { |
351 | /* LDO1_OUT --> SDIO */ | 351 | /* LDO1_OUT --> SDIO */ |
352 | regulator-name = "ldo1"; | 352 | regulator-name = "ldo1"; |
353 | regulator-min-microvolt = <1800000>; | 353 | regulator-min-microvolt = <1800000>; |
354 | regulator-max-microvolt = <3300000>; | 354 | regulator-max-microvolt = <3300000>; |
355 | regulator-boot-on; | 355 | regulator-boot-on; |
356 | regulator-always-on; | 356 | regulator-always-on; |
357 | }; | 357 | }; |
358 | 358 | ||
359 | ldo2_reg: ldo2 { | 359 | ldo2_reg: ldo2 { |
360 | /* VDD_RTCIO */ | 360 | /* VDD_RTCIO */ |
361 | /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ | 361 | /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ |
362 | regulator-name = "ldo2"; | 362 | regulator-name = "ldo2"; |
363 | regulator-min-microvolt = <3300000>; | 363 | regulator-min-microvolt = <3300000>; |
364 | regulator-max-microvolt = <3300000>; | 364 | regulator-max-microvolt = <3300000>; |
365 | regulator-boot-on; | 365 | regulator-boot-on; |
366 | regulator-always-on; | 366 | regulator-always-on; |
367 | }; | 367 | }; |
368 | 368 | ||
369 | ldo3_reg: ldo3 { | 369 | ldo3_reg: ldo3 { |
370 | /* VDDA_1V8_PHY */ | 370 | /* VDDA_1V8_PHY */ |
371 | regulator-name = "ldo3"; | 371 | regulator-name = "ldo3"; |
372 | regulator-min-microvolt = <1800000>; | 372 | regulator-min-microvolt = <1800000>; |
373 | regulator-max-microvolt = <1800000>; | 373 | regulator-max-microvolt = <1800000>; |
374 | regulator-always-on; | 374 | regulator-always-on; |
375 | regulator-boot-on; | 375 | regulator-boot-on; |
376 | }; | 376 | }; |
377 | 377 | ||
378 | ldo9_reg: ldo9 { | 378 | ldo9_reg: ldo9 { |
379 | /* VDD_RTC */ | 379 | /* VDD_RTC */ |
380 | regulator-name = "ldo9"; | 380 | regulator-name = "ldo9"; |
381 | regulator-min-microvolt = <1050000>; | 381 | regulator-min-microvolt = <1050000>; |
382 | regulator-max-microvolt = <1050000>; | 382 | regulator-max-microvolt = <1050000>; |
383 | regulator-boot-on; | 383 | regulator-boot-on; |
384 | regulator-always-on; | 384 | regulator-always-on; |
385 | }; | 385 | }; |
386 | 386 | ||
387 | ldoln_reg: ldoln { | 387 | ldoln_reg: ldoln { |
388 | /* VDDA_1V8_PLL */ | 388 | /* VDDA_1V8_PLL */ |
389 | regulator-name = "ldoln"; | 389 | regulator-name = "ldoln"; |
390 | regulator-min-microvolt = <1800000>; | 390 | regulator-min-microvolt = <1800000>; |
391 | regulator-max-microvolt = <1800000>; | 391 | regulator-max-microvolt = <1800000>; |
392 | regulator-always-on; | 392 | regulator-always-on; |
393 | regulator-boot-on; | 393 | regulator-boot-on; |
394 | }; | 394 | }; |
395 | 395 | ||
396 | ldousb_reg: ldousb { | 396 | ldousb_reg: ldousb { |
397 | /* VDDA_3V_USB: VDDA_USBHS33 */ | 397 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
398 | regulator-name = "ldousb"; | 398 | regulator-name = "ldousb"; |
399 | regulator-min-microvolt = <3300000>; | 399 | regulator-min-microvolt = <3300000>; |
400 | regulator-max-microvolt = <3300000>; | 400 | regulator-max-microvolt = <3300000>; |
401 | regulator-boot-on; | 401 | regulator-boot-on; |
402 | regulator-always-on; | 402 | regulator-always-on; |
403 | }; | 403 | }; |
404 | 404 | ||
405 | /* REGEN1 is unused */ | 405 | /* REGEN1 is unused */ |
406 | 406 | ||
407 | regen2: regen2 { | 407 | regen2: regen2 { |
408 | /* Needed for PMIC internal resources */ | 408 | /* Needed for PMIC internal resources */ |
409 | regulator-name = "regen2"; | 409 | regulator-name = "regen2"; |
410 | regulator-boot-on; | 410 | regulator-boot-on; |
411 | regulator-always-on; | 411 | regulator-always-on; |
412 | }; | 412 | }; |
413 | 413 | ||
414 | /* REGEN3 is unused */ | 414 | /* REGEN3 is unused */ |
415 | 415 | ||
416 | sysen1: sysen1 { | 416 | sysen1: sysen1 { |
417 | /* PMIC_REGEN_3V3 */ | 417 | /* PMIC_REGEN_3V3 */ |
418 | regulator-name = "sysen1"; | 418 | regulator-name = "sysen1"; |
419 | regulator-boot-on; | 419 | regulator-boot-on; |
420 | regulator-always-on; | 420 | regulator-always-on; |
421 | }; | 421 | }; |
422 | 422 | ||
423 | sysen2: sysen2 { | 423 | sysen2: sysen2 { |
424 | /* PMIC_REGEN_DDR */ | 424 | /* PMIC_REGEN_DDR */ |
425 | regulator-name = "sysen2"; | 425 | regulator-name = "sysen2"; |
426 | regulator-boot-on; | 426 | regulator-boot-on; |
427 | regulator-always-on; | 427 | regulator-always-on; |
428 | }; | 428 | }; |
429 | }; | 429 | }; |
430 | }; | 430 | }; |
431 | }; | 431 | }; |
432 | 432 | ||
433 | pcf_lcd: gpio@20 { | 433 | pcf_lcd: gpio@20 { |
434 | compatible = "nxp,pcf8575"; | 434 | compatible = "nxp,pcf8575"; |
435 | reg = <0x20>; | 435 | reg = <0x20>; |
436 | gpio-controller; | 436 | gpio-controller; |
437 | #gpio-cells = <2>; | 437 | #gpio-cells = <2>; |
438 | }; | 438 | }; |
439 | 439 | ||
440 | pcf_gpio_21: gpio@21 { | 440 | pcf_gpio_21: gpio@21 { |
441 | compatible = "nxp,pcf8575"; | 441 | compatible = "nxp,pcf8575"; |
442 | reg = <0x21>; | 442 | reg = <0x21>; |
443 | lines-initial-states = <0x1408>; | 443 | lines-initial-states = <0x1408>; |
444 | gpio-controller; | 444 | gpio-controller; |
445 | #gpio-cells = <2>; | 445 | #gpio-cells = <2>; |
446 | interrupt-parent = <&gpio6>; | 446 | interrupt-parent = <&gpio6>; |
447 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; | 447 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; |
448 | interrupt-controller; | 448 | interrupt-controller; |
449 | #interrupt-cells = <2>; | 449 | #interrupt-cells = <2>; |
450 | }; | 450 | }; |
451 | 451 | ||
452 | mxt244: touchscreen@4a { | 452 | mxt244: touchscreen@4a { |
453 | compatible = "atmel,mXT244"; | 453 | compatible = "atmel,mXT244"; |
454 | status = "okay"; | 454 | status = "okay"; |
455 | reg = <0x4a>; | 455 | reg = <0x4a>; |
456 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | 456 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
457 | 457 | ||
458 | atmel,config = < | 458 | atmel,config = < |
459 | /* MXT244_GEN_COMMAND(6) */ | 459 | /* MXT244_GEN_COMMAND(6) */ |
460 | 0x00 0x00 0x00 0x00 0x00 0x00 | 460 | 0x00 0x00 0x00 0x00 0x00 0x00 |
461 | /* MXT244_GEN_POWER(7) */ | 461 | /* MXT244_GEN_POWER(7) */ |
462 | 0x20 0xff 0x32 | 462 | 0x20 0xff 0x32 |
463 | /* MXT244_GEN_ACQUIRE(8) */ | 463 | /* MXT244_GEN_ACQUIRE(8) */ |
464 | 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23 | 464 | 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23 |
465 | /* MXT244_TOUCH_MULTI(9) */ | 465 | /* MXT244_TOUCH_MULTI(9) */ |
466 | 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00 | 466 | 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00 |
467 | 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00 | 467 | 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00 |
468 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 468 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
469 | 0x00 | 469 | 0x00 |
470 | /* MXT244_TOUCH_KEYARRAY(15) */ | 470 | /* MXT244_TOUCH_KEYARRAY(15) */ |
471 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 471 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
472 | 0x00 | 472 | 0x00 |
473 | /* MXT244_COMMSCONFIG_T18(2) */ | 473 | /* MXT244_COMMSCONFIG_T18(2) */ |
474 | 0x00 0x00 | 474 | 0x00 0x00 |
475 | /* MXT244_SPT_GPIOPWM(19) */ | 475 | /* MXT244_SPT_GPIOPWM(19) */ |
476 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 476 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
477 | 0x00 0x00 0x00 0x00 0x00 0x00 | 477 | 0x00 0x00 0x00 0x00 0x00 0x00 |
478 | /* MXT244_PROCI_GRIPFACE(20) */ | 478 | /* MXT244_PROCI_GRIPFACE(20) */ |
479 | 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04 | 479 | 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04 |
480 | 0x0f 0x0a | 480 | 0x0f 0x0a |
481 | /* MXT244_PROCG_NOISE(22) */ | 481 | /* MXT244_PROCG_NOISE(22) */ |
482 | 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00 | 482 | 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00 |
483 | 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03 | 483 | 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03 |
484 | /* MXT244_TOUCH_PROXIMITY(23) */ | 484 | /* MXT244_TOUCH_PROXIMITY(23) */ |
485 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 485 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
486 | 0x00 0x00 0x00 0x00 0x00 | 486 | 0x00 0x00 0x00 0x00 0x00 |
487 | /* MXT244_PROCI_ONETOUCH(24) */ | 487 | /* MXT244_PROCI_ONETOUCH(24) */ |
488 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 488 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
489 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 489 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
490 | /* MXT244_SPT_SELFTEST(25) */ | 490 | /* MXT244_SPT_SELFTEST(25) */ |
491 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 491 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
492 | 0x00 0x00 0x00 0x00 | 492 | 0x00 0x00 0x00 0x00 |
493 | /* MXT244_PROCI_TWOTOUCH(27) */ | 493 | /* MXT244_PROCI_TWOTOUCH(27) */ |
494 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 494 | 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
495 | /* MXT244_SPT_CTECONFIG(28) */ | 495 | /* MXT244_SPT_CTECONFIG(28) */ |
496 | 0x00 0x00 0x02 0x08 0x10 0x00 | 496 | 0x00 0x00 0x02 0x08 0x10 0x00 |
497 | >; | 497 | >; |
498 | 498 | ||
499 | atmel,x_line = <18>; | 499 | atmel,x_line = <18>; |
500 | atmel,y_line = <12>; | 500 | atmel,y_line = <12>; |
501 | atmel,x_size = <800>; | 501 | atmel,x_size = <800>; |
502 | atmel,y_size = <480>; | 502 | atmel,y_size = <480>; |
503 | atmel,blen = <0x01>; | 503 | atmel,blen = <0x01>; |
504 | atmel,threshold = <30>; | 504 | atmel,threshold = <30>; |
505 | atmel,voltage = <2800000>; | 505 | atmel,voltage = <2800000>; |
506 | atmel,orient = <0x4>; | 506 | atmel,orient = <0x4>; |
507 | }; | 507 | }; |
508 | 508 | ||
509 | tlv320aic3106: tlv320aic3106@18 { | 509 | tlv320aic3106: tlv320aic3106@18 { |
510 | compatible = "ti,tlv320aic3106"; | 510 | compatible = "ti,tlv320aic3106"; |
511 | reg = <0x18>; | 511 | reg = <0x18>; |
512 | adc-settle-ms = <40>; | 512 | adc-settle-ms = <40>; |
513 | ai3x-micbias-vg = <1>; /* 2.0V */ | 513 | ai3x-micbias-vg = <1>; /* 2.0V */ |
514 | status = "okay"; | 514 | status = "okay"; |
515 | 515 | ||
516 | /* Regulators */ | 516 | /* Regulators */ |
517 | AVDD-supply = <&evm_3v3_sw>; | 517 | AVDD-supply = <&evm_3v3_sw>; |
518 | IOVDD-supply = <&evm_3v3_sw>; | 518 | IOVDD-supply = <&evm_3v3_sw>; |
519 | DRVDD-supply = <&evm_3v3_sw>; | 519 | DRVDD-supply = <&evm_3v3_sw>; |
520 | DVDD-supply = <&aic_dvdd>; | 520 | DVDD-supply = <&aic_dvdd>; |
521 | }; | 521 | }; |
522 | }; | 522 | }; |
523 | 523 | ||
524 | &i2c2 { | 524 | &i2c2 { |
525 | status = "okay"; | 525 | status = "okay"; |
526 | clock-frequency = <400000>; | 526 | clock-frequency = <400000>; |
527 | 527 | ||
528 | pcf_hdmi: gpio@26 { | 528 | pcf_hdmi: gpio@26 { |
529 | compatible = "nxp,pcf8575"; | 529 | compatible = "nxp,pcf8575"; |
530 | reg = <0x26>; | 530 | reg = <0x26>; |
531 | lines-initial-states = <0xffeb>; | 531 | lines-initial-states = <0xffeb>; |
532 | gpio-controller; | 532 | gpio-controller; |
533 | #gpio-cells = <2>; | 533 | #gpio-cells = <2>; |
534 | }; | 534 | }; |
535 | }; | 535 | }; |
536 | 536 | ||
537 | &i2c3 { | 537 | &i2c3 { |
538 | status = "okay"; | 538 | status = "okay"; |
539 | clock-frequency = <3400000>; | 539 | clock-frequency = <3400000>; |
540 | }; | 540 | }; |
541 | 541 | ||
542 | &mcspi1 { | 542 | &mcspi1 { |
543 | status = "okay"; | 543 | status = "okay"; |
544 | }; | 544 | }; |
545 | 545 | ||
546 | &mcspi2 { | 546 | &mcspi2 { |
547 | status = "okay"; | 547 | status = "okay"; |
548 | }; | 548 | }; |
549 | 549 | ||
550 | &uart1 { | 550 | &uart1 { |
551 | status = "okay"; | 551 | status = "okay"; |
552 | interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH | 552 | interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH |
553 | &dra7_pmx_core 0x3e0>; | 553 | &dra7_pmx_core 0x3e0>; |
554 | }; | 554 | }; |
555 | 555 | ||
556 | &uart2 { | 556 | &uart2 { |
557 | status = "okay"; | 557 | status = "okay"; |
558 | }; | 558 | }; |
559 | 559 | ||
560 | &uart3 { | 560 | &uart3 { |
561 | status = "okay"; | 561 | status = "okay"; |
562 | gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>; | 562 | gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>; |
563 | }; | 563 | }; |
564 | 564 | ||
565 | &mmc1 { | 565 | &mmc1 { |
566 | status = "okay"; | 566 | status = "okay"; |
567 | pbias-supply = <&pbias_mmc_reg>; | 567 | pbias-supply = <&pbias_mmc_reg>; |
568 | vmmc-supply = <&evm_3v3_sd>; | 568 | vmmc-supply = <&evm_3v3_sd>; |
569 | vmmc_aux-supply = <&ldo1_reg>; | 569 | vmmc_aux-supply = <&ldo1_reg>; |
570 | bus-width = <4>; | 570 | bus-width = <4>; |
571 | /* | 571 | /* |
572 | * SDCD signal is not being used here - using the fact that GPIO mode | 572 | * SDCD signal is not being used here - using the fact that GPIO mode |
573 | * is always hardwired. | 573 | * is always hardwired. |
574 | */ | 574 | */ |
575 | cd-gpios = <&gpio6 27 0>; | 575 | cd-gpios = <&gpio6 27 0>; |
576 | pinctrl-names = "default", "hs"; | 576 | pinctrl-names = "default", "hs"; |
577 | pinctrl-0 = <&mmc1_pins_default>; | 577 | pinctrl-0 = <&mmc1_pins_default>; |
578 | pinctrl-1 = <&mmc1_pins_hs>; | 578 | pinctrl-1 = <&mmc1_pins_hs>; |
579 | }; | 579 | }; |
580 | 580 | ||
581 | &mmc2 { | 581 | &mmc2 { |
582 | status = "okay"; | 582 | status = "okay"; |
583 | vmmc-supply = <&evm_3v3_sw>; | 583 | vmmc-supply = <&evm_3v3_sw>; |
584 | bus-width = <8>; | 584 | bus-width = <8>; |
585 | pinctrl-names = "default", "hs"; | 585 | pinctrl-names = "default", "hs"; |
586 | pinctrl-0 = <&mmc2_pins_default>; | 586 | pinctrl-0 = <&mmc2_pins_default>; |
587 | pinctrl-1 = <&mmc2_pins_hs>; | 587 | pinctrl-1 = <&mmc2_pins_hs>; |
588 | }; | 588 | }; |
589 | 589 | ||
590 | &mmc4 { | 590 | &mmc4 { |
591 | status = "okay"; | 591 | status = "okay"; |
592 | vmmc-supply = <&vmmcwl_fixed>; | 592 | vmmc-supply = <&vmmcwl_fixed>; |
593 | bus-width = <4>; | 593 | bus-width = <4>; |
594 | pinctrl-names = "default"; | 594 | pinctrl-names = "default"; |
595 | pinctrl-0 = <&wlan_pins &wlirq_pins>; | 595 | pinctrl-0 = <&wlan_pins &wlirq_pins>; |
596 | cap-power-off-card; | 596 | cap-power-off-card; |
597 | keep-power-in-suspend; | 597 | keep-power-in-suspend; |
598 | ti,non-removable; | 598 | ti,non-removable; |
599 | 599 | ||
600 | #address-cells = <1>; | 600 | #address-cells = <1>; |
601 | #size-cells = <0>; | 601 | #size-cells = <0>; |
602 | wlcore: wlcore@0 { | 602 | wlcore: wlcore@0 { |
603 | compatible = "ti,wlcore"; | 603 | compatible = "ti,wlcore"; |
604 | reg = <2>; | 604 | reg = <2>; |
605 | interrupt-parent = <&gpio5>; | 605 | interrupt-parent = <&gpio5>; |
606 | interrupts = <7 IRQ_TYPE_NONE>; | 606 | interrupts = <7 IRQ_TYPE_NONE>; |
607 | }; | 607 | }; |
608 | }; | 608 | }; |
609 | 609 | ||
610 | &cpu0 { | 610 | &cpu0 { |
611 | cpu0-voltdm = <&voltdm_mpu>; | 611 | cpu0-voltdm = <&voltdm_mpu>; |
612 | voltage-tolerance = <1>; | 612 | voltage-tolerance = <1>; |
613 | }; | 613 | }; |
614 | 614 | ||
615 | &voltdm_mpu { | 615 | &voltdm_mpu { |
616 | vdd-supply = <&smps123_reg>; | 616 | vdd-supply = <&smps123_reg>; |
617 | }; | 617 | }; |
618 | 618 | ||
619 | &voltdm_dspeve { | 619 | &voltdm_dspeve { |
620 | vdd-supply = <&smps45_reg>; | 620 | vdd-supply = <&smps45_reg>; |
621 | }; | 621 | }; |
622 | 622 | ||
623 | &voltdm_gpu { | 623 | &voltdm_gpu { |
624 | vdd-supply = <&smps6_reg>; | 624 | vdd-supply = <&smps6_reg>; |
625 | }; | 625 | }; |
626 | 626 | ||
627 | &voltdm_ivahd { | 627 | &voltdm_ivahd { |
628 | vdd-supply = <&smps8_reg>; | 628 | vdd-supply = <&smps8_reg>; |
629 | }; | 629 | }; |
630 | 630 | ||
631 | &voltdm_core { | 631 | &voltdm_core { |
632 | vdd-supply = <&smps7_reg>; | 632 | vdd-supply = <&smps7_reg>; |
633 | }; | 633 | }; |
634 | 634 | ||
635 | &qspi { | 635 | &qspi { |
636 | status = "okay"; | 636 | status = "okay"; |
637 | 637 | ||
638 | spi-max-frequency = <48000000>; | 638 | spi-max-frequency = <48000000>; |
639 | m25p80@0 { | 639 | m25p80@0 { |
640 | compatible = "s25fl256s1"; | 640 | compatible = "s25fl256s1"; |
641 | spi-max-frequency = <48000000>; | 641 | spi-max-frequency = <48000000>; |
642 | reg = <0>; | 642 | reg = <0>; |
643 | spi-tx-bus-width = <1>; | 643 | spi-tx-bus-width = <1>; |
644 | spi-rx-bus-width = <4>; | 644 | spi-rx-bus-width = <4>; |
645 | spi-cpol; | 645 | spi-cpol; |
646 | spi-cpha; | 646 | spi-cpha; |
647 | #address-cells = <1>; | 647 | #address-cells = <1>; |
648 | #size-cells = <1>; | 648 | #size-cells = <1>; |
649 | 649 | ||
650 | /* MTD partition table. | 650 | /* MTD partition table. |
651 | * The ROM checks the first four physical blocks | 651 | * The ROM checks the first four physical blocks |
652 | * for a valid file to boot and the flash here is | 652 | * for a valid file to boot and the flash here is |
653 | * 64KiB block size. | 653 | * 64KiB block size. |
654 | */ | 654 | */ |
655 | partition@0 { | 655 | partition@0 { |
656 | label = "QSPI.SPL"; | 656 | label = "QSPI.SPL"; |
657 | reg = <0x00000000 0x000010000>; | 657 | reg = <0x00000000 0x000010000>; |
658 | }; | 658 | }; |
659 | partition@1 { | 659 | partition@1 { |
660 | label = "QSPI.SPL.backup1"; | 660 | label = "QSPI.SPL.backup1"; |
661 | reg = <0x00010000 0x00010000>; | 661 | reg = <0x00010000 0x00010000>; |
662 | }; | 662 | }; |
663 | partition@2 { | 663 | partition@2 { |
664 | label = "QSPI.SPL.backup2"; | 664 | label = "QSPI.SPL.backup2"; |
665 | reg = <0x00020000 0x00010000>; | 665 | reg = <0x00020000 0x00010000>; |
666 | }; | 666 | }; |
667 | partition@3 { | 667 | partition@3 { |
668 | label = "QSPI.SPL.backup3"; | 668 | label = "QSPI.SPL.backup3"; |
669 | reg = <0x00030000 0x00010000>; | 669 | reg = <0x00030000 0x00010000>; |
670 | }; | 670 | }; |
671 | partition@4 { | 671 | partition@4 { |
672 | label = "QSPI.u-boot"; | 672 | label = "QSPI.u-boot"; |
673 | reg = <0x00040000 0x00100000>; | 673 | reg = <0x00040000 0x00100000>; |
674 | }; | 674 | }; |
675 | partition@5 { | 675 | partition@5 { |
676 | label = "QSPI.u-boot-spl-os"; | 676 | label = "QSPI.u-boot-spl-os"; |
677 | reg = <0x00140000 0x00080000>; | 677 | reg = <0x00140000 0x00080000>; |
678 | }; | 678 | }; |
679 | partition@6 { | 679 | partition@6 { |
680 | label = "QSPI.u-boot-env"; | 680 | label = "QSPI.u-boot-env"; |
681 | reg = <0x001c0000 0x00010000>; | 681 | reg = <0x001c0000 0x00010000>; |
682 | }; | 682 | }; |
683 | partition@7 { | 683 | partition@7 { |
684 | label = "QSPI.u-boot-env.backup1"; | 684 | label = "QSPI.u-boot-env.backup1"; |
685 | reg = <0x001d0000 0x0010000>; | 685 | reg = <0x001d0000 0x0010000>; |
686 | }; | 686 | }; |
687 | partition@8 { | 687 | partition@8 { |
688 | label = "QSPI.kernel"; | 688 | label = "QSPI.kernel"; |
689 | reg = <0x001e0000 0x0800000>; | 689 | reg = <0x001e0000 0x0800000>; |
690 | }; | 690 | }; |
691 | partition@9 { | 691 | partition@9 { |
692 | label = "QSPI.file-system"; | 692 | label = "QSPI.file-system"; |
693 | reg = <0x009e0000 0x01620000>; | 693 | reg = <0x009e0000 0x01620000>; |
694 | }; | 694 | }; |
695 | }; | 695 | }; |
696 | }; | 696 | }; |
697 | 697 | ||
698 | &omap_dwc3_1 { | 698 | &omap_dwc3_1 { |
699 | extcon = <&extcon_usb1>; | 699 | extcon = <&extcon_usb1>; |
700 | }; | 700 | }; |
701 | 701 | ||
702 | &omap_dwc3_2 { | 702 | &omap_dwc3_2 { |
703 | extcon = <&extcon_usb2>; | 703 | extcon = <&extcon_usb2>; |
704 | }; | 704 | }; |
705 | 705 | ||
706 | &usb1 { | 706 | &usb1 { |
707 | dr_mode = "otg"; | 707 | dr_mode = "otg"; |
708 | }; | 708 | }; |
709 | 709 | ||
710 | &usb2 { | 710 | &usb2 { |
711 | dr_mode = "host"; | 711 | dr_mode = "host"; |
712 | }; | 712 | }; |
713 | 713 | ||
714 | &mac { | 714 | &mac { |
715 | status = "okay"; | 715 | status = "okay"; |
716 | dual_emac; | 716 | dual_emac; |
717 | ti,no-idle; | ||
717 | }; | 718 | }; |
718 | 719 | ||
719 | &cpsw_emac0 { | 720 | &cpsw_emac0 { |
720 | phy_id = <&davinci_mdio>, <2>; | 721 | phy_id = <&davinci_mdio>, <2>; |
721 | phy-mode = "rgmii"; | 722 | phy-mode = "rgmii"; |
722 | dual_emac_res_vlan = <1>; | 723 | dual_emac_res_vlan = <1>; |
723 | }; | 724 | }; |
724 | 725 | ||
725 | &cpsw_emac1 { | 726 | &cpsw_emac1 { |
726 | phy_id = <&davinci_mdio>, <3>; | 727 | phy_id = <&davinci_mdio>, <3>; |
727 | phy-mode = "rgmii"; | 728 | phy-mode = "rgmii"; |
728 | dual_emac_res_vlan = <2>; | 729 | dual_emac_res_vlan = <2>; |
729 | }; | 730 | }; |
730 | 731 | ||
731 | &elm { | 732 | &elm { |
732 | status = "okay"; | 733 | status = "okay"; |
733 | }; | 734 | }; |
734 | 735 | ||
735 | &gpmc { | 736 | &gpmc { |
736 | status = "disabled"; | 737 | status = "disabled"; |
737 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ | 738 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ |
738 | nand@0,0 { | 739 | nand@0,0 { |
739 | reg = <0 0 4>; /* device IO registers */ | 740 | reg = <0 0 4>; /* device IO registers */ |
740 | ti,nand-ecc-opt = "bch8"; | 741 | ti,nand-ecc-opt = "bch8"; |
741 | ti,elm-id = <&elm>; | 742 | ti,elm-id = <&elm>; |
742 | nand-bus-width = <16>; | 743 | nand-bus-width = <16>; |
743 | gpmc,device-width = <2>; | 744 | gpmc,device-width = <2>; |
744 | gpmc,sync-clk-ps = <0>; | 745 | gpmc,sync-clk-ps = <0>; |
745 | gpmc,cs-on-ns = <0>; | 746 | gpmc,cs-on-ns = <0>; |
746 | gpmc,cs-rd-off-ns = <80>; | 747 | gpmc,cs-rd-off-ns = <80>; |
747 | gpmc,cs-wr-off-ns = <80>; | 748 | gpmc,cs-wr-off-ns = <80>; |
748 | gpmc,adv-on-ns = <0>; | 749 | gpmc,adv-on-ns = <0>; |
749 | gpmc,adv-rd-off-ns = <60>; | 750 | gpmc,adv-rd-off-ns = <60>; |
750 | gpmc,adv-wr-off-ns = <60>; | 751 | gpmc,adv-wr-off-ns = <60>; |
751 | gpmc,we-on-ns = <10>; | 752 | gpmc,we-on-ns = <10>; |
752 | gpmc,we-off-ns = <50>; | 753 | gpmc,we-off-ns = <50>; |
753 | gpmc,oe-on-ns = <4>; | 754 | gpmc,oe-on-ns = <4>; |
754 | gpmc,oe-off-ns = <40>; | 755 | gpmc,oe-off-ns = <40>; |
755 | gpmc,access-ns = <40>; | 756 | gpmc,access-ns = <40>; |
756 | gpmc,wr-access-ns = <80>; | 757 | gpmc,wr-access-ns = <80>; |
757 | gpmc,rd-cycle-ns = <80>; | 758 | gpmc,rd-cycle-ns = <80>; |
758 | gpmc,wr-cycle-ns = <80>; | 759 | gpmc,wr-cycle-ns = <80>; |
759 | gpmc,bus-turnaround-ns = <0>; | 760 | gpmc,bus-turnaround-ns = <0>; |
760 | gpmc,cycle2cycle-delay-ns = <0>; | 761 | gpmc,cycle2cycle-delay-ns = <0>; |
761 | gpmc,clk-activation-ns = <0>; | 762 | gpmc,clk-activation-ns = <0>; |
762 | gpmc,wait-monitoring-ns = <0>; | 763 | gpmc,wait-monitoring-ns = <0>; |
763 | gpmc,wr-data-mux-bus-ns = <0>; | 764 | gpmc,wr-data-mux-bus-ns = <0>; |
764 | /* MTD partition table */ | 765 | /* MTD partition table */ |
765 | /* All SPL-* partitions are sized to minimal length | 766 | /* All SPL-* partitions are sized to minimal length |
766 | * which can be independently programmable. For | 767 | * which can be independently programmable. For |
767 | * NAND flash this is equal to size of erase-block */ | 768 | * NAND flash this is equal to size of erase-block */ |
768 | #address-cells = <1>; | 769 | #address-cells = <1>; |
769 | #size-cells = <1>; | 770 | #size-cells = <1>; |
770 | partition@0 { | 771 | partition@0 { |
771 | label = "NAND.SPL"; | 772 | label = "NAND.SPL"; |
772 | reg = <0x00000000 0x000020000>; | 773 | reg = <0x00000000 0x000020000>; |
773 | }; | 774 | }; |
774 | partition@1 { | 775 | partition@1 { |
775 | label = "NAND.SPL.backup1"; | 776 | label = "NAND.SPL.backup1"; |
776 | reg = <0x00020000 0x00020000>; | 777 | reg = <0x00020000 0x00020000>; |
777 | }; | 778 | }; |
778 | partition@2 { | 779 | partition@2 { |
779 | label = "NAND.SPL.backup2"; | 780 | label = "NAND.SPL.backup2"; |
780 | reg = <0x00040000 0x00020000>; | 781 | reg = <0x00040000 0x00020000>; |
781 | }; | 782 | }; |
782 | partition@3 { | 783 | partition@3 { |
783 | label = "NAND.SPL.backup3"; | 784 | label = "NAND.SPL.backup3"; |
784 | reg = <0x00060000 0x00020000>; | 785 | reg = <0x00060000 0x00020000>; |
785 | }; | 786 | }; |
786 | partition@4 { | 787 | partition@4 { |
787 | label = "NAND.u-boot-spl-os"; | 788 | label = "NAND.u-boot-spl-os"; |
788 | reg = <0x00080000 0x00040000>; | 789 | reg = <0x00080000 0x00040000>; |
789 | }; | 790 | }; |
790 | partition@5 { | 791 | partition@5 { |
791 | label = "NAND.u-boot"; | 792 | label = "NAND.u-boot"; |
792 | reg = <0x000c0000 0x00100000>; | 793 | reg = <0x000c0000 0x00100000>; |
793 | }; | 794 | }; |
794 | partition@6 { | 795 | partition@6 { |
795 | label = "NAND.u-boot-env"; | 796 | label = "NAND.u-boot-env"; |
796 | reg = <0x001c0000 0x00020000>; | 797 | reg = <0x001c0000 0x00020000>; |
797 | }; | 798 | }; |
798 | partition@7 { | 799 | partition@7 { |
799 | label = "NAND.u-boot-env.backup1"; | 800 | label = "NAND.u-boot-env.backup1"; |
800 | reg = <0x001e0000 0x00020000>; | 801 | reg = <0x001e0000 0x00020000>; |
801 | }; | 802 | }; |
802 | partition@8 { | 803 | partition@8 { |
803 | label = "NAND.kernel"; | 804 | label = "NAND.kernel"; |
804 | reg = <0x00200000 0x00800000>; | 805 | reg = <0x00200000 0x00800000>; |
805 | }; | 806 | }; |
806 | partition@9 { | 807 | partition@9 { |
807 | label = "NAND.file-system"; | 808 | label = "NAND.file-system"; |
808 | reg = <0x00a00000 0x0f600000>; | 809 | reg = <0x00a00000 0x0f600000>; |
809 | }; | 810 | }; |
810 | }; | 811 | }; |
811 | }; | 812 | }; |
812 | 813 | ||
813 | &gpio7 { | 814 | &gpio7 { |
814 | ti,no-reset-on-init; | 815 | ti,no-reset-on-init; |
815 | ti,no-idle-on-init; | 816 | ti,no-idle-on-init; |
816 | }; | 817 | }; |
817 | 818 | ||
818 | &dss { | 819 | &dss { |
819 | status = "ok"; | 820 | status = "ok"; |
820 | 821 | ||
821 | vdda_video-supply = <&ldoln_reg>; | 822 | vdda_video-supply = <&ldoln_reg>; |
822 | }; | 823 | }; |
823 | 824 | ||
824 | &hdmi { | 825 | &hdmi { |
825 | status = "ok"; | 826 | status = "ok"; |
826 | vdda-supply = <&ldo3_reg>; | 827 | vdda-supply = <&ldo3_reg>; |
827 | 828 | ||
828 | port { | 829 | port { |
829 | hdmi_out: endpoint { | 830 | hdmi_out: endpoint { |
830 | remote-endpoint = <&tpd12s015_in>; | 831 | remote-endpoint = <&tpd12s015_in>; |
831 | }; | 832 | }; |
832 | }; | 833 | }; |
833 | }; | 834 | }; |
834 | 835 | ||
835 | &dcan1 { | 836 | &dcan1 { |
836 | status = "ok"; | 837 | status = "ok"; |
837 | pinctrl-names = "default", "sleep"; | 838 | pinctrl-names = "default", "sleep"; |
838 | pinctrl-0 = <&dcan1_pins_default>; | 839 | pinctrl-0 = <&dcan1_pins_default>; |
839 | pinctrl-1 = <&dcan1_pins_sleep>; | 840 | pinctrl-1 = <&dcan1_pins_sleep>; |
840 | }; | 841 | }; |
841 | 842 | ||
842 | &mailbox5 { | 843 | &mailbox5 { |
843 | status = "okay"; | 844 | status = "okay"; |
844 | mbox_ipu1_legacy: mbox_ipu1_legacy { | 845 | mbox_ipu1_legacy: mbox_ipu1_legacy { |
845 | status = "okay"; | 846 | status = "okay"; |
846 | }; | 847 | }; |
847 | mbox_dsp1_legacy: mbox_dsp1_legacy { | 848 | mbox_dsp1_legacy: mbox_dsp1_legacy { |
848 | status = "okay"; | 849 | status = "okay"; |
849 | }; | 850 | }; |
850 | }; | 851 | }; |
851 | 852 | ||
852 | &mailbox6 { | 853 | &mailbox6 { |
853 | status = "okay"; | 854 | status = "okay"; |
854 | mbox_ipu2_legacy: mbox_ipu2_legacy { | 855 | mbox_ipu2_legacy: mbox_ipu2_legacy { |
855 | status = "okay"; | 856 | status = "okay"; |
856 | }; | 857 | }; |
857 | mbox_dsp2_legacy: mbox_dsp2_legacy { | 858 | mbox_dsp2_legacy: mbox_dsp2_legacy { |
858 | status = "okay"; | 859 | status = "okay"; |
859 | }; | 860 | }; |
860 | }; | 861 | }; |
861 | 862 | ||
862 | &mmu0_dsp1 { | 863 | &mmu0_dsp1 { |
863 | status = "okay"; | 864 | status = "okay"; |
864 | }; | 865 | }; |
865 | 866 | ||
866 | &mmu1_dsp1 { | 867 | &mmu1_dsp1 { |
867 | status = "okay"; | 868 | status = "okay"; |
868 | }; | 869 | }; |
869 | 870 | ||
870 | &mmu0_dsp2 { | 871 | &mmu0_dsp2 { |
871 | status = "okay"; | 872 | status = "okay"; |
872 | }; | 873 | }; |
873 | 874 | ||
874 | &mmu1_dsp2 { | 875 | &mmu1_dsp2 { |
875 | status = "okay"; | 876 | status = "okay"; |
876 | }; | 877 | }; |
877 | 878 | ||
878 | &mmu_ipu1 { | 879 | &mmu_ipu1 { |
879 | status = "okay"; | 880 | status = "okay"; |
880 | }; | 881 | }; |
881 | 882 | ||
882 | &mmu_ipu2 { | 883 | &mmu_ipu2 { |
883 | status = "okay"; | 884 | status = "okay"; |
884 | }; | 885 | }; |
885 | 886 | ||
886 | &ipu2 { | 887 | &ipu2 { |
887 | status = "okay"; | 888 | status = "okay"; |
888 | memory-region = <&ipu2_cma_pool>; | 889 | memory-region = <&ipu2_cma_pool>; |
889 | mboxes = <&mailbox6 &mbox_ipu2_legacy>; | 890 | mboxes = <&mailbox6 &mbox_ipu2_legacy>; |
890 | timers = <&timer3>; | 891 | timers = <&timer3>; |
891 | watchdog-timers = <&timer4>, <&timer9>; | 892 | watchdog-timers = <&timer4>, <&timer9>; |
892 | }; | 893 | }; |
893 | 894 | ||
894 | &ipu1 { | 895 | &ipu1 { |
895 | status = "okay"; | 896 | status = "okay"; |
896 | memory-region = <&ipu1_cma_pool>; | 897 | memory-region = <&ipu1_cma_pool>; |
897 | mboxes = <&mailbox5 &mbox_ipu1_legacy>; | 898 | mboxes = <&mailbox5 &mbox_ipu1_legacy>; |
898 | timers = <&timer11>; | 899 | timers = <&timer11>; |
899 | }; | 900 | }; |
900 | 901 | ||
901 | &dsp1 { | 902 | &dsp1 { |
902 | status = "okay"; | 903 | status = "okay"; |
903 | memory-region = <&dsp1_cma_pool>; | 904 | memory-region = <&dsp1_cma_pool>; |
904 | mboxes = <&mailbox5 &mbox_dsp1_legacy>; | 905 | mboxes = <&mailbox5 &mbox_dsp1_legacy>; |
905 | timers = <&timer5>; | 906 | timers = <&timer5>; |
906 | }; | 907 | }; |
907 | 908 | ||
908 | &dsp2 { | 909 | &dsp2 { |
909 | status = "okay"; | 910 | status = "okay"; |
910 | memory-region = <&dsp2_cma_pool>; | 911 | memory-region = <&dsp2_cma_pool>; |
911 | mboxes = <&mailbox6 &mbox_dsp2_legacy>; | 912 | mboxes = <&mailbox6 &mbox_dsp2_legacy>; |
912 | timers = <&timer6>; | 913 | timers = <&timer6>; |
913 | }; | 914 | }; |
914 | 915 | ||
915 | &atl { | 916 | &atl { |
916 | status = "okay"; | 917 | status = "okay"; |
917 | 918 | ||
918 | atl2 { | 919 | atl2 { |
919 | bws = <DRA7_ATL_WS_MCASP2_FSX>; | 920 | bws = <DRA7_ATL_WS_MCASP2_FSX>; |
920 | aws = <DRA7_ATL_WS_MCASP3_FSX>; | 921 | aws = <DRA7_ATL_WS_MCASP3_FSX>; |
921 | }; | 922 | }; |
922 | }; | 923 | }; |
923 | 924 | ||
924 | &mcasp3 { | 925 | &mcasp3 { |
925 | fck_parent = "atl_clkin2_ck"; | 926 | fck_parent = "atl_clkin2_ck"; |
926 | 927 | ||
927 | status = "okay"; | 928 | status = "okay"; |
928 | 929 | ||
929 | op-mode = <0>; /* MCASP_IIS_MODE */ | 930 | op-mode = <0>; /* MCASP_IIS_MODE */ |
930 | tdm-slots = <2>; | 931 | tdm-slots = <2>; |
931 | /* 4 serializer */ | 932 | /* 4 serializer */ |
932 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | 933 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
933 | 1 2 0 0 | 934 | 1 2 0 0 |
934 | >; | 935 | >; |
935 | }; | 936 | }; |
936 | 937 | ||
937 | &usb2_phy1 { | 938 | &usb2_phy1 { |
938 | phy-supply = <&ldousb_reg>; | 939 | phy-supply = <&ldousb_reg>; |
939 | }; | 940 | }; |
940 | 941 | ||
941 | &usb2_phy2 { | 942 | &usb2_phy2 { |
942 | phy-supply = <&ldousb_reg>; | 943 | phy-supply = <&ldousb_reg>; |
943 | }; | 944 | }; |
944 | 945 |
arch/arm/boot/dts/dra72-evm.dts
1 | /* | 1 | /* |
2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
7 | */ | 7 | */ |
8 | /dts-v1/; | 8 | /dts-v1/; |
9 | 9 | ||
10 | #include "dra72x.dtsi" | 10 | #include "dra72x.dtsi" |
11 | #include <dt-bindings/gpio/gpio.h> | 11 | #include <dt-bindings/gpio/gpio.h> |
12 | #include <dt-bindings/clk/ti-dra7-atl.h> | 12 | #include <dt-bindings/clk/ti-dra7-atl.h> |
13 | 13 | ||
14 | / { | 14 | / { |
15 | model = "TI DRA722"; | 15 | model = "TI DRA722"; |
16 | compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; | 16 | compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; |
17 | 17 | ||
18 | aliases { | 18 | aliases { |
19 | display0 = &hdmi0; | 19 | display0 = &hdmi0; |
20 | sound0 = &primary_sound; | 20 | sound0 = &primary_sound; |
21 | sound1 = &hdmi; | 21 | sound1 = &hdmi; |
22 | }; | 22 | }; |
23 | 23 | ||
24 | memory { | 24 | memory { |
25 | device_type = "memory"; | 25 | device_type = "memory"; |
26 | reg = <0x80000000 0x40000000>; /* 1024 MB */ | 26 | reg = <0x80000000 0x40000000>; /* 1024 MB */ |
27 | }; | 27 | }; |
28 | 28 | ||
29 | tpd12s015: encoder@0 { | 29 | tpd12s015: encoder@0 { |
30 | compatible = "ti,tpd12s015"; | 30 | compatible = "ti,tpd12s015"; |
31 | 31 | ||
32 | pinctrl-names = "default"; | 32 | pinctrl-names = "default"; |
33 | pinctrl-0 = <&hpd_pin>; | 33 | pinctrl-0 = <&hpd_pin>; |
34 | 34 | ||
35 | gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ | 35 | gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ |
36 | <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ | 36 | <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ |
37 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ | 37 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ |
38 | 38 | ||
39 | ports { | 39 | ports { |
40 | #address-cells = <1>; | 40 | #address-cells = <1>; |
41 | #size-cells = <0>; | 41 | #size-cells = <0>; |
42 | 42 | ||
43 | port@0 { | 43 | port@0 { |
44 | reg = <0>; | 44 | reg = <0>; |
45 | 45 | ||
46 | tpd12s015_in: endpoint@0 { | 46 | tpd12s015_in: endpoint@0 { |
47 | remote-endpoint = <&hdmi_out>; | 47 | remote-endpoint = <&hdmi_out>; |
48 | }; | 48 | }; |
49 | }; | 49 | }; |
50 | 50 | ||
51 | port@1 { | 51 | port@1 { |
52 | reg = <1>; | 52 | reg = <1>; |
53 | 53 | ||
54 | tpd12s015_out: endpoint@0 { | 54 | tpd12s015_out: endpoint@0 { |
55 | remote-endpoint = <&hdmi_connector_in>; | 55 | remote-endpoint = <&hdmi_connector_in>; |
56 | }; | 56 | }; |
57 | }; | 57 | }; |
58 | }; | 58 | }; |
59 | }; | 59 | }; |
60 | 60 | ||
61 | hdmi0: connector@0 { | 61 | hdmi0: connector@0 { |
62 | compatible = "hdmi-connector"; | 62 | compatible = "hdmi-connector"; |
63 | label = "hdmi"; | 63 | label = "hdmi"; |
64 | 64 | ||
65 | type = "a"; | 65 | type = "a"; |
66 | 66 | ||
67 | port { | 67 | port { |
68 | hdmi_connector_in: endpoint { | 68 | hdmi_connector_in: endpoint { |
69 | remote-endpoint = <&tpd12s015_out>; | 69 | remote-endpoint = <&tpd12s015_out>; |
70 | }; | 70 | }; |
71 | }; | 71 | }; |
72 | }; | 72 | }; |
73 | 73 | ||
74 | reserved-memory { | 74 | reserved-memory { |
75 | #address-cells = <1>; | 75 | #address-cells = <1>; |
76 | #size-cells = <1>; | 76 | #size-cells = <1>; |
77 | ranges; | 77 | ranges; |
78 | 78 | ||
79 | ipu2_cma_pool: ipu2_cma@95800000 { | 79 | ipu2_cma_pool: ipu2_cma@95800000 { |
80 | compatible = "shared-dma-pool"; | 80 | compatible = "shared-dma-pool"; |
81 | reg = <0x95800000 0x3800000>; | 81 | reg = <0x95800000 0x3800000>; |
82 | reusable; | 82 | reusable; |
83 | status = "okay"; | 83 | status = "okay"; |
84 | }; | 84 | }; |
85 | 85 | ||
86 | dsp1_cma_pool: dsp1_cma@99000000 { | 86 | dsp1_cma_pool: dsp1_cma@99000000 { |
87 | compatible = "shared-dma-pool"; | 87 | compatible = "shared-dma-pool"; |
88 | reg = <0x99000000 0x4000000>; | 88 | reg = <0x99000000 0x4000000>; |
89 | reusable; | 89 | reusable; |
90 | status = "okay"; | 90 | status = "okay"; |
91 | }; | 91 | }; |
92 | 92 | ||
93 | ipu1_cma_pool: ipu1_cma@9d000000 { | 93 | ipu1_cma_pool: ipu1_cma@9d000000 { |
94 | compatible = "shared-dma-pool"; | 94 | compatible = "shared-dma-pool"; |
95 | reg = <0x9d000000 0x2000000>; | 95 | reg = <0x9d000000 0x2000000>; |
96 | reusable; | 96 | reusable; |
97 | status = "okay"; | 97 | status = "okay"; |
98 | }; | 98 | }; |
99 | }; | 99 | }; |
100 | 100 | ||
101 | extcon_usb1: extcon_usb1 { | 101 | extcon_usb1: extcon_usb1 { |
102 | compatible = "linux,extcon-usb-gpio"; | 102 | compatible = "linux,extcon-usb-gpio"; |
103 | id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; | 103 | id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; |
104 | }; | 104 | }; |
105 | 105 | ||
106 | extcon_usb2: extcon_usb2 { | 106 | extcon_usb2: extcon_usb2 { |
107 | compatible = "linux,extcon-usb-gpio"; | 107 | compatible = "linux,extcon-usb-gpio"; |
108 | id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; | 108 | id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; |
109 | }; | 109 | }; |
110 | 110 | ||
111 | evm_3v3_sd: fixedregulator-sd { | 111 | evm_3v3_sd: fixedregulator-sd { |
112 | compatible = "regulator-fixed"; | 112 | compatible = "regulator-fixed"; |
113 | regulator-name = "evm_3v3_sd"; | 113 | regulator-name = "evm_3v3_sd"; |
114 | regulator-min-microvolt = <3300000>; | 114 | regulator-min-microvolt = <3300000>; |
115 | regulator-max-microvolt = <3300000>; | 115 | regulator-max-microvolt = <3300000>; |
116 | enable-active-high; | 116 | enable-active-high; |
117 | gpio = <&pcf_gpio_21 5 0>; | 117 | gpio = <&pcf_gpio_21 5 0>; |
118 | }; | 118 | }; |
119 | 119 | ||
120 | evm_3v3: fixedregulator-evm_3v3 { | 120 | evm_3v3: fixedregulator-evm_3v3 { |
121 | compatible = "regulator-fixed"; | 121 | compatible = "regulator-fixed"; |
122 | regulator-name = "evm_3v3"; | 122 | regulator-name = "evm_3v3"; |
123 | regulator-min-microvolt = <3300000>; | 123 | regulator-min-microvolt = <3300000>; |
124 | regulator-max-microvolt = <3300000>; | 124 | regulator-max-microvolt = <3300000>; |
125 | }; | 125 | }; |
126 | 126 | ||
127 | aic_dvdd: fixedregulator-aic_dvdd { | 127 | aic_dvdd: fixedregulator-aic_dvdd { |
128 | /* TPS77018DBVT */ | 128 | /* TPS77018DBVT */ |
129 | compatible = "regulator-fixed"; | 129 | compatible = "regulator-fixed"; |
130 | regulator-name = "aic_dvdd"; | 130 | regulator-name = "aic_dvdd"; |
131 | vin-supply = <&evm_3v3>; | 131 | vin-supply = <&evm_3v3>; |
132 | regulator-min-microvolt = <1800000>; | 132 | regulator-min-microvolt = <1800000>; |
133 | regulator-max-microvolt = <1800000>; | 133 | regulator-max-microvolt = <1800000>; |
134 | }; | 134 | }; |
135 | 135 | ||
136 | primary_sound: primary_sound { | 136 | primary_sound: primary_sound { |
137 | compatible = "ti,dra7xx-evm-audio"; | 137 | compatible = "ti,dra7xx-evm-audio"; |
138 | ti,model = "DRA7xx-EVM"; | 138 | ti,model = "DRA7xx-EVM"; |
139 | ti,audio-codec = <&tlv320aic3106>; | 139 | ti,audio-codec = <&tlv320aic3106>; |
140 | ti,mcasp-controller = <&mcasp3>; | 140 | ti,mcasp-controller = <&mcasp3>; |
141 | ti,codec-clock-rate = <5644800>; | 141 | ti,codec-clock-rate = <5644800>; |
142 | clocks = <&atl_clkin2_ck>; | 142 | clocks = <&atl_clkin2_ck>; |
143 | clock-names = "mclk"; | 143 | clock-names = "mclk"; |
144 | ti,audio-routing = | 144 | ti,audio-routing = |
145 | "Headphone Jack", "HPLOUT", | 145 | "Headphone Jack", "HPLOUT", |
146 | "Headphone Jack", "HPROUT", | 146 | "Headphone Jack", "HPROUT", |
147 | "Line Out", "LLOUT", | 147 | "Line Out", "LLOUT", |
148 | "Line Out", "RLOUT", | 148 | "Line Out", "RLOUT", |
149 | "MIC3L", "Mic Jack", | 149 | "MIC3L", "Mic Jack", |
150 | "MIC3R", "Mic Jack", | 150 | "MIC3R", "Mic Jack", |
151 | "Mic Jack", "Mic Bias", | 151 | "Mic Jack", "Mic Bias", |
152 | "LINE1L", "Line In", | 152 | "LINE1L", "Line In", |
153 | "LINE1R", "Line In"; | 153 | "LINE1R", "Line In"; |
154 | }; | 154 | }; |
155 | }; | 155 | }; |
156 | 156 | ||
157 | &dra7_pmx_core { | 157 | &dra7_pmx_core { |
158 | i2c1_pins: pinmux_i2c1_pins { | 158 | i2c1_pins: pinmux_i2c1_pins { |
159 | pinctrl-single,pins = < | 159 | pinctrl-single,pins = < |
160 | 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ | 160 | 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ |
161 | 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ | 161 | 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ |
162 | >; | 162 | >; |
163 | }; | 163 | }; |
164 | 164 | ||
165 | uart1_pins: pinmix_uart1_pins { | 165 | uart1_pins: pinmix_uart1_pins { |
166 | pinctrl-single,pins = < | 166 | pinctrl-single,pins = < |
167 | 0x3e0 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd */ | 167 | 0x3e0 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd */ |
168 | 0x3e4 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_txd */ | 168 | 0x3e4 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_txd */ |
169 | >; | 169 | >; |
170 | }; | 170 | }; |
171 | 171 | ||
172 | i2c2_pins: pinmux_i2c2_pins { | 172 | i2c2_pins: pinmux_i2c2_pins { |
173 | pinctrl-single,pins = < | 173 | pinctrl-single,pins = < |
174 | 0x408 (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_scl */ | 174 | 0x408 (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_scl */ |
175 | 0x40c (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_sda */ | 175 | 0x40c (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_sda */ |
176 | >; | 176 | >; |
177 | }; | 177 | }; |
178 | 178 | ||
179 | cpsw_default: cpsw_default { | 179 | cpsw_default: cpsw_default { |
180 | pinctrl-single,pins = < | 180 | pinctrl-single,pins = < |
181 | /* Slave 2 */ | 181 | /* Slave 2 */ |
182 | 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */ | 182 | 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */ |
183 | 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */ | 183 | 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */ |
184 | 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */ | 184 | 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */ |
185 | 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */ | 185 | 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */ |
186 | 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */ | 186 | 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */ |
187 | 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */ | 187 | 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */ |
188 | 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */ | 188 | 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */ |
189 | 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */ | 189 | 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */ |
190 | 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */ | 190 | 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */ |
191 | 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */ | 191 | 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */ |
192 | 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */ | 192 | 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */ |
193 | 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */ | 193 | 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */ |
194 | >; | 194 | >; |
195 | 195 | ||
196 | }; | 196 | }; |
197 | 197 | ||
198 | cpsw_sleep: cpsw_sleep { | 198 | cpsw_sleep: cpsw_sleep { |
199 | pinctrl-single,pins = < | 199 | pinctrl-single,pins = < |
200 | /* Slave 1 */ | 200 | /* Slave 1 */ |
201 | 0x198 (PIN_OFF_NONE) | 201 | 0x198 (PIN_OFF_NONE) |
202 | 0x19c (PIN_OFF_NONE) | 202 | 0x19c (PIN_OFF_NONE) |
203 | 0x1a0 (PIN_OFF_NONE) | 203 | 0x1a0 (PIN_OFF_NONE) |
204 | 0x1a4 (PIN_OFF_NONE) | 204 | 0x1a4 (PIN_OFF_NONE) |
205 | 0x1a8 (PIN_OFF_NONE) | 205 | 0x1a8 (PIN_OFF_NONE) |
206 | 0x1ac (PIN_OFF_NONE) | 206 | 0x1ac (PIN_OFF_NONE) |
207 | 0x1b0 (PIN_OFF_NONE) | 207 | 0x1b0 (PIN_OFF_NONE) |
208 | 0x1b4 (PIN_OFF_NONE) | 208 | 0x1b4 (PIN_OFF_NONE) |
209 | 0x1b8 (PIN_OFF_NONE) | 209 | 0x1b8 (PIN_OFF_NONE) |
210 | 0x1bc (PIN_OFF_NONE) | 210 | 0x1bc (PIN_OFF_NONE) |
211 | 0x1c0 (PIN_OFF_NONE) | 211 | 0x1c0 (PIN_OFF_NONE) |
212 | 0x1c4 (PIN_OFF_NONE) | 212 | 0x1c4 (PIN_OFF_NONE) |
213 | >; | 213 | >; |
214 | }; | 214 | }; |
215 | 215 | ||
216 | davinci_mdio_default: davinci_mdio_default { | 216 | davinci_mdio_default: davinci_mdio_default { |
217 | pinctrl-single,pins = < | 217 | pinctrl-single,pins = < |
218 | /* MDIO */ | 218 | /* MDIO */ |
219 | 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */ | 219 | 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */ |
220 | 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */ | 220 | 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */ |
221 | >; | 221 | >; |
222 | }; | 222 | }; |
223 | 223 | ||
224 | davinci_mdio_sleep: davinci_mdio_sleep { | 224 | davinci_mdio_sleep: davinci_mdio_sleep { |
225 | pinctrl-single,pins = < | 225 | pinctrl-single,pins = < |
226 | 0x23c (PIN_OFF_NONE) | 226 | 0x23c (PIN_OFF_NONE) |
227 | 0x240 (PIN_OFF_NONE) | 227 | 0x240 (PIN_OFF_NONE) |
228 | >; | 228 | >; |
229 | }; | 229 | }; |
230 | 230 | ||
231 | tps65917_pins_default: tps65917_pins_default { | 231 | tps65917_pins_default: tps65917_pins_default { |
232 | pinctrl-single,pins = < | 232 | pinctrl-single,pins = < |
233 | 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ | 233 | 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ |
234 | >; | 234 | >; |
235 | }; | 235 | }; |
236 | 236 | ||
237 | nand_default: nand_default { | 237 | nand_default: nand_default { |
238 | pinctrl-single,pins = < | 238 | pinctrl-single,pins = < |
239 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ | 239 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ |
240 | 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ | 240 | 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ |
241 | 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ | 241 | 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ |
242 | 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ | 242 | 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ |
243 | 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ | 243 | 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ |
244 | 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ | 244 | 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ |
245 | 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ | 245 | 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ |
246 | 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ | 246 | 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ |
247 | 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ | 247 | 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ |
248 | 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ | 248 | 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ |
249 | 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ | 249 | 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ |
250 | 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ | 250 | 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ |
251 | 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ | 251 | 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ |
252 | 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ | 252 | 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ |
253 | 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ | 253 | 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ |
254 | 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ | 254 | 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ |
255 | 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ | 255 | 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ |
256 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ | 256 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ |
257 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ | 257 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ |
258 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ | 258 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ |
259 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ | 259 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ |
260 | 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ | 260 | 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ |
261 | >; | 261 | >; |
262 | }; | 262 | }; |
263 | 263 | ||
264 | vout1_pins: pinmux_vout1_pins { | 264 | vout1_pins: pinmux_vout1_pins { |
265 | pinctrl-single,pins = < | 265 | pinctrl-single,pins = < |
266 | 0x1C8 (PIN_OUTPUT | MUX_MODE0) /* vout1_clk */ | 266 | 0x1C8 (PIN_OUTPUT | MUX_MODE0) /* vout1_clk */ |
267 | 0x1CC (PIN_OUTPUT | MUX_MODE0) /* vout1_de */ | 267 | 0x1CC (PIN_OUTPUT | MUX_MODE0) /* vout1_de */ |
268 | 0x1D0 (PIN_OUTPUT | MUX_MODE0) /* vout1_fld */ | 268 | 0x1D0 (PIN_OUTPUT | MUX_MODE0) /* vout1_fld */ |
269 | 0x1D4 (PIN_OUTPUT | MUX_MODE0) /* vout1_hsync */ | 269 | 0x1D4 (PIN_OUTPUT | MUX_MODE0) /* vout1_hsync */ |
270 | 0x1D8 (PIN_OUTPUT | MUX_MODE0) /* vout1_vsync */ | 270 | 0x1D8 (PIN_OUTPUT | MUX_MODE0) /* vout1_vsync */ |
271 | 0x1DC (PIN_OUTPUT | MUX_MODE0) /* vout1_d0 */ | 271 | 0x1DC (PIN_OUTPUT | MUX_MODE0) /* vout1_d0 */ |
272 | 0x1E0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d1 */ | 272 | 0x1E0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d1 */ |
273 | 0x1E4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d2 */ | 273 | 0x1E4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d2 */ |
274 | 0x1E8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d3 */ | 274 | 0x1E8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d3 */ |
275 | 0x1EC (PIN_OUTPUT | MUX_MODE0) /* vout1_d4 */ | 275 | 0x1EC (PIN_OUTPUT | MUX_MODE0) /* vout1_d4 */ |
276 | 0x1F0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d5 */ | 276 | 0x1F0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d5 */ |
277 | 0x1F4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d6 */ | 277 | 0x1F4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d6 */ |
278 | 0x1F8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d7 */ | 278 | 0x1F8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d7 */ |
279 | 0x1FC (PIN_OUTPUT | MUX_MODE0) /* vout1_d8 */ | 279 | 0x1FC (PIN_OUTPUT | MUX_MODE0) /* vout1_d8 */ |
280 | 0x200 (PIN_OUTPUT | MUX_MODE0) /* vout1_d9 */ | 280 | 0x200 (PIN_OUTPUT | MUX_MODE0) /* vout1_d9 */ |
281 | 0x204 (PIN_OUTPUT | MUX_MODE0) /* vout1_d10 */ | 281 | 0x204 (PIN_OUTPUT | MUX_MODE0) /* vout1_d10 */ |
282 | 0x208 (PIN_OUTPUT | MUX_MODE0) /* vout1_d11 */ | 282 | 0x208 (PIN_OUTPUT | MUX_MODE0) /* vout1_d11 */ |
283 | 0x20C (PIN_OUTPUT | MUX_MODE0) /* vout1_d12 */ | 283 | 0x20C (PIN_OUTPUT | MUX_MODE0) /* vout1_d12 */ |
284 | 0x210 (PIN_OUTPUT | MUX_MODE0) /* vout1_d13 */ | 284 | 0x210 (PIN_OUTPUT | MUX_MODE0) /* vout1_d13 */ |
285 | 0x214 (PIN_OUTPUT | MUX_MODE0) /* vout1_d14 */ | 285 | 0x214 (PIN_OUTPUT | MUX_MODE0) /* vout1_d14 */ |
286 | 0x218 (PIN_OUTPUT | MUX_MODE0) /* vout1_d15 */ | 286 | 0x218 (PIN_OUTPUT | MUX_MODE0) /* vout1_d15 */ |
287 | 0x21C (PIN_OUTPUT | MUX_MODE0) /* vout1_d16 */ | 287 | 0x21C (PIN_OUTPUT | MUX_MODE0) /* vout1_d16 */ |
288 | 0x220 (PIN_OUTPUT | MUX_MODE0) /* vout1_d17 */ | 288 | 0x220 (PIN_OUTPUT | MUX_MODE0) /* vout1_d17 */ |
289 | 0x224 (PIN_OUTPUT | MUX_MODE0) /* vout1_d18 */ | 289 | 0x224 (PIN_OUTPUT | MUX_MODE0) /* vout1_d18 */ |
290 | 0x228 (PIN_OUTPUT | MUX_MODE0) /* vout1_d19 */ | 290 | 0x228 (PIN_OUTPUT | MUX_MODE0) /* vout1_d19 */ |
291 | 0x22C (PIN_OUTPUT | MUX_MODE0) /* vout1_d20 */ | 291 | 0x22C (PIN_OUTPUT | MUX_MODE0) /* vout1_d20 */ |
292 | 0x230 (PIN_OUTPUT | MUX_MODE0) /* vout1_d21 */ | 292 | 0x230 (PIN_OUTPUT | MUX_MODE0) /* vout1_d21 */ |
293 | 0x234 (PIN_OUTPUT | MUX_MODE0) /* vout1_d22 */ | 293 | 0x234 (PIN_OUTPUT | MUX_MODE0) /* vout1_d22 */ |
294 | 0x238 (PIN_OUTPUT | MUX_MODE0) /* vout1_d23 */ | 294 | 0x238 (PIN_OUTPUT | MUX_MODE0) /* vout1_d23 */ |
295 | >; | 295 | >; |
296 | }; | 296 | }; |
297 | 297 | ||
298 | hpd_pin: pinmux_hpd_pin { | 298 | hpd_pin: pinmux_hpd_pin { |
299 | pinctrl-single,pins = < | 299 | pinctrl-single,pins = < |
300 | 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 */ | 300 | 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 */ |
301 | >; | 301 | >; |
302 | }; | 302 | }; |
303 | 303 | ||
304 | atl_pins: pinmux_atl_pins { | 304 | atl_pins: pinmux_atl_pins { |
305 | pinctrl-single,pins = < | 305 | pinctrl-single,pins = < |
306 | 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ | 306 | 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ |
307 | 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ | 307 | 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ |
308 | >; | 308 | >; |
309 | }; | 309 | }; |
310 | 310 | ||
311 | mcasp3_pins: pinmux_mcasp3_pins { | 311 | mcasp3_pins: pinmux_mcasp3_pins { |
312 | pinctrl-single,pins = < | 312 | pinctrl-single,pins = < |
313 | 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ | 313 | 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ |
314 | 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ | 314 | 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ |
315 | 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ | 315 | 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ |
316 | 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ | 316 | 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ |
317 | >; | 317 | >; |
318 | }; | 318 | }; |
319 | 319 | ||
320 | mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { | 320 | mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { |
321 | pinctrl-single,pins = < | 321 | pinctrl-single,pins = < |
322 | 0x324 (PIN_OFF_NONE) | 322 | 0x324 (PIN_OFF_NONE) |
323 | 0x328 (PIN_OFF_NONE) | 323 | 0x328 (PIN_OFF_NONE) |
324 | 0x32c (PIN_OFF_NONE) | 324 | 0x32c (PIN_OFF_NONE) |
325 | 0x330 (PIN_OFF_NONE) | 325 | 0x330 (PIN_OFF_NONE) |
326 | >; | 326 | >; |
327 | }; | 327 | }; |
328 | 328 | ||
329 | usb1_pins: pinmux_usb1_pins { | 329 | usb1_pins: pinmux_usb1_pins { |
330 | pinctrl-single,pins = < | 330 | pinctrl-single,pins = < |
331 | 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ | 331 | 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ |
332 | >; | 332 | >; |
333 | }; | 333 | }; |
334 | 334 | ||
335 | usb2_pins: pinmux_usb2_pins { | 335 | usb2_pins: pinmux_usb2_pins { |
336 | pinctrl-single,pins = < | 336 | pinctrl-single,pins = < |
337 | 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ | 337 | 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ |
338 | >; | 338 | >; |
339 | }; | 339 | }; |
340 | 340 | ||
341 | qspi1_pins: pinmux_qspi1_pins { | 341 | qspi1_pins: pinmux_qspi1_pins { |
342 | pinctrl-single,pins = < | 342 | pinctrl-single,pins = < |
343 | 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ | 343 | 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ |
344 | 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ | 344 | 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ |
345 | 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ | 345 | 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ |
346 | 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ | 346 | 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ |
347 | 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ | 347 | 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ |
348 | 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ | 348 | 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ |
349 | 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ | 349 | 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ |
350 | >; | 350 | >; |
351 | }; | 351 | }; |
352 | 352 | ||
353 | dcan1_pins_default: dcan1_pins_default { | 353 | dcan1_pins_default: dcan1_pins_default { |
354 | pinctrl-single,pins = < | 354 | pinctrl-single,pins = < |
355 | 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ | 355 | 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ |
356 | 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ | 356 | 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ |
357 | >; | 357 | >; |
358 | }; | 358 | }; |
359 | 359 | ||
360 | dcan1_pins_sleep: dcan1_pins_sleep { | 360 | dcan1_pins_sleep: dcan1_pins_sleep { |
361 | pinctrl-single,pins = < | 361 | pinctrl-single,pins = < |
362 | 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ | 362 | 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ |
363 | 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ | 363 | 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ |
364 | >; | 364 | >; |
365 | }; | 365 | }; |
366 | }; | 366 | }; |
367 | 367 | ||
368 | &i2c1 { | 368 | &i2c1 { |
369 | status = "okay"; | 369 | status = "okay"; |
370 | pinctrl-names = "default"; | 370 | pinctrl-names = "default"; |
371 | pinctrl-0 = <&i2c1_pins>; | 371 | pinctrl-0 = <&i2c1_pins>; |
372 | clock-frequency = <400000>; | 372 | clock-frequency = <400000>; |
373 | 373 | ||
374 | tps65917: tps65917@58 { | 374 | tps65917: tps65917@58 { |
375 | compatible = "ti,tps65917"; | 375 | compatible = "ti,tps65917"; |
376 | reg = <0x58>; | 376 | reg = <0x58>; |
377 | 377 | ||
378 | pinctrl-names = "default"; | 378 | pinctrl-names = "default"; |
379 | pinctrl-0 = <&tps65917_pins_default>; | 379 | pinctrl-0 = <&tps65917_pins_default>; |
380 | interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE | 380 | interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE |
381 | &dra7_pmx_core 0x424>; | 381 | &dra7_pmx_core 0x424>; |
382 | interrupt-parent = <&gic>; | 382 | interrupt-parent = <&gic>; |
383 | interrupt-controller; | 383 | interrupt-controller; |
384 | #interrupt-cells = <2>; | 384 | #interrupt-cells = <2>; |
385 | 385 | ||
386 | ti,system-power-controller; | 386 | ti,system-power-controller; |
387 | 387 | ||
388 | tps65917_pmic { | 388 | tps65917_pmic { |
389 | compatible = "ti,tps65917-pmic"; | 389 | compatible = "ti,tps65917-pmic"; |
390 | 390 | ||
391 | regulators { | 391 | regulators { |
392 | smps1_reg: smps1 { | 392 | smps1_reg: smps1 { |
393 | /* VDD_MPU */ | 393 | /* VDD_MPU */ |
394 | regulator-name = "smps1"; | 394 | regulator-name = "smps1"; |
395 | regulator-min-microvolt = <850000>; | 395 | regulator-min-microvolt = <850000>; |
396 | regulator-max-microvolt = <1250000>; | 396 | regulator-max-microvolt = <1250000>; |
397 | regulator-always-on; | 397 | regulator-always-on; |
398 | regulator-boot-on; | 398 | regulator-boot-on; |
399 | }; | 399 | }; |
400 | 400 | ||
401 | smps2_reg: smps2 { | 401 | smps2_reg: smps2 { |
402 | /* VDD_CORE */ | 402 | /* VDD_CORE */ |
403 | regulator-name = "smps2"; | 403 | regulator-name = "smps2"; |
404 | regulator-min-microvolt = <850000>; | 404 | regulator-min-microvolt = <850000>; |
405 | regulator-max-microvolt = <1060000>; | 405 | regulator-max-microvolt = <1060000>; |
406 | regulator-boot-on; | 406 | regulator-boot-on; |
407 | regulator-always-on; | 407 | regulator-always-on; |
408 | }; | 408 | }; |
409 | 409 | ||
410 | smps3_reg: smps3 { | 410 | smps3_reg: smps3 { |
411 | /* VDD_GPU IVA DSPEVE */ | 411 | /* VDD_GPU IVA DSPEVE */ |
412 | regulator-name = "smps3"; | 412 | regulator-name = "smps3"; |
413 | regulator-min-microvolt = <850000>; | 413 | regulator-min-microvolt = <850000>; |
414 | regulator-max-microvolt = <1250000>; | 414 | regulator-max-microvolt = <1250000>; |
415 | regulator-boot-on; | 415 | regulator-boot-on; |
416 | regulator-always-on; | 416 | regulator-always-on; |
417 | }; | 417 | }; |
418 | 418 | ||
419 | smps4_reg: smps4 { | 419 | smps4_reg: smps4 { |
420 | /* VDDS1V8 */ | 420 | /* VDDS1V8 */ |
421 | regulator-name = "smps4"; | 421 | regulator-name = "smps4"; |
422 | regulator-min-microvolt = <1800000>; | 422 | regulator-min-microvolt = <1800000>; |
423 | regulator-max-microvolt = <1800000>; | 423 | regulator-max-microvolt = <1800000>; |
424 | regulator-always-on; | 424 | regulator-always-on; |
425 | regulator-boot-on; | 425 | regulator-boot-on; |
426 | }; | 426 | }; |
427 | 427 | ||
428 | smps5_reg: smps5 { | 428 | smps5_reg: smps5 { |
429 | /* VDD_DDR */ | 429 | /* VDD_DDR */ |
430 | regulator-name = "smps5"; | 430 | regulator-name = "smps5"; |
431 | regulator-min-microvolt = <1350000>; | 431 | regulator-min-microvolt = <1350000>; |
432 | regulator-max-microvolt = <1350000>; | 432 | regulator-max-microvolt = <1350000>; |
433 | regulator-boot-on; | 433 | regulator-boot-on; |
434 | regulator-always-on; | 434 | regulator-always-on; |
435 | }; | 435 | }; |
436 | 436 | ||
437 | ldo1_reg: ldo1 { | 437 | ldo1_reg: ldo1 { |
438 | /* LDO1_OUT --> SDIO */ | 438 | /* LDO1_OUT --> SDIO */ |
439 | regulator-name = "ldo1"; | 439 | regulator-name = "ldo1"; |
440 | regulator-min-microvolt = <1800000>; | 440 | regulator-min-microvolt = <1800000>; |
441 | regulator-max-microvolt = <3300000>; | 441 | regulator-max-microvolt = <3300000>; |
442 | regulator-boot-on; | 442 | regulator-boot-on; |
443 | }; | 443 | }; |
444 | 444 | ||
445 | ldo2_reg: ldo2 { | 445 | ldo2_reg: ldo2 { |
446 | /* LDO2_OUT --> TP1017 (UNUSED) */ | 446 | /* LDO2_OUT --> TP1017 (UNUSED) */ |
447 | regulator-name = "ldo2"; | 447 | regulator-name = "ldo2"; |
448 | regulator-min-microvolt = <1800000>; | 448 | regulator-min-microvolt = <1800000>; |
449 | regulator-max-microvolt = <3300000>; | 449 | regulator-max-microvolt = <3300000>; |
450 | }; | 450 | }; |
451 | 451 | ||
452 | ldo3_reg: ldo3 { | 452 | ldo3_reg: ldo3 { |
453 | /* VDDA_1V8_PHY */ | 453 | /* VDDA_1V8_PHY */ |
454 | regulator-name = "ldo3"; | 454 | regulator-name = "ldo3"; |
455 | regulator-min-microvolt = <1800000>; | 455 | regulator-min-microvolt = <1800000>; |
456 | regulator-max-microvolt = <1800000>; | 456 | regulator-max-microvolt = <1800000>; |
457 | regulator-boot-on; | 457 | regulator-boot-on; |
458 | regulator-always-on; | 458 | regulator-always-on; |
459 | }; | 459 | }; |
460 | 460 | ||
461 | ldo5_reg: ldo5 { | 461 | ldo5_reg: ldo5 { |
462 | /* VDDA_1V8_PLL */ | 462 | /* VDDA_1V8_PLL */ |
463 | regulator-name = "ldo5"; | 463 | regulator-name = "ldo5"; |
464 | regulator-min-microvolt = <1800000>; | 464 | regulator-min-microvolt = <1800000>; |
465 | regulator-max-microvolt = <1800000>; | 465 | regulator-max-microvolt = <1800000>; |
466 | regulator-always-on; | 466 | regulator-always-on; |
467 | regulator-boot-on; | 467 | regulator-boot-on; |
468 | }; | 468 | }; |
469 | 469 | ||
470 | ldo4_reg: ldo4 { | 470 | ldo4_reg: ldo4 { |
471 | /* VDDA_3V_USB: VDDA_USBHS33 */ | 471 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
472 | regulator-name = "ldo4"; | 472 | regulator-name = "ldo4"; |
473 | regulator-min-microvolt = <3300000>; | 473 | regulator-min-microvolt = <3300000>; |
474 | regulator-max-microvolt = <3300000>; | 474 | regulator-max-microvolt = <3300000>; |
475 | regulator-boot-on; | 475 | regulator-boot-on; |
476 | }; | 476 | }; |
477 | }; | 477 | }; |
478 | }; | 478 | }; |
479 | 479 | ||
480 | tps65917_power_button { | 480 | tps65917_power_button { |
481 | compatible = "ti,palmas-pwrbutton"; | 481 | compatible = "ti,palmas-pwrbutton"; |
482 | interrupt-parent = <&tps65917>; | 482 | interrupt-parent = <&tps65917>; |
483 | interrupts = <1 IRQ_TYPE_NONE>; | 483 | interrupts = <1 IRQ_TYPE_NONE>; |
484 | wakeup-source; | 484 | wakeup-source; |
485 | ti,palmas-long-press-seconds = <6>; | 485 | ti,palmas-long-press-seconds = <6>; |
486 | }; | 486 | }; |
487 | }; | 487 | }; |
488 | 488 | ||
489 | pcf_lcd: gpio@20 { | 489 | pcf_lcd: gpio@20 { |
490 | compatible = "nxp,pcf8575"; | 490 | compatible = "nxp,pcf8575"; |
491 | reg = <0x20>; | 491 | reg = <0x20>; |
492 | gpio-controller; | 492 | gpio-controller; |
493 | #gpio-cells = <2>; | 493 | #gpio-cells = <2>; |
494 | }; | 494 | }; |
495 | 495 | ||
496 | pcf_gpio_21: gpio@21 { | 496 | pcf_gpio_21: gpio@21 { |
497 | compatible = "nxp,pcf8575"; | 497 | compatible = "nxp,pcf8575"; |
498 | reg = <0x21>; | 498 | reg = <0x21>; |
499 | lines-initial-states = <0x1408>; | 499 | lines-initial-states = <0x1408>; |
500 | gpio-controller; | 500 | gpio-controller; |
501 | #gpio-cells = <2>; | 501 | #gpio-cells = <2>; |
502 | interrupt-parent = <&gpio6>; | 502 | interrupt-parent = <&gpio6>; |
503 | interrupts = <11 2>; | 503 | interrupts = <11 2>; |
504 | interrupt-controller; | 504 | interrupt-controller; |
505 | #interrupt-cells = <2>; | 505 | #interrupt-cells = <2>; |
506 | 506 | ||
507 | cpsw_sel_s0 { | 507 | cpsw_sel_s0 { |
508 | gpio-hog; | 508 | gpio-hog; |
509 | gpios = <4 GPIO_ACTIVE_HIGH>; | 509 | gpios = <4 GPIO_ACTIVE_HIGH>; |
510 | output-low; | 510 | output-low; |
511 | }; | 511 | }; |
512 | }; | 512 | }; |
513 | 513 | ||
514 | tlv320aic3106: tlv320aic3106@19 { | 514 | tlv320aic3106: tlv320aic3106@19 { |
515 | compatible = "ti,tlv320aic3106"; | 515 | compatible = "ti,tlv320aic3106"; |
516 | reg = <0x19>; | 516 | reg = <0x19>; |
517 | adc-settle-ms = <40>; | 517 | adc-settle-ms = <40>; |
518 | ai3x-micbias-vg = <1>; /* 2.0V */ | 518 | ai3x-micbias-vg = <1>; /* 2.0V */ |
519 | status = "okay"; | 519 | status = "okay"; |
520 | 520 | ||
521 | /* Regulators */ | 521 | /* Regulators */ |
522 | AVDD-supply = <&evm_3v3>; | 522 | AVDD-supply = <&evm_3v3>; |
523 | IOVDD-supply = <&evm_3v3>; | 523 | IOVDD-supply = <&evm_3v3>; |
524 | DRVDD-supply = <&evm_3v3>; | 524 | DRVDD-supply = <&evm_3v3>; |
525 | DVDD-supply = <&aic_dvdd>; | 525 | DVDD-supply = <&aic_dvdd>; |
526 | }; | 526 | }; |
527 | }; | 527 | }; |
528 | 528 | ||
529 | &dra7_pmx_core { | 529 | &dra7_pmx_core { |
530 | i2c5_pins: pinmux_i2c5_pins { | 530 | i2c5_pins: pinmux_i2c5_pins { |
531 | pinctrl-single,pins = < | 531 | pinctrl-single,pins = < |
532 | 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ | 532 | 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ |
533 | 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ | 533 | 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ |
534 | >; | 534 | >; |
535 | }; | 535 | }; |
536 | }; | 536 | }; |
537 | 537 | ||
538 | &i2c5 { | 538 | &i2c5 { |
539 | status = "okay"; | 539 | status = "okay"; |
540 | pinctrl-names = "default"; | 540 | pinctrl-names = "default"; |
541 | pinctrl-0 = <&i2c5_pins>; | 541 | pinctrl-0 = <&i2c5_pins>; |
542 | clock-frequency = <400000>; | 542 | clock-frequency = <400000>; |
543 | 543 | ||
544 | pcf_hdmi: pcf8575@26 { | 544 | pcf_hdmi: pcf8575@26 { |
545 | compatible = "nxp,pcf8575"; | 545 | compatible = "nxp,pcf8575"; |
546 | reg = <0x26>; | 546 | reg = <0x26>; |
547 | gpio-controller; | 547 | gpio-controller; |
548 | #gpio-cells = <2>; | 548 | #gpio-cells = <2>; |
549 | /* | 549 | /* |
550 | * initial state is used here to keep the mdio interface | 550 | * initial state is used here to keep the mdio interface |
551 | * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and | 551 | * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and |
552 | * VIN2_S0 driven high otherwise Ethernet stops working | 552 | * VIN2_S0 driven high otherwise Ethernet stops working |
553 | * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 | 553 | * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 |
554 | */ | 554 | */ |
555 | lines-initial-states = <0x0f2b>; | 555 | lines-initial-states = <0x0f2b>; |
556 | }; | 556 | }; |
557 | }; | 557 | }; |
558 | 558 | ||
559 | &uart1 { | 559 | &uart1 { |
560 | pinctrl-names = "default"; | 560 | pinctrl-names = "default"; |
561 | pinctrl-0 = <&uart1_pins>; | 561 | pinctrl-0 = <&uart1_pins>; |
562 | 562 | ||
563 | interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH | 563 | interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH |
564 | &dra7_pmx_core 0x3e0>; | 564 | &dra7_pmx_core 0x3e0>; |
565 | status = "okay"; | 565 | status = "okay"; |
566 | }; | 566 | }; |
567 | 567 | ||
568 | &mmc1 { | 568 | &mmc1 { |
569 | /* Using default configured pins */ | 569 | /* Using default configured pins */ |
570 | status = "okay"; | 570 | status = "okay"; |
571 | pbias-supply = <&pbias_mmc_reg>; | 571 | pbias-supply = <&pbias_mmc_reg>; |
572 | vmmc-supply = <&evm_3v3_sd>; | 572 | vmmc-supply = <&evm_3v3_sd>; |
573 | vmmc_aux-supply = <&ldo1_reg>; | 573 | vmmc_aux-supply = <&ldo1_reg>; |
574 | bus-width = <4>; | 574 | bus-width = <4>; |
575 | /* | 575 | /* |
576 | * SDCD signal is not being used here - using the fact that GPIO mode | 576 | * SDCD signal is not being used here - using the fact that GPIO mode |
577 | * is always hardwired. | 577 | * is always hardwired. |
578 | */ | 578 | */ |
579 | cd-gpios = <&gpio6 27 0>; | 579 | cd-gpios = <&gpio6 27 0>; |
580 | sd-uhs-sdr104; | 580 | sd-uhs-sdr104; |
581 | sd-uhs-sdr50; | 581 | sd-uhs-sdr50; |
582 | sd-uhs-ddr50; | 582 | sd-uhs-ddr50; |
583 | sd-uhs-sdr25; | 583 | sd-uhs-sdr25; |
584 | sd-uhs-sdr12; | 584 | sd-uhs-sdr12; |
585 | max-frequency = <192000000>; | 585 | max-frequency = <192000000>; |
586 | }; | 586 | }; |
587 | 587 | ||
588 | &mmc2 { | 588 | &mmc2 { |
589 | /* Using default configured pins */ | 589 | /* Using default configured pins */ |
590 | status = "okay"; | 590 | status = "okay"; |
591 | vmmc-supply = <&evm_3v3>; | 591 | vmmc-supply = <&evm_3v3>; |
592 | bus-width = <8>; | 592 | bus-width = <8>; |
593 | ti,non-removable; | 593 | ti,non-removable; |
594 | mmc-hs200-1_8v; | 594 | mmc-hs200-1_8v; |
595 | max-frequency = <192000000>; | 595 | max-frequency = <192000000>; |
596 | }; | 596 | }; |
597 | 597 | ||
598 | &mac { | 598 | &mac { |
599 | status = "okay"; | 599 | status = "okay"; |
600 | pinctrl-names = "default", "sleep"; | 600 | pinctrl-names = "default", "sleep"; |
601 | pinctrl-0 = <&cpsw_default>; | 601 | pinctrl-0 = <&cpsw_default>; |
602 | pinctrl-1 = <&cpsw_sleep>; | 602 | pinctrl-1 = <&cpsw_sleep>; |
603 | slaves = <1>; | 603 | slaves = <1>; |
604 | ti,no-idle; | ||
604 | }; | 605 | }; |
605 | 606 | ||
606 | &cpsw_emac0 { | 607 | &cpsw_emac0 { |
607 | phy_id = <&davinci_mdio>, <3>; | 608 | phy_id = <&davinci_mdio>, <3>; |
608 | phy-mode = "rgmii"; | 609 | phy-mode = "rgmii"; |
609 | }; | 610 | }; |
610 | 611 | ||
611 | &davinci_mdio { | 612 | &davinci_mdio { |
612 | pinctrl-names = "default", "sleep"; | 613 | pinctrl-names = "default", "sleep"; |
613 | pinctrl-0 = <&davinci_mdio_default>; | 614 | pinctrl-0 = <&davinci_mdio_default>; |
614 | pinctrl-1 = <&davinci_mdio_sleep>; | 615 | pinctrl-1 = <&davinci_mdio_sleep>; |
615 | }; | 616 | }; |
616 | 617 | ||
617 | &cpu0 { | 618 | &cpu0 { |
618 | cpu0-voltdm = <&voltdm_mpu>; | 619 | cpu0-voltdm = <&voltdm_mpu>; |
619 | voltage-tolerance = <1>; | 620 | voltage-tolerance = <1>; |
620 | }; | 621 | }; |
621 | 622 | ||
622 | &voltdm_mpu { | 623 | &voltdm_mpu { |
623 | vdd-supply = <&smps1_reg>; | 624 | vdd-supply = <&smps1_reg>; |
624 | }; | 625 | }; |
625 | 626 | ||
626 | &voltdm_core { | 627 | &voltdm_core { |
627 | vdd-supply = <&smps2_reg>; | 628 | vdd-supply = <&smps2_reg>; |
628 | }; | 629 | }; |
629 | 630 | ||
630 | &voltdm_dspeve { | 631 | &voltdm_dspeve { |
631 | vdd-supply = <&smps3_reg>; | 632 | vdd-supply = <&smps3_reg>; |
632 | }; | 633 | }; |
633 | 634 | ||
634 | &voltdm_gpu { | 635 | &voltdm_gpu { |
635 | vdd-supply = <&smps3_reg>; | 636 | vdd-supply = <&smps3_reg>; |
636 | }; | 637 | }; |
637 | 638 | ||
638 | &voltdm_ivahd { | 639 | &voltdm_ivahd { |
639 | vdd-supply = <&smps3_reg>; | 640 | vdd-supply = <&smps3_reg>; |
640 | }; | 641 | }; |
641 | 642 | ||
642 | &elm { | 643 | &elm { |
643 | status = "okay"; | 644 | status = "okay"; |
644 | }; | 645 | }; |
645 | 646 | ||
646 | &gpmc { | 647 | &gpmc { |
647 | status = "okay"; | 648 | status = "okay"; |
648 | pinctrl-names = "default"; | 649 | pinctrl-names = "default"; |
649 | pinctrl-0 = <&nand_default>; | 650 | pinctrl-0 = <&nand_default>; |
650 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ | 651 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ |
651 | nand@0,0 { | 652 | nand@0,0 { |
652 | /* To use NAND, DIP switch SW5 must be set like so: | 653 | /* To use NAND, DIP switch SW5 must be set like so: |
653 | * SW5.1 (NAND_SELn) = ON (LOW) | 654 | * SW5.1 (NAND_SELn) = ON (LOW) |
654 | * SW5.9 (GPMC_WPN) = OFF (HIGH) | 655 | * SW5.9 (GPMC_WPN) = OFF (HIGH) |
655 | */ | 656 | */ |
656 | reg = <0 0 4>; /* device IO registers */ | 657 | reg = <0 0 4>; /* device IO registers */ |
657 | ti,nand-ecc-opt = "bch8"; | 658 | ti,nand-ecc-opt = "bch8"; |
658 | ti,elm-id = <&elm>; | 659 | ti,elm-id = <&elm>; |
659 | nand-bus-width = <16>; | 660 | nand-bus-width = <16>; |
660 | gpmc,device-width = <2>; | 661 | gpmc,device-width = <2>; |
661 | gpmc,sync-clk-ps = <0>; | 662 | gpmc,sync-clk-ps = <0>; |
662 | gpmc,cs-on-ns = <0>; | 663 | gpmc,cs-on-ns = <0>; |
663 | gpmc,cs-rd-off-ns = <80>; | 664 | gpmc,cs-rd-off-ns = <80>; |
664 | gpmc,cs-wr-off-ns = <80>; | 665 | gpmc,cs-wr-off-ns = <80>; |
665 | gpmc,adv-on-ns = <0>; | 666 | gpmc,adv-on-ns = <0>; |
666 | gpmc,adv-rd-off-ns = <60>; | 667 | gpmc,adv-rd-off-ns = <60>; |
667 | gpmc,adv-wr-off-ns = <60>; | 668 | gpmc,adv-wr-off-ns = <60>; |
668 | gpmc,we-on-ns = <10>; | 669 | gpmc,we-on-ns = <10>; |
669 | gpmc,we-off-ns = <50>; | 670 | gpmc,we-off-ns = <50>; |
670 | gpmc,oe-on-ns = <4>; | 671 | gpmc,oe-on-ns = <4>; |
671 | gpmc,oe-off-ns = <40>; | 672 | gpmc,oe-off-ns = <40>; |
672 | gpmc,access-ns = <40>; | 673 | gpmc,access-ns = <40>; |
673 | gpmc,wr-access-ns = <80>; | 674 | gpmc,wr-access-ns = <80>; |
674 | gpmc,rd-cycle-ns = <80>; | 675 | gpmc,rd-cycle-ns = <80>; |
675 | gpmc,wr-cycle-ns = <80>; | 676 | gpmc,wr-cycle-ns = <80>; |
676 | gpmc,bus-turnaround-ns = <0>; | 677 | gpmc,bus-turnaround-ns = <0>; |
677 | gpmc,cycle2cycle-delay-ns = <0>; | 678 | gpmc,cycle2cycle-delay-ns = <0>; |
678 | gpmc,clk-activation-ns = <0>; | 679 | gpmc,clk-activation-ns = <0>; |
679 | gpmc,wait-monitoring-ns = <0>; | 680 | gpmc,wait-monitoring-ns = <0>; |
680 | gpmc,wr-data-mux-bus-ns = <0>; | 681 | gpmc,wr-data-mux-bus-ns = <0>; |
681 | /* MTD partition table */ | 682 | /* MTD partition table */ |
682 | /* All SPL-* partitions are sized to minimal length | 683 | /* All SPL-* partitions are sized to minimal length |
683 | * which can be independently programmable. For | 684 | * which can be independently programmable. For |
684 | * NAND flash this is equal to size of erase-block */ | 685 | * NAND flash this is equal to size of erase-block */ |
685 | #address-cells = <1>; | 686 | #address-cells = <1>; |
686 | #size-cells = <1>; | 687 | #size-cells = <1>; |
687 | partition@0 { | 688 | partition@0 { |
688 | label = "NAND.SPL"; | 689 | label = "NAND.SPL"; |
689 | reg = <0x00000000 0x000020000>; | 690 | reg = <0x00000000 0x000020000>; |
690 | }; | 691 | }; |
691 | partition@1 { | 692 | partition@1 { |
692 | label = "NAND.SPL.backup1"; | 693 | label = "NAND.SPL.backup1"; |
693 | reg = <0x00020000 0x00020000>; | 694 | reg = <0x00020000 0x00020000>; |
694 | }; | 695 | }; |
695 | partition@2 { | 696 | partition@2 { |
696 | label = "NAND.SPL.backup2"; | 697 | label = "NAND.SPL.backup2"; |
697 | reg = <0x00040000 0x00020000>; | 698 | reg = <0x00040000 0x00020000>; |
698 | }; | 699 | }; |
699 | partition@3 { | 700 | partition@3 { |
700 | label = "NAND.SPL.backup3"; | 701 | label = "NAND.SPL.backup3"; |
701 | reg = <0x00060000 0x00020000>; | 702 | reg = <0x00060000 0x00020000>; |
702 | }; | 703 | }; |
703 | partition@4 { | 704 | partition@4 { |
704 | label = "NAND.u-boot-spl-os"; | 705 | label = "NAND.u-boot-spl-os"; |
705 | reg = <0x00080000 0x00040000>; | 706 | reg = <0x00080000 0x00040000>; |
706 | }; | 707 | }; |
707 | partition@5 { | 708 | partition@5 { |
708 | label = "NAND.u-boot"; | 709 | label = "NAND.u-boot"; |
709 | reg = <0x000c0000 0x00100000>; | 710 | reg = <0x000c0000 0x00100000>; |
710 | }; | 711 | }; |
711 | partition@6 { | 712 | partition@6 { |
712 | label = "NAND.u-boot-env"; | 713 | label = "NAND.u-boot-env"; |
713 | reg = <0x001c0000 0x00020000>; | 714 | reg = <0x001c0000 0x00020000>; |
714 | }; | 715 | }; |
715 | partition@7 { | 716 | partition@7 { |
716 | label = "NAND.u-boot-env.backup1"; | 717 | label = "NAND.u-boot-env.backup1"; |
717 | reg = <0x001e0000 0x00020000>; | 718 | reg = <0x001e0000 0x00020000>; |
718 | }; | 719 | }; |
719 | partition@8 { | 720 | partition@8 { |
720 | label = "NAND.kernel"; | 721 | label = "NAND.kernel"; |
721 | reg = <0x00200000 0x00800000>; | 722 | reg = <0x00200000 0x00800000>; |
722 | }; | 723 | }; |
723 | partition@9 { | 724 | partition@9 { |
724 | label = "NAND.file-system"; | 725 | label = "NAND.file-system"; |
725 | reg = <0x00a00000 0x0f600000>; | 726 | reg = <0x00a00000 0x0f600000>; |
726 | }; | 727 | }; |
727 | }; | 728 | }; |
728 | }; | 729 | }; |
729 | 730 | ||
730 | &dss { | 731 | &dss { |
731 | status = "ok"; | 732 | status = "ok"; |
732 | 733 | ||
733 | vdda_video-supply = <&ldo5_reg>; | 734 | vdda_video-supply = <&ldo5_reg>; |
734 | }; | 735 | }; |
735 | 736 | ||
736 | &hdmi { | 737 | &hdmi { |
737 | status = "ok"; | 738 | status = "ok"; |
738 | vdda-supply = <&ldo3_reg>; | 739 | vdda-supply = <&ldo3_reg>; |
739 | pinctrl-names = "default"; | 740 | pinctrl-names = "default"; |
740 | pinctrl-0 = <&i2c2_pins>; | 741 | pinctrl-0 = <&i2c2_pins>; |
741 | 742 | ||
742 | port { | 743 | port { |
743 | hdmi_out: endpoint { | 744 | hdmi_out: endpoint { |
744 | remote-endpoint = <&tpd12s015_in>; | 745 | remote-endpoint = <&tpd12s015_in>; |
745 | }; | 746 | }; |
746 | }; | 747 | }; |
747 | }; | 748 | }; |
748 | 749 | ||
749 | &mailbox5 { | 750 | &mailbox5 { |
750 | status = "okay"; | 751 | status = "okay"; |
751 | mbox_ipu1_legacy: mbox_ipu1_legacy { | 752 | mbox_ipu1_legacy: mbox_ipu1_legacy { |
752 | status = "okay"; | 753 | status = "okay"; |
753 | }; | 754 | }; |
754 | mbox_dsp1_legacy: mbox_dsp1_legacy { | 755 | mbox_dsp1_legacy: mbox_dsp1_legacy { |
755 | status = "okay"; | 756 | status = "okay"; |
756 | }; | 757 | }; |
757 | }; | 758 | }; |
758 | 759 | ||
759 | &mailbox6 { | 760 | &mailbox6 { |
760 | status = "okay"; | 761 | status = "okay"; |
761 | mbox_ipu2_legacy: mbox_ipu2_legacy { | 762 | mbox_ipu2_legacy: mbox_ipu2_legacy { |
762 | status = "okay"; | 763 | status = "okay"; |
763 | }; | 764 | }; |
764 | }; | 765 | }; |
765 | 766 | ||
766 | &mmu0_dsp1 { | 767 | &mmu0_dsp1 { |
767 | status = "okay"; | 768 | status = "okay"; |
768 | }; | 769 | }; |
769 | 770 | ||
770 | &mmu1_dsp1 { | 771 | &mmu1_dsp1 { |
771 | status = "okay"; | 772 | status = "okay"; |
772 | }; | 773 | }; |
773 | 774 | ||
774 | &mmu_ipu1 { | 775 | &mmu_ipu1 { |
775 | status = "okay"; | 776 | status = "okay"; |
776 | }; | 777 | }; |
777 | 778 | ||
778 | &mmu_ipu2 { | 779 | &mmu_ipu2 { |
779 | status = "okay"; | 780 | status = "okay"; |
780 | }; | 781 | }; |
781 | 782 | ||
782 | &ipu2 { | 783 | &ipu2 { |
783 | status = "okay"; | 784 | status = "okay"; |
784 | memory-region = <&ipu2_cma_pool>; | 785 | memory-region = <&ipu2_cma_pool>; |
785 | mboxes = <&mailbox6 &mbox_ipu2_legacy>; | 786 | mboxes = <&mailbox6 &mbox_ipu2_legacy>; |
786 | timers = <&timer3>; | 787 | timers = <&timer3>; |
787 | watchdog-timers = <&timer4>, <&timer9>; | 788 | watchdog-timers = <&timer4>, <&timer9>; |
788 | }; | 789 | }; |
789 | 790 | ||
790 | &ipu1 { | 791 | &ipu1 { |
791 | status = "okay"; | 792 | status = "okay"; |
792 | memory-region = <&ipu1_cma_pool>; | 793 | memory-region = <&ipu1_cma_pool>; |
793 | mboxes = <&mailbox5 &mbox_ipu1_legacy>; | 794 | mboxes = <&mailbox5 &mbox_ipu1_legacy>; |
794 | timers = <&timer11>; | 795 | timers = <&timer11>; |
795 | }; | 796 | }; |
796 | 797 | ||
797 | &dsp1 { | 798 | &dsp1 { |
798 | status = "okay"; | 799 | status = "okay"; |
799 | memory-region = <&dsp1_cma_pool>; | 800 | memory-region = <&dsp1_cma_pool>; |
800 | mboxes = <&mailbox5 &mbox_dsp1_legacy>; | 801 | mboxes = <&mailbox5 &mbox_dsp1_legacy>; |
801 | timers = <&timer5>; | 802 | timers = <&timer5>; |
802 | }; | 803 | }; |
803 | 804 | ||
804 | &atl { | 805 | &atl { |
805 | pinctrl-names = "default"; | 806 | pinctrl-names = "default"; |
806 | pinctrl-0 = <&atl_pins>; | 807 | pinctrl-0 = <&atl_pins>; |
807 | 808 | ||
808 | status = "okay"; | 809 | status = "okay"; |
809 | 810 | ||
810 | atl2 { | 811 | atl2 { |
811 | bws = <DRA7_ATL_WS_MCASP2_FSX>; | 812 | bws = <DRA7_ATL_WS_MCASP2_FSX>; |
812 | aws = <DRA7_ATL_WS_MCASP3_FSX>; | 813 | aws = <DRA7_ATL_WS_MCASP3_FSX>; |
813 | }; | 814 | }; |
814 | }; | 815 | }; |
815 | 816 | ||
816 | &mcasp3 { | 817 | &mcasp3 { |
817 | pinctrl-names = "default", "sleep"; | 818 | pinctrl-names = "default", "sleep"; |
818 | pinctrl-0 = <&mcasp3_pins>; | 819 | pinctrl-0 = <&mcasp3_pins>; |
819 | pinctrl-1 = <&mcasp3_sleep_pins>; | 820 | pinctrl-1 = <&mcasp3_sleep_pins>; |
820 | 821 | ||
821 | fck_parent = "atl_clkin2_ck"; | 822 | fck_parent = "atl_clkin2_ck"; |
822 | 823 | ||
823 | status = "okay"; | 824 | status = "okay"; |
824 | 825 | ||
825 | op-mode = <0>; /* MCASP_IIS_MODE */ | 826 | op-mode = <0>; /* MCASP_IIS_MODE */ |
826 | tdm-slots = <2>; | 827 | tdm-slots = <2>; |
827 | /* 4 serializer */ | 828 | /* 4 serializer */ |
828 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | 829 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
829 | 1 2 0 0 | 830 | 1 2 0 0 |
830 | >; | 831 | >; |
831 | }; | 832 | }; |
832 | 833 | ||
833 | &omap_dwc3_1 { | 834 | &omap_dwc3_1 { |
834 | extcon = <&extcon_usb1>; | 835 | extcon = <&extcon_usb1>; |
835 | }; | 836 | }; |
836 | 837 | ||
837 | &omap_dwc3_2 { | 838 | &omap_dwc3_2 { |
838 | extcon = <&extcon_usb2>; | 839 | extcon = <&extcon_usb2>; |
839 | }; | 840 | }; |
840 | 841 | ||
841 | &usb2_phy1 { | 842 | &usb2_phy1 { |
842 | phy-supply = <&ldo4_reg>; | 843 | phy-supply = <&ldo4_reg>; |
843 | }; | 844 | }; |
844 | 845 | ||
845 | &usb2_phy2 { | 846 | &usb2_phy2 { |
846 | phy-supply = <&ldo4_reg>; | 847 | phy-supply = <&ldo4_reg>; |
847 | }; | 848 | }; |
848 | 849 | ||
849 | &usb1 { | 850 | &usb1 { |
850 | dr_mode = "otg"; | 851 | dr_mode = "otg"; |
851 | pinctrl-names = "default"; | 852 | pinctrl-names = "default"; |
852 | pinctrl-0 = <&usb1_pins>; | 853 | pinctrl-0 = <&usb1_pins>; |
853 | }; | 854 | }; |
854 | 855 | ||
855 | &usb2 { | 856 | &usb2 { |
856 | dr_mode = "host"; | 857 | dr_mode = "host"; |
857 | pinctrl-names = "default"; | 858 | pinctrl-names = "default"; |
858 | pinctrl-0 = <&usb2_pins>; | 859 | pinctrl-0 = <&usb2_pins>; |
859 | }; | 860 | }; |
860 | 861 | ||
861 | &qspi { | 862 | &qspi { |
862 | status = "okay"; | 863 | status = "okay"; |
863 | pinctrl-names = "default"; | 864 | pinctrl-names = "default"; |
864 | pinctrl-0 = <&qspi1_pins>; | 865 | pinctrl-0 = <&qspi1_pins>; |
865 | 866 | ||
866 | spi-max-frequency = <48000000>; | 867 | spi-max-frequency = <48000000>; |
867 | m25p80@0 { | 868 | m25p80@0 { |
868 | compatible = "s25fl256s1"; | 869 | compatible = "s25fl256s1"; |
869 | spi-max-frequency = <48000000>; | 870 | spi-max-frequency = <48000000>; |
870 | reg = <0>; | 871 | reg = <0>; |
871 | spi-tx-bus-width = <1>; | 872 | spi-tx-bus-width = <1>; |
872 | spi-rx-bus-width = <4>; | 873 | spi-rx-bus-width = <4>; |
873 | spi-cpol; | 874 | spi-cpol; |
874 | spi-cpha; | 875 | spi-cpha; |
875 | #address-cells = <1>; | 876 | #address-cells = <1>; |
876 | #size-cells = <1>; | 877 | #size-cells = <1>; |
877 | 878 | ||
878 | /* MTD partition table. | 879 | /* MTD partition table. |
879 | * The ROM checks the first four physical blocks | 880 | * The ROM checks the first four physical blocks |
880 | * for a valid file to boot and the flash here is | 881 | * for a valid file to boot and the flash here is |
881 | * 64KiB block size. | 882 | * 64KiB block size. |
882 | */ | 883 | */ |
883 | partition@0 { | 884 | partition@0 { |
884 | label = "QSPI.SPL"; | 885 | label = "QSPI.SPL"; |
885 | reg = <0x00000000 0x000010000>; | 886 | reg = <0x00000000 0x000010000>; |
886 | }; | 887 | }; |
887 | partition@1 { | 888 | partition@1 { |
888 | label = "QSPI.SPL.backup1"; | 889 | label = "QSPI.SPL.backup1"; |
889 | reg = <0x00010000 0x00010000>; | 890 | reg = <0x00010000 0x00010000>; |
890 | }; | 891 | }; |
891 | partition@2 { | 892 | partition@2 { |
892 | label = "QSPI.SPL.backup2"; | 893 | label = "QSPI.SPL.backup2"; |
893 | reg = <0x00020000 0x00010000>; | 894 | reg = <0x00020000 0x00010000>; |
894 | }; | 895 | }; |
895 | partition@3 { | 896 | partition@3 { |
896 | label = "QSPI.SPL.backup3"; | 897 | label = "QSPI.SPL.backup3"; |
897 | reg = <0x00030000 0x00010000>; | 898 | reg = <0x00030000 0x00010000>; |
898 | }; | 899 | }; |
899 | partition@4 { | 900 | partition@4 { |
900 | label = "QSPI.u-boot"; | 901 | label = "QSPI.u-boot"; |
901 | reg = <0x00040000 0x00100000>; | 902 | reg = <0x00040000 0x00100000>; |
902 | }; | 903 | }; |
903 | partition@5 { | 904 | partition@5 { |
904 | label = "QSPI.u-boot-spl-os"; | 905 | label = "QSPI.u-boot-spl-os"; |
905 | reg = <0x00140000 0x00080000>; | 906 | reg = <0x00140000 0x00080000>; |
906 | }; | 907 | }; |
907 | partition@6 { | 908 | partition@6 { |
908 | label = "QSPI.u-boot-env"; | 909 | label = "QSPI.u-boot-env"; |
909 | reg = <0x001c0000 0x00010000>; | 910 | reg = <0x001c0000 0x00010000>; |
910 | }; | 911 | }; |
911 | partition@7 { | 912 | partition@7 { |
912 | label = "QSPI.u-boot-env.backup1"; | 913 | label = "QSPI.u-boot-env.backup1"; |
913 | reg = <0x001d0000 0x0010000>; | 914 | reg = <0x001d0000 0x0010000>; |
914 | }; | 915 | }; |
915 | partition@8 { | 916 | partition@8 { |
916 | label = "QSPI.kernel"; | 917 | label = "QSPI.kernel"; |
917 | reg = <0x001e0000 0x0800000>; | 918 | reg = <0x001e0000 0x0800000>; |
918 | }; | 919 | }; |
919 | partition@9 { | 920 | partition@9 { |
920 | label = "QSPI.file-system"; | 921 | label = "QSPI.file-system"; |
921 | reg = <0x009e0000 0x01620000>; | 922 | reg = <0x009e0000 0x01620000>; |
922 | }; | 923 | }; |
923 | }; | 924 | }; |
924 | }; | 925 | }; |
925 | 926 | ||
926 | &dcan1 { | 927 | &dcan1 { |
927 | status = "ok"; | 928 | status = "ok"; |
928 | pinctrl-names = "default", "sleep"; | 929 | pinctrl-names = "default", "sleep"; |
929 | pinctrl-0 = <&dcan1_pins_default>; | 930 | pinctrl-0 = <&dcan1_pins_default>; |
930 | pinctrl-1 = <&dcan1_pins_sleep>; | 931 | pinctrl-1 = <&dcan1_pins_sleep>; |
931 | }; | 932 | }; |
932 | 933 |