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Commit fa6d79d27614223d82418023b7f5300f1a1530d3

Authored by Santosh Shilimkar
1 parent 5698bd757d
Exists in master and in 20 other branches dlt-processor-sdk-linux-03.00.00.04, newt-ti-linux-3.12.y, processor-sdk-linux-01.00.00, processor-sdk-linux-02.00.01, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y, smarc-ti-linux-3.14.y, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.12.y, ti-linux-3.14.y, ti-linux-3.15.y, ti-lsk-linux-4.1.y

ARM: OMAP: Add initialisation for the real-time counter. 

The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.

The ratio registers needs to be configured based on system clock
only onetime. After initialisation, hardware takes care of adjusting
the clock in different low power modes to keep counter rate constant.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Showing 2 changed files with 93 additions and 1 deletions Inline Diff

arch/arm/mach-omap2/Kconfig
Diff comments   View file @ fa6d79d
1 if ARCH_OMAP2PLUS 1 if ARCH_OMAP2PLUS
2 2
3 menu "TI OMAP2/3/4 Specific Features" 3 menu "TI OMAP2/3/4 Specific Features"
4 4
5 config ARCH_OMAP2PLUS_TYPICAL 5 config ARCH_OMAP2PLUS_TYPICAL
6 bool "Typical OMAP configuration" 6 bool "Typical OMAP configuration"
7 default y 7 default y
8 select AEABI 8 select AEABI
9 select REGULATOR 9 select REGULATOR
10 select PM_RUNTIME 10 select PM_RUNTIME
11 select VFP 11 select VFP
12 select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 12 select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
13 select SERIAL_OMAP 13 select SERIAL_OMAP
14 select SERIAL_OMAP_CONSOLE 14 select SERIAL_OMAP_CONSOLE
15 select I2C 15 select I2C
16 select I2C_OMAP 16 select I2C_OMAP
17 select MENELAUS if ARCH_OMAP2 17 select MENELAUS if ARCH_OMAP2
18 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 18 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
19 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 19 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
20 select HIGHMEM 20 select HIGHMEM
21 help 21 help
22 Compile a kernel suitable for booting most boards 22 Compile a kernel suitable for booting most boards
23 23
24 config SOC_HAS_OMAP2_SDRC 24 config SOC_HAS_OMAP2_SDRC
25 bool "OMAP2 SDRAM Controller support" 25 bool "OMAP2 SDRAM Controller support"
26 26
27 config SOC_HAS_REALTIME_COUNTER
28 bool "Real time free running counter"
29
27 config ARCH_OMAP2 30 config ARCH_OMAP2
28 bool "TI OMAP2" 31 bool "TI OMAP2"
29 depends on ARCH_OMAP2PLUS 32 depends on ARCH_OMAP2PLUS
30 default y 33 default y
31 select CPU_V6 34 select CPU_V6
32 select MULTI_IRQ_HANDLER 35 select MULTI_IRQ_HANDLER
33 select SOC_HAS_OMAP2_SDRC 36 select SOC_HAS_OMAP2_SDRC
34 37
35 config ARCH_OMAP3 38 config ARCH_OMAP3
36 bool "TI OMAP3" 39 bool "TI OMAP3"
37 depends on ARCH_OMAP2PLUS 40 depends on ARCH_OMAP2PLUS
38 default y 41 default y
39 select CPU_V7 42 select CPU_V7
40 select USB_ARCH_HAS_EHCI if USB_SUPPORT 43 select USB_ARCH_HAS_EHCI if USB_SUPPORT
41 select ARCH_HAS_OPP 44 select ARCH_HAS_OPP
42 select PM_RUNTIME if CPU_IDLE 45 select PM_RUNTIME if CPU_IDLE
43 select PM_OPP if PM 46 select PM_OPP if PM
44 select ARM_CPU_SUSPEND if PM 47 select ARM_CPU_SUSPEND if PM
45 select MULTI_IRQ_HANDLER 48 select MULTI_IRQ_HANDLER
46 select SOC_HAS_OMAP2_SDRC 49 select SOC_HAS_OMAP2_SDRC
47 50
48 config ARCH_OMAP4 51 config ARCH_OMAP4
49 bool "TI OMAP4" 52 bool "TI OMAP4"
50 default y 53 default y
51 depends on ARCH_OMAP2PLUS 54 depends on ARCH_OMAP2PLUS
52 select CACHE_L2X0 55 select CACHE_L2X0
53 select CPU_V7 56 select CPU_V7
54 select ARM_GIC 57 select ARM_GIC
55 select HAVE_SMP 58 select HAVE_SMP
56 select LOCAL_TIMERS if SMP 59 select LOCAL_TIMERS if SMP
57 select PL310_ERRATA_588369 60 select PL310_ERRATA_588369
58 select PL310_ERRATA_727915 61 select PL310_ERRATA_727915
59 select ARM_ERRATA_720789 62 select ARM_ERRATA_720789
60 select ARCH_HAS_OPP 63 select ARCH_HAS_OPP
61 select PM_RUNTIME if CPU_IDLE 64 select PM_RUNTIME if CPU_IDLE
62 select PM_OPP if PM 65 select PM_OPP if PM
63 select USB_ARCH_HAS_EHCI if USB_SUPPORT 66 select USB_ARCH_HAS_EHCI if USB_SUPPORT
64 select ARM_CPU_SUSPEND if PM 67 select ARM_CPU_SUSPEND if PM
65 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 68 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
66 69
67 config SOC_OMAP5 70 config SOC_OMAP5
68 bool "TI OMAP5" 71 bool "TI OMAP5"
69 select CPU_V7 72 select CPU_V7
70 select ARM_GIC 73 select ARM_GIC
71 select HAVE_SMP 74 select HAVE_SMP
72 select ARM_CPU_SUSPEND if PM 75 select ARM_CPU_SUSPEND if PM
76 select SOC_HAS_REALTIME_COUNTER
73 77
74 comment "OMAP Core Type" 78 comment "OMAP Core Type"
75 depends on ARCH_OMAP2 79 depends on ARCH_OMAP2
76 80
77 config SOC_OMAP2420 81 config SOC_OMAP2420
78 bool "OMAP2420 support" 82 bool "OMAP2420 support"
79 depends on ARCH_OMAP2 83 depends on ARCH_OMAP2
80 default y 84 default y
81 select OMAP_DM_TIMER 85 select OMAP_DM_TIMER
82 select SOC_HAS_OMAP2_SDRC 86 select SOC_HAS_OMAP2_SDRC
83 87
84 config SOC_OMAP2430 88 config SOC_OMAP2430
85 bool "OMAP2430 support" 89 bool "OMAP2430 support"
86 depends on ARCH_OMAP2 90 depends on ARCH_OMAP2
87 default y 91 default y
88 select SOC_HAS_OMAP2_SDRC 92 select SOC_HAS_OMAP2_SDRC
89 93
90 config SOC_OMAP3430 94 config SOC_OMAP3430
91 bool "OMAP3430 support" 95 bool "OMAP3430 support"
92 depends on ARCH_OMAP3 96 depends on ARCH_OMAP3
93 default y 97 default y
94 select SOC_HAS_OMAP2_SDRC 98 select SOC_HAS_OMAP2_SDRC
95 99
96 config SOC_TI81XX 100 config SOC_TI81XX
97 bool "TI81XX support" 101 bool "TI81XX support"
98 depends on ARCH_OMAP3 102 depends on ARCH_OMAP3
99 default y 103 default y
100 104
101 config SOC_AM33XX 105 config SOC_AM33XX
102 bool "AM33XX support" 106 bool "AM33XX support"
103 default y 107 default y
104 select CPU_V7 108 select CPU_V7
105 select ARM_CPU_SUSPEND if PM 109 select ARM_CPU_SUSPEND if PM
106 select MULTI_IRQ_HANDLER 110 select MULTI_IRQ_HANDLER
107 111
108 config OMAP_PACKAGE_ZAF 112 config OMAP_PACKAGE_ZAF
109 bool 113 bool
110 114
111 config OMAP_PACKAGE_ZAC 115 config OMAP_PACKAGE_ZAC
112 bool 116 bool
113 117
114 config OMAP_PACKAGE_CBC 118 config OMAP_PACKAGE_CBC
115 bool 119 bool
116 120
117 config OMAP_PACKAGE_CBB 121 config OMAP_PACKAGE_CBB
118 bool 122 bool
119 123
120 config OMAP_PACKAGE_CUS 124 config OMAP_PACKAGE_CUS
121 bool 125 bool
122 126
123 config OMAP_PACKAGE_CBP 127 config OMAP_PACKAGE_CBP
124 bool 128 bool
125 129
126 config OMAP_PACKAGE_CBL 130 config OMAP_PACKAGE_CBL
127 bool 131 bool
128 132
129 config OMAP_PACKAGE_CBS 133 config OMAP_PACKAGE_CBS
130 bool 134 bool
131 135
132 comment "OMAP Board Type" 136 comment "OMAP Board Type"
133 depends on ARCH_OMAP2PLUS 137 depends on ARCH_OMAP2PLUS
134 138
135 config MACH_OMAP_GENERIC 139 config MACH_OMAP_GENERIC
136 bool "Generic OMAP2+ board" 140 bool "Generic OMAP2+ board"
137 depends on ARCH_OMAP2PLUS 141 depends on ARCH_OMAP2PLUS
138 default y 142 default y
139 help 143 help
140 Support for generic TI OMAP2+ boards using Flattened Device Tree. 144 Support for generic TI OMAP2+ boards using Flattened Device Tree.
141 More information at Documentation/devicetree 145 More information at Documentation/devicetree
142 146
143 config MACH_OMAP2_TUSB6010 147 config MACH_OMAP2_TUSB6010
144 bool 148 bool
145 depends on ARCH_OMAP2 && SOC_OMAP2420 149 depends on ARCH_OMAP2 && SOC_OMAP2420
146 default y if MACH_NOKIA_N8X0 150 default y if MACH_NOKIA_N8X0
147 151
148 config MACH_OMAP_H4 152 config MACH_OMAP_H4
149 bool "OMAP 2420 H4 board" 153 bool "OMAP 2420 H4 board"
150 depends on SOC_OMAP2420 154 depends on SOC_OMAP2420
151 default y 155 default y
152 select OMAP_PACKAGE_ZAF 156 select OMAP_PACKAGE_ZAF
153 select OMAP_DEBUG_DEVICES 157 select OMAP_DEBUG_DEVICES
154 158
155 config MACH_OMAP_APOLLON 159 config MACH_OMAP_APOLLON
156 bool "OMAP 2420 Apollon board" 160 bool "OMAP 2420 Apollon board"
157 depends on SOC_OMAP2420 161 depends on SOC_OMAP2420
158 default y 162 default y
159 select OMAP_PACKAGE_ZAC 163 select OMAP_PACKAGE_ZAC
160 164
161 config MACH_OMAP_2430SDP 165 config MACH_OMAP_2430SDP
162 bool "OMAP 2430 SDP board" 166 bool "OMAP 2430 SDP board"
163 depends on SOC_OMAP2430 167 depends on SOC_OMAP2430
164 default y 168 default y
165 select OMAP_PACKAGE_ZAC 169 select OMAP_PACKAGE_ZAC
166 170
167 config MACH_OMAP3_BEAGLE 171 config MACH_OMAP3_BEAGLE
168 bool "OMAP3 BEAGLE board" 172 bool "OMAP3 BEAGLE board"
169 depends on ARCH_OMAP3 173 depends on ARCH_OMAP3
170 default y 174 default y
171 select OMAP_PACKAGE_CBB 175 select OMAP_PACKAGE_CBB
172 176
173 config MACH_DEVKIT8000 177 config MACH_DEVKIT8000
174 bool "DEVKIT8000 board" 178 bool "DEVKIT8000 board"
175 depends on ARCH_OMAP3 179 depends on ARCH_OMAP3
176 default y 180 default y
177 select OMAP_PACKAGE_CUS 181 select OMAP_PACKAGE_CUS
178 182
179 config MACH_OMAP_LDP 183 config MACH_OMAP_LDP
180 bool "OMAP3 LDP board" 184 bool "OMAP3 LDP board"
181 depends on ARCH_OMAP3 185 depends on ARCH_OMAP3
182 default y 186 default y
183 select OMAP_PACKAGE_CBB 187 select OMAP_PACKAGE_CBB
184 188
185 config MACH_OMAP3530_LV_SOM 189 config MACH_OMAP3530_LV_SOM
186 bool "OMAP3 Logic 3530 LV SOM board" 190 bool "OMAP3 Logic 3530 LV SOM board"
187 depends on ARCH_OMAP3 191 depends on ARCH_OMAP3
188 select OMAP_PACKAGE_CBB 192 select OMAP_PACKAGE_CBB
189 default y 193 default y
190 help 194 help
191 Support for the LogicPD OMAP3530 SOM Development kit 195 Support for the LogicPD OMAP3530 SOM Development kit
192 for full description please see the products webpage at 196 for full description please see the products webpage at
193 http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit 197 http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit
194 198
195 config MACH_OMAP3_TORPEDO 199 config MACH_OMAP3_TORPEDO
196 bool "OMAP3 Logic 35x Torpedo board" 200 bool "OMAP3 Logic 35x Torpedo board"
197 depends on ARCH_OMAP3 201 depends on ARCH_OMAP3
198 select OMAP_PACKAGE_CBB 202 select OMAP_PACKAGE_CBB
199 default y 203 default y
200 help 204 help
201 Support for the LogicPD OMAP35x Torpedo Development kit 205 Support for the LogicPD OMAP35x Torpedo Development kit
202 for full description please see the products webpage at 206 for full description please see the products webpage at
203 http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit 207 http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
204 208
205 config MACH_OVERO 209 config MACH_OVERO
206 bool "Gumstix Overo board" 210 bool "Gumstix Overo board"
207 depends on ARCH_OMAP3 211 depends on ARCH_OMAP3
208 default y 212 default y
209 select OMAP_PACKAGE_CBB 213 select OMAP_PACKAGE_CBB
210 214
211 config MACH_OMAP3EVM 215 config MACH_OMAP3EVM
212 bool "OMAP 3530 EVM board" 216 bool "OMAP 3530 EVM board"
213 depends on ARCH_OMAP3 217 depends on ARCH_OMAP3
214 default y 218 default y
215 select OMAP_PACKAGE_CBB 219 select OMAP_PACKAGE_CBB
216 220
217 config MACH_OMAP3517EVM 221 config MACH_OMAP3517EVM
218 bool "OMAP3517/ AM3517 EVM board" 222 bool "OMAP3517/ AM3517 EVM board"
219 depends on ARCH_OMAP3 223 depends on ARCH_OMAP3
220 default y 224 default y
221 select OMAP_PACKAGE_CBB 225 select OMAP_PACKAGE_CBB
222 226
223 config MACH_CRANEBOARD 227 config MACH_CRANEBOARD
224 bool "AM3517/05 CRANE board" 228 bool "AM3517/05 CRANE board"
225 depends on ARCH_OMAP3 229 depends on ARCH_OMAP3
226 select OMAP_PACKAGE_CBB 230 select OMAP_PACKAGE_CBB
227 231
228 config MACH_OMAP3_PANDORA 232 config MACH_OMAP3_PANDORA
229 bool "OMAP3 Pandora" 233 bool "OMAP3 Pandora"
230 depends on ARCH_OMAP3 234 depends on ARCH_OMAP3
231 default y 235 default y
232 select OMAP_PACKAGE_CBB 236 select OMAP_PACKAGE_CBB
233 select REGULATOR_FIXED_VOLTAGE if REGULATOR 237 select REGULATOR_FIXED_VOLTAGE if REGULATOR
234 238
235 config MACH_TOUCHBOOK 239 config MACH_TOUCHBOOK
236 bool "OMAP3 Touch Book" 240 bool "OMAP3 Touch Book"
237 depends on ARCH_OMAP3 241 depends on ARCH_OMAP3
238 default y 242 default y
239 select OMAP_PACKAGE_CBB 243 select OMAP_PACKAGE_CBB
240 244
241 config MACH_OMAP_3430SDP 245 config MACH_OMAP_3430SDP
242 bool "OMAP 3430 SDP board" 246 bool "OMAP 3430 SDP board"
243 depends on ARCH_OMAP3 247 depends on ARCH_OMAP3
244 default y 248 default y
245 select OMAP_PACKAGE_CBB 249 select OMAP_PACKAGE_CBB
246 250
247 config MACH_NOKIA_N800 251 config MACH_NOKIA_N800
248 bool 252 bool
249 253
250 config MACH_NOKIA_N810 254 config MACH_NOKIA_N810
251 bool 255 bool
252 256
253 config MACH_NOKIA_N810_WIMAX 257 config MACH_NOKIA_N810_WIMAX
254 bool 258 bool
255 259
256 config MACH_NOKIA_N8X0 260 config MACH_NOKIA_N8X0
257 bool "Nokia N800/N810" 261 bool "Nokia N800/N810"
258 depends on SOC_OMAP2420 262 depends on SOC_OMAP2420
259 default y 263 default y
260 select OMAP_PACKAGE_ZAC 264 select OMAP_PACKAGE_ZAC
261 select MACH_NOKIA_N800 265 select MACH_NOKIA_N800
262 select MACH_NOKIA_N810 266 select MACH_NOKIA_N810
263 select MACH_NOKIA_N810_WIMAX 267 select MACH_NOKIA_N810_WIMAX
264 268
265 config MACH_NOKIA_RM680 269 config MACH_NOKIA_RM680
266 bool "Nokia RM-680/696 board" 270 bool "Nokia RM-680/696 board"
267 depends on ARCH_OMAP3 271 depends on ARCH_OMAP3
268 default y 272 default y
269 select OMAP_PACKAGE_CBB 273 select OMAP_PACKAGE_CBB
270 select MACH_NOKIA_RM696 274 select MACH_NOKIA_RM696
271 275
272 config MACH_NOKIA_RX51 276 config MACH_NOKIA_RX51
273 bool "Nokia RX-51 board" 277 bool "Nokia RX-51 board"
274 depends on ARCH_OMAP3 278 depends on ARCH_OMAP3
275 default y 279 default y
276 select OMAP_PACKAGE_CBB 280 select OMAP_PACKAGE_CBB
277 281
278 config MACH_OMAP_ZOOM2 282 config MACH_OMAP_ZOOM2
279 bool "OMAP3 Zoom2 board" 283 bool "OMAP3 Zoom2 board"
280 depends on ARCH_OMAP3 284 depends on ARCH_OMAP3
281 default y 285 default y
282 select OMAP_PACKAGE_CBB 286 select OMAP_PACKAGE_CBB
283 select SERIAL_8250 287 select SERIAL_8250
284 select SERIAL_CORE_CONSOLE 288 select SERIAL_CORE_CONSOLE
285 select SERIAL_8250_CONSOLE 289 select SERIAL_8250_CONSOLE
286 select REGULATOR_FIXED_VOLTAGE if REGULATOR 290 select REGULATOR_FIXED_VOLTAGE if REGULATOR
287 291
288 config MACH_OMAP_ZOOM3 292 config MACH_OMAP_ZOOM3
289 bool "OMAP3630 Zoom3 board" 293 bool "OMAP3630 Zoom3 board"
290 depends on ARCH_OMAP3 294 depends on ARCH_OMAP3
291 default y 295 default y
292 select OMAP_PACKAGE_CBP 296 select OMAP_PACKAGE_CBP
293 select SERIAL_8250 297 select SERIAL_8250
294 select SERIAL_CORE_CONSOLE 298 select SERIAL_CORE_CONSOLE
295 select SERIAL_8250_CONSOLE 299 select SERIAL_8250_CONSOLE
296 select REGULATOR_FIXED_VOLTAGE if REGULATOR 300 select REGULATOR_FIXED_VOLTAGE if REGULATOR
297 301
298 config MACH_CM_T35 302 config MACH_CM_T35
299 bool "CompuLab CM-T35/CM-T3730 modules" 303 bool "CompuLab CM-T35/CM-T3730 modules"
300 depends on ARCH_OMAP3 304 depends on ARCH_OMAP3
301 default y 305 default y
302 select MACH_CM_T3730 306 select MACH_CM_T3730
303 select OMAP_PACKAGE_CUS 307 select OMAP_PACKAGE_CUS
304 308
305 config MACH_CM_T3517 309 config MACH_CM_T3517
306 bool "CompuLab CM-T3517 module" 310 bool "CompuLab CM-T3517 module"
307 depends on ARCH_OMAP3 311 depends on ARCH_OMAP3
308 default y 312 default y
309 select OMAP_PACKAGE_CBB 313 select OMAP_PACKAGE_CBB
310 314
311 config MACH_CM_T3730 315 config MACH_CM_T3730
312 bool 316 bool
313 317
314 config MACH_IGEP0020 318 config MACH_IGEP0020
315 bool "IGEP v2 board" 319 bool "IGEP v2 board"
316 depends on ARCH_OMAP3 320 depends on ARCH_OMAP3
317 default y 321 default y
318 select OMAP_PACKAGE_CBB 322 select OMAP_PACKAGE_CBB
319 323
320 config MACH_IGEP0030 324 config MACH_IGEP0030
321 bool "IGEP OMAP3 module" 325 bool "IGEP OMAP3 module"
322 depends on ARCH_OMAP3 326 depends on ARCH_OMAP3
323 default y 327 default y
324 select OMAP_PACKAGE_CBB 328 select OMAP_PACKAGE_CBB
325 select MACH_IGEP0020 329 select MACH_IGEP0020
326 330
327 config MACH_SBC3530 331 config MACH_SBC3530
328 bool "OMAP3 SBC STALKER board" 332 bool "OMAP3 SBC STALKER board"
329 depends on ARCH_OMAP3 333 depends on ARCH_OMAP3
330 default y 334 default y
331 select OMAP_PACKAGE_CUS 335 select OMAP_PACKAGE_CUS
332 336
333 config MACH_OMAP_3630SDP 337 config MACH_OMAP_3630SDP
334 bool "OMAP3630 SDP board" 338 bool "OMAP3630 SDP board"
335 depends on ARCH_OMAP3 339 depends on ARCH_OMAP3
336 default y 340 default y
337 select OMAP_PACKAGE_CBP 341 select OMAP_PACKAGE_CBP
338 342
339 config MACH_TI8168EVM 343 config MACH_TI8168EVM
340 bool "TI8168 Evaluation Module" 344 bool "TI8168 Evaluation Module"
341 depends on SOC_TI81XX 345 depends on SOC_TI81XX
342 default y 346 default y
343 347
344 config MACH_TI8148EVM 348 config MACH_TI8148EVM
345 bool "TI8148 Evaluation Module" 349 bool "TI8148 Evaluation Module"
346 depends on SOC_TI81XX 350 depends on SOC_TI81XX
347 default y 351 default y
348 352
349 config MACH_OMAP_4430SDP 353 config MACH_OMAP_4430SDP
350 bool "OMAP 4430 SDP board" 354 bool "OMAP 4430 SDP board"
351 default y 355 default y
352 depends on ARCH_OMAP4 356 depends on ARCH_OMAP4
353 select OMAP_PACKAGE_CBL 357 select OMAP_PACKAGE_CBL
354 select OMAP_PACKAGE_CBS 358 select OMAP_PACKAGE_CBS
355 select REGULATOR_FIXED_VOLTAGE if REGULATOR 359 select REGULATOR_FIXED_VOLTAGE if REGULATOR
356 360
357 config MACH_OMAP4_PANDA 361 config MACH_OMAP4_PANDA
358 bool "OMAP4 Panda Board" 362 bool "OMAP4 Panda Board"
359 default y 363 default y
360 depends on ARCH_OMAP4 364 depends on ARCH_OMAP4
361 select OMAP_PACKAGE_CBL 365 select OMAP_PACKAGE_CBL
362 select OMAP_PACKAGE_CBS 366 select OMAP_PACKAGE_CBS
363 select REGULATOR_FIXED_VOLTAGE if REGULATOR 367 select REGULATOR_FIXED_VOLTAGE if REGULATOR
364 368
365 config OMAP3_EMU 369 config OMAP3_EMU
366 bool "OMAP3 debugging peripherals" 370 bool "OMAP3 debugging peripherals"
367 depends on ARCH_OMAP3 371 depends on ARCH_OMAP3
368 select ARM_AMBA 372 select ARM_AMBA
369 select OC_ETM 373 select OC_ETM
370 help 374 help
371 Say Y here to enable debugging hardware of omap3 375 Say Y here to enable debugging hardware of omap3
372 376
373 config OMAP3_SDRC_AC_TIMING 377 config OMAP3_SDRC_AC_TIMING
374 bool "Enable SDRC AC timing register changes" 378 bool "Enable SDRC AC timing register changes"
375 depends on ARCH_OMAP3 379 depends on ARCH_OMAP3
376 default n 380 default n
377 help 381 help
378 If you know that none of your system initiators will attempt to 382 If you know that none of your system initiators will attempt to
379 access SDRAM during CORE DVFS, select Y here. This should boost 383 access SDRAM during CORE DVFS, select Y here. This should boost
380 SDRAM performance at lower CORE OPPs. There are relatively few 384 SDRAM performance at lower CORE OPPs. There are relatively few
381 users who will wish to say yes at this point - almost everyone will 385 users who will wish to say yes at this point - almost everyone will
382 wish to say no. Selecting yes without understanding what is 386 wish to say no. Selecting yes without understanding what is
383 going on could result in system crashes; 387 going on could result in system crashes;
384 388
385 config OMAP4_ERRATA_I688 389 config OMAP4_ERRATA_I688
386 bool "OMAP4 errata: Async Bridge Corruption" 390 bool "OMAP4 errata: Async Bridge Corruption"
387 depends on ARCH_OMAP4 391 depends on ARCH_OMAP4
388 select ARCH_HAS_BARRIERS 392 select ARCH_HAS_BARRIERS
389 help 393 help
390 If a data is stalled inside asynchronous bridge because of back 394 If a data is stalled inside asynchronous bridge because of back
391 pressure, it may be accepted multiple times, creating pointer 395 pressure, it may be accepted multiple times, creating pointer
392 misalignment that will corrupt next transfers on that data path 396 misalignment that will corrupt next transfers on that data path
393 until next reset of the system (No recovery procedure once the 397 until next reset of the system (No recovery procedure once the
394 issue is hit, the path remains consistently broken). Async bridge 398 issue is hit, the path remains consistently broken). Async bridge
395 can be found on path between MPU to EMIF and MPU to L3 interconnect. 399 can be found on path between MPU to EMIF and MPU to L3 interconnect.
396 This situation can happen only when the idle is initiated by a 400 This situation can happen only when the idle is initiated by a
397 Master Request Disconnection (which is trigged by software when 401 Master Request Disconnection (which is trigged by software when
398 executing WFI on CPU). 402 executing WFI on CPU).
399 The work-around for this errata needs all the initiators connected 403 The work-around for this errata needs all the initiators connected
400 through async bridge must ensure that data path is properly drained 404 through async bridge must ensure that data path is properly drained
401 before issuing WFI. This condition will be met if one Strongly ordered 405 before issuing WFI. This condition will be met if one Strongly ordered
402 access is performed to the target right before executing the WFI. 406 access is performed to the target right before executing the WFI.
403 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. 407 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
404 IO barrier ensure that there is no synchronisation loss on initiators 408 IO barrier ensure that there is no synchronisation loss on initiators
405 operating on both interconnect port simultaneously. 409 operating on both interconnect port simultaneously.
406 endmenu 410 endmenu
407 411
408 endif 412 endif
409 413
arch/arm/mach-omap2/timer.c
Diff comments   View file @ fa6d79d
1 /* 1 /*
2 * linux/arch/arm/mach-omap2/timer.c 2 * linux/arch/arm/mach-omap2/timer.c
3 * 3 *
4 * OMAP2 GP timer support. 4 * OMAP2 GP timer support.
5 * 5 *
6 * Copyright (C) 2009 Nokia Corporation 6 * Copyright (C) 2009 Nokia Corporation
7 * 7 *
8 * Update to use new clocksource/clockevent layers 8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc. 10 * Copyright (C) 2007 MontaVista Software, Inc.
11 * 11 *
12 * Original driver: 12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation 13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com> 14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjรถlรค <juha.yrjola@nokia.com> 15 * Juha Yrjรถlรค <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras 16 * OMAP Dual-mode timer framework support by Timo Teras
17 * 17 *
18 * Some parts based off of TI's 24xx code: 18 * Some parts based off of TI's 24xx code:
19 * 19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 * 21 *
22 * Roughly modelled after the OMAP1 MPU timer code. 22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 * 24 *
25 * This file is subject to the terms and conditions of the GNU General Public 25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive 26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details. 27 * for more details.
28 */ 28 */
29 #include <linux/init.h> 29 #include <linux/init.h>
30 #include <linux/time.h> 30 #include <linux/time.h>
31 #include <linux/interrupt.h> 31 #include <linux/interrupt.h>
32 #include <linux/err.h> 32 #include <linux/err.h>
33 #include <linux/clk.h> 33 #include <linux/clk.h>
34 #include <linux/delay.h> 34 #include <linux/delay.h>
35 #include <linux/irq.h> 35 #include <linux/irq.h>
36 #include <linux/clocksource.h> 36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h> 37 #include <linux/clockchips.h>
38 #include <linux/slab.h> 38 #include <linux/slab.h>
39 39
40 #include <asm/mach/time.h> 40 #include <asm/mach/time.h>
41 #include <plat/dmtimer.h> 41 #include <plat/dmtimer.h>
42 #include <asm/smp_twd.h> 42 #include <asm/smp_twd.h>
43 #include <asm/sched_clock.h> 43 #include <asm/sched_clock.h>
44 #include "common.h" 44 #include "common.h"
45 #include <plat/omap_hwmod.h> 45 #include <plat/omap_hwmod.h>
46 #include <plat/omap_device.h> 46 #include <plat/omap_device.h>
47 #include <plat/omap-pm.h> 47 #include <plat/omap-pm.h>
48 48
49 #include "powerdomain.h" 49 #include "powerdomain.h"
50 50
51 /* Parent clocks, eventually these will come from the clock framework */ 51 /* Parent clocks, eventually these will come from the clock framework */
52 52
53 #define OMAP2_MPU_SOURCE "sys_ck" 53 #define OMAP2_MPU_SOURCE "sys_ck"
54 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE 54 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
55 #define OMAP4_MPU_SOURCE "sys_clkin_ck" 55 #define OMAP4_MPU_SOURCE "sys_clkin_ck"
56 #define OMAP2_32K_SOURCE "func_32k_ck" 56 #define OMAP2_32K_SOURCE "func_32k_ck"
57 #define OMAP3_32K_SOURCE "omap_32k_fck" 57 #define OMAP3_32K_SOURCE "omap_32k_fck"
58 #define OMAP4_32K_SOURCE "sys_32k_ck" 58 #define OMAP4_32K_SOURCE "sys_32k_ck"
59 59
60 #ifdef CONFIG_OMAP_32K_TIMER 60 #ifdef CONFIG_OMAP_32K_TIMER
61 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE 61 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
62 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE 62 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
63 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE 63 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
64 #define OMAP3_SECURE_TIMER 12 64 #define OMAP3_SECURE_TIMER 12
65 #else 65 #else
66 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE 66 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
67 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE 67 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
68 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE 68 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
69 #define OMAP3_SECURE_TIMER 1 69 #define OMAP3_SECURE_TIMER 1
70 #endif 70 #endif
71 71
72 #define REALTIME_COUNTER_BASE 0x48243200
73 #define INCREMENTER_NUMERATOR_OFFSET 0x10
74 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
75 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
76
72 /* Clockevent code */ 77 /* Clockevent code */
73 78
74 static struct omap_dm_timer clkev; 79 static struct omap_dm_timer clkev;
75 static struct clock_event_device clockevent_gpt; 80 static struct clock_event_device clockevent_gpt;
76 81
77 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 82 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
78 { 83 {
79 struct clock_event_device *evt = &clockevent_gpt; 84 struct clock_event_device *evt = &clockevent_gpt;
80 85
81 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 86 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
82 87
83 evt->event_handler(evt); 88 evt->event_handler(evt);
84 return IRQ_HANDLED; 89 return IRQ_HANDLED;
85 } 90 }
86 91
87 static struct irqaction omap2_gp_timer_irq = { 92 static struct irqaction omap2_gp_timer_irq = {
88 .name = "gp_timer", 93 .name = "gp_timer",
89 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 94 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
90 .handler = omap2_gp_timer_interrupt, 95 .handler = omap2_gp_timer_interrupt,
91 }; 96 };
92 97
93 static int omap2_gp_timer_set_next_event(unsigned long cycles, 98 static int omap2_gp_timer_set_next_event(unsigned long cycles,
94 struct clock_event_device *evt) 99 struct clock_event_device *evt)
95 { 100 {
96 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 101 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
97 0xffffffff - cycles, 1); 102 0xffffffff - cycles, 1);
98 103
99 return 0; 104 return 0;
100 } 105 }
101 106
102 static void omap2_gp_timer_set_mode(enum clock_event_mode mode, 107 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
103 struct clock_event_device *evt) 108 struct clock_event_device *evt)
104 { 109 {
105 u32 period; 110 u32 period;
106 111
107 __omap_dm_timer_stop(&clkev, 1, clkev.rate); 112 __omap_dm_timer_stop(&clkev, 1, clkev.rate);
108 113
109 switch (mode) { 114 switch (mode) {
110 case CLOCK_EVT_MODE_PERIODIC: 115 case CLOCK_EVT_MODE_PERIODIC:
111 period = clkev.rate / HZ; 116 period = clkev.rate / HZ;
112 period -= 1; 117 period -= 1;
113 /* Looks like we need to first set the load value separately */ 118 /* Looks like we need to first set the load value separately */
114 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 119 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
115 0xffffffff - period, 1); 120 0xffffffff - period, 1);
116 __omap_dm_timer_load_start(&clkev, 121 __omap_dm_timer_load_start(&clkev,
117 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 122 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
118 0xffffffff - period, 1); 123 0xffffffff - period, 1);
119 break; 124 break;
120 case CLOCK_EVT_MODE_ONESHOT: 125 case CLOCK_EVT_MODE_ONESHOT:
121 break; 126 break;
122 case CLOCK_EVT_MODE_UNUSED: 127 case CLOCK_EVT_MODE_UNUSED:
123 case CLOCK_EVT_MODE_SHUTDOWN: 128 case CLOCK_EVT_MODE_SHUTDOWN:
124 case CLOCK_EVT_MODE_RESUME: 129 case CLOCK_EVT_MODE_RESUME:
125 break; 130 break;
126 } 131 }
127 } 132 }
128 133
129 static struct clock_event_device clockevent_gpt = { 134 static struct clock_event_device clockevent_gpt = {
130 .name = "gp_timer", 135 .name = "gp_timer",
131 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 136 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
132 .shift = 32, 137 .shift = 32,
133 .rating = 300, 138 .rating = 300,
134 .set_next_event = omap2_gp_timer_set_next_event, 139 .set_next_event = omap2_gp_timer_set_next_event,
135 .set_mode = omap2_gp_timer_set_mode, 140 .set_mode = omap2_gp_timer_set_mode,
136 }; 141 };
137 142
138 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 143 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
139 int gptimer_id, 144 int gptimer_id,
140 const char *fck_source) 145 const char *fck_source)
141 { 146 {
142 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 147 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
143 struct omap_hwmod *oh; 148 struct omap_hwmod *oh;
144 struct resource irq_rsrc, mem_rsrc; 149 struct resource irq_rsrc, mem_rsrc;
145 size_t size; 150 size_t size;
146 int res = 0; 151 int res = 0;
147 int r; 152 int r;
148 153
149 sprintf(name, "timer%d", gptimer_id); 154 sprintf(name, "timer%d", gptimer_id);
150 omap_hwmod_setup_one(name); 155 omap_hwmod_setup_one(name);
151 oh = omap_hwmod_lookup(name); 156 oh = omap_hwmod_lookup(name);
152 if (!oh) 157 if (!oh)
153 return -ENODEV; 158 return -ENODEV;
154 159
155 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); 160 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
156 if (r) 161 if (r)
157 return -ENXIO; 162 return -ENXIO;
158 timer->irq = irq_rsrc.start; 163 timer->irq = irq_rsrc.start;
159 164
160 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); 165 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
161 if (r) 166 if (r)
162 return -ENXIO; 167 return -ENXIO;
163 timer->phys_base = mem_rsrc.start; 168 timer->phys_base = mem_rsrc.start;
164 size = mem_rsrc.end - mem_rsrc.start; 169 size = mem_rsrc.end - mem_rsrc.start;
165 170
166 /* Static mapping, never released */ 171 /* Static mapping, never released */
167 timer->io_base = ioremap(timer->phys_base, size); 172 timer->io_base = ioremap(timer->phys_base, size);
168 if (!timer->io_base) 173 if (!timer->io_base)
169 return -ENXIO; 174 return -ENXIO;
170 175
171 /* After the dmtimer is using hwmod these clocks won't be needed */ 176 /* After the dmtimer is using hwmod these clocks won't be needed */
172 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 177 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
173 if (IS_ERR(timer->fclk)) 178 if (IS_ERR(timer->fclk))
174 return -ENODEV; 179 return -ENODEV;
175 180
176 omap_hwmod_enable(oh); 181 omap_hwmod_enable(oh);
177 182
178 if (omap_dm_timer_reserve_systimer(gptimer_id)) 183 if (omap_dm_timer_reserve_systimer(gptimer_id))
179 return -ENODEV; 184 return -ENODEV;
180 185
181 if (gptimer_id != 12) { 186 if (gptimer_id != 12) {
182 struct clk *src; 187 struct clk *src;
183 188
184 src = clk_get(NULL, fck_source); 189 src = clk_get(NULL, fck_source);
185 if (IS_ERR(src)) { 190 if (IS_ERR(src)) {
186 res = -EINVAL; 191 res = -EINVAL;
187 } else { 192 } else {
188 res = __omap_dm_timer_set_source(timer->fclk, src); 193 res = __omap_dm_timer_set_source(timer->fclk, src);
189 if (IS_ERR_VALUE(res)) 194 if (IS_ERR_VALUE(res))
190 pr_warning("%s: timer%i cannot set source\n", 195 pr_warning("%s: timer%i cannot set source\n",
191 __func__, gptimer_id); 196 __func__, gptimer_id);
192 clk_put(src); 197 clk_put(src);
193 } 198 }
194 } 199 }
195 __omap_dm_timer_init_regs(timer); 200 __omap_dm_timer_init_regs(timer);
196 __omap_dm_timer_reset(timer, 1, 1); 201 __omap_dm_timer_reset(timer, 1, 1);
197 timer->posted = 1; 202 timer->posted = 1;
198 203
199 timer->rate = clk_get_rate(timer->fclk); 204 timer->rate = clk_get_rate(timer->fclk);
200 205
201 timer->reserved = 1; 206 timer->reserved = 1;
202 207
203 return res; 208 return res;
204 } 209 }
205 210
206 static void __init omap2_gp_clockevent_init(int gptimer_id, 211 static void __init omap2_gp_clockevent_init(int gptimer_id,
207 const char *fck_source) 212 const char *fck_source)
208 { 213 {
209 int res; 214 int res;
210 215
211 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); 216 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
212 BUG_ON(res); 217 BUG_ON(res);
213 218
214 omap2_gp_timer_irq.dev_id = (void *)&clkev; 219 omap2_gp_timer_irq.dev_id = (void *)&clkev;
215 setup_irq(clkev.irq, &omap2_gp_timer_irq); 220 setup_irq(clkev.irq, &omap2_gp_timer_irq);
216 221
217 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 222 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
218 223
219 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, 224 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
220 clockevent_gpt.shift); 225 clockevent_gpt.shift);
221 clockevent_gpt.max_delta_ns = 226 clockevent_gpt.max_delta_ns =
222 clockevent_delta2ns(0xffffffff, &clockevent_gpt); 227 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
223 clockevent_gpt.min_delta_ns = 228 clockevent_gpt.min_delta_ns =
224 clockevent_delta2ns(3, &clockevent_gpt); 229 clockevent_delta2ns(3, &clockevent_gpt);
225 /* Timer internal resynch latency. */ 230 /* Timer internal resynch latency. */
226 231
227 clockevent_gpt.cpumask = cpu_possible_mask; 232 clockevent_gpt.cpumask = cpu_possible_mask;
228 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 233 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
229 clockevents_register_device(&clockevent_gpt); 234 clockevents_register_device(&clockevent_gpt);
230 235
231 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", 236 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
232 gptimer_id, clkev.rate); 237 gptimer_id, clkev.rate);
233 } 238 }
234 239
235 /* Clocksource code */ 240 /* Clocksource code */
236 static struct omap_dm_timer clksrc; 241 static struct omap_dm_timer clksrc;
237 static bool use_gptimer_clksrc; 242 static bool use_gptimer_clksrc;
238 243
239 /* 244 /*
240 * clocksource 245 * clocksource
241 */ 246 */
242 static cycle_t clocksource_read_cycles(struct clocksource *cs) 247 static cycle_t clocksource_read_cycles(struct clocksource *cs)
243 { 248 {
244 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); 249 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
245 } 250 }
246 251
247 static struct clocksource clocksource_gpt = { 252 static struct clocksource clocksource_gpt = {
248 .name = "gp_timer", 253 .name = "gp_timer",
249 .rating = 300, 254 .rating = 300,
250 .read = clocksource_read_cycles, 255 .read = clocksource_read_cycles,
251 .mask = CLOCKSOURCE_MASK(32), 256 .mask = CLOCKSOURCE_MASK(32),
252 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 257 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
253 }; 258 };
254 259
255 static u32 notrace dmtimer_read_sched_clock(void) 260 static u32 notrace dmtimer_read_sched_clock(void)
256 { 261 {
257 if (clksrc.reserved) 262 if (clksrc.reserved)
258 return __omap_dm_timer_read_counter(&clksrc, 1); 263 return __omap_dm_timer_read_counter(&clksrc, 1);
259 264
260 return 0; 265 return 0;
261 } 266 }
262 267
263 #ifdef CONFIG_OMAP_32K_TIMER 268 #ifdef CONFIG_OMAP_32K_TIMER
264 /* Setup free-running counter for clocksource */ 269 /* Setup free-running counter for clocksource */
265 static int __init omap2_sync32k_clocksource_init(void) 270 static int __init omap2_sync32k_clocksource_init(void)
266 { 271 {
267 int ret; 272 int ret;
268 struct omap_hwmod *oh; 273 struct omap_hwmod *oh;
269 void __iomem *vbase; 274 void __iomem *vbase;
270 const char *oh_name = "counter_32k"; 275 const char *oh_name = "counter_32k";
271 276
272 /* 277 /*
273 * First check hwmod data is available for sync32k counter 278 * First check hwmod data is available for sync32k counter
274 */ 279 */
275 oh = omap_hwmod_lookup(oh_name); 280 oh = omap_hwmod_lookup(oh_name);
276 if (!oh || oh->slaves_cnt == 0) 281 if (!oh || oh->slaves_cnt == 0)
277 return -ENODEV; 282 return -ENODEV;
278 283
279 omap_hwmod_setup_one(oh_name); 284 omap_hwmod_setup_one(oh_name);
280 285
281 vbase = omap_hwmod_get_mpu_rt_va(oh); 286 vbase = omap_hwmod_get_mpu_rt_va(oh);
282 if (!vbase) { 287 if (!vbase) {
283 pr_warn("%s: failed to get counter_32k resource\n", __func__); 288 pr_warn("%s: failed to get counter_32k resource\n", __func__);
284 return -ENXIO; 289 return -ENXIO;
285 } 290 }
286 291
287 ret = omap_hwmod_enable(oh); 292 ret = omap_hwmod_enable(oh);
288 if (ret) { 293 if (ret) {
289 pr_warn("%s: failed to enable counter_32k module (%d)\n", 294 pr_warn("%s: failed to enable counter_32k module (%d)\n",
290 __func__, ret); 295 __func__, ret);
291 return ret; 296 return ret;
292 } 297 }
293 298
294 ret = omap_init_clocksource_32k(vbase); 299 ret = omap_init_clocksource_32k(vbase);
295 if (ret) { 300 if (ret) {
296 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", 301 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
297 __func__, ret); 302 __func__, ret);
298 omap_hwmod_idle(oh); 303 omap_hwmod_idle(oh);
299 } 304 }
300 305
301 return ret; 306 return ret;
302 } 307 }
303 #else 308 #else
304 static inline int omap2_sync32k_clocksource_init(void) 309 static inline int omap2_sync32k_clocksource_init(void)
305 { 310 {
306 return -ENODEV; 311 return -ENODEV;
307 } 312 }
308 #endif 313 #endif
309 314
310 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 315 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
311 const char *fck_source) 316 const char *fck_source)
312 { 317 {
313 int res; 318 int res;
314 319
315 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); 320 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
316 BUG_ON(res); 321 BUG_ON(res);
317 322
318 __omap_dm_timer_load_start(&clksrc, 323 __omap_dm_timer_load_start(&clksrc,
319 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); 324 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
320 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 325 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
321 326
322 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 327 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
323 pr_err("Could not register clocksource %s\n", 328 pr_err("Could not register clocksource %s\n",
324 clocksource_gpt.name); 329 clocksource_gpt.name);
325 else 330 else
326 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", 331 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
327 gptimer_id, clksrc.rate); 332 gptimer_id, clksrc.rate);
328 } 333 }
329 334
330 static void __init omap2_clocksource_init(int gptimer_id, 335 static void __init omap2_clocksource_init(int gptimer_id,
331 const char *fck_source) 336 const char *fck_source)
332 { 337 {
333 /* 338 /*
334 * First give preference to kernel parameter configuration 339 * First give preference to kernel parameter configuration
335 * by user (clocksource="gp_timer"). 340 * by user (clocksource="gp_timer").
336 * 341 *
337 * In case of missing kernel parameter for clocksource, 342 * In case of missing kernel parameter for clocksource,
338 * first check for availability for 32k-sync timer, in case 343 * first check for availability for 32k-sync timer, in case
339 * of failure in finding 32k_counter module or registering 344 * of failure in finding 32k_counter module or registering
340 * it as clocksource, execution will fallback to gp-timer. 345 * it as clocksource, execution will fallback to gp-timer.
341 */ 346 */
342 if (use_gptimer_clksrc == true) 347 if (use_gptimer_clksrc == true)
343 omap2_gptimer_clocksource_init(gptimer_id, fck_source); 348 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
344 else if (omap2_sync32k_clocksource_init()) 349 else if (omap2_sync32k_clocksource_init())
345 /* Fall back to gp-timer code */ 350 /* Fall back to gp-timer code */
346 omap2_gptimer_clocksource_init(gptimer_id, fck_source); 351 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
347 } 352 }
348 353
354 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
355 /*
356 * The realtime counter also called master counter, is a free-running
357 * counter, which is related to real time. It produces the count used
358 * by the CPU local timer peripherals in the MPU cluster. The timer counts
359 * at a rate of 6.144 MHz. Because the device operates on different clocks
360 * in different power modes, the master counter shifts operation between
361 * clocks, adjusting the increment per clock in hardware accordingly to
362 * maintain a constant count rate.
363 */
364 static void __init realtime_counter_init(void)
365 {
366 void __iomem *base;
367 static struct clk *sys_clk;
368 unsigned long rate;
369 unsigned int reg, num, den;
370
371 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
372 if (!base) {
373 pr_err("%s: ioremap failed\n", __func__);
374 return;
375 }
376 sys_clk = clk_get(NULL, "sys_clkin_ck");
377 if (!sys_clk) {
378 pr_err("%s: failed to get system clock handle\n", __func__);
379 iounmap(base);
380 return;
381 }
382
383 rate = clk_get_rate(sys_clk);
384 /* Numerator/denumerator values refer TRM Realtime Counter section */
385 switch (rate) {
386 case 1200000:
387 num = 64;
388 den = 125;
389 break;
390 case 1300000:
391 num = 768;
392 den = 1625;
393 break;
394 case 19200000:
395 num = 8;
396 den = 25;
397 break;
398 case 2600000:
399 num = 384;
400 den = 1625;
401 break;
402 case 2700000:
403 num = 256;
404 den = 1125;
405 break;
406 case 38400000:
407 default:
408 /* Program it for 38.4 MHz */
409 num = 4;
410 den = 25;
411 break;
412 }
413
414 /* Program numerator and denumerator registers */
415 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
416 NUMERATOR_DENUMERATOR_MASK;
417 reg |= num;
418 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
419
420 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
421 NUMERATOR_DENUMERATOR_MASK;
422 reg |= den;
423 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
424
425 iounmap(base);
426 }
427 #else
428 static inline void __init realtime_counter_init(void)
429 {}
430 #endif
431
349 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ 432 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
350 clksrc_nr, clksrc_src) \ 433 clksrc_nr, clksrc_src) \
351 static void __init omap##name##_timer_init(void) \ 434 static void __init omap##name##_timer_init(void) \
352 { \ 435 { \
353 omap2_gp_clockevent_init((clkev_nr), clkev_src); \ 436 omap2_gp_clockevent_init((clkev_nr), clkev_src); \
354 omap2_clocksource_init((clksrc_nr), clksrc_src); \ 437 omap2_clocksource_init((clksrc_nr), clksrc_src); \
355 } 438 }
356 439
357 #define OMAP_SYS_TIMER(name) \ 440 #define OMAP_SYS_TIMER(name) \
358 struct sys_timer omap##name##_timer = { \ 441 struct sys_timer omap##name##_timer = { \
359 .init = omap##name##_timer_init, \ 442 .init = omap##name##_timer_init, \
360 }; 443 };
361 444
362 #ifdef CONFIG_ARCH_OMAP2 445 #ifdef CONFIG_ARCH_OMAP2
363 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) 446 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
364 OMAP_SYS_TIMER(2) 447 OMAP_SYS_TIMER(2)
365 #endif 448 #endif
366 449
367 #ifdef CONFIG_ARCH_OMAP3 450 #ifdef CONFIG_ARCH_OMAP3
368 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) 451 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
369 OMAP_SYS_TIMER(3) 452 OMAP_SYS_TIMER(3)
370 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, 453 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
371 2, OMAP3_MPU_SOURCE) 454 2, OMAP3_MPU_SOURCE)
372 OMAP_SYS_TIMER(3_secure) 455 OMAP_SYS_TIMER(3_secure)
373 #endif 456 #endif
374 457
375 #ifdef CONFIG_SOC_AM33XX 458 #ifdef CONFIG_SOC_AM33XX
376 OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) 459 OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
377 OMAP_SYS_TIMER(3_am33xx) 460 OMAP_SYS_TIMER(3_am33xx)
378 #endif 461 #endif
379 462
380 #ifdef CONFIG_ARCH_OMAP4 463 #ifdef CONFIG_ARCH_OMAP4
381 #ifdef CONFIG_LOCAL_TIMERS 464 #ifdef CONFIG_LOCAL_TIMERS
382 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 465 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
383 OMAP44XX_LOCAL_TWD_BASE, 466 OMAP44XX_LOCAL_TWD_BASE,
384 OMAP44XX_IRQ_LOCALTIMER); 467 OMAP44XX_IRQ_LOCALTIMER);
385 #endif 468 #endif
386 469
387 static void __init omap4_timer_init(void) 470 static void __init omap4_timer_init(void)
388 { 471 {
389 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); 472 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
390 omap2_clocksource_init(2, OMAP4_MPU_SOURCE); 473 omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
391 #ifdef CONFIG_LOCAL_TIMERS 474 #ifdef CONFIG_LOCAL_TIMERS
392 /* Local timers are not supprted on OMAP4430 ES1.0 */ 475 /* Local timers are not supprted on OMAP4430 ES1.0 */
393 if (omap_rev() != OMAP4430_REV_ES1_0) { 476 if (omap_rev() != OMAP4430_REV_ES1_0) {
394 int err; 477 int err;
395 478
396 err = twd_local_timer_register(&twd_local_timer); 479 err = twd_local_timer_register(&twd_local_timer);
397 if (err) 480 if (err)
398 pr_err("twd_local_timer_register failed %d\n", err); 481 pr_err("twd_local_timer_register failed %d\n", err);
399 } 482 }
400 #endif 483 #endif
401 } 484 }
402 OMAP_SYS_TIMER(4) 485 OMAP_SYS_TIMER(4)
403 #endif 486 #endif
404 487
405 #ifdef CONFIG_SOC_OMAP5 488 #ifdef CONFIG_SOC_OMAP5
406 OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE) 489 static void __init omap5_timer_init(void)
490 {
491 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
492 omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
493 realtime_counter_init();
494 }
407 OMAP_SYS_TIMER(5) 495 OMAP_SYS_TIMER(5)
408 #endif 496 #endif
409 497
410 /** 498 /**
411 * omap_timer_init - build and register timer device with an 499 * omap_timer_init - build and register timer device with an
412 * associated timer hwmod 500 * associated timer hwmod
413 * @oh: timer hwmod pointer to be used to build timer device 501 * @oh: timer hwmod pointer to be used to build timer device
414 * @user: parameter that can be passed from calling hwmod API 502 * @user: parameter that can be passed from calling hwmod API
415 * 503 *
416 * Called by omap_hwmod_for_each_by_class to register each of the timer 504 * Called by omap_hwmod_for_each_by_class to register each of the timer
417 * devices present in the system. The number of timer devices is known 505 * devices present in the system. The number of timer devices is known
418 * by parsing through the hwmod database for a given class name. At the 506 * by parsing through the hwmod database for a given class name. At the
419 * end of function call memory is allocated for timer device and it is 507 * end of function call memory is allocated for timer device and it is
420 * registered to the framework ready to be proved by the driver. 508 * registered to the framework ready to be proved by the driver.
421 */ 509 */
422 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 510 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
423 { 511 {
424 int id; 512 int id;
425 int ret = 0; 513 int ret = 0;
426 char *name = "omap_timer"; 514 char *name = "omap_timer";
427 struct dmtimer_platform_data *pdata; 515 struct dmtimer_platform_data *pdata;
428 struct platform_device *pdev; 516 struct platform_device *pdev;
429 struct omap_timer_capability_dev_attr *timer_dev_attr; 517 struct omap_timer_capability_dev_attr *timer_dev_attr;
430 518
431 pr_debug("%s: %s\n", __func__, oh->name); 519 pr_debug("%s: %s\n", __func__, oh->name);
432 520
433 /* on secure device, do not register secure timer */ 521 /* on secure device, do not register secure timer */
434 timer_dev_attr = oh->dev_attr; 522 timer_dev_attr = oh->dev_attr;
435 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 523 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
436 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 524 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
437 return ret; 525 return ret;
438 526
439 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 527 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
440 if (!pdata) { 528 if (!pdata) {
441 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 529 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
442 return -ENOMEM; 530 return -ENOMEM;
443 } 531 }
444 532
445 /* 533 /*
446 * Extract the IDs from name field in hwmod database 534 * Extract the IDs from name field in hwmod database
447 * and use the same for constructing ids' for the 535 * and use the same for constructing ids' for the
448 * timer devices. In a way, we are avoiding usage of 536 * timer devices. In a way, we are avoiding usage of
449 * static variable witin the function to do the same. 537 * static variable witin the function to do the same.
450 * CAUTION: We have to be careful and make sure the 538 * CAUTION: We have to be careful and make sure the
451 * name in hwmod database does not change in which case 539 * name in hwmod database does not change in which case
452 * we might either make corresponding change here or 540 * we might either make corresponding change here or
453 * switch back static variable mechanism. 541 * switch back static variable mechanism.
454 */ 542 */
455 sscanf(oh->name, "timer%2d", &id); 543 sscanf(oh->name, "timer%2d", &id);
456 544
457 if (timer_dev_attr) 545 if (timer_dev_attr)
458 pdata->timer_capability = timer_dev_attr->timer_capability; 546 pdata->timer_capability = timer_dev_attr->timer_capability;
459 547
460 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 548 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
461 NULL, 0, 0); 549 NULL, 0, 0);
462 550
463 if (IS_ERR(pdev)) { 551 if (IS_ERR(pdev)) {
464 pr_err("%s: Can't build omap_device for %s: %s.\n", 552 pr_err("%s: Can't build omap_device for %s: %s.\n",
465 __func__, name, oh->name); 553 __func__, name, oh->name);
466 ret = -EINVAL; 554 ret = -EINVAL;
467 } 555 }
468 556
469 kfree(pdata); 557 kfree(pdata);
470 558
471 return ret; 559 return ret;
472 } 560 }
473 561
474 /** 562 /**
475 * omap2_dm_timer_init - top level regular device initialization 563 * omap2_dm_timer_init - top level regular device initialization
476 * 564 *
477 * Uses dedicated hwmod api to parse through hwmod database for 565 * Uses dedicated hwmod api to parse through hwmod database for
478 * given class name and then build and register the timer device. 566 * given class name and then build and register the timer device.
479 */ 567 */
480 static int __init omap2_dm_timer_init(void) 568 static int __init omap2_dm_timer_init(void)
481 { 569 {
482 int ret; 570 int ret;
483 571
484 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 572 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
485 if (unlikely(ret)) { 573 if (unlikely(ret)) {
486 pr_err("%s: device registration failed.\n", __func__); 574 pr_err("%s: device registration failed.\n", __func__);
487 return -EINVAL; 575 return -EINVAL;
488 } 576 }
489 577
490 return 0; 578 return 0;
491 } 579 }
492 arch_initcall(omap2_dm_timer_init); 580 arch_initcall(omap2_dm_timer_init);
493 581
494 /** 582 /**
495 * omap2_override_clocksource - clocksource override with user configuration 583 * omap2_override_clocksource - clocksource override with user configuration
496 * 584 *
497 * Allows user to override default clocksource, using kernel parameter 585 * Allows user to override default clocksource, using kernel parameter
498 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 586 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
499 * 587 *
500 * Note that, here we are using same standard kernel parameter "clocksource=", 588 * Note that, here we are using same standard kernel parameter "clocksource=",
501 * and not introducing any OMAP specific interface. 589 * and not introducing any OMAP specific interface.
502 */ 590 */
503 static int __init omap2_override_clocksource(char *str) 591 static int __init omap2_override_clocksource(char *str)
504 { 592 {
505 if (!str) 593 if (!str)
506 return 0; 594 return 0;
507 /* 595 /*
508 * For OMAP architecture, we only have two options 596 * For OMAP architecture, we only have two options
509 * - sync_32k (default) 597 * - sync_32k (default)
510 * - gp_timer (sys_clk based) 598 * - gp_timer (sys_clk based)
511 */ 599 */
512 if (!strcmp(str, "gp_timer")) 600 if (!strcmp(str, "gp_timer"))
513 use_gptimer_clksrc = true; 601 use_gptimer_clksrc = true;
514 602
515 return 0; 603 return 0;
516 } 604 }
517 early_param("clocksource", omap2_override_clocksource); 605 early_param("clocksource", omap2_override_clocksource);
518 606