Commit fb5c973628929c9072c02d3b9c1ef377bc6919d2
1 parent
84e9252dbf
Fix SPI device tree node error
Showing 1 changed file with 4 additions and 2 deletions Inline Diff
arch/arm/boot/dts/am437x-smarct437x.dts
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* AM437x SMARC-T437X */ | 9 | /* AM437x SMARC-T437X */ |
| 10 | 10 | ||
| 11 | /dts-v1/; | 11 | /dts-v1/; |
| 12 | 12 | ||
| 13 | #include "am4372.dtsi" | 13 | #include "am4372.dtsi" |
| 14 | #include <dt-bindings/pinctrl/am43xx.h> | 14 | #include <dt-bindings/pinctrl/am43xx.h> |
| 15 | #include <dt-bindings/pwm/pwm.h> | 15 | #include <dt-bindings/pwm/pwm.h> |
| 16 | #include <dt-bindings/gpio/gpio.h> | 16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/input/input.h> | 17 | #include <dt-bindings/input/input.h> |
| 18 | 18 | ||
| 19 | / { | 19 | / { |
| 20 | model = "TI AM437x SMARCT437X"; | 20 | model = "TI AM437x SMARCT437X"; |
| 21 | compatible = "ti,am437x-smarct437x","ti,am4372","ti,am43"; | 21 | compatible = "ti,am437x-smarct437x","ti,am4372","ti,am43"; |
| 22 | 22 | ||
| 23 | aliases { | 23 | aliases { |
| 24 | display0 = &lcd0; | 24 | display0 = &lcd0; |
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | vmmcwl_fixed: fixedregulator-mmcwl { | 27 | vmmcwl_fixed: fixedregulator-mmcwl { |
| 28 | compatible = "regulator-fixed"; | 28 | compatible = "regulator-fixed"; |
| 29 | regulator-name = "vmmcwl_fixed"; | 29 | regulator-name = "vmmcwl_fixed"; |
| 30 | regulator-min-microvolt = <1800000>; | 30 | regulator-min-microvolt = <1800000>; |
| 31 | regulator-max-microvolt = <1800000>; | 31 | regulator-max-microvolt = <1800000>; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | backlight { | 34 | backlight { |
| 35 | compatible = "pwm-backlight"; | 35 | compatible = "pwm-backlight"; |
| 36 | enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/ | 36 | enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/ |
| 37 | pwms = <&ehrpwm0 1 250000 PWM_POLARITY_INVERTED>; | 37 | pwms = <&ehrpwm0 1 250000 PWM_POLARITY_INVERTED>; |
| 38 | brightness-levels = <0 51 53 56 62 75 128 212 255>; | 38 | brightness-levels = <0 51 53 56 62 75 128 212 255>; |
| 39 | default-brightness-level = <7>; /* 7 is the brightest */ | 39 | default-brightness-level = <7>; /* 7 is the brightest */ |
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | sound: sound@0 { | 42 | sound: sound@0 { |
| 43 | compatible = "simple-audio-card"; | 43 | compatible = "simple-audio-card"; |
| 44 | simple-audio-card,name = "SMARCT437X SOUND CARD"; | 44 | simple-audio-card,name = "SMARCT437X SOUND CARD"; |
| 45 | simple-audio-card,widgets = | 45 | simple-audio-card,widgets = |
| 46 | "Headphone", "Headphone Jack", | 46 | "Headphone", "Headphone Jack", |
| 47 | "Line", "Line In"; | 47 | "Line", "Line In"; |
| 48 | simple-audio-card,routing = | 48 | simple-audio-card,routing = |
| 49 | "Headphone Jack", "HPLOUT", | 49 | "Headphone Jack", "HPLOUT", |
| 50 | "Headphone Jack", "HPROUT", | 50 | "Headphone Jack", "HPROUT", |
| 51 | "LINE1L", "Line In", | 51 | "LINE1L", "Line In", |
| 52 | "LINE1R", "Line In"; | 52 | "LINE1R", "Line In"; |
| 53 | simple-audio-card,format = "dsp_b"; | 53 | simple-audio-card,format = "dsp_b"; |
| 54 | simple-audio-card,bitclock-master = <&sound_master>; | 54 | simple-audio-card,bitclock-master = <&sound_master>; |
| 55 | simple-audio-card,frame-master = <&sound_master>; | 55 | simple-audio-card,frame-master = <&sound_master>; |
| 56 | simple-audio-card,bitclock-inversion; | 56 | simple-audio-card,bitclock-inversion; |
| 57 | 57 | ||
| 58 | simple-audio-card,cpu { | 58 | simple-audio-card,cpu { |
| 59 | sound-dai = <&mcasp1>; | 59 | sound-dai = <&mcasp1>; |
| 60 | system-clock-frequency = <12000000>; | 60 | system-clock-frequency = <12000000>; |
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | /* For TI TLV320AIC3106 Audio Codec */ | 63 | /* For TI TLV320AIC3106 Audio Codec */ |
| 64 | /*sound_master: simple-audio-card,codec { | 64 | /*sound_master: simple-audio-card,codec { |
| 65 | sound-dai = <&tlv320aic3106>; | 65 | sound-dai = <&tlv320aic3106>; |
| 66 | system-clock-frequency = <24576000>;*/ | 66 | system-clock-frequency = <24576000>;*/ |
| 67 | 67 | ||
| 68 | /* For Freescale SGTL5000 Audio Codec */ | 68 | /* For Freescale SGTL5000 Audio Codec */ |
| 69 | sound_master: simple-audio-card,codec { | 69 | sound_master: simple-audio-card,codec { |
| 70 | sound-dai = <&sgtl5000>; | 70 | sound-dai = <&sgtl5000>; |
| 71 | system-clock-frequency = <24000000>; | 71 | system-clock-frequency = <24000000>; |
| 72 | }; | 72 | }; |
| 73 | }; | 73 | }; |
| 74 | 74 | ||
| 75 | audio_mstrclk: mclk_osc { | 75 | audio_mstrclk: mclk_osc { |
| 76 | compatible = "fixed-clock"; | 76 | compatible = "fixed-clock"; |
| 77 | #clock-cells = <0>; | 77 | #clock-cells = <0>; |
| 78 | clock-frequency = <24000000>; | 78 | clock-frequency = <24000000>; |
| 79 | }; | 79 | }; |
| 80 | 80 | ||
| 81 | lcd0: display { | 81 | lcd0: display { |
| 82 | compatible = "primeview,pm070wl4", "panel-dpi"; | 82 | compatible = "primeview,pm070wl4", "panel-dpi"; |
| 83 | label = "lcd"; | 83 | label = "lcd"; |
| 84 | 84 | ||
| 85 | pinctrl-names = "default"; | 85 | pinctrl-names = "default"; |
| 86 | pinctrl-0 = <&lcd_pins>; | 86 | pinctrl-0 = <&lcd_pins>; |
| 87 | 87 | ||
| 88 | enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; | 88 | enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; |
| 89 | 89 | ||
| 90 | panel-timing { | 90 | panel-timing { |
| 91 | clock-frequency = <32000000>; | 91 | clock-frequency = <32000000>; |
| 92 | hactive = <800>; | 92 | hactive = <800>; |
| 93 | vactive = <480>; | 93 | vactive = <480>; |
| 94 | hfront-porch = <42>; | 94 | hfront-porch = <42>; |
| 95 | hback-porch = <84>; | 95 | hback-porch = <84>; |
| 96 | hsync-len = <128>; | 96 | hsync-len = <128>; |
| 97 | vback-porch = <33>; | 97 | vback-porch = <33>; |
| 98 | vfront-porch = <10>; | 98 | vfront-porch = <10>; |
| 99 | vsync-len = <2>; | 99 | vsync-len = <2>; |
| 100 | hsync-active = <0>; | 100 | hsync-active = <0>; |
| 101 | vsync-active = <0>; | 101 | vsync-active = <0>; |
| 102 | de-active = <1>; | 102 | de-active = <1>; |
| 103 | pixelclk-active = <1>; | 103 | pixelclk-active = <1>; |
| 104 | }; | 104 | }; |
| 105 | 105 | ||
| 106 | port { | 106 | port { |
| 107 | lcd_in: endpoint { | 107 | lcd_in: endpoint { |
| 108 | remote-endpoint = <&dpi_out>; | 108 | remote-endpoint = <&dpi_out>; |
| 109 | }; | 109 | }; |
| 110 | }; | 110 | }; |
| 111 | }; | 111 | }; |
| 112 | }; | 112 | }; |
| 113 | 113 | ||
| 114 | &am43xx_pinmux { | 114 | &am43xx_pinmux { |
| 115 | pinctrl-names = "default"; | 115 | pinctrl-names = "default"; |
| 116 | pinctrl-0 = <&clkout1_pin &clkout2_pin &gpio_pins_default &wdt_time_out_pins_default &debugss_pins>; | 116 | pinctrl-0 = <&clkout1_pin &clkout2_pin &gpio_pins_default &wdt_time_out_pins_default &debugss_pins>; |
| 117 | 117 | ||
| 118 | i2c0_pins: i2c0_pins { | 118 | i2c0_pins: i2c0_pins { |
| 119 | pinctrl-single,pins = < | 119 | pinctrl-single,pins = < |
| 120 | 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | 120 | 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 121 | 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | 121 | 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| 122 | >; | 122 | >; |
| 123 | }; | 123 | }; |
| 124 | 124 | ||
| 125 | i2c1_pins: i2c1_pins { | 125 | i2c1_pins: i2c1_pins { |
| 126 | pinctrl-single,pins = < | 126 | pinctrl-single,pins = < |
| 127 | 0x110 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_rxerr.i2c1_scl */ | 127 | 0x110 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_rxerr.i2c1_scl */ |
| 128 | 0x10c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_crs.i2c1_sda */ | 128 | 0x10c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_crs.i2c1_sda */ |
| 129 | >; | 129 | >; |
| 130 | }; | 130 | }; |
| 131 | 131 | ||
| 132 | i2c2_pins: i2c2_pins { | 132 | i2c2_pins: i2c2_pins { |
| 133 | pinctrl-single,pins = < | 133 | pinctrl-single,pins = < |
| 134 | 0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ | 134 | 0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ |
| 135 | 0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ | 135 | 0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ |
| 136 | >; | 136 | >; |
| 137 | }; | 137 | }; |
| 138 | 138 | ||
| 139 | mmc1_pins: pinmux_mmc1_pins { | 139 | mmc1_pins: pinmux_mmc1_pins { |
| 140 | pinctrl-single,pins = < | 140 | pinctrl-single,pins = < |
| 141 | 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ | 141 | 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ |
| 142 | 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ | 142 | 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ |
| 143 | 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ | 143 | 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ |
| 144 | 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ | 144 | 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ |
| 145 | 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ | 145 | 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ |
| 146 | 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ | 146 | 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ |
| 147 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | 147 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
| 148 | >; | 148 | >; |
| 149 | }; | 149 | }; |
| 150 | 150 | ||
| 151 | emmc_pins: pinmux_emmc_pins { | 151 | emmc_pins: pinmux_emmc_pins { |
| 152 | pinctrl-single,pins = < | 152 | pinctrl-single,pins = < |
| 153 | 0x80 (PIN_INPUT | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ | 153 | 0x80 (PIN_INPUT | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ |
| 154 | 0x84 (PIN_INPUT | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ | 154 | 0x84 (PIN_INPUT | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ |
| 155 | 0x00 (PIN_INPUT | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ | 155 | 0x00 (PIN_INPUT | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ |
| 156 | 0x04 (PIN_INPUT | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ | 156 | 0x04 (PIN_INPUT | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ |
| 157 | 0x08 (PIN_INPUT | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ | 157 | 0x08 (PIN_INPUT | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ |
| 158 | 0x0c (PIN_INPUT | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ | 158 | 0x0c (PIN_INPUT | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ |
| 159 | 0x10 (PIN_INPUT | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ | 159 | 0x10 (PIN_INPUT | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ |
| 160 | 0x14 (PIN_INPUT | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ | 160 | 0x14 (PIN_INPUT | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ |
| 161 | 0x18 (PIN_INPUT | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ | 161 | 0x18 (PIN_INPUT | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ |
| 162 | 0x1c (PIN_INPUT | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ | 162 | 0x1c (PIN_INPUT | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ |
| 163 | >; | 163 | >; |
| 164 | }; | 164 | }; |
| 165 | 165 | ||
| 166 | sdmmc_pins: pinmux_sdmmc_pins { | 166 | sdmmc_pins: pinmux_sdmmc_pins { |
| 167 | pinctrl-single,pins = < | 167 | pinctrl-single,pins = < |
| 168 | 0x8c (PIN_INPUT | MUX_MODE3) /* gpmc_clk.mmc2_clk */ | 168 | 0x8c (PIN_INPUT | MUX_MODE3) /* gpmc_clk.mmc2_clk */ |
| 169 | 0x88 (PIN_INPUT | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ | 169 | 0x88 (PIN_INPUT | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ |
| 170 | 0x30 (PIN_INPUT | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ | 170 | 0x30 (PIN_INPUT | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ |
| 171 | 0x34 (PIN_INPUT | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ | 171 | 0x34 (PIN_INPUT | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ |
| 172 | 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ | 172 | 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ |
| 173 | 0x3c (PIN_INPUT | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ | 173 | 0x3c (PIN_INPUT | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ |
| 174 | 0x20 (PIN_INPUT | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ | 174 | 0x20 (PIN_INPUT | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ |
| 175 | 0x24 (PIN_INPUT | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ | 175 | 0x24 (PIN_INPUT | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ |
| 176 | 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ | 176 | 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ |
| 177 | 0x2c (PIN_INPUT | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ | 177 | 0x2c (PIN_INPUT | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ |
| 178 | >; | 178 | >; |
| 179 | }; | 179 | }; |
| 180 | 180 | ||
| 181 | ehrpwm0b_pins: backlight_pins { | 181 | ehrpwm0b_pins: backlight_pins { |
| 182 | pinctrl-single,pins = < | 182 | pinctrl-single,pins = < |
| 183 | 0x1d8 (PIN_OUTPUT | MUX_MODE6) /* cam1_vd.ehrpwm0B */ | 183 | 0x1d8 (PIN_OUTPUT | MUX_MODE6) /* cam1_vd.ehrpwm0B */ |
| 184 | >; | 184 | >; |
| 185 | }; | 185 | }; |
| 186 | 186 | ||
| 187 | clkout1_pin: pinmux_clkout1_pin { | 187 | clkout1_pin: pinmux_clkout1_pin { |
| 188 | pinctrl-single,pins = < | 188 | pinctrl-single,pins = < |
| 189 | 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ | 189 | 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ |
| 190 | >; | 190 | >; |
| 191 | }; | 191 | }; |
| 192 | 192 | ||
| 193 | clkout2_pin: pinmux_clkout2_pin { | 193 | clkout2_pin: pinmux_clkout2_pin { |
| 194 | pinctrl-single,pins = < | 194 | pinctrl-single,pins = < |
| 195 | 0x274 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR1/CLKOUT2 */ | 195 | 0x274 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR1/CLKOUT2 */ |
| 196 | >; | 196 | >; |
| 197 | }; | 197 | }; |
| 198 | 198 | ||
| 199 | dcan0_default: dcan0_default_pins { | 199 | dcan0_default: dcan0_default_pins { |
| 200 | pinctrl-single,pins = < | 200 | pinctrl-single,pins = < |
| 201 | 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.dcan0_rx */ | 201 | 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.dcan0_rx */ |
| 202 | 0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.dcan0_tx */ | 202 | 0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.dcan0_tx */ |
| 203 | >; | 203 | >; |
| 204 | }; | 204 | }; |
| 205 | 205 | ||
| 206 | dcan1_default: dcan1_default_pins { | 206 | dcan1_default: dcan1_default_pins { |
| 207 | pinctrl-single,pins = < | 207 | pinctrl-single,pins = < |
| 208 | 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.dcan1_rx */ | 208 | 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.dcan1_rx */ |
| 209 | 0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.dcan1_tx */ | 209 | 0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.dcan1_tx */ |
| 210 | >; | 210 | >; |
| 211 | }; | 211 | }; |
| 212 | 212 | ||
| 213 | uart0_pins: pinmux_uart0_pins { | 213 | uart0_pins: pinmux_uart0_pins { |
| 214 | pinctrl-single,pins = < | 214 | pinctrl-single,pins = < |
| 215 | 0x168 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ | 215 | 0x168 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ |
| 216 | 0x16c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ | 216 | 0x16c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ |
| 217 | 0x170 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | 217 | 0x170 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
| 218 | 0x174 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ | 218 | 0x174 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
| 219 | >; | 219 | >; |
| 220 | }; | 220 | }; |
| 221 | 221 | ||
| 222 | uart0_pins_sleep: pinmux_uart0_pins_sleep { | 222 | uart0_pins_sleep: pinmux_uart0_pins_sleep { |
| 223 | pinctrl-single,pins = < | 223 | pinctrl-single,pins = < |
| 224 | 0x168 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 224 | 0x168 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 225 | 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 225 | 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 226 | 0x170 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 226 | 0x170 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 227 | 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 227 | 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 228 | >; | 228 | >; |
| 229 | }; | 229 | }; |
| 230 | 230 | ||
| 231 | uart3_pins: pinmux_uart3_pins { | 231 | uart3_pins: pinmux_uart3_pins { |
| 232 | pinctrl-single,pins = < | 232 | pinctrl-single,pins = < |
| 233 | 0x228 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_rxd.uart3_rxd */ | 233 | 0x228 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_rxd.uart3_rxd */ |
| 234 | 0x22c (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_txd.uart3_txd */ | 234 | 0x22c (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_txd.uart3_txd */ |
| 235 | >; | 235 | >; |
| 236 | }; | 236 | }; |
| 237 | 237 | ||
| 238 | uart3_pins_sleep: pinmux_uart3_pins_sleep { | 238 | uart3_pins_sleep: pinmux_uart3_pins_sleep { |
| 239 | pinctrl-single,pins = < | 239 | pinctrl-single,pins = < |
| 240 | 0x228 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 240 | 0x228 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 241 | 0x22c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 241 | 0x22c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 242 | >; | 242 | >; |
| 243 | }; | 243 | }; |
| 244 | 244 | ||
| 245 | uart2_pins: pinmux_uart2_pins { | 245 | uart2_pins: pinmux_uart2_pins { |
| 246 | pinctrl-single,pins = < | 246 | pinctrl-single,pins = < |
| 247 | 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data6.uart2_ctsn */ | 247 | 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data6.uart2_ctsn */ |
| 248 | 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data7_rtsn.uart2_rtsn */ | 248 | 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data7_rtsn.uart2_rtsn */ |
| 249 | 0x1f8 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data4_uart2rxd */ | 249 | 0x1f8 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data4_uart2rxd */ |
| 250 | 0x1fc (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data5.uart2_txd */ | 250 | 0x1fc (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data5.uart2_txd */ |
| 251 | >; | 251 | >; |
| 252 | }; | 252 | }; |
| 253 | 253 | ||
| 254 | uart2_pins_sleep: pinmux_uart2_pins_sleep { | 254 | uart2_pins_sleep: pinmux_uart2_pins_sleep { |
| 255 | pinctrl-single,pins = < | 255 | pinctrl-single,pins = < |
| 256 | 0x200 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 256 | 0x200 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 257 | 0x204 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 257 | 0x204 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 258 | 0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 258 | 0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 259 | 0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7) | 259 | 0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 260 | >; | 260 | >; |
| 261 | }; | 261 | }; |
| 262 | 262 | ||
| 263 | uart4_pins: pinmux_uart4_pins { | 263 | uart4_pins: pinmux_uart4_pins { |
| 264 | pinctrl-single,pins = < | 264 | pinctrl-single,pins = < |
| 265 | 0x070 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ | 265 | 0x070 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ |
| 266 | 0x074 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ | 266 | 0x074 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ |
| 267 | >; | 267 | >; |
| 268 | }; | 268 | }; |
| 269 | 269 | ||
| 270 | uart4_pins_sleep: pinmux_uart4_pins_sleep { | 270 | uart4_pins_sleep: pinmux_uart4_pins_sleep { |
| 271 | pinctrl-single,pins = < | 271 | pinctrl-single,pins = < |
| 272 | 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 272 | 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 273 | 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 273 | 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 274 | >; | 274 | >; |
| 275 | }; | 275 | }; |
| 276 | 276 | ||
| 277 | /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/ | 277 | /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/ |
| 278 | gpio_pins_default: pinmux_gpio_pin { | 278 | gpio_pins_default: pinmux_gpio_pin { |
| 279 | pinctrl-single,pins = < | 279 | pinctrl-single,pins = < |
| 280 | 0x26c (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_cs0.gpio0_23 */ | 280 | 0x26c (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_cs0.gpio0_23 */ |
| 281 | 0x264 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d0.gpio0_20 */ | 281 | 0x264 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d0.gpio0_20 */ |
| 282 | 0x268 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d1.gpio0_21 */ | 282 | 0x268 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d1.gpio0_21 */ |
| 283 | 0x260 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_sclk.gpio0_22 */ | 283 | 0x260 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_sclk.gpio0_22 */ |
| 284 | 0x21c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data5.gpio4_27 */ | 284 | 0x21c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data5.gpio4_27 */ |
| 285 | 0x224 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data7.gpio4_29 */ | 285 | 0x224 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data7.gpio4_29 */ |
| 286 | 0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ | 286 | 0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ |
| 287 | 0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0.gpio3_16 */ | 287 | 0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0.gpio3_16 */ |
| 288 | 0x210 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data2.gpio4_24 */ | 288 | 0x210 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data2.gpio4_24 */ |
| 289 | 0x214 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data3.gpio4_25 */ | 289 | 0x214 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data3.gpio4_25 */ |
| 290 | 0x218 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data4.gpio4_26 */ | 290 | 0x218 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data4.gpio4_26 */ |
| 291 | 0x220 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data6.gpio4_28 */ | 291 | 0x220 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data6.gpio4_28 */ |
| 292 | >; | 292 | >; |
| 293 | }; | 293 | }; |
| 294 | 294 | ||
| 295 | wdt_time_out_pins_default: pinmux_wdt_time_out_pin { | 295 | wdt_time_out_pins_default: pinmux_wdt_time_out_pin { |
| 296 | pinctrl-single,pins = < | 296 | pinctrl-single,pins = < |
| 297 | 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* uart3_rtsn.ehrpwm5B */ | 297 | 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* uart3_rtsn.ehrpwm5B */ |
| 298 | >; | 298 | >; |
| 299 | }; | 299 | }; |
| 300 | 300 | ||
| 301 | cpsw_default: cpsw_default { | 301 | cpsw_default: cpsw_default { |
| 302 | pinctrl-single,pins = < | 302 | pinctrl-single,pins = < |
| 303 | /* Slave 1 */ | 303 | /* Slave 1 */ |
| 304 | 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ | 304 | 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ |
| 305 | 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ | 305 | 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ |
| 306 | 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ | 306 | 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ |
| 307 | 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ | 307 | 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ |
| 308 | 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ | 308 | 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ |
| 309 | 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ | 309 | 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ |
| 310 | 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ | 310 | 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ |
| 311 | 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ | 311 | 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ |
| 312 | 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ | 312 | 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ |
| 313 | 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ | 313 | 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ |
| 314 | 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ | 314 | 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ |
| 315 | 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ | 315 | 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ |
| 316 | 316 | ||
| 317 | /* Slave 2 */ | 317 | /* Slave 2 */ |
| 318 | 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ | 318 | 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ |
| 319 | 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ | 319 | 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ |
| 320 | 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ | 320 | 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ |
| 321 | 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ | 321 | 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ |
| 322 | 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ | 322 | 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ |
| 323 | 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ | 323 | 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ |
| 324 | 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ | 324 | 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ |
| 325 | 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ | 325 | 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ |
| 326 | 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ | 326 | 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ |
| 327 | 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ | 327 | 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ |
| 328 | 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ | 328 | 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ |
| 329 | 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ | 329 | 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ |
| 330 | >; | 330 | >; |
| 331 | }; | 331 | }; |
| 332 | 332 | ||
| 333 | cpsw_sleep: cpsw_sleep { | 333 | cpsw_sleep: cpsw_sleep { |
| 334 | pinctrl-single,pins = < | 334 | pinctrl-single,pins = < |
| 335 | /* Slave 1 reset value */ | 335 | /* Slave 1 reset value */ |
| 336 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 336 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 337 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 337 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 338 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 338 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 339 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 339 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 340 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 340 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 341 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 341 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 342 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 342 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 343 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 343 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 344 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 344 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 345 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 345 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 346 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 346 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 347 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 347 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 348 | 348 | ||
| 349 | /* Slave 2 reset value */ | 349 | /* Slave 2 reset value */ |
| 350 | 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 350 | 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 351 | 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 351 | 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 352 | 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 352 | 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 353 | 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 353 | 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 354 | 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 354 | 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 355 | 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 355 | 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 356 | 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 356 | 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 357 | 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 357 | 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 358 | 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 358 | 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 359 | 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 359 | 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 360 | 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 360 | 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 361 | 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 361 | 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 362 | >; | 362 | >; |
| 363 | }; | 363 | }; |
| 364 | 364 | ||
| 365 | davinci_mdio_default: davinci_mdio_default { | 365 | davinci_mdio_default: davinci_mdio_default { |
| 366 | pinctrl-single,pins = < | 366 | pinctrl-single,pins = < |
| 367 | /* MDIO */ | 367 | /* MDIO */ |
| 368 | 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | 368 | 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 369 | 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ | 369 | 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| 370 | >; | 370 | >; |
| 371 | }; | 371 | }; |
| 372 | 372 | ||
| 373 | davinci_mdio_sleep: davinci_mdio_sleep { | 373 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 374 | pinctrl-single,pins = < | 374 | pinctrl-single,pins = < |
| 375 | /* MDIO reset value */ | 375 | /* MDIO reset value */ |
| 376 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 376 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 377 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 377 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 378 | >; | 378 | >; |
| 379 | }; | 379 | }; |
| 380 | 380 | ||
| 381 | dss_pins: dss_pins { | 381 | dss_pins: dss_pins { |
| 382 | pinctrl-single,pins = < | 382 | pinctrl-single,pins = < |
| 383 | 0x1b0 (PIN_OUTPUT | MUX_MODE2) /* cam0_hd.dss_data23 */ | 383 | 0x1b0 (PIN_OUTPUT | MUX_MODE2) /* cam0_hd.dss_data23 */ |
| 384 | 0x1b4 (PIN_OUTPUT | MUX_MODE2) /* cam0_vd.dss_data22 */ | 384 | 0x1b4 (PIN_OUTPUT | MUX_MODE2) /* cam0_vd.dss_data22 */ |
| 385 | 0x1b8 (PIN_OUTPUT | MUX_MODE2) /* cam0_field.dss_data21 */ | 385 | 0x1b8 (PIN_OUTPUT | MUX_MODE2) /* cam0_field.dss_data21 */ |
| 386 | 0x1bc (PIN_OUTPUT | MUX_MODE2) /* cam0_wen.dss_data20 */ | 386 | 0x1bc (PIN_OUTPUT | MUX_MODE2) /* cam0_wen.dss_data20 */ |
| 387 | 0x1c0 (PIN_OUTPUT | MUX_MODE2) /* cam0_pclk.dss_data19 */ | 387 | 0x1c0 (PIN_OUTPUT | MUX_MODE2) /* cam0_pclk.dss_data19 */ |
| 388 | 0x1c4 (PIN_OUTPUT | MUX_MODE2) /* cam0_data8.dss_data18 */ | 388 | 0x1c4 (PIN_OUTPUT | MUX_MODE2) /* cam0_data8.dss_data18 */ |
| 389 | 0x1c8 (PIN_OUTPUT | MUX_MODE2) /* cam0_data9.dss_data17 */ | 389 | 0x1c8 (PIN_OUTPUT | MUX_MODE2) /* cam0_data9.dss_data17 */ |
| 390 | 0x1cc (PIN_OUTPUT | MUX_MODE2) /* cam1_data9.dss_data16 */ | 390 | 0x1cc (PIN_OUTPUT | MUX_MODE2) /* cam1_data9.dss_data16 */ |
| 391 | 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ | 391 | 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ |
| 392 | 0x0a4 (PIN_OUTPUT | MUX_MODE0) | 392 | 0x0a4 (PIN_OUTPUT | MUX_MODE0) |
| 393 | 0x0a8 (PIN_OUTPUT | MUX_MODE0) | 393 | 0x0a8 (PIN_OUTPUT | MUX_MODE0) |
| 394 | 0x0ac (PIN_OUTPUT | MUX_MODE0) | 394 | 0x0ac (PIN_OUTPUT | MUX_MODE0) |
| 395 | 0x0b0 (PIN_OUTPUT | MUX_MODE0) | 395 | 0x0b0 (PIN_OUTPUT | MUX_MODE0) |
| 396 | 0x0b4 (PIN_OUTPUT | MUX_MODE0) | 396 | 0x0b4 (PIN_OUTPUT | MUX_MODE0) |
| 397 | 0x0b8 (PIN_OUTPUT | MUX_MODE0) | 397 | 0x0b8 (PIN_OUTPUT | MUX_MODE0) |
| 398 | 0x0bc (PIN_OUTPUT | MUX_MODE0) | 398 | 0x0bc (PIN_OUTPUT | MUX_MODE0) |
| 399 | 0x0c0 (PIN_OUTPUT | MUX_MODE0) | 399 | 0x0c0 (PIN_OUTPUT | MUX_MODE0) |
| 400 | 0x0c4 (PIN_OUTPUT | MUX_MODE0) | 400 | 0x0c4 (PIN_OUTPUT | MUX_MODE0) |
| 401 | 0x0c8 (PIN_OUTPUT | MUX_MODE0) | 401 | 0x0c8 (PIN_OUTPUT | MUX_MODE0) |
| 402 | 0x0cc (PIN_OUTPUT | MUX_MODE0) | 402 | 0x0cc (PIN_OUTPUT | MUX_MODE0) |
| 403 | 0x0d0 (PIN_OUTPUT | MUX_MODE0) | 403 | 0x0d0 (PIN_OUTPUT | MUX_MODE0) |
| 404 | 0x0d4 (PIN_OUTPUT | MUX_MODE0) | 404 | 0x0d4 (PIN_OUTPUT | MUX_MODE0) |
| 405 | 0x0d8 (PIN_OUTPUT | MUX_MODE0) | 405 | 0x0d8 (PIN_OUTPUT | MUX_MODE0) |
| 406 | 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ | 406 | 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ |
| 407 | 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ | 407 | 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ |
| 408 | 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ | 408 | 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ |
| 409 | 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ | 409 | 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ |
| 410 | 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ | 410 | 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ |
| 411 | 411 | ||
| 412 | >; | 412 | >; |
| 413 | }; | 413 | }; |
| 414 | 414 | ||
| 415 | /* SPI_NOR Pins */ | 415 | /* SPI_NOR Pins */ |
| 416 | spi0_pins: spi0_pins { | 416 | spi0_pins: spi0_pins { |
| 417 | pinctrl-single,pins = < | 417 | pinctrl-single,pins = < |
| 418 | 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ | 418 | 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ |
| 419 | 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ | 419 | 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ |
| 420 | 0x154 (PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ | 420 | 0x154 (PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ |
| 421 | 0x158 (PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ | 421 | 0x158 (PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ |
| 422 | >; | 422 | >; |
| 423 | }; | 423 | }; |
| 424 | 424 | ||
| 425 | /* SPI0 Pins */ | 425 | /* SPI0 Pins */ |
| 426 | spi2_pins: spi2_pins { | 426 | spi2_pins: spi2_pins { |
| 427 | pinctrl-single,pins = < | 427 | pinctrl-single,pins = < |
| 428 | 0x1d4 (PIN_OUTPUT | MUX_MODE4) /* cam1_hd.spi2_cs0 */ | 428 | 0x1d4 (PIN_OUTPUT | MUX_MODE4) /* cam1_hd.spi2_cs0 */ |
| 429 | 0x1e0 (PIN_OUTPUT | MUX_MODE4) /* cam1_field.spi2_cs0 */ | 429 | 0x1e0 (PIN_OUTPUT | MUX_MODE4) /* cam1_field.spi2_cs0 */ |
| 430 | 0x1dc (PIN_INPUT | MUX_MODE4) /* cam1_pclk.spi2_sclk */ | 430 | 0x1dc (PIN_INPUT | MUX_MODE4) /* cam1_pclk.spi2_sclk */ |
| 431 | 0x1d0 (PIN_INPUT | MUX_MODE4) /* cam1_data8.spi2_d0 */ | 431 | 0x1d0 (PIN_INPUT | MUX_MODE4) /* cam1_data8.spi2_d0 */ |
| 432 | 0x1e4 (PIN_OUTPUT | MUX_MODE4) /* cam1_wen.spi2_d1 */ | 432 | 0x1e4 (PIN_OUTPUT | MUX_MODE4) /* cam1_wen.spi2_d1 */ |
| 433 | >; | 433 | >; |
| 434 | }; | 434 | }; |
| 435 | 435 | ||
| 436 | /* SPI1 Pins */ | 436 | /* SPI1 Pins */ |
| 437 | spi4_pins: spi4_pins { | 437 | spi4_pins: spi4_pins { |
| 438 | pinctrl-single,pins = < | 438 | pinctrl-single,pins = < |
| 439 | 0x25c (PIN_OUTPUT | MUX_MODE0) /* spi4_cs0.spi4_cs0 */ | 439 | 0x25c (PIN_OUTPUT | MUX_MODE0) /* spi4_cs0.spi4_cs0 */ |
| 440 | 0x230 (PIN_OUTPUT | MUX_MODE2) /* uart3_cstn.spi4_cs1 */ | 440 | 0x230 (PIN_OUTPUT | MUX_MODE2) /* uart3_cstn.spi4_cs1 */ |
| 441 | 0x250 (PIN_INPUT | MUX_MODE0) /* spi4_sclk.spi4_sclk */ | 441 | 0x250 (PIN_INPUT | MUX_MODE0) /* spi4_sclk.spi4_sclk */ |
| 442 | 0x254 (PIN_INPUT | MUX_MODE0) /* spi4_d0.spi4_d0 */ | 442 | 0x254 (PIN_INPUT | MUX_MODE0) /* spi4_d0.spi4_d0 */ |
| 443 | 0x258 (PIN_OUTPUT | MUX_MODE0) /* spi4_d1.spi4_d1 */ | 443 | 0x258 (PIN_OUTPUT | MUX_MODE0) /* spi4_d1.spi4_d1 */ |
| 444 | >; | 444 | >; |
| 445 | }; | 445 | }; |
| 446 | 446 | ||
| 447 | mcasp1_pins: mcasp1_pins { | 447 | mcasp1_pins: mcasp1_pins { |
| 448 | pinctrl-single,pins = < | 448 | pinctrl-single,pins = < |
| 449 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkr.mcasp1_aclkx */ | 449 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkr.mcasp1_aclkx */ |
| 450 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_fsr.mcasp1_fsx */ | 450 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_fsr.mcasp1_fsx */ |
| 451 | 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */ | 451 | 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */ |
| 452 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_ahclkx.mcasp1_axr1 */ | 452 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_ahclkx.mcasp1_axr1 */ |
| 453 | >; | 453 | >; |
| 454 | }; | 454 | }; |
| 455 | 455 | ||
| 456 | mcasp1_sleep_pins: mcasp1_sleep_pins { | 456 | mcasp1_sleep_pins: mcasp1_sleep_pins { |
| 457 | pinctrl-single,pins = < | 457 | pinctrl-single,pins = < |
| 458 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 458 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 459 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 459 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 460 | 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 460 | 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 461 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) | 461 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 462 | >; | 462 | >; |
| 463 | }; | 463 | }; |
| 464 | 464 | ||
| 465 | lcd_pins: lcd_pins { | 465 | lcd_pins: lcd_pins { |
| 466 | pinctrl-single,pins = < | 466 | pinctrl-single,pins = < |
| 467 | 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_be0n_cle.gpio2_5 */ | 467 | 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_be0n_cle.gpio2_5 */ |
| 468 | >; | 468 | >; |
| 469 | }; | 469 | }; |
| 470 | 470 | ||
| 471 | debugss_pins: pinmux_debugss_pins { | 471 | debugss_pins: pinmux_debugss_pins { |
| 472 | pinctrl-single,pins = < | 472 | pinctrl-single,pins = < |
| 473 | 0x290 (PIN_INPUT_PULLDOWN) | 473 | 0x290 (PIN_INPUT_PULLDOWN) |
| 474 | 0x294 (PIN_INPUT_PULLDOWN) | 474 | 0x294 (PIN_INPUT_PULLDOWN) |
| 475 | 0x298 (PIN_INPUT_PULLDOWN) | 475 | 0x298 (PIN_INPUT_PULLDOWN) |
| 476 | 0x29C (PIN_INPUT_PULLDOWN) | 476 | 0x29C (PIN_INPUT_PULLDOWN) |
| 477 | 0x2A0 (PIN_INPUT_PULLDOWN) | 477 | 0x2A0 (PIN_INPUT_PULLDOWN) |
| 478 | 0x2A4 (PIN_INPUT_PULLDOWN) | 478 | 0x2A4 (PIN_INPUT_PULLDOWN) |
| 479 | 0x2A8 (PIN_INPUT_PULLDOWN) | 479 | 0x2A8 (PIN_INPUT_PULLDOWN) |
| 480 | >; | 480 | >; |
| 481 | }; | 481 | }; |
| 482 | 482 | ||
| 483 | usb1_pins: usb1_pins { | 483 | usb1_pins: usb1_pins { |
| 484 | pinctrl-single,pins = < | 484 | pinctrl-single,pins = < |
| 485 | 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ | 485 | 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ |
| 486 | /* USB0 Over Current */ | 486 | /* USB0 Over Current */ |
| 487 | 0x108 (PIN_INPUT | MUX_MODE9) /* mii1_col.gpio0_0 */ | 487 | 0x108 (PIN_INPUT | MUX_MODE9) /* mii1_col.gpio0_0 */ |
| 488 | >; | 488 | >; |
| 489 | }; | 489 | }; |
| 490 | 490 | ||
| 491 | usb2_pins: usb2_pins { | 491 | usb2_pins: usb2_pins { |
| 492 | pinctrl-single,pins = < | 492 | pinctrl-single,pins = < |
| 493 | 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ | 493 | 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ |
| 494 | /* USB1 Over Current */ | 494 | /* USB1 Over Current */ |
| 495 | 0x078 (PIN_INPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ | 495 | 0x078 (PIN_INPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ |
| 496 | >; | 496 | >; |
| 497 | }; | 497 | }; |
| 498 | }; | 498 | }; |
| 499 | 499 | ||
| 500 | &i2c0 { | 500 | &i2c0 { |
| 501 | status = "okay"; | 501 | status = "okay"; |
| 502 | pinctrl-names = "default"; | 502 | pinctrl-names = "default"; |
| 503 | pinctrl-0 = <&i2c0_pins>; | 503 | pinctrl-0 = <&i2c0_pins>; |
| 504 | clock-frequency = <100000>; | 504 | clock-frequency = <100000>; |
| 505 | }; | 505 | }; |
| 506 | 506 | ||
| 507 | &i2c1 { | 507 | &i2c1 { |
| 508 | status = "okay"; | 508 | status = "okay"; |
| 509 | pinctrl-names = "default"; | 509 | pinctrl-names = "default"; |
| 510 | pinctrl-0 = <&i2c1_pins>; | 510 | pinctrl-0 = <&i2c1_pins>; |
| 511 | clock-frequency = <100000>; | 511 | clock-frequency = <100000>; |
| 512 | 512 | ||
| 513 | tps@24 { | 513 | tps@24 { |
| 514 | compatible = "ti,tps65218"; | 514 | compatible = "ti,tps65218"; |
| 515 | reg = <0x24>; | 515 | reg = <0x24>; |
| 516 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | 516 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 517 | interrupt-controller; | 517 | interrupt-controller; |
| 518 | #interrupt-cells = <2>; | 518 | #interrupt-cells = <2>; |
| 519 | 519 | ||
| 520 | dcdc1: regulator-dcdc1 { | 520 | dcdc1: regulator-dcdc1 { |
| 521 | compatible = "ti,tps65218-dcdc1"; | 521 | compatible = "ti,tps65218-dcdc1"; |
| 522 | /* VDD_CORE limits min of OPP50 and max of OPP100 */ | 522 | /* VDD_CORE limits min of OPP50 and max of OPP100 */ |
| 523 | regulator-name = "vdd_core"; | 523 | regulator-name = "vdd_core"; |
| 524 | regulator-min-microvolt = <912000>; | 524 | regulator-min-microvolt = <912000>; |
| 525 | regulator-max-microvolt = <1144000>; | 525 | regulator-max-microvolt = <1144000>; |
| 526 | regulator-boot-on; | 526 | regulator-boot-on; |
| 527 | regulator-always-on; | 527 | regulator-always-on; |
| 528 | }; | 528 | }; |
| 529 | 529 | ||
| 530 | dcdc2: regulator-dcdc2 { | 530 | dcdc2: regulator-dcdc2 { |
| 531 | compatible = "ti,tps65218-dcdc2"; | 531 | compatible = "ti,tps65218-dcdc2"; |
| 532 | /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ | 532 | /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ |
| 533 | regulator-name = "vdd_mpu"; | 533 | regulator-name = "vdd_mpu"; |
| 534 | regulator-min-microvolt = <912000>; | 534 | regulator-min-microvolt = <912000>; |
| 535 | regulator-max-microvolt = <1378000>; | 535 | regulator-max-microvolt = <1378000>; |
| 536 | regulator-boot-on; | 536 | regulator-boot-on; |
| 537 | regulator-always-on; | 537 | regulator-always-on; |
| 538 | }; | 538 | }; |
| 539 | 539 | ||
| 540 | dcdc3: regulator-dcdc3 { | 540 | dcdc3: regulator-dcdc3 { |
| 541 | compatible = "ti,tps65218-dcdc3"; | 541 | compatible = "ti,tps65218-dcdc3"; |
| 542 | regulator-name = "vdds_ddr"; | 542 | regulator-name = "vdds_ddr"; |
| 543 | regulator-min-microvolt = <1500000>; | 543 | regulator-min-microvolt = <1500000>; |
| 544 | regulator-max-microvolt = <1500000>; | 544 | regulator-max-microvolt = <1500000>; |
| 545 | regulator-boot-on; | 545 | regulator-boot-on; |
| 546 | regulator-always-on; | 546 | regulator-always-on; |
| 547 | regulator-state-mem { | 547 | regulator-state-mem { |
| 548 | regulator-on-in-suspend; | 548 | regulator-on-in-suspend; |
| 549 | }; | 549 | }; |
| 550 | regulator-state-disk { | 550 | regulator-state-disk { |
| 551 | regulator-off-in-suspend; | 551 | regulator-off-in-suspend; |
| 552 | }; | 552 | }; |
| 553 | }; | 553 | }; |
| 554 | 554 | ||
| 555 | dcdc4: regulator-dcdc4 { | 555 | dcdc4: regulator-dcdc4 { |
| 556 | compatible = "ti,tps65218-dcdc4"; | 556 | compatible = "ti,tps65218-dcdc4"; |
| 557 | regulator-name = "v3_3d"; | 557 | regulator-name = "v3_3d"; |
| 558 | regulator-min-microvolt = <3300000>; | 558 | regulator-min-microvolt = <3300000>; |
| 559 | regulator-max-microvolt = <3300000>; | 559 | regulator-max-microvolt = <3300000>; |
| 560 | regulator-boot-on; | 560 | regulator-boot-on; |
| 561 | regulator-always-on; | 561 | regulator-always-on; |
| 562 | }; | 562 | }; |
| 563 | 563 | ||
| 564 | dcdc5: regulator-dcdc5 { | 564 | dcdc5: regulator-dcdc5 { |
| 565 | compatible = "ti,tps65218-dcdc5"; | 565 | compatible = "ti,tps65218-dcdc5"; |
| 566 | regulator-name = "v1_0bat"; | 566 | regulator-name = "v1_0bat"; |
| 567 | regulator-min-microvolt = <1000000>; | 567 | regulator-min-microvolt = <1000000>; |
| 568 | regulator-max-microvolt = <1000000>; | 568 | regulator-max-microvolt = <1000000>; |
| 569 | regulator-boot-on; | 569 | regulator-boot-on; |
| 570 | regulator-always-on; | 570 | regulator-always-on; |
| 571 | regulator-state-mem { | 571 | regulator-state-mem { |
| 572 | regulator-on-in-suspend; | 572 | regulator-on-in-suspend; |
| 573 | }; | 573 | }; |
| 574 | }; | 574 | }; |
| 575 | 575 | ||
| 576 | dcdc6: regulator-dcdc6 { | 576 | dcdc6: regulator-dcdc6 { |
| 577 | compatible = "ti,tps65218-dcdc6"; | 577 | compatible = "ti,tps65218-dcdc6"; |
| 578 | regulator-name = "v1_8bat"; | 578 | regulator-name = "v1_8bat"; |
| 579 | regulator-min-microvolt = <1800000>; | 579 | regulator-min-microvolt = <1800000>; |
| 580 | regulator-max-microvolt = <1800000>; | 580 | regulator-max-microvolt = <1800000>; |
| 581 | regulator-boot-on; | 581 | regulator-boot-on; |
| 582 | regulator-always-on; | 582 | regulator-always-on; |
| 583 | regulator-state-mem { | 583 | regulator-state-mem { |
| 584 | regulator-on-in-suspend; | 584 | regulator-on-in-suspend; |
| 585 | }; | 585 | }; |
| 586 | }; | 586 | }; |
| 587 | 587 | ||
| 588 | ldo1: regulator-ldo1 { | 588 | ldo1: regulator-ldo1 { |
| 589 | compatible = "ti,tps65218-ldo1"; | 589 | compatible = "ti,tps65218-ldo1"; |
| 590 | regulator-name = "v1_8d"; | 590 | regulator-name = "v1_8d"; |
| 591 | regulator-min-microvolt = <1800000>; | 591 | regulator-min-microvolt = <1800000>; |
| 592 | regulator-max-microvolt = <1800000>; | 592 | regulator-max-microvolt = <1800000>; |
| 593 | regulator-boot-on; | 593 | regulator-boot-on; |
| 594 | regulator-always-on; | 594 | regulator-always-on; |
| 595 | }; | 595 | }; |
| 596 | 596 | ||
| 597 | power-button { | 597 | power-button { |
| 598 | compatible = "ti,tps65218-pwrbutton"; | 598 | compatible = "ti,tps65218-pwrbutton"; |
| 599 | status = "okay"; | 599 | status = "okay"; |
| 600 | interrupts = <3 IRQ_TYPE_EDGE_BOTH>; | 600 | interrupts = <3 IRQ_TYPE_EDGE_BOTH>; |
| 601 | }; | 601 | }; |
| 602 | }; | 602 | }; |
| 603 | 603 | ||
| 604 | s35390a: s35390a@30 { | 604 | s35390a: s35390a@30 { |
| 605 | compatible = "s35390a"; | 605 | compatible = "s35390a"; |
| 606 | reg = <0x30>; | 606 | reg = <0x30>; |
| 607 | }; | 607 | }; |
| 608 | 608 | ||
| 609 | at24@50 { | 609 | at24@50 { |
| 610 | compatible = "at24,24c256"; | 610 | compatible = "at24,24c256"; |
| 611 | reg = <0x50>; | 611 | reg = <0x50>; |
| 612 | }; | 612 | }; |
| 613 | 613 | ||
| 614 | at24@57 { | 614 | at24@57 { |
| 615 | compatible = "at24,24c256"; | 615 | compatible = "at24,24c256"; |
| 616 | reg = <0x57>; | 616 | reg = <0x57>; |
| 617 | }; | 617 | }; |
| 618 | 618 | ||
| 619 | /* For TI TLV320AIC3106 Audio Codec */ | 619 | /* For TI TLV320AIC3106 Audio Codec */ |
| 620 | /*tlv320aic3106: tlv320aic3106@1b { | 620 | /*tlv320aic3106: tlv320aic3106@1b { |
| 621 | #sound-dai-cells = <0>; | 621 | #sound-dai-cells = <0>; |
| 622 | compatible = "ti,tlv320aic3106"; | 622 | compatible = "ti,tlv320aic3106"; |
| 623 | reg = <0x1b>; | 623 | reg = <0x1b>; |
| 624 | status = "okay"; | 624 | status = "okay"; |
| 625 | 625 | ||
| 626 | AVDD-supply = <&dcdc4>; | 626 | AVDD-supply = <&dcdc4>; |
| 627 | IOVDD-supply = <&dcdc6>; | 627 | IOVDD-supply = <&dcdc6>; |
| 628 | DRVDD-supply = <&dcdc4>; | 628 | DRVDD-supply = <&dcdc4>; |
| 629 | DVDD-supply = <&ldo1>; | 629 | DVDD-supply = <&ldo1>; |
| 630 | };*/ | 630 | };*/ |
| 631 | 631 | ||
| 632 | /* For Freescale SGTL5000 Audio Codec */ | 632 | /* For Freescale SGTL5000 Audio Codec */ |
| 633 | sgtl5000: sgtl5000@0a { | 633 | sgtl5000: sgtl5000@0a { |
| 634 | #sound-dai-cells = <0>; | 634 | #sound-dai-cells = <0>; |
| 635 | compatible = "fsl,sgtl5000"; | 635 | compatible = "fsl,sgtl5000"; |
| 636 | reg = <0x0a>; | 636 | reg = <0x0a>; |
| 637 | clocks = <&audio_mstrclk>; | 637 | clocks = <&audio_mstrclk>; |
| 638 | VDDA-supply = <&dcdc4>; | 638 | VDDA-supply = <&dcdc4>; |
| 639 | VDDIO-supply = <&dcdc6>; | 639 | VDDIO-supply = <&dcdc6>; |
| 640 | VDDD-supply = <&ldo1>; | 640 | VDDD-supply = <&ldo1>; |
| 641 | }; | 641 | }; |
| 642 | }; | 642 | }; |
| 643 | 643 | ||
| 644 | &i2c2 { | 644 | &i2c2 { |
| 645 | status = "okay"; | 645 | status = "okay"; |
| 646 | pinctrl-names = "default"; | 646 | pinctrl-names = "default"; |
| 647 | pinctrl-0 = <&i2c2_pins>; | 647 | pinctrl-0 = <&i2c2_pins>; |
| 648 | clock-frequency = <100000>; | 648 | clock-frequency = <100000>; |
| 649 | 649 | ||
| 650 | /* CH7055A Parallel LCD to VGA D-SUB 15 way */ | 650 | /* CH7055A Parallel LCD to VGA D-SUB 15 way */ |
| 651 | eeprom@76 { | 651 | eeprom@76 { |
| 652 | compatible = "at,24c256"; | 652 | compatible = "at,24c256"; |
| 653 | reg = <0x76>; | 653 | reg = <0x76>; |
| 654 | }; | 654 | }; |
| 655 | }; | 655 | }; |
| 656 | 656 | ||
| 657 | 657 | ||
| 658 | &epwmss0 { | 658 | &epwmss0 { |
| 659 | status = "okay"; | 659 | status = "okay"; |
| 660 | 660 | ||
| 661 | ehrpwm0: ehrpwm@48300200 { | 661 | ehrpwm0: ehrpwm@48300200 { |
| 662 | status = "okay"; | 662 | status = "okay"; |
| 663 | pinctrl-names = "default"; | 663 | pinctrl-names = "default"; |
| 664 | pinctrl-0 = <&ehrpwm0b_pins>; | 664 | pinctrl-0 = <&ehrpwm0b_pins>; |
| 665 | }; | 665 | }; |
| 666 | }; | 666 | }; |
| 667 | 667 | ||
| 668 | &gpio0 { | 668 | &gpio0 { |
| 669 | status = "okay"; | 669 | status = "okay"; |
| 670 | }; | 670 | }; |
| 671 | 671 | ||
| 672 | &gpio1 { | 672 | &gpio1 { |
| 673 | status = "okay"; | 673 | status = "okay"; |
| 674 | }; | 674 | }; |
| 675 | 675 | ||
| 676 | &gpio2 { | 676 | &gpio2 { |
| 677 | status = "okay"; | 677 | status = "okay"; |
| 678 | }; | 678 | }; |
| 679 | 679 | ||
| 680 | &gpio3 { | 680 | &gpio3 { |
| 681 | status = "okay"; | 681 | status = "okay"; |
| 682 | }; | 682 | }; |
| 683 | 683 | ||
| 684 | &gpio4 { | 684 | &gpio4 { |
| 685 | status = "okay"; | 685 | status = "okay"; |
| 686 | }; | 686 | }; |
| 687 | 687 | ||
| 688 | &gpio5 { | 688 | &gpio5 { |
| 689 | status = "okay"; | 689 | status = "okay"; |
| 690 | }; | 690 | }; |
| 691 | 691 | ||
| 692 | &mmc1 { | 692 | &mmc1 { |
| 693 | status = "okay"; | 693 | status = "okay"; |
| 694 | pinctrl-names = "default"; | 694 | pinctrl-names = "default"; |
| 695 | pinctrl-0 = <&mmc1_pins>; | 695 | pinctrl-0 = <&mmc1_pins>; |
| 696 | 696 | ||
| 697 | vmmc-supply = <&dcdc4>; | 697 | vmmc-supply = <&dcdc4>; |
| 698 | bus-width = <4>; | 698 | bus-width = <4>; |
| 699 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; | 699 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; |
| 700 | }; | 700 | }; |
| 701 | 701 | ||
| 702 | &mmc2 { | 702 | &mmc2 { |
| 703 | pinctrl-names = "default"; | 703 | pinctrl-names = "default"; |
| 704 | pinctrl-0 = <&emmc_pins>; | 704 | pinctrl-0 = <&emmc_pins>; |
| 705 | bus-width = <8>; | 705 | bus-width = <8>; |
| 706 | vmmc-supply = <&vmmcwl_fixed>; | 706 | vmmc-supply = <&vmmcwl_fixed>; |
| 707 | status = "okay"; | 707 | status = "okay"; |
| 708 | ti,non-removable; | 708 | ti,non-removable; |
| 709 | }; | 709 | }; |
| 710 | 710 | ||
| 711 | /*If carrier board eMMC (or 2nd SD slot) is present and used, un-comment out the following nodes. SD card will be emulated /dev/mmcblk2 instead of /dev/mmcblk1*/ | 711 | /*If carrier board eMMC (or 2nd SD slot) is present and used, un-comment out the following nodes. SD card will be emulated /dev/mmcblk2 instead of /dev/mmcblk1*/ |
| 712 | 712 | ||
| 713 | /*&mmc3 { | 713 | /*&mmc3 { |
| 714 | status = "okay"; | 714 | status = "okay"; |
| 715 | dmas = <&edma 30 | 715 | dmas = <&edma 30 |
| 716 | &edma 31>; | 716 | &edma 31>; |
| 717 | dma-names = "tx", "rx"; | 717 | dma-names = "tx", "rx"; |
| 718 | vmmc-supply = <&vmmcwl_fixed>; | 718 | vmmc-supply = <&vmmcwl_fixed>; |
| 719 | bus-width = <8>; | 719 | bus-width = <8>; |
| 720 | pinctrl-names = "default"; | 720 | pinctrl-names = "default"; |
| 721 | pinctrl-0 = <&sdmmc_pins>; | 721 | pinctrl-0 = <&sdmmc_pins>; |
| 722 | keep-power-in-suspend; | 722 | keep-power-in-suspend; |
| 723 | ti,non-removable; | 723 | ti,non-removable; |
| 724 | }; | 724 | }; |
| 725 | 725 | ||
| 726 | &edma { | 726 | &edma { |
| 727 | ti,edma-xbar-event-map = /bits/ 16 <1 30 | 727 | ti,edma-xbar-event-map = /bits/ 16 <1 30 |
| 728 | 2 31>; | 728 | 2 31>; |
| 729 | };*/ | 729 | };*/ |
| 730 | 730 | ||
| 731 | /* Four-Wire Resistive Touch */ | 731 | /* Four-Wire Resistive Touch */ |
| 732 | &tscadc { | 732 | &tscadc { |
| 733 | status = "disabled"; | 733 | status = "disabled"; |
| 734 | tsc { | 734 | tsc { |
| 735 | ti,wires = <4>; | 735 | ti,wires = <4>; |
| 736 | ti,x-plate-resistance = <200>; | 736 | ti,x-plate-resistance = <200>; |
| 737 | ti,coordinate-readouts = <5>; | 737 | ti,coordinate-readouts = <5>; |
| 738 | ti,wire-config = <0x00 0x11 0x22 0x33>; | 738 | ti,wire-config = <0x00 0x11 0x22 0x33>; |
| 739 | ti,charge-delay = <0xB000>; | 739 | ti,charge-delay = <0xB000>; |
| 740 | }; | 740 | }; |
| 741 | 741 | ||
| 742 | adc { | 742 | adc { |
| 743 | ti,adc-channels = <0 1 2 3>; | 743 | ti,adc-channels = <0 1 2 3>; |
| 744 | }; | 744 | }; |
| 745 | }; | 745 | }; |
| 746 | 746 | ||
| 747 | &usb2_phy1 { | 747 | &usb2_phy1 { |
| 748 | status = "okay"; | 748 | status = "okay"; |
| 749 | }; | 749 | }; |
| 750 | 750 | ||
| 751 | &usb1 { | 751 | &usb1 { |
| 752 | dr_mode = "host"; | 752 | dr_mode = "host"; |
| 753 | status = "okay"; | 753 | status = "okay"; |
| 754 | pinctrl-names = "default"; | 754 | pinctrl-names = "default"; |
| 755 | pinctrl-0 = <&usb1_pins>; | 755 | pinctrl-0 = <&usb1_pins>; |
| 756 | }; | 756 | }; |
| 757 | 757 | ||
| 758 | &usb2_phy2 { | 758 | &usb2_phy2 { |
| 759 | status = "okay"; | 759 | status = "okay"; |
| 760 | }; | 760 | }; |
| 761 | 761 | ||
| 762 | &usb2 { | 762 | &usb2 { |
| 763 | dr_mode = "host"; | 763 | dr_mode = "host"; |
| 764 | status = "okay"; | 764 | status = "okay"; |
| 765 | pinctrl-names = "default"; | 765 | pinctrl-names = "default"; |
| 766 | pinctrl-0 = <&usb2_pins>; | 766 | pinctrl-0 = <&usb2_pins>; |
| 767 | }; | 767 | }; |
| 768 | 768 | ||
| 769 | &spi0 { | 769 | &spi0 { |
| 770 | ti,spi-num-cs = <1>; | 770 | ti,spi-num-cs = <1>; |
| 771 | status = "okay"; | 771 | status = "okay"; |
| 772 | pinctrl-names = "default"; | 772 | pinctrl-names = "default"; |
| 773 | pinctrl-0 = <&spi0_pins>; | 773 | pinctrl-0 = <&spi0_pins>; |
| 774 | dmas = <&edma 16 | 774 | dmas = <&edma 16 |
| 775 | &edma 17>; | 775 | &edma 17>; |
| 776 | dma-names = "tx0", "rx0"; | 776 | dma-names = "tx0", "rx0"; |
| 777 | 777 | ||
| 778 | flash: mx25u3235f@0 { | 778 | flash: mx25u3235f@0 { |
| 779 | #address-cells = <1>; | 779 | #address-cells = <1>; |
| 780 | #size-cells = <1>; | 780 | #size-cells = <1>; |
| 781 | compatible = "jedec,spi-nor"; | 781 | compatible = "jedec,spi-nor"; |
| 782 | spi-max-frequency = <24000000>; | 782 | spi-max-frequency = <24000000>; |
| 783 | reg = <0>; | 783 | reg = <0>; |
| 784 | 784 | ||
| 785 | /* MTD partition table. | 785 | /* MTD partition table. |
| 786 | * The ROM checks the first 512KiB | 786 | * The ROM checks the first 512KiB |
| 787 | * for a valid file to boot(XIP). | 787 | * for a valid file to boot(XIP). |
| 788 | */ | 788 | */ |
| 789 | partition@0 { | 789 | partition@0 { |
| 790 | label = "U-Boot"; | 790 | label = "U-Boot"; |
| 791 | reg = <0x0 0x100000>; | 791 | reg = <0x0 0x100000>; |
| 792 | }; | 792 | }; |
| 793 | 793 | ||
| 794 | partition@100000 { | 794 | partition@100000 { |
| 795 | label = "U-Boot Environment"; | 795 | label = "U-Boot Environment"; |
| 796 | reg = <0x100000 0x080000>; | 796 | reg = <0x100000 0x080000>; |
| 797 | }; | 797 | }; |
| 798 | 798 | ||
| 799 | partition@180000 { | 799 | partition@180000 { |
| 800 | label = "Flattened Device Tree"; | 800 | label = "Flattened Device Tree"; |
| 801 | reg = <0x180000 0x200000>; | 801 | reg = <0x180000 0x200000>; |
| 802 | }; | 802 | }; |
| 803 | 803 | ||
| 804 | }; | 804 | }; |
| 805 | }; | 805 | }; |
| 806 | 806 | ||
| 807 | &spi1 { | 807 | /* SPI0, spidev2 */ |
| 808 | &spi2 { | ||
| 808 | ti,spi-num-cs = <2>; | 809 | ti,spi-num-cs = <2>; |
| 809 | status = "okay"; | 810 | status = "okay"; |
| 810 | pinctrl-names = "default"; | 811 | pinctrl-names = "default"; |
| 811 | pinctrl-0 = <&spi2_pins>; | 812 | pinctrl-0 = <&spi2_pins>; |
| 812 | dmas = <&edma 18 | 813 | dmas = <&edma 18 |
| 813 | &edma 19 | 814 | &edma 19 |
| 814 | &edma 20 | 815 | &edma 20 |
| 815 | &edma 21>; | 816 | &edma 21>; |
| 816 | dma-names = "tx0", "rx0", "tx1", "rx1"; | 817 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 817 | 818 | ||
| 818 | spidev1: spidev@0 { | 819 | spidev1: spidev@0 { |
| 819 | #address-cells = <1>; | 820 | #address-cells = <1>; |
| 820 | #size-cells = <0>; | 821 | #size-cells = <0>; |
| 821 | compatible = "spidev"; | 822 | compatible = "spidev"; |
| 822 | reg = <0>; | 823 | reg = <0>; |
| 823 | spi-max-frequency = <24000000>; | 824 | spi-max-frequency = <24000000>; |
| 824 | }; | 825 | }; |
| 825 | 826 | ||
| 826 | spidev2: spidev@1 { | 827 | spidev2: spidev@1 { |
| 827 | #address-cells = <1>; | 828 | #address-cells = <1>; |
| 828 | #size-cells = <0>; | 829 | #size-cells = <0>; |
| 829 | compatible = "spidev"; | 830 | compatible = "spidev"; |
| 830 | reg = <1>; | 831 | reg = <1>; |
| 831 | spi-max-frequency = <24000000>; | 832 | spi-max-frequency = <24000000>; |
| 832 | }; | 833 | }; |
| 833 | }; | 834 | }; |
| 834 | 835 | ||
| 835 | &spi3 { | 836 | /* SPI1, spidev3 */ |
| 837 | &spi4 { | ||
| 836 | ti,spi-num-cs = <2>; | 838 | ti,spi-num-cs = <2>; |
| 837 | status = "okay"; | 839 | status = "okay"; |
| 838 | pinctrl-names = "default"; | 840 | pinctrl-names = "default"; |
| 839 | pinctrl-0 = <&spi4_pins>; | 841 | pinctrl-0 = <&spi4_pins>; |
| 840 | dmas = <&edma 26 | 842 | dmas = <&edma 26 |
| 841 | &edma 27 | 843 | &edma 27 |
| 842 | &edma 28 | 844 | &edma 28 |
| 843 | &edma 29>; | 845 | &edma 29>; |
| 844 | dma-names = "tx0", "rx0", "tx1", "rx1"; | 846 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 845 | 847 | ||
| 846 | spidev3: spidev@0 { | 848 | spidev3: spidev@0 { |
| 847 | #address-cells = <1>; | 849 | #address-cells = <1>; |
| 848 | #size-cells = <0>; | 850 | #size-cells = <0>; |
| 849 | compatible = "spidev"; | 851 | compatible = "spidev"; |
| 850 | reg = <0>; | 852 | reg = <0>; |
| 851 | spi-max-frequency = <24000000>; | 853 | spi-max-frequency = <24000000>; |
| 852 | }; | 854 | }; |
| 853 | 855 | ||
| 854 | spidev4: spidev@1 { | 856 | spidev4: spidev@1 { |
| 855 | #address-cells = <1>; | 857 | #address-cells = <1>; |
| 856 | #size-cells = <0>; | 858 | #size-cells = <0>; |
| 857 | compatible = "spidev"; | 859 | compatible = "spidev"; |
| 858 | reg = <1>; | 860 | reg = <1>; |
| 859 | spi-max-frequency = <24000000>; | 861 | spi-max-frequency = <24000000>; |
| 860 | }; | 862 | }; |
| 861 | }; | 863 | }; |
| 862 | 864 | ||
| 863 | &uart0 { | 865 | &uart0 { |
| 864 | pinctrl-names = "default"; | 866 | pinctrl-names = "default"; |
| 865 | pinctrl-0 = <&uart0_pins>; | 867 | pinctrl-0 = <&uart0_pins>; |
| 866 | pinctrl-1 = <&uart0_pins_sleep>; | 868 | pinctrl-1 = <&uart0_pins_sleep>; |
| 867 | 869 | ||
| 868 | status = "okay"; | 870 | status = "okay"; |
| 869 | }; | 871 | }; |
| 870 | 872 | ||
| 871 | &uart3 { | 873 | &uart3 { |
| 872 | pinctrl-names = "default"; | 874 | pinctrl-names = "default"; |
| 873 | pinctrl-0 = <&uart3_pins>; | 875 | pinctrl-0 = <&uart3_pins>; |
| 874 | pinctrl-1 = <&uart3_pins_sleep>; | 876 | pinctrl-1 = <&uart3_pins_sleep>; |
| 875 | 877 | ||
| 876 | status = "okay"; | 878 | status = "okay"; |
| 877 | }; | 879 | }; |
| 878 | 880 | ||
| 879 | &uart2 { | 881 | &uart2 { |
| 880 | pinctrl-names = "default"; | 882 | pinctrl-names = "default"; |
| 881 | pinctrl-0 = <&uart2_pins>; | 883 | pinctrl-0 = <&uart2_pins>; |
| 882 | pinctrl-1 = <&uart2_pins_sleep>; | 884 | pinctrl-1 = <&uart2_pins_sleep>; |
| 883 | 885 | ||
| 884 | status = "okay"; | 886 | status = "okay"; |
| 885 | }; | 887 | }; |
| 886 | 888 | ||
| 887 | &uart4 { | 889 | &uart4 { |
| 888 | pinctrl-names = "default"; | 890 | pinctrl-names = "default"; |
| 889 | pinctrl-0 = <&uart4_pins>; | 891 | pinctrl-0 = <&uart4_pins>; |
| 890 | pinctrl-1 = <&uart4_pins_sleep>; | 892 | pinctrl-1 = <&uart4_pins_sleep>; |
| 891 | 893 | ||
| 892 | status = "okay"; | 894 | status = "okay"; |
| 893 | }; | 895 | }; |
| 894 | 896 | ||
| 895 | &dcan0 { | 897 | &dcan0 { |
| 896 | pinctrl-names = "default"; | 898 | pinctrl-names = "default"; |
| 897 | pinctrl-0 = <&dcan0_default>; | 899 | pinctrl-0 = <&dcan0_default>; |
| 898 | status = "okay"; | 900 | status = "okay"; |
| 899 | }; | 901 | }; |
| 900 | 902 | ||
| 901 | &dcan1 { | 903 | &dcan1 { |
| 902 | pinctrl-names = "default"; | 904 | pinctrl-names = "default"; |
| 903 | pinctrl-0 = <&dcan1_default>; | 905 | pinctrl-0 = <&dcan1_default>; |
| 904 | status = "okay"; | 906 | status = "okay"; |
| 905 | }; | 907 | }; |
| 906 | 908 | ||
| 907 | &mac { | 909 | &mac { |
| 908 | pinctrl-names = "default", "sleep"; | 910 | pinctrl-names = "default", "sleep"; |
| 909 | pinctrl-0 = <&cpsw_default>; | 911 | pinctrl-0 = <&cpsw_default>; |
| 910 | pinctrl-1 = <&cpsw_sleep>; | 912 | pinctrl-1 = <&cpsw_sleep>; |
| 911 | dual_emac = <1>; | 913 | dual_emac = <1>; |
| 912 | status = "okay"; | 914 | status = "okay"; |
| 913 | }; | 915 | }; |
| 914 | 916 | ||
| 915 | &davinci_mdio { | 917 | &davinci_mdio { |
| 916 | pinctrl-names = "default", "sleep"; | 918 | pinctrl-names = "default", "sleep"; |
| 917 | pinctrl-0 = <&davinci_mdio_default>; | 919 | pinctrl-0 = <&davinci_mdio_default>; |
| 918 | pinctrl-1 = <&davinci_mdio_sleep>; | 920 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 919 | status = "okay"; | 921 | status = "okay"; |
| 920 | }; | 922 | }; |
| 921 | 923 | ||
| 922 | &cpsw_emac0 { | 924 | &cpsw_emac0 { |
| 923 | phy_id = <&davinci_mdio>, <6>; | 925 | phy_id = <&davinci_mdio>, <6>; |
| 924 | phy-mode = "rgmii"; | 926 | phy-mode = "rgmii"; |
| 925 | dual_emac_res_vlan = <1>; | 927 | dual_emac_res_vlan = <1>; |
| 926 | }; | 928 | }; |
| 927 | 929 | ||
| 928 | &cpsw_emac1 { | 930 | &cpsw_emac1 { |
| 929 | phy_id = <&davinci_mdio>, <7>; | 931 | phy_id = <&davinci_mdio>, <7>; |
| 930 | phy-mode = "rgmii"; | 932 | phy-mode = "rgmii"; |
| 931 | dual_emac_res_vlan = <2>; | 933 | dual_emac_res_vlan = <2>; |
| 932 | }; | 934 | }; |
| 933 | 935 | ||
| 934 | &elm { | 936 | &elm { |
| 935 | status = "okay"; | 937 | status = "okay"; |
| 936 | }; | 938 | }; |
| 937 | 939 | ||
| 938 | &mcasp1 { | 940 | &mcasp1 { |
| 939 | #sound-dai-cells = <0>; | 941 | #sound-dai-cells = <0>; |
| 940 | pinctrl-names = "default", "sleep"; | 942 | pinctrl-names = "default", "sleep"; |
| 941 | pinctrl-0 = <&mcasp1_pins>; | 943 | pinctrl-0 = <&mcasp1_pins>; |
| 942 | pinctrl-1 = <&mcasp1_sleep_pins>; | 944 | pinctrl-1 = <&mcasp1_sleep_pins>; |
| 943 | 945 | ||
| 944 | status = "okay"; | 946 | status = "okay"; |
| 945 | 947 | ||
| 946 | op-mode = <0>; /* MCASP_IIS_MODE */ | 948 | op-mode = <0>; /* MCASP_IIS_MODE */ |
| 947 | tdm-slots = <2>; | 949 | tdm-slots = <2>; |
| 948 | /* 4 serializers */ | 950 | /* 4 serializers */ |
| 949 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | 951 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 950 | 1 2 0 0 | 952 | 1 2 0 0 |
| 951 | >; | 953 | >; |
| 952 | 954 | ||
| 953 | tx-num-evt = <1>; | 955 | tx-num-evt = <1>; |
| 954 | rx-num-evt = <1>; | 956 | rx-num-evt = <1>; |
| 955 | }; | 957 | }; |
| 956 | 958 | ||
| 957 | &dss { | 959 | &dss { |
| 958 | status = "okay"; | 960 | status = "okay"; |
| 959 | 961 | ||
| 960 | pinctrl-names = "default"; | 962 | pinctrl-names = "default"; |
| 961 | pinctrl-0 = <&dss_pins>; | 963 | pinctrl-0 = <&dss_pins>; |
| 962 | 964 | ||
| 963 | port { | 965 | port { |
| 964 | dpi_out: endpoint@0 { | 966 | dpi_out: endpoint@0 { |
| 965 | remote-endpoint = <&lcd_in>; | 967 | remote-endpoint = <&lcd_in>; |
| 966 | data-lines = <24>; | 968 | data-lines = <24>; |
| 967 | }; | 969 | }; |
| 968 | }; | 970 | }; |
| 969 | }; | 971 | }; |
| 970 | 972 | ||
| 971 | &rtc { | 973 | &rtc { |
| 972 | status = "disabled"; /* Use Seiko S35390A on Module instead */ | 974 | status = "disabled"; /* Use Seiko S35390A on Module instead */ |
| 973 | ext-clk-src; | 975 | ext-clk-src; |
| 974 | }; | 976 | }; |
| 975 | 977 | ||
| 976 | &wdt { | 978 | &wdt { |
| 977 | status = "okay"; | 979 | status = "okay"; |
| 978 | }; | 980 | }; |
| 979 | 981 | ||
| 980 | &cpu { | 982 | &cpu { |
| 981 | cpu0-supply = <&dcdc2>; | 983 | cpu0-supply = <&dcdc2>; |
| 982 | }; | 984 | }; |
| 983 | 985 | ||
| 984 | &wkup_m3_ipc { | 986 | &wkup_m3_ipc { |
| 985 | ti,scale-data-fw = "am43x-evm-scale-data.bin"; | 987 | ti,scale-data-fw = "am43x-evm-scale-data.bin"; |
| 986 | }; | 988 | }; |
| 987 | 989 | ||
| 988 | &sgx { | 990 | &sgx { |
| 989 | status = "okay"; | 991 | status = "okay"; |
| 990 | }; | 992 | }; |
| 991 | 993 |