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Commit fe07adec730d271c91f4160f96a0f24fe7553c63

Authored by Wolfram Sang
Committed by Wolfram Sang
1 parent b074cf80a7
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

i2c: sh_mobile: fix uninitialized var when debug is enabled 

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

Showing 1 changed file with 1 additions and 0 deletions Inline Diff

drivers/i2c/busses/i2c-sh_mobile.c
Diff comments   View file @ fe07ade
1 /* 1 /*
2 * SuperH Mobile I2C Controller 2 * SuperH Mobile I2C Controller
3 * 3 *
4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> 4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
5 * 5 *
6 * Copyright (C) 2008 Magnus Damm 6 * Copyright (C) 2008 Magnus Damm
7 * 7 *
8 * Portions of the code based on out-of-tree driver i2c-sh7343.c 8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> 9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License 13 * the Free Software Foundation; either version 2 of the License
14 * 14 *
15 * This program is distributed in the hope that it will be useful, 15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 */ 19 */
20 20
21 #include <linux/clk.h> 21 #include <linux/clk.h>
22 #include <linux/delay.h> 22 #include <linux/delay.h>
23 #include <linux/dmaengine.h> 23 #include <linux/dmaengine.h>
24 #include <linux/dma-mapping.h> 24 #include <linux/dma-mapping.h>
25 #include <linux/err.h> 25 #include <linux/err.h>
26 #include <linux/i2c.h> 26 #include <linux/i2c.h>
27 #include <linux/i2c/i2c-sh_mobile.h> 27 #include <linux/i2c/i2c-sh_mobile.h>
28 #include <linux/init.h> 28 #include <linux/init.h>
29 #include <linux/interrupt.h> 29 #include <linux/interrupt.h>
30 #include <linux/io.h> 30 #include <linux/io.h>
31 #include <linux/kernel.h> 31 #include <linux/kernel.h>
32 #include <linux/module.h> 32 #include <linux/module.h>
33 #include <linux/of_device.h> 33 #include <linux/of_device.h>
34 #include <linux/platform_device.h> 34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h> 35 #include <linux/pm_runtime.h>
36 #include <linux/slab.h> 36 #include <linux/slab.h>
37 37
38 /* Transmit operation: */ 38 /* Transmit operation: */
39 /* */ 39 /* */
40 /* 0 byte transmit */ 40 /* 0 byte transmit */
41 /* BUS: S A8 ACK P(*) */ 41 /* BUS: S A8 ACK P(*) */
42 /* IRQ: DTE WAIT */ 42 /* IRQ: DTE WAIT */
43 /* ICIC: */ 43 /* ICIC: */
44 /* ICCR: 0x94 0x90 */ 44 /* ICCR: 0x94 0x90 */
45 /* ICDR: A8 */ 45 /* ICDR: A8 */
46 /* */ 46 /* */
47 /* 1 byte transmit */ 47 /* 1 byte transmit */
48 /* BUS: S A8 ACK D8(1) ACK P(*) */ 48 /* BUS: S A8 ACK D8(1) ACK P(*) */
49 /* IRQ: DTE WAIT WAIT */ 49 /* IRQ: DTE WAIT WAIT */
50 /* ICIC: -DTE */ 50 /* ICIC: -DTE */
51 /* ICCR: 0x94 0x90 */ 51 /* ICCR: 0x94 0x90 */
52 /* ICDR: A8 D8(1) */ 52 /* ICDR: A8 D8(1) */
53 /* */ 53 /* */
54 /* 2 byte transmit */ 54 /* 2 byte transmit */
55 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */ 55 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
56 /* IRQ: DTE WAIT WAIT WAIT */ 56 /* IRQ: DTE WAIT WAIT WAIT */
57 /* ICIC: -DTE */ 57 /* ICIC: -DTE */
58 /* ICCR: 0x94 0x90 */ 58 /* ICCR: 0x94 0x90 */
59 /* ICDR: A8 D8(1) D8(2) */ 59 /* ICDR: A8 D8(1) D8(2) */
60 /* */ 60 /* */
61 /* 3 bytes or more, +---------+ gets repeated */ 61 /* 3 bytes or more, +---------+ gets repeated */
62 /* */ 62 /* */
63 /* */ 63 /* */
64 /* Receive operation: */ 64 /* Receive operation: */
65 /* */ 65 /* */
66 /* 0 byte receive - not supported since slave may hold SDA low */ 66 /* 0 byte receive - not supported since slave may hold SDA low */
67 /* */ 67 /* */
68 /* 1 byte receive [TX] | [RX] */ 68 /* 1 byte receive [TX] | [RX] */
69 /* BUS: S A8 ACK | D8(1) ACK P(*) */ 69 /* BUS: S A8 ACK | D8(1) ACK P(*) */
70 /* IRQ: DTE WAIT | WAIT DTE */ 70 /* IRQ: DTE WAIT | WAIT DTE */
71 /* ICIC: -DTE | +DTE */ 71 /* ICIC: -DTE | +DTE */
72 /* ICCR: 0x94 0x81 | 0xc0 */ 72 /* ICCR: 0x94 0x81 | 0xc0 */
73 /* ICDR: A8 | D8(1) */ 73 /* ICDR: A8 | D8(1) */
74 /* */ 74 /* */
75 /* 2 byte receive [TX]| [RX] */ 75 /* 2 byte receive [TX]| [RX] */
76 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */ 76 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
77 /* IRQ: DTE WAIT | WAIT WAIT DTE */ 77 /* IRQ: DTE WAIT | WAIT WAIT DTE */
78 /* ICIC: -DTE | +DTE */ 78 /* ICIC: -DTE | +DTE */
79 /* ICCR: 0x94 0x81 | 0xc0 */ 79 /* ICCR: 0x94 0x81 | 0xc0 */
80 /* ICDR: A8 | D8(1) D8(2) */ 80 /* ICDR: A8 | D8(1) D8(2) */
81 /* */ 81 /* */
82 /* 3 byte receive [TX] | [RX] (*) */ 82 /* 3 byte receive [TX] | [RX] (*) */
83 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 83 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
84 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 84 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
85 /* ICIC: -DTE | +DTE */ 85 /* ICIC: -DTE | +DTE */
86 /* ICCR: 0x94 0x81 | 0xc0 */ 86 /* ICCR: 0x94 0x81 | 0xc0 */
87 /* ICDR: A8 | D8(1) D8(2) D8(3) */ 87 /* ICDR: A8 | D8(1) D8(2) D8(3) */
88 /* */ 88 /* */
89 /* 4 bytes or more, this part is repeated +---------+ */ 89 /* 4 bytes or more, this part is repeated +---------+ */
90 /* */ 90 /* */
91 /* */ 91 /* */
92 /* Interrupt order and BUSY flag */ 92 /* Interrupt order and BUSY flag */
93 /* ___ _ */ 93 /* ___ _ */
94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
95 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 95 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
96 /* */ 96 /* */
97 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */ 97 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
98 /* ___ */ 98 /* ___ */
99 /* WAIT IRQ ________________________________/ \___________ */ 99 /* WAIT IRQ ________________________________/ \___________ */
100 /* TACK IRQ ____________________________________/ \_______ */ 100 /* TACK IRQ ____________________________________/ \_______ */
101 /* DTE IRQ __________________________________________/ \_ */ 101 /* DTE IRQ __________________________________________/ \_ */
102 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 102 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
103 /* _______________________________________________ */ 103 /* _______________________________________________ */
104 /* BUSY __/ \_ */ 104 /* BUSY __/ \_ */
105 /* */ 105 /* */
106 /* (*) The STOP condition is only sent by the master at the end of the last */ 106 /* (*) The STOP condition is only sent by the master at the end of the last */
107 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */ 107 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
108 /* only cleared after the STOP condition, so, between messages we have to */ 108 /* only cleared after the STOP condition, so, between messages we have to */
109 /* poll for the DTE bit. */ 109 /* poll for the DTE bit. */
110 /* */ 110 /* */
111 111
112 enum sh_mobile_i2c_op { 112 enum sh_mobile_i2c_op {
113 OP_START = 0, 113 OP_START = 0,
114 OP_TX_FIRST, 114 OP_TX_FIRST,
115 OP_TX, 115 OP_TX,
116 OP_TX_STOP, 116 OP_TX_STOP,
117 OP_TX_STOP_DATA, 117 OP_TX_STOP_DATA,
118 OP_TX_TO_RX, 118 OP_TX_TO_RX,
119 OP_RX, 119 OP_RX,
120 OP_RX_STOP, 120 OP_RX_STOP,
121 OP_RX_STOP_DATA, 121 OP_RX_STOP_DATA,
122 }; 122 };
123 123
124 struct sh_mobile_i2c_data { 124 struct sh_mobile_i2c_data {
125 struct device *dev; 125 struct device *dev;
126 void __iomem *reg; 126 void __iomem *reg;
127 struct i2c_adapter adap; 127 struct i2c_adapter adap;
128 unsigned long bus_speed; 128 unsigned long bus_speed;
129 unsigned int clks_per_count; 129 unsigned int clks_per_count;
130 struct clk *clk; 130 struct clk *clk;
131 u_int8_t icic; 131 u_int8_t icic;
132 u_int8_t flags; 132 u_int8_t flags;
133 u_int16_t iccl; 133 u_int16_t iccl;
134 u_int16_t icch; 134 u_int16_t icch;
135 135
136 spinlock_t lock; 136 spinlock_t lock;
137 wait_queue_head_t wait; 137 wait_queue_head_t wait;
138 struct i2c_msg *msg; 138 struct i2c_msg *msg;
139 int pos; 139 int pos;
140 int sr; 140 int sr;
141 bool send_stop; 141 bool send_stop;
142 142
143 struct resource *res; 143 struct resource *res;
144 struct dma_chan *dma_tx; 144 struct dma_chan *dma_tx;
145 struct dma_chan *dma_rx; 145 struct dma_chan *dma_rx;
146 struct scatterlist sg; 146 struct scatterlist sg;
147 enum dma_data_direction dma_direction; 147 enum dma_data_direction dma_direction;
148 }; 148 };
149 149
150 struct sh_mobile_dt_config { 150 struct sh_mobile_dt_config {
151 int clks_per_count; 151 int clks_per_count;
152 }; 152 };
153 153
154 #define IIC_FLAG_HAS_ICIC67 (1 << 0) 154 #define IIC_FLAG_HAS_ICIC67 (1 << 0)
155 155
156 #define STANDARD_MODE 100000 156 #define STANDARD_MODE 100000
157 #define FAST_MODE 400000 157 #define FAST_MODE 400000
158 158
159 /* Register offsets */ 159 /* Register offsets */
160 #define ICDR 0x00 160 #define ICDR 0x00
161 #define ICCR 0x04 161 #define ICCR 0x04
162 #define ICSR 0x08 162 #define ICSR 0x08
163 #define ICIC 0x0c 163 #define ICIC 0x0c
164 #define ICCL 0x10 164 #define ICCL 0x10
165 #define ICCH 0x14 165 #define ICCH 0x14
166 166
167 /* Register bits */ 167 /* Register bits */
168 #define ICCR_ICE 0x80 168 #define ICCR_ICE 0x80
169 #define ICCR_RACK 0x40 169 #define ICCR_RACK 0x40
170 #define ICCR_TRS 0x10 170 #define ICCR_TRS 0x10
171 #define ICCR_BBSY 0x04 171 #define ICCR_BBSY 0x04
172 #define ICCR_SCP 0x01 172 #define ICCR_SCP 0x01
173 173
174 #define ICSR_SCLM 0x80 174 #define ICSR_SCLM 0x80
175 #define ICSR_SDAM 0x40 175 #define ICSR_SDAM 0x40
176 #define SW_DONE 0x20 176 #define SW_DONE 0x20
177 #define ICSR_BUSY 0x10 177 #define ICSR_BUSY 0x10
178 #define ICSR_AL 0x08 178 #define ICSR_AL 0x08
179 #define ICSR_TACK 0x04 179 #define ICSR_TACK 0x04
180 #define ICSR_WAIT 0x02 180 #define ICSR_WAIT 0x02
181 #define ICSR_DTE 0x01 181 #define ICSR_DTE 0x01
182 182
183 #define ICIC_ICCLB8 0x80 183 #define ICIC_ICCLB8 0x80
184 #define ICIC_ICCHB8 0x40 184 #define ICIC_ICCHB8 0x40
185 #define ICIC_TDMAE 0x20 185 #define ICIC_TDMAE 0x20
186 #define ICIC_RDMAE 0x10 186 #define ICIC_RDMAE 0x10
187 #define ICIC_ALE 0x08 187 #define ICIC_ALE 0x08
188 #define ICIC_TACKE 0x04 188 #define ICIC_TACKE 0x04
189 #define ICIC_WAITE 0x02 189 #define ICIC_WAITE 0x02
190 #define ICIC_DTEE 0x01 190 #define ICIC_DTEE 0x01
191 191
192 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) 192 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
193 { 193 {
194 if (offs == ICIC) 194 if (offs == ICIC)
195 data |= pd->icic; 195 data |= pd->icic;
196 196
197 iowrite8(data, pd->reg + offs); 197 iowrite8(data, pd->reg + offs);
198 } 198 }
199 199
200 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) 200 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
201 { 201 {
202 return ioread8(pd->reg + offs); 202 return ioread8(pd->reg + offs);
203 } 203 }
204 204
205 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, 205 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
206 unsigned char set, unsigned char clr) 206 unsigned char set, unsigned char clr)
207 { 207 {
208 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 208 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
209 } 209 }
210 210
211 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf) 211 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
212 { 212 {
213 /* 213 /*
214 * Conditional expression: 214 * Conditional expression:
215 * ICCL >= COUNT_CLK * (tLOW + tf) 215 * ICCL >= COUNT_CLK * (tLOW + tf)
216 * 216 *
217 * SH-Mobile IIC hardware starts counting the LOW period of 217 * SH-Mobile IIC hardware starts counting the LOW period of
218 * the SCL signal (tLOW) as soon as it pulls the SCL line. 218 * the SCL signal (tLOW) as soon as it pulls the SCL line.
219 * In order to meet the tLOW timing spec, we need to take into 219 * In order to meet the tLOW timing spec, we need to take into
220 * account the fall time of SCL signal (tf). Default tf value 220 * account the fall time of SCL signal (tf). Default tf value
221 * should be 0.3 us, for safety. 221 * should be 0.3 us, for safety.
222 */ 222 */
223 return (((count_khz * (tLOW + tf)) + 5000) / 10000); 223 return (((count_khz * (tLOW + tf)) + 5000) / 10000);
224 } 224 }
225 225
226 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf) 226 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
227 { 227 {
228 /* 228 /*
229 * Conditional expression: 229 * Conditional expression:
230 * ICCH >= COUNT_CLK * (tHIGH + tf) 230 * ICCH >= COUNT_CLK * (tHIGH + tf)
231 * 231 *
232 * SH-Mobile IIC hardware is aware of SCL transition period 'tr', 232 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
233 * and can ignore it. SH-Mobile IIC controller starts counting 233 * and can ignore it. SH-Mobile IIC controller starts counting
234 * the HIGH period of the SCL signal (tHIGH) after the SCL input 234 * the HIGH period of the SCL signal (tHIGH) after the SCL input
235 * voltage increases at VIH. 235 * voltage increases at VIH.
236 * 236 *
237 * Afterward it turned out calculating ICCH using only tHIGH spec 237 * Afterward it turned out calculating ICCH using only tHIGH spec
238 * will result in violation of the tHD;STA timing spec. We need 238 * will result in violation of the tHD;STA timing spec. We need
239 * to take into account the fall time of SDA signal (tf) at START 239 * to take into account the fall time of SDA signal (tf) at START
240 * condition, in order to meet both tHIGH and tHD;STA specs. 240 * condition, in order to meet both tHIGH and tHD;STA specs.
241 */ 241 */
242 return (((count_khz * (tHIGH + tf)) + 5000) / 10000); 242 return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
243 } 243 }
244 244
245 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) 245 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
246 { 246 {
247 unsigned long i2c_clk_khz; 247 unsigned long i2c_clk_khz;
248 u32 tHIGH, tLOW, tf; 248 u32 tHIGH, tLOW, tf;
249 uint16_t max_val; 249 uint16_t max_val;
250 250
251 /* Get clock rate after clock is enabled */ 251 /* Get clock rate after clock is enabled */
252 clk_prepare_enable(pd->clk); 252 clk_prepare_enable(pd->clk);
253 i2c_clk_khz = clk_get_rate(pd->clk) / 1000; 253 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
254 clk_disable_unprepare(pd->clk); 254 clk_disable_unprepare(pd->clk);
255 i2c_clk_khz /= pd->clks_per_count; 255 i2c_clk_khz /= pd->clks_per_count;
256 256
257 if (pd->bus_speed == STANDARD_MODE) { 257 if (pd->bus_speed == STANDARD_MODE) {
258 tLOW = 47; /* tLOW = 4.7 us */ 258 tLOW = 47; /* tLOW = 4.7 us */
259 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ 259 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
260 tf = 3; /* tf = 0.3 us */ 260 tf = 3; /* tf = 0.3 us */
261 } else if (pd->bus_speed == FAST_MODE) { 261 } else if (pd->bus_speed == FAST_MODE) {
262 tLOW = 13; /* tLOW = 1.3 us */ 262 tLOW = 13; /* tLOW = 1.3 us */
263 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ 263 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
264 tf = 3; /* tf = 0.3 us */ 264 tf = 3; /* tf = 0.3 us */
265 } else { 265 } else {
266 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", 266 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
267 pd->bus_speed); 267 pd->bus_speed);
268 return -EINVAL; 268 return -EINVAL;
269 } 269 }
270 270
271 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf); 271 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
272 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf); 272 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
273 273
274 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff; 274 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
275 if (pd->iccl > max_val || pd->icch > max_val) { 275 if (pd->iccl > max_val || pd->icch > max_val) {
276 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n", 276 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
277 pd->iccl, pd->icch); 277 pd->iccl, pd->icch);
278 return -EINVAL; 278 return -EINVAL;
279 } 279 }
280 280
281 /* one more bit of ICCL in ICIC */ 281 /* one more bit of ICCL in ICIC */
282 if (pd->iccl & 0x100) 282 if (pd->iccl & 0x100)
283 pd->icic |= ICIC_ICCLB8; 283 pd->icic |= ICIC_ICCLB8;
284 else 284 else
285 pd->icic &= ~ICIC_ICCLB8; 285 pd->icic &= ~ICIC_ICCLB8;
286 286
287 /* one more bit of ICCH in ICIC */ 287 /* one more bit of ICCH in ICIC */
288 if (pd->icch & 0x100) 288 if (pd->icch & 0x100)
289 pd->icic |= ICIC_ICCHB8; 289 pd->icic |= ICIC_ICCHB8;
290 else 290 else
291 pd->icic &= ~ICIC_ICCHB8; 291 pd->icic &= ~ICIC_ICCHB8;
292 292
293 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch); 293 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
294 return 0; 294 return 0;
295 } 295 }
296 296
297 static void activate_ch(struct sh_mobile_i2c_data *pd) 297 static void activate_ch(struct sh_mobile_i2c_data *pd)
298 { 298 {
299 /* Wake up device and enable clock */ 299 /* Wake up device and enable clock */
300 pm_runtime_get_sync(pd->dev); 300 pm_runtime_get_sync(pd->dev);
301 clk_prepare_enable(pd->clk); 301 clk_prepare_enable(pd->clk);
302 302
303 /* Enable channel and configure rx ack */ 303 /* Enable channel and configure rx ack */
304 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 304 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
305 305
306 /* Mask all interrupts */ 306 /* Mask all interrupts */
307 iic_wr(pd, ICIC, 0); 307 iic_wr(pd, ICIC, 0);
308 308
309 /* Set the clock */ 309 /* Set the clock */
310 iic_wr(pd, ICCL, pd->iccl & 0xff); 310 iic_wr(pd, ICCL, pd->iccl & 0xff);
311 iic_wr(pd, ICCH, pd->icch & 0xff); 311 iic_wr(pd, ICCH, pd->icch & 0xff);
312 } 312 }
313 313
314 static void deactivate_ch(struct sh_mobile_i2c_data *pd) 314 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
315 { 315 {
316 /* Clear/disable interrupts */ 316 /* Clear/disable interrupts */
317 iic_wr(pd, ICSR, 0); 317 iic_wr(pd, ICSR, 0);
318 iic_wr(pd, ICIC, 0); 318 iic_wr(pd, ICIC, 0);
319 319
320 /* Disable channel */ 320 /* Disable channel */
321 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 321 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
322 322
323 /* Disable clock and mark device as idle */ 323 /* Disable clock and mark device as idle */
324 clk_disable_unprepare(pd->clk); 324 clk_disable_unprepare(pd->clk);
325 pm_runtime_put_sync(pd->dev); 325 pm_runtime_put_sync(pd->dev);
326 } 326 }
327 327
328 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 328 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
329 enum sh_mobile_i2c_op op, unsigned char data) 329 enum sh_mobile_i2c_op op, unsigned char data)
330 { 330 {
331 unsigned char ret = 0; 331 unsigned char ret = 0;
332 unsigned long flags; 332 unsigned long flags;
333 333
334 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); 334 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
335 335
336 spin_lock_irqsave(&pd->lock, flags); 336 spin_lock_irqsave(&pd->lock, flags);
337 337
338 switch (op) { 338 switch (op) {
339 case OP_START: /* issue start and trigger DTE interrupt */ 339 case OP_START: /* issue start and trigger DTE interrupt */
340 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY); 340 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
341 break; 341 break;
342 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 342 case OP_TX_FIRST: /* disable DTE interrupt and write data */
343 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 343 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
344 iic_wr(pd, ICDR, data); 344 iic_wr(pd, ICDR, data);
345 break; 345 break;
346 case OP_TX: /* write data */ 346 case OP_TX: /* write data */
347 iic_wr(pd, ICDR, data); 347 iic_wr(pd, ICDR, data);
348 break; 348 break;
349 case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */ 349 case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
350 iic_wr(pd, ICDR, data); 350 iic_wr(pd, ICDR, data);
351 /* fallthrough */ 351 /* fallthrough */
352 case OP_TX_STOP: /* issue a stop */ 352 case OP_TX_STOP: /* issue a stop */
353 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS 353 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
354 : ICCR_ICE | ICCR_TRS | ICCR_BBSY); 354 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
355 break; 355 break;
356 case OP_TX_TO_RX: /* select read mode */ 356 case OP_TX_TO_RX: /* select read mode */
357 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP); 357 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
358 break; 358 break;
359 case OP_RX: /* just read data */ 359 case OP_RX: /* just read data */
360 ret = iic_rd(pd, ICDR); 360 ret = iic_rd(pd, ICDR);
361 break; 361 break;
362 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 362 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
363 iic_wr(pd, ICIC, 363 iic_wr(pd, ICIC,
364 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 364 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
365 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 365 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
366 break; 366 break;
367 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 367 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
368 iic_wr(pd, ICIC, 368 iic_wr(pd, ICIC,
369 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 369 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
370 ret = iic_rd(pd, ICDR); 370 ret = iic_rd(pd, ICDR);
371 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 371 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
372 break; 372 break;
373 } 373 }
374 374
375 spin_unlock_irqrestore(&pd->lock, flags); 375 spin_unlock_irqrestore(&pd->lock, flags);
376 376
377 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); 377 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
378 return ret; 378 return ret;
379 } 379 }
380 380
381 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) 381 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
382 { 382 {
383 return pd->pos == -1; 383 return pd->pos == -1;
384 } 384 }
385 385
386 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) 386 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
387 { 387 {
388 return pd->pos == pd->msg->len - 1; 388 return pd->pos == pd->msg->len - 1;
389 } 389 }
390 390
391 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, 391 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
392 unsigned char *buf) 392 unsigned char *buf)
393 { 393 {
394 switch (pd->pos) { 394 switch (pd->pos) {
395 case -1: 395 case -1:
396 *buf = (pd->msg->addr & 0x7f) << 1; 396 *buf = (pd->msg->addr & 0x7f) << 1;
397 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; 397 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
398 break; 398 break;
399 default: 399 default:
400 *buf = pd->msg->buf[pd->pos]; 400 *buf = pd->msg->buf[pd->pos];
401 } 401 }
402 } 402 }
403 403
404 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 404 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
405 { 405 {
406 unsigned char data; 406 unsigned char data;
407 407
408 if (pd->pos == pd->msg->len) { 408 if (pd->pos == pd->msg->len) {
409 /* Send stop if we haven't yet (DMA case) */ 409 /* Send stop if we haven't yet (DMA case) */
410 if (pd->send_stop && (iic_rd(pd, ICCR) & ICCR_BBSY)) 410 if (pd->send_stop && (iic_rd(pd, ICCR) & ICCR_BBSY))
411 i2c_op(pd, OP_TX_STOP, 0); 411 i2c_op(pd, OP_TX_STOP, 0);
412 return 1; 412 return 1;
413 } 413 }
414 414
415 sh_mobile_i2c_get_data(pd, &data); 415 sh_mobile_i2c_get_data(pd, &data);
416 416
417 if (sh_mobile_i2c_is_last_byte(pd)) 417 if (sh_mobile_i2c_is_last_byte(pd))
418 i2c_op(pd, OP_TX_STOP_DATA, data); 418 i2c_op(pd, OP_TX_STOP_DATA, data);
419 else if (sh_mobile_i2c_is_first_byte(pd)) 419 else if (sh_mobile_i2c_is_first_byte(pd))
420 i2c_op(pd, OP_TX_FIRST, data); 420 i2c_op(pd, OP_TX_FIRST, data);
421 else 421 else
422 i2c_op(pd, OP_TX, data); 422 i2c_op(pd, OP_TX, data);
423 423
424 pd->pos++; 424 pd->pos++;
425 return 0; 425 return 0;
426 } 426 }
427 427
428 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) 428 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
429 { 429 {
430 unsigned char data; 430 unsigned char data;
431 int real_pos; 431 int real_pos;
432 432
433 do { 433 do {
434 if (pd->pos <= -1) { 434 if (pd->pos <= -1) {
435 sh_mobile_i2c_get_data(pd, &data); 435 sh_mobile_i2c_get_data(pd, &data);
436 436
437 if (sh_mobile_i2c_is_first_byte(pd)) 437 if (sh_mobile_i2c_is_first_byte(pd))
438 i2c_op(pd, OP_TX_FIRST, data); 438 i2c_op(pd, OP_TX_FIRST, data);
439 else 439 else
440 i2c_op(pd, OP_TX, data); 440 i2c_op(pd, OP_TX, data);
441 break; 441 break;
442 } 442 }
443 443
444 if (pd->pos == 0) { 444 if (pd->pos == 0) {
445 i2c_op(pd, OP_TX_TO_RX, 0); 445 i2c_op(pd, OP_TX_TO_RX, 0);
446 break; 446 break;
447 } 447 }
448 448
449 real_pos = pd->pos - 2; 449 real_pos = pd->pos - 2;
450 450
451 if (pd->pos == pd->msg->len) { 451 if (pd->pos == pd->msg->len) {
452 if (real_pos < 0) { 452 if (real_pos < 0) {
453 i2c_op(pd, OP_RX_STOP, 0); 453 i2c_op(pd, OP_RX_STOP, 0);
454 break; 454 break;
455 } 455 }
456 data = i2c_op(pd, OP_RX_STOP_DATA, 0); 456 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
457 } else 457 } else
458 data = i2c_op(pd, OP_RX, 0); 458 data = i2c_op(pd, OP_RX, 0);
459 459
460 if (real_pos >= 0) 460 if (real_pos >= 0)
461 pd->msg->buf[real_pos] = data; 461 pd->msg->buf[real_pos] = data;
462 } while (0); 462 } while (0);
463 463
464 pd->pos++; 464 pd->pos++;
465 return pd->pos == (pd->msg->len + 2); 465 return pd->pos == (pd->msg->len + 2);
466 } 466 }
467 467
468 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 468 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
469 { 469 {
470 struct sh_mobile_i2c_data *pd = dev_id; 470 struct sh_mobile_i2c_data *pd = dev_id;
471 unsigned char sr; 471 unsigned char sr;
472 int wakeup = 0; 472 int wakeup = 0;
473 473
474 sr = iic_rd(pd, ICSR); 474 sr = iic_rd(pd, ICSR);
475 pd->sr |= sr; /* remember state */ 475 pd->sr |= sr; /* remember state */
476 476
477 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 477 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
478 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 478 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
479 pd->pos, pd->msg->len); 479 pd->pos, pd->msg->len);
480 480
481 /* Kick off TxDMA after preface was done */ 481 /* Kick off TxDMA after preface was done */
482 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0) 482 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
483 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0); 483 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
484 else if (sr & (ICSR_AL | ICSR_TACK)) 484 else if (sr & (ICSR_AL | ICSR_TACK))
485 /* don't interrupt transaction - continue to issue stop */ 485 /* don't interrupt transaction - continue to issue stop */
486 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); 486 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
487 else if (pd->msg->flags & I2C_M_RD) 487 else if (pd->msg->flags & I2C_M_RD)
488 wakeup = sh_mobile_i2c_isr_rx(pd); 488 wakeup = sh_mobile_i2c_isr_rx(pd);
489 else 489 else
490 wakeup = sh_mobile_i2c_isr_tx(pd); 490 wakeup = sh_mobile_i2c_isr_tx(pd);
491 491
492 /* Kick off RxDMA after preface was done */ 492 /* Kick off RxDMA after preface was done */
493 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1) 493 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
494 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0); 494 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
495 495
496 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 496 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
497 iic_wr(pd, ICSR, sr & ~ICSR_WAIT); 497 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
498 498
499 if (wakeup) { 499 if (wakeup) {
500 pd->sr |= SW_DONE; 500 pd->sr |= SW_DONE;
501 wake_up(&pd->wait); 501 wake_up(&pd->wait);
502 } 502 }
503 503
504 /* defeat write posting to avoid spurious WAIT interrupts */ 504 /* defeat write posting to avoid spurious WAIT interrupts */
505 iic_rd(pd, ICSR); 505 iic_rd(pd, ICSR);
506 506
507 return IRQ_HANDLED; 507 return IRQ_HANDLED;
508 } 508 }
509 509
510 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd) 510 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
511 { 511 {
512 struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE 512 struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
513 ? pd->dma_rx : pd->dma_tx; 513 ? pd->dma_rx : pd->dma_tx;
514 514
515 dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg), 515 dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
516 pd->msg->len, pd->dma_direction); 516 pd->msg->len, pd->dma_direction);
517 517
518 pd->dma_direction = DMA_NONE; 518 pd->dma_direction = DMA_NONE;
519 } 519 }
520 520
521 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd) 521 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
522 { 522 {
523 if (pd->dma_direction == DMA_NONE) 523 if (pd->dma_direction == DMA_NONE)
524 return; 524 return;
525 else if (pd->dma_direction == DMA_FROM_DEVICE) 525 else if (pd->dma_direction == DMA_FROM_DEVICE)
526 dmaengine_terminate_all(pd->dma_rx); 526 dmaengine_terminate_all(pd->dma_rx);
527 else if (pd->dma_direction == DMA_TO_DEVICE) 527 else if (pd->dma_direction == DMA_TO_DEVICE)
528 dmaengine_terminate_all(pd->dma_tx); 528 dmaengine_terminate_all(pd->dma_tx);
529 529
530 sh_mobile_i2c_dma_unmap(pd); 530 sh_mobile_i2c_dma_unmap(pd);
531 } 531 }
532 532
533 static void sh_mobile_i2c_dma_callback(void *data) 533 static void sh_mobile_i2c_dma_callback(void *data)
534 { 534 {
535 struct sh_mobile_i2c_data *pd = data; 535 struct sh_mobile_i2c_data *pd = data;
536 536
537 sh_mobile_i2c_dma_unmap(pd); 537 sh_mobile_i2c_dma_unmap(pd);
538 pd->pos = pd->msg->len; 538 pd->pos = pd->msg->len;
539 539
540 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE); 540 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
541 } 541 }
542 542
543 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev, 543 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
544 enum dma_transfer_direction dir, dma_addr_t port_addr) 544 enum dma_transfer_direction dir, dma_addr_t port_addr)
545 { 545 {
546 struct dma_chan *chan; 546 struct dma_chan *chan;
547 struct dma_slave_config cfg; 547 struct dma_slave_config cfg;
548 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 548 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
549 int ret; 549 int ret;
550 550
551 chan = dma_request_slave_channel_reason(dev, chan_name); 551 chan = dma_request_slave_channel_reason(dev, chan_name);
552 if (IS_ERR(chan)) { 552 if (IS_ERR(chan)) {
553 ret = PTR_ERR(chan);
553 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret); 554 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
554 return chan; 555 return chan;
555 } 556 }
556 557
557 memset(&cfg, 0, sizeof(cfg)); 558 memset(&cfg, 0, sizeof(cfg));
558 cfg.direction = dir; 559 cfg.direction = dir;
559 if (dir == DMA_MEM_TO_DEV) { 560 if (dir == DMA_MEM_TO_DEV) {
560 cfg.dst_addr = port_addr; 561 cfg.dst_addr = port_addr;
561 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 562 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
562 } else { 563 } else {
563 cfg.src_addr = port_addr; 564 cfg.src_addr = port_addr;
564 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 565 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
565 } 566 }
566 567
567 ret = dmaengine_slave_config(chan, &cfg); 568 ret = dmaengine_slave_config(chan, &cfg);
568 if (ret) { 569 if (ret) {
569 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret); 570 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
570 dma_release_channel(chan); 571 dma_release_channel(chan);
571 return ERR_PTR(ret); 572 return ERR_PTR(ret);
572 } 573 }
573 574
574 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 575 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
575 return chan; 576 return chan;
576 } 577 }
577 578
578 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd) 579 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
579 { 580 {
580 bool read = pd->msg->flags & I2C_M_RD; 581 bool read = pd->msg->flags & I2C_M_RD;
581 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 582 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
582 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx; 583 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
583 struct dma_async_tx_descriptor *txdesc; 584 struct dma_async_tx_descriptor *txdesc;
584 dma_addr_t dma_addr; 585 dma_addr_t dma_addr;
585 dma_cookie_t cookie; 586 dma_cookie_t cookie;
586 587
587 if (PTR_ERR(chan) == -EPROBE_DEFER) { 588 if (PTR_ERR(chan) == -EPROBE_DEFER) {
588 if (read) 589 if (read)
589 chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM, 590 chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
590 pd->res->start + ICDR); 591 pd->res->start + ICDR);
591 else 592 else
592 chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV, 593 chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
593 pd->res->start + ICDR); 594 pd->res->start + ICDR);
594 } 595 }
595 596
596 if (IS_ERR(chan)) 597 if (IS_ERR(chan))
597 return; 598 return;
598 599
599 dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir); 600 dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
600 if (dma_mapping_error(pd->dev, dma_addr)) { 601 if (dma_mapping_error(pd->dev, dma_addr)) {
601 dev_dbg(pd->dev, "dma map failed, using PIO\n"); 602 dev_dbg(pd->dev, "dma map failed, using PIO\n");
602 return; 603 return;
603 } 604 }
604 605
605 sg_dma_len(&pd->sg) = pd->msg->len; 606 sg_dma_len(&pd->sg) = pd->msg->len;
606 sg_dma_address(&pd->sg) = dma_addr; 607 sg_dma_address(&pd->sg) = dma_addr;
607 608
608 pd->dma_direction = dir; 609 pd->dma_direction = dir;
609 610
610 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1, 611 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
611 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 612 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
612 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 613 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
613 if (!txdesc) { 614 if (!txdesc) {
614 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n"); 615 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
615 sh_mobile_i2c_cleanup_dma(pd); 616 sh_mobile_i2c_cleanup_dma(pd);
616 return; 617 return;
617 } 618 }
618 619
619 txdesc->callback = sh_mobile_i2c_dma_callback; 620 txdesc->callback = sh_mobile_i2c_dma_callback;
620 txdesc->callback_param = pd; 621 txdesc->callback_param = pd;
621 622
622 cookie = dmaengine_submit(txdesc); 623 cookie = dmaengine_submit(txdesc);
623 if (dma_submit_error(cookie)) { 624 if (dma_submit_error(cookie)) {
624 dev_dbg(pd->dev, "submitting dma failed, using PIO\n"); 625 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
625 sh_mobile_i2c_cleanup_dma(pd); 626 sh_mobile_i2c_cleanup_dma(pd);
626 return; 627 return;
627 } 628 }
628 629
629 dma_async_issue_pending(chan); 630 dma_async_issue_pending(chan);
630 } 631 }
631 632
632 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, 633 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
633 bool do_init) 634 bool do_init)
634 { 635 {
635 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { 636 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
636 dev_err(pd->dev, "Unsupported zero length i2c read\n"); 637 dev_err(pd->dev, "Unsupported zero length i2c read\n");
637 return -EOPNOTSUPP; 638 return -EOPNOTSUPP;
638 } 639 }
639 640
640 if (do_init) { 641 if (do_init) {
641 /* Initialize channel registers */ 642 /* Initialize channel registers */
642 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 643 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
643 644
644 /* Enable channel and configure rx ack */ 645 /* Enable channel and configure rx ack */
645 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 646 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
646 647
647 /* Set the clock */ 648 /* Set the clock */
648 iic_wr(pd, ICCL, pd->iccl & 0xff); 649 iic_wr(pd, ICCL, pd->iccl & 0xff);
649 iic_wr(pd, ICCH, pd->icch & 0xff); 650 iic_wr(pd, ICCH, pd->icch & 0xff);
650 } 651 }
651 652
652 pd->msg = usr_msg; 653 pd->msg = usr_msg;
653 pd->pos = -1; 654 pd->pos = -1;
654 pd->sr = 0; 655 pd->sr = 0;
655 656
656 if (pd->msg->len > 8) 657 if (pd->msg->len > 8)
657 sh_mobile_i2c_xfer_dma(pd); 658 sh_mobile_i2c_xfer_dma(pd);
658 659
659 /* Enable all interrupts to begin with */ 660 /* Enable all interrupts to begin with */
660 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 661 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
661 return 0; 662 return 0;
662 } 663 }
663 664
664 static int poll_dte(struct sh_mobile_i2c_data *pd) 665 static int poll_dte(struct sh_mobile_i2c_data *pd)
665 { 666 {
666 int i; 667 int i;
667 668
668 for (i = 1000; i; i--) { 669 for (i = 1000; i; i--) {
669 u_int8_t val = iic_rd(pd, ICSR); 670 u_int8_t val = iic_rd(pd, ICSR);
670 671
671 if (val & ICSR_DTE) 672 if (val & ICSR_DTE)
672 break; 673 break;
673 674
674 if (val & ICSR_TACK) 675 if (val & ICSR_TACK)
675 return -ENXIO; 676 return -ENXIO;
676 677
677 udelay(10); 678 udelay(10);
678 } 679 }
679 680
680 return i ? 0 : -ETIMEDOUT; 681 return i ? 0 : -ETIMEDOUT;
681 } 682 }
682 683
683 static int poll_busy(struct sh_mobile_i2c_data *pd) 684 static int poll_busy(struct sh_mobile_i2c_data *pd)
684 { 685 {
685 int i; 686 int i;
686 687
687 for (i = 1000; i; i--) { 688 for (i = 1000; i; i--) {
688 u_int8_t val = iic_rd(pd, ICSR); 689 u_int8_t val = iic_rd(pd, ICSR);
689 690
690 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 691 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
691 692
692 /* the interrupt handler may wake us up before the 693 /* the interrupt handler may wake us up before the
693 * transfer is finished, so poll the hardware 694 * transfer is finished, so poll the hardware
694 * until we're done. 695 * until we're done.
695 */ 696 */
696 if (!(val & ICSR_BUSY)) { 697 if (!(val & ICSR_BUSY)) {
697 /* handle missing acknowledge and arbitration lost */ 698 /* handle missing acknowledge and arbitration lost */
698 val |= pd->sr; 699 val |= pd->sr;
699 if (val & ICSR_TACK) 700 if (val & ICSR_TACK)
700 return -ENXIO; 701 return -ENXIO;
701 if (val & ICSR_AL) 702 if (val & ICSR_AL)
702 return -EAGAIN; 703 return -EAGAIN;
703 break; 704 break;
704 } 705 }
705 706
706 udelay(10); 707 udelay(10);
707 } 708 }
708 709
709 return i ? 0 : -ETIMEDOUT; 710 return i ? 0 : -ETIMEDOUT;
710 } 711 }
711 712
712 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 713 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
713 struct i2c_msg *msgs, 714 struct i2c_msg *msgs,
714 int num) 715 int num)
715 { 716 {
716 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 717 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
717 struct i2c_msg *msg; 718 struct i2c_msg *msg;
718 int err = 0; 719 int err = 0;
719 int i, k; 720 int i, k;
720 721
721 activate_ch(pd); 722 activate_ch(pd);
722 723
723 /* Process all messages */ 724 /* Process all messages */
724 for (i = 0; i < num; i++) { 725 for (i = 0; i < num; i++) {
725 bool do_start = pd->send_stop || !i; 726 bool do_start = pd->send_stop || !i;
726 msg = &msgs[i]; 727 msg = &msgs[i];
727 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP; 728 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
728 729
729 err = start_ch(pd, msg, do_start); 730 err = start_ch(pd, msg, do_start);
730 if (err) 731 if (err)
731 break; 732 break;
732 733
733 if (do_start) 734 if (do_start)
734 i2c_op(pd, OP_START, 0); 735 i2c_op(pd, OP_START, 0);
735 736
736 /* The interrupt handler takes care of the rest... */ 737 /* The interrupt handler takes care of the rest... */
737 k = wait_event_timeout(pd->wait, 738 k = wait_event_timeout(pd->wait,
738 pd->sr & (ICSR_TACK | SW_DONE), 739 pd->sr & (ICSR_TACK | SW_DONE),
739 5 * HZ); 740 5 * HZ);
740 if (!k) { 741 if (!k) {
741 dev_err(pd->dev, "Transfer request timed out\n"); 742 dev_err(pd->dev, "Transfer request timed out\n");
742 if (pd->dma_direction != DMA_NONE) 743 if (pd->dma_direction != DMA_NONE)
743 sh_mobile_i2c_cleanup_dma(pd); 744 sh_mobile_i2c_cleanup_dma(pd);
744 745
745 err = -ETIMEDOUT; 746 err = -ETIMEDOUT;
746 break; 747 break;
747 } 748 }
748 749
749 if (pd->send_stop) 750 if (pd->send_stop)
750 err = poll_busy(pd); 751 err = poll_busy(pd);
751 else 752 else
752 err = poll_dte(pd); 753 err = poll_dte(pd);
753 if (err < 0) 754 if (err < 0)
754 break; 755 break;
755 } 756 }
756 757
757 deactivate_ch(pd); 758 deactivate_ch(pd);
758 759
759 if (!err) 760 if (!err)
760 err = num; 761 err = num;
761 return err; 762 return err;
762 } 763 }
763 764
764 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 765 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
765 { 766 {
766 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 767 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
767 } 768 }
768 769
769 static struct i2c_algorithm sh_mobile_i2c_algorithm = { 770 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
770 .functionality = sh_mobile_i2c_func, 771 .functionality = sh_mobile_i2c_func,
771 .master_xfer = sh_mobile_i2c_xfer, 772 .master_xfer = sh_mobile_i2c_xfer,
772 }; 773 };
773 774
774 static const struct sh_mobile_dt_config default_dt_config = { 775 static const struct sh_mobile_dt_config default_dt_config = {
775 .clks_per_count = 1, 776 .clks_per_count = 1,
776 }; 777 };
777 778
778 static const struct sh_mobile_dt_config fast_clock_dt_config = { 779 static const struct sh_mobile_dt_config fast_clock_dt_config = {
779 .clks_per_count = 2, 780 .clks_per_count = 2,
780 }; 781 };
781 782
782 static const struct of_device_id sh_mobile_i2c_dt_ids[] = { 783 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
783 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, 784 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
784 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config }, 785 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
785 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config }, 786 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
786 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config }, 787 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
787 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config }, 788 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
788 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config }, 789 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
789 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config }, 790 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
790 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config }, 791 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
791 {}, 792 {},
792 }; 793 };
793 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); 794 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
794 795
795 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd) 796 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
796 { 797 {
797 if (!IS_ERR(pd->dma_tx)) { 798 if (!IS_ERR(pd->dma_tx)) {
798 dma_release_channel(pd->dma_tx); 799 dma_release_channel(pd->dma_tx);
799 pd->dma_tx = ERR_PTR(-EPROBE_DEFER); 800 pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
800 } 801 }
801 802
802 if (!IS_ERR(pd->dma_rx)) { 803 if (!IS_ERR(pd->dma_rx)) {
803 dma_release_channel(pd->dma_rx); 804 dma_release_channel(pd->dma_rx);
804 pd->dma_rx = ERR_PTR(-EPROBE_DEFER); 805 pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
805 } 806 }
806 } 807 }
807 808
808 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd) 809 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
809 { 810 {
810 struct resource *res; 811 struct resource *res;
811 resource_size_t n; 812 resource_size_t n;
812 int k = 0, ret; 813 int k = 0, ret;
813 814
814 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 815 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
815 for (n = res->start; n <= res->end; n++) { 816 for (n = res->start; n <= res->end; n++) {
816 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr, 817 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
817 0, dev_name(&dev->dev), pd); 818 0, dev_name(&dev->dev), pd);
818 if (ret) { 819 if (ret) {
819 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n); 820 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
820 return ret; 821 return ret;
821 } 822 }
822 } 823 }
823 k++; 824 k++;
824 } 825 }
825 826
826 return k > 0 ? 0 : -ENOENT; 827 return k > 0 ? 0 : -ENOENT;
827 } 828 }
828 829
829 static int sh_mobile_i2c_probe(struct platform_device *dev) 830 static int sh_mobile_i2c_probe(struct platform_device *dev)
830 { 831 {
831 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev); 832 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
832 struct sh_mobile_i2c_data *pd; 833 struct sh_mobile_i2c_data *pd;
833 struct i2c_adapter *adap; 834 struct i2c_adapter *adap;
834 struct resource *res; 835 struct resource *res;
835 int ret; 836 int ret;
836 u32 bus_speed; 837 u32 bus_speed;
837 838
838 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); 839 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
839 if (!pd) 840 if (!pd)
840 return -ENOMEM; 841 return -ENOMEM;
841 842
842 pd->clk = devm_clk_get(&dev->dev, NULL); 843 pd->clk = devm_clk_get(&dev->dev, NULL);
843 if (IS_ERR(pd->clk)) { 844 if (IS_ERR(pd->clk)) {
844 dev_err(&dev->dev, "cannot get clock\n"); 845 dev_err(&dev->dev, "cannot get clock\n");
845 return PTR_ERR(pd->clk); 846 return PTR_ERR(pd->clk);
846 } 847 }
847 848
848 ret = sh_mobile_i2c_hook_irqs(dev, pd); 849 ret = sh_mobile_i2c_hook_irqs(dev, pd);
849 if (ret) 850 if (ret)
850 return ret; 851 return ret;
851 852
852 pd->dev = &dev->dev; 853 pd->dev = &dev->dev;
853 platform_set_drvdata(dev, pd); 854 platform_set_drvdata(dev, pd);
854 855
855 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 856 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
856 857
857 pd->res = res; 858 pd->res = res;
858 pd->reg = devm_ioremap_resource(&dev->dev, res); 859 pd->reg = devm_ioremap_resource(&dev->dev, res);
859 if (IS_ERR(pd->reg)) 860 if (IS_ERR(pd->reg))
860 return PTR_ERR(pd->reg); 861 return PTR_ERR(pd->reg);
861 862
862 /* Use platform data bus speed or STANDARD_MODE */ 863 /* Use platform data bus speed or STANDARD_MODE */
863 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed); 864 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
864 pd->bus_speed = ret ? STANDARD_MODE : bus_speed; 865 pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
865 866
866 pd->clks_per_count = 1; 867 pd->clks_per_count = 1;
867 868
868 if (dev->dev.of_node) { 869 if (dev->dev.of_node) {
869 const struct of_device_id *match; 870 const struct of_device_id *match;
870 871
871 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev); 872 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
872 if (match) { 873 if (match) {
873 const struct sh_mobile_dt_config *config; 874 const struct sh_mobile_dt_config *config;
874 875
875 config = match->data; 876 config = match->data;
876 pd->clks_per_count = config->clks_per_count; 877 pd->clks_per_count = config->clks_per_count;
877 } 878 }
878 } else { 879 } else {
879 if (pdata && pdata->bus_speed) 880 if (pdata && pdata->bus_speed)
880 pd->bus_speed = pdata->bus_speed; 881 pd->bus_speed = pdata->bus_speed;
881 if (pdata && pdata->clks_per_count) 882 if (pdata && pdata->clks_per_count)
882 pd->clks_per_count = pdata->clks_per_count; 883 pd->clks_per_count = pdata->clks_per_count;
883 } 884 }
884 885
885 /* The IIC blocks on SH-Mobile ARM processors 886 /* The IIC blocks on SH-Mobile ARM processors
886 * come with two new bits in ICIC. 887 * come with two new bits in ICIC.
887 */ 888 */
888 if (resource_size(res) > 0x17) 889 if (resource_size(res) > 0x17)
889 pd->flags |= IIC_FLAG_HAS_ICIC67; 890 pd->flags |= IIC_FLAG_HAS_ICIC67;
890 891
891 ret = sh_mobile_i2c_init(pd); 892 ret = sh_mobile_i2c_init(pd);
892 if (ret) 893 if (ret)
893 return ret; 894 return ret;
894 895
895 /* Init DMA */ 896 /* Init DMA */
896 sg_init_table(&pd->sg, 1); 897 sg_init_table(&pd->sg, 1);
897 pd->dma_direction = DMA_NONE; 898 pd->dma_direction = DMA_NONE;
898 pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER); 899 pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
899 900
900 /* Enable Runtime PM for this device. 901 /* Enable Runtime PM for this device.
901 * 902 *
902 * Also tell the Runtime PM core to ignore children 903 * Also tell the Runtime PM core to ignore children
903 * for this device since it is valid for us to suspend 904 * for this device since it is valid for us to suspend
904 * this I2C master driver even though the slave devices 905 * this I2C master driver even though the slave devices
905 * on the I2C bus may not be suspended. 906 * on the I2C bus may not be suspended.
906 * 907 *
907 * The state of the I2C hardware bus is unaffected by 908 * The state of the I2C hardware bus is unaffected by
908 * the Runtime PM state. 909 * the Runtime PM state.
909 */ 910 */
910 pm_suspend_ignore_children(&dev->dev, true); 911 pm_suspend_ignore_children(&dev->dev, true);
911 pm_runtime_enable(&dev->dev); 912 pm_runtime_enable(&dev->dev);
912 913
913 /* setup the private data */ 914 /* setup the private data */
914 adap = &pd->adap; 915 adap = &pd->adap;
915 i2c_set_adapdata(adap, pd); 916 i2c_set_adapdata(adap, pd);
916 917
917 adap->owner = THIS_MODULE; 918 adap->owner = THIS_MODULE;
918 adap->algo = &sh_mobile_i2c_algorithm; 919 adap->algo = &sh_mobile_i2c_algorithm;
919 adap->dev.parent = &dev->dev; 920 adap->dev.parent = &dev->dev;
920 adap->retries = 5; 921 adap->retries = 5;
921 adap->nr = dev->id; 922 adap->nr = dev->id;
922 adap->dev.of_node = dev->dev.of_node; 923 adap->dev.of_node = dev->dev.of_node;
923 924
924 strlcpy(adap->name, dev->name, sizeof(adap->name)); 925 strlcpy(adap->name, dev->name, sizeof(adap->name));
925 926
926 spin_lock_init(&pd->lock); 927 spin_lock_init(&pd->lock);
927 init_waitqueue_head(&pd->wait); 928 init_waitqueue_head(&pd->wait);
928 929
929 ret = i2c_add_numbered_adapter(adap); 930 ret = i2c_add_numbered_adapter(adap);
930 if (ret < 0) { 931 if (ret < 0) {
931 sh_mobile_i2c_release_dma(pd); 932 sh_mobile_i2c_release_dma(pd);
932 dev_err(&dev->dev, "cannot add numbered adapter\n"); 933 dev_err(&dev->dev, "cannot add numbered adapter\n");
933 return ret; 934 return ret;
934 } 935 }
935 936
936 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed); 937 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
937 938
938 return 0; 939 return 0;
939 } 940 }
940 941
941 static int sh_mobile_i2c_remove(struct platform_device *dev) 942 static int sh_mobile_i2c_remove(struct platform_device *dev)
942 { 943 {
943 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 944 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
944 945
945 i2c_del_adapter(&pd->adap); 946 i2c_del_adapter(&pd->adap);
946 sh_mobile_i2c_release_dma(pd); 947 sh_mobile_i2c_release_dma(pd);
947 pm_runtime_disable(&dev->dev); 948 pm_runtime_disable(&dev->dev);
948 return 0; 949 return 0;
949 } 950 }
950 951
951 static int sh_mobile_i2c_runtime_nop(struct device *dev) 952 static int sh_mobile_i2c_runtime_nop(struct device *dev)
952 { 953 {
953 /* Runtime PM callback shared between ->runtime_suspend() 954 /* Runtime PM callback shared between ->runtime_suspend()
954 * and ->runtime_resume(). Simply returns success. 955 * and ->runtime_resume(). Simply returns success.
955 * 956 *
956 * This driver re-initializes all registers after 957 * This driver re-initializes all registers after
957 * pm_runtime_get_sync() anyway so there is no need 958 * pm_runtime_get_sync() anyway so there is no need
958 * to save and restore registers here. 959 * to save and restore registers here.
959 */ 960 */
960 return 0; 961 return 0;
961 } 962 }
962 963
963 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { 964 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
964 .runtime_suspend = sh_mobile_i2c_runtime_nop, 965 .runtime_suspend = sh_mobile_i2c_runtime_nop,
965 .runtime_resume = sh_mobile_i2c_runtime_nop, 966 .runtime_resume = sh_mobile_i2c_runtime_nop,
966 }; 967 };
967 968
968 static struct platform_driver sh_mobile_i2c_driver = { 969 static struct platform_driver sh_mobile_i2c_driver = {
969 .driver = { 970 .driver = {
970 .name = "i2c-sh_mobile", 971 .name = "i2c-sh_mobile",
971 .pm = &sh_mobile_i2c_dev_pm_ops, 972 .pm = &sh_mobile_i2c_dev_pm_ops,
972 .of_match_table = sh_mobile_i2c_dt_ids, 973 .of_match_table = sh_mobile_i2c_dt_ids,
973 }, 974 },
974 .probe = sh_mobile_i2c_probe, 975 .probe = sh_mobile_i2c_probe,
975 .remove = sh_mobile_i2c_remove, 976 .remove = sh_mobile_i2c_remove,
976 }; 977 };
977 978
978 static int __init sh_mobile_i2c_adap_init(void) 979 static int __init sh_mobile_i2c_adap_init(void)
979 { 980 {
980 return platform_driver_register(&sh_mobile_i2c_driver); 981 return platform_driver_register(&sh_mobile_i2c_driver);
981 } 982 }
982 subsys_initcall(sh_mobile_i2c_adap_init); 983 subsys_initcall(sh_mobile_i2c_adap_init);
983 984
984 static void __exit sh_mobile_i2c_adap_exit(void) 985 static void __exit sh_mobile_i2c_adap_exit(void)
985 { 986 {
986 platform_driver_unregister(&sh_mobile_i2c_driver); 987 platform_driver_unregister(&sh_mobile_i2c_driver);
987 } 988 }
988 module_exit(sh_mobile_i2c_adap_exit); 989 module_exit(sh_mobile_i2c_adap_exit);
989 990
990 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 991 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
991 MODULE_AUTHOR("Magnus Damm and Wolfram Sang"); 992 MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
992 MODULE_LICENSE("GPL v2"); 993 MODULE_LICENSE("GPL v2");
993 MODULE_ALIAS("platform:i2c-sh_mobile"); 994 MODULE_ALIAS("platform:i2c-sh_mobile");
994 995