edac: Improve the comments to better describe the memory concepts

The Computer memory terminology has changed with time since EDAC was originally written: new concepts were introduced, and some things have different meanings, depending on the memory architecture. Improve the definition of all related terms. Also, describe each memory type in a more detailed fashion. No functional changes. Just comments were touched. Acked-by: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

edac: Improve the comments to better describe the memory concepts
The Computer memory terminology has changed with time since EDAC was originally written: new concepts were introduced, and some things have different meanings, depending on the memory architecture. Improve the definition of all related terms. Also, describe each memory type in a more detailed fashion. No functional changes. Just comments were touched. Acked-by: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Mauro Carvalho Chehab
1 parent b877763ea0
Showing 1 changed file with 111 additions and 46 deletions Side-by-side Diff
include/linux/edac.h
@@ -66,25 +66,64 @@
 #define DEV_FLAG_X32		BIT(DEV_X32)
 #define DEV_FLAG_X64		BIT(DEV_X64)
  
-/* memory types */
+/**
+ * enum mem_type - memory types. For a more detailed reference, please see
+ *			http://en.wikipedia.org/wiki/DRAM
+ *
+ * @MEM_EMPTY		Empty csrow
+ * @MEM_RESERVED:	Reserved csrow type
+ * @MEM_UNKNOWN:	Unknown csrow type
+ * @MEM_FPM:		FPM - Fast Page Mode, used on systems up to 1995.
+ * @MEM_EDO:		EDO - Extended data out, used on systems up to 1998.
+ * @MEM_BEDO:		BEDO - Burst Extended data out, an EDO variant.
+ * @MEM_SDR:		SDR - Single data rate SDRAM
+ *			http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
+ *			They use 3 pins for chip select: Pins 0 and 2 are
+ *			for rank 0; pins 1 and 3 are for rank 1, if the memory
+ *			is dual-rank.
+ * @MEM_RDR:		Registered SDR SDRAM
+ * @MEM_DDR:		Double data rate SDRAM
+ *			http://en.wikipedia.org/wiki/DDR_SDRAM
+ * @MEM_RDDR:		Registered Double data rate SDRAM
+ *			This is a variant of the DDR memories.
+ *			A registered memory has a buffer inside it, hiding
+ *			part of the memory details to the memory controller.
+ * @MEM_RMBS:		Rambus DRAM, used on a few Pentium III/IV controllers.
+ * @MEM_DDR2:		DDR2 RAM, as described at JEDEC JESD79-2F.
+ *			Those memories are labed as "PC2-" instead of "PC" to
+ *			differenciate from DDR.
+ * @MEM_FB_DDR2:	Fully-Buffered DDR2, as described at JEDEC Std No. 205
+ *			and JESD206.
+ *			Those memories are accessed per DIMM slot, and not by
+ *			a chip select signal.
+ * @MEM_RDDR2:		Registered DDR2 RAM
+ *			This is a variant of the DDR2 memories.
+ * @MEM_XDR:		Rambus XDR
+ *			It is an evolution of the original RAMBUS memories,
+ *			created to compete with DDR2. Weren't used on any
+ *			x86 arch, but cell_edac PPC memory controller uses it.
+ * @MEM_DDR3:		DDR3 RAM
+ * @MEM_RDDR3:		Registered DDR3 RAM
+ *			This is a variant of the DDR3 memories.
+ */
 enum mem_type {
-	MEM_EMPTY = 0,		/* Empty csrow */
-	MEM_RESERVED,		/* Reserved csrow type */
-	MEM_UNKNOWN,		/* Unknown csrow type */
-	MEM_FPM,		/* Fast page mode */
-	MEM_EDO,		/* Extended data out */
-	MEM_BEDO,		/* Burst Extended data out */
-	MEM_SDR,		/* Single data rate SDRAM */
-	MEM_RDR,		/* Registered single data rate SDRAM */
-	MEM_DDR,		/* Double data rate SDRAM */
-	MEM_RDDR,		/* Registered Double data rate SDRAM */
-	MEM_RMBS,		/* Rambus DRAM */
-	MEM_DDR2,		/* DDR2 RAM */
-	MEM_FB_DDR2,		/* fully buffered DDR2 */
-	MEM_RDDR2,		/* Registered DDR2 RAM */
-	MEM_XDR,		/* Rambus XDR */
-	MEM_DDR3,		/* DDR3 RAM */
-	MEM_RDDR3,		/* Registered DDR3 RAM */
+	MEM_EMPTY = 0,
+	MEM_RESERVED,
+	MEM_UNKNOWN,
+	MEM_FPM,
+	MEM_EDO,
+	MEM_BEDO,
+	MEM_SDR,
+	MEM_RDR,
+	MEM_DDR,
+	MEM_RDDR,
+	MEM_RMBS,
+	MEM_DDR2,
+	MEM_FB_DDR2,
+	MEM_RDDR2,
+	MEM_XDR,
+	MEM_DDR3,
+	MEM_RDDR3,
 };
  
 #define MEM_FLAG_EMPTY		BIT(MEM_EMPTY)
  
@@ -162,9 +201,10 @@
 #define OP_OFFLINE		0x300
  
 /*
+ * Concepts used at the EDAC subsystem
+ *
  * There are several things to be aware of that aren't at all obvious:
  *
- *
  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
  *
  * These are some of the many terms that are thrown about that don't always
  
  
  
  
  
@@ -172,37 +212,62 @@
  * creating a common ground for discussion, terms and their definitions
  * will be established.
  *
- * Memory devices:	The individual chip on a memory stick.  These devices
- *			commonly output 4 and 8 bits each.  Grouping several
- *			of these in parallel provides 64 bits which is common
- *			for a memory stick.
+ * Memory devices:	The individual DRAM chips on a memory stick.  These
+ *			devices commonly output 4 and 8 bits each (x4, x8).
+ *			Grouping several of these in parallel provides the
+ *			number of bits that the memory controller expects:
+ *			typically 72 bits, in order to provide 64 bits +
+ *			8 bits of ECC data.
  *
  * Memory Stick:	A printed circuit board that aggregates multiple
- *			memory devices in parallel.  This is the atomic
- *			memory component that is purchaseable by Joe consumer
- *			and loaded into a memory socket.
+ *			memory devices in parallel.  In general, this is the
+ *			Field Replaceable Unit (FRU) which gets replaced, in
+ *			the case of excessive errors. Most often it is also
+ *			called DIMM (Dual Inline Memory Module).
  *
- * Socket:		A physical connector on the motherboard that accepts
- *			a single memory stick.
+ * Memory Socket:	A physical connector on the motherboard that accepts
+ *			a single memory stick. Also called as "slot" on several
+ *			datasheets.
  *
- * Channel:		Set of memory devices on a memory stick that must be
- *			grouped in parallel with one or more additional
- *			channels from other memory sticks.  This parallel
- *			grouping of the output from multiple channels are
- *			necessary for the smallest granularity of memory access.
- *			Some memory controllers are capable of single channel -
- *			which means that memory sticks can be loaded
- *			individually.  Other memory controllers are only
- *			capable of dual channel - which means that memory
- *			sticks must be loaded as pairs (see "socket set").
+ * Channel:		A memory controller channel, responsible to communicate
+ *			with a group of DIMMs. Each channel has its own
+ *			independent control (command) and data bus, and can
+ *			be used independently or grouped with other channels.
  *
- * Chip-select row:	All of the memory devices that are selected together.
- *			for a single, minimum grain of memory access.
- *			This selects all of the parallel memory devices across
- *			all of the parallel channels.  Common chip-select rows
- *			for single channel are 64 bits, for dual channel 128
- *			bits.
+ * Branch:		It is typically the highest hierarchy on a
+ *			Fully-Buffered DIMM memory controller.
+ *			Typically, it contains two channels.
+ *			Two channels at the same branch can be used in single
+ *			mode or in lockstep mode.
+ *			When lockstep is enabled, the cacheline is doubled,
+ *			but it generally brings some performance penalty.
+ *			Also, it is generally not possible to point to just one
+ *			memory stick when an error occurs, as the error
+ *			correction code is calculated using two DIMMs instead
+ *			of one. Due to that, it is capable of correcting more
+ *			errors than on single mode.
  *
+ * Single-channel:	The data accessed by the memory controller is contained
+ *			into one dimm only. E. g. if the data is 64 bits-wide,
+ *			the data flows to the CPU using one 64 bits parallel
+ *			access.
+ *			Typically used with SDR, DDR, DDR2 and DDR3 memories.
+ *			FB-DIMM and RAMBUS use a different concept for channel,
+ *			so this concept doesn't apply there.
+ *
+ * Double-channel:	The data size accessed by the memory controller is
+ *			interlaced into two dimms, accessed at the same time.
+ *			E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
+ *			the data flows to the CPU using a 128 bits parallel
+ *			access.
+ *
+ * Chip-select row:	This is the name of the DRAM signal used to select the
+ *			DRAM ranks to be accessed. Common chip-select rows for
+ *			single channel are 64 bits, for dual channel 128 bits.
+ *			It may not be visible by the memory controller, as some
+ *			DIMM types have a memory buffer that can hide direct
+ *			access to it from the Memory Controller.
+ *
  * Single-Ranked stick:	A Single-ranked stick has 1 chip-select row of memory.
  *			Motherboards commonly drive two chip-select pins to
  *			a memory stick. A single-ranked stick, will occupy
@@ -214,8 +279,8 @@
  *
  * Double-sided stick:	DEPRECATED TERM, see Double-Ranked stick.
  *			A double-sided stick has two chip-select rows which
- *			access different sets of memory devices.  The two
- *			rows cannot be accessed concurrently.  "Double-sided"
+ *			access different sets of memory devices. The two
+ *			rows cannot be accessed concurrently. "Double-sided"
  *			is irrespective of the memory devices being mounted
  *			on both sides of the memory stick.
  *
...	...	@@ -66,25 +66,64 @@
66	66	#define DEV_FLAG_X32 BIT(DEV_X32)
67	67	#define DEV_FLAG_X64 BIT(DEV_X64)
68	68
69		-/* memory types */
	69	+/**
	70	+ * enum mem_type - memory types. For a more detailed reference, please see
	71	+ * http://en.wikipedia.org/wiki/DRAM
	72	+ *
	73	+ * @MEM_EMPTY Empty csrow
	74	+ * @MEM_RESERVED: Reserved csrow type
	75	+ * @MEM_UNKNOWN: Unknown csrow type
	76	+ * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
	77	+ * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
	78	+ * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
	79	+ * @MEM_SDR: SDR - Single data rate SDRAM
	80	+ * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
	81	+ * They use 3 pins for chip select: Pins 0 and 2 are
	82	+ * for rank 0; pins 1 and 3 are for rank 1, if the memory
	83	+ * is dual-rank.
	84	+ * @MEM_RDR: Registered SDR SDRAM
	85	+ * @MEM_DDR: Double data rate SDRAM
	86	+ * http://en.wikipedia.org/wiki/DDR_SDRAM
	87	+ * @MEM_RDDR: Registered Double data rate SDRAM
	88	+ * This is a variant of the DDR memories.
	89	+ * A registered memory has a buffer inside it, hiding
	90	+ * part of the memory details to the memory controller.
	91	+ * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
	92	+ * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
	93	+ * Those memories are labed as "PC2-" instead of "PC" to
	94	+ * differenciate from DDR.
	95	+ * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
	96	+ * and JESD206.
	97	+ * Those memories are accessed per DIMM slot, and not by
	98	+ * a chip select signal.
	99	+ * @MEM_RDDR2: Registered DDR2 RAM
	100	+ * This is a variant of the DDR2 memories.
	101	+ * @MEM_XDR: Rambus XDR
	102	+ * It is an evolution of the original RAMBUS memories,
	103	+ * created to compete with DDR2. Weren't used on any
	104	+ * x86 arch, but cell_edac PPC memory controller uses it.
	105	+ * @MEM_DDR3: DDR3 RAM
	106	+ * @MEM_RDDR3: Registered DDR3 RAM
	107	+ * This is a variant of the DDR3 memories.
	108	+ */
70	109	enum mem_type {
71		- MEM_EMPTY = 0, /* Empty csrow */
72		- MEM_RESERVED, /* Reserved csrow type */
73		- MEM_UNKNOWN, /* Unknown csrow type */
74		- MEM_FPM, /* Fast page mode */
75		- MEM_EDO, /* Extended data out */
76		- MEM_BEDO, /* Burst Extended data out */
77		- MEM_SDR, /* Single data rate SDRAM */
78		- MEM_RDR, /* Registered single data rate SDRAM */
79		- MEM_DDR, /* Double data rate SDRAM */
80		- MEM_RDDR, /* Registered Double data rate SDRAM */
81		- MEM_RMBS, /* Rambus DRAM */
82		- MEM_DDR2, /* DDR2 RAM */
83		- MEM_FB_DDR2, /* fully buffered DDR2 */
84		- MEM_RDDR2, /* Registered DDR2 RAM */
85		- MEM_XDR, /* Rambus XDR */
86		- MEM_DDR3, /* DDR3 RAM */
87		- MEM_RDDR3, /* Registered DDR3 RAM */
	110	+ MEM_EMPTY = 0,
	111	+ MEM_RESERVED,
	112	+ MEM_UNKNOWN,
	113	+ MEM_FPM,
	114	+ MEM_EDO,
	115	+ MEM_BEDO,
	116	+ MEM_SDR,
	117	+ MEM_RDR,
	118	+ MEM_DDR,
	119	+ MEM_RDDR,
	120	+ MEM_RMBS,
	121	+ MEM_DDR2,
	122	+ MEM_FB_DDR2,
	123	+ MEM_RDDR2,
	124	+ MEM_XDR,
	125	+ MEM_DDR3,
	126	+ MEM_RDDR3,
88	127	};
89	128
90	129	#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
91	130
...	...	@@ -162,9 +201,10 @@
162	201	#define OP_OFFLINE 0x300
163	202
164	203	/*
	204	+ * Concepts used at the EDAC subsystem
	205	+ *
165	206	* There are several things to be aware of that aren't at all obvious:
166	207	*
167		- *
168	208	* SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
169	209	*
170	210	* These are some of the many terms that are thrown about that don't always
171	211
172	212
173	213
174	214
175	215
...	...	@@ -172,37 +212,62 @@
172	212	* creating a common ground for discussion, terms and their definitions
173	213	* will be established.
174	214	*
175		- * Memory devices: The individual chip on a memory stick. These devices
176		- * commonly output 4 and 8 bits each. Grouping several
177		- * of these in parallel provides 64 bits which is common
178		- * for a memory stick.
	215	+ * Memory devices: The individual DRAM chips on a memory stick. These
	216	+ * devices commonly output 4 and 8 bits each (x4, x8).
	217	+ * Grouping several of these in parallel provides the
	218	+ * number of bits that the memory controller expects:
	219	+ * typically 72 bits, in order to provide 64 bits +
	220	+ * 8 bits of ECC data.
179	221	*
180	222	* Memory Stick: A printed circuit board that aggregates multiple
181		- * memory devices in parallel. This is the atomic
182		- * memory component that is purchaseable by Joe consumer
183		- * and loaded into a memory socket.
	223	+ * memory devices in parallel. In general, this is the
	224	+ * Field Replaceable Unit (FRU) which gets replaced, in
	225	+ * the case of excessive errors. Most often it is also
	226	+ * called DIMM (Dual Inline Memory Module).
184	227	*
185		- * Socket: A physical connector on the motherboard that accepts
186		- * a single memory stick.
	228	+ * Memory Socket: A physical connector on the motherboard that accepts
	229	+ * a single memory stick. Also called as "slot" on several
	230	+ * datasheets.
187	231	*
188		- * Channel: Set of memory devices on a memory stick that must be
189		- * grouped in parallel with one or more additional
190		- * channels from other memory sticks. This parallel
191		- * grouping of the output from multiple channels are
192		- * necessary for the smallest granularity of memory access.
193		- * Some memory controllers are capable of single channel -
194		- * which means that memory sticks can be loaded
195		- * individually. Other memory controllers are only
196		- * capable of dual channel - which means that memory
197		- * sticks must be loaded as pairs (see "socket set").
	232	+ * Channel: A memory controller channel, responsible to communicate
	233	+ * with a group of DIMMs. Each channel has its own
	234	+ * independent control (command) and data bus, and can
	235	+ * be used independently or grouped with other channels.
198	236	*
199		- * Chip-select row: All of the memory devices that are selected together.
200		- * for a single, minimum grain of memory access.
201		- * This selects all of the parallel memory devices across
202		- * all of the parallel channels. Common chip-select rows
203		- * for single channel are 64 bits, for dual channel 128
204		- * bits.
	237	+ * Branch: It is typically the highest hierarchy on a
	238	+ * Fully-Buffered DIMM memory controller.
	239	+ * Typically, it contains two channels.
	240	+ * Two channels at the same branch can be used in single
	241	+ * mode or in lockstep mode.
	242	+ * When lockstep is enabled, the cacheline is doubled,
	243	+ * but it generally brings some performance penalty.
	244	+ * Also, it is generally not possible to point to just one
	245	+ * memory stick when an error occurs, as the error
	246	+ * correction code is calculated using two DIMMs instead
	247	+ * of one. Due to that, it is capable of correcting more
	248	+ * errors than on single mode.
205	249	*
	250	+ * Single-channel: The data accessed by the memory controller is contained
	251	+ * into one dimm only. E. g. if the data is 64 bits-wide,
	252	+ * the data flows to the CPU using one 64 bits parallel
	253	+ * access.
	254	+ * Typically used with SDR, DDR, DDR2 and DDR3 memories.
	255	+ * FB-DIMM and RAMBUS use a different concept for channel,
	256	+ * so this concept doesn't apply there.
	257	+ *
	258	+ * Double-channel: The data size accessed by the memory controller is
	259	+ * interlaced into two dimms, accessed at the same time.
	260	+ * E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
	261	+ * the data flows to the CPU using a 128 bits parallel
	262	+ * access.
	263	+ *
	264	+ * Chip-select row: This is the name of the DRAM signal used to select the
	265	+ * DRAM ranks to be accessed. Common chip-select rows for
	266	+ * single channel are 64 bits, for dual channel 128 bits.
	267	+ * It may not be visible by the memory controller, as some
	268	+ * DIMM types have a memory buffer that can hide direct
	269	+ * access to it from the Memory Controller.
	270	+ *
206	271	* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
207	272	* Motherboards commonly drive two chip-select pins to
208	273	* a memory stick. A single-ranked stick, will occupy
...	...	@@ -214,8 +279,8 @@
214	279	*
215	280	* Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
216	281	* A double-sided stick has two chip-select rows which
217		- * access different sets of memory devices. The two
218		- * rows cannot be accessed concurrently. "Double-sided"
	282	+ * access different sets of memory devices. The two
	283	+ * rows cannot be accessed concurrently. "Double-sided"
219	284	* is irrespective of the memory devices being mounted
220	285	* on both sides of the memory stick.
221	286	*