Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 021a52ac70802a94e699badb52af9d0fa728d5cd

Authored by Matt Porter
Committed by Linus Torvalds
1 parent 534afb90a9
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[PATCH] ppc32: ppc440 pagetable attributes (comments updates) 

Here's an incremental patch with comment updates and some additional
grammar cleanups.

Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 1 changed file with 13 additions and 13 deletions Side-by-side Diff

include/asm-ppc/pgtable.h
Diff comments   View file @ 021a52a
... ... @@ -227,21 +227,21 @@
227 227 * doesn't support SMP. So we can use this as software bit, like
228 228 * DIRTY.
229 229 *
230   - * PPC Book-E Linux implementation uses PPC HW PTE bit field definition,
231   - * even it doesn't have HW PTE. 0-11th LSB of PTE stand for memory
232   - * protection-related function. (See PTE structure in include/asm-ppc/mmu.h)
233   - * Definition of _PAGE_XXX in "include/asm-ppc/pagetable.h" stands for
234   - * above bits. Note that those bits values are CPU dependent, not
235   - * architecture.
  230 + * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
  231 + * for memory protection related functions (see PTE structure in
  232 + * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
  233 + * above bits. Note that the bit values are CPU specific, not architecture
  234 + * specific.
236 235 *
237   - * Kernel PTE entry holds arch-dependent swp_entry structure under certain
238   - * situation. In other words, in such situation, some portion of PTE bits
239   - * are used as swp_entry. In PPC implementation, 3-24th LSB are shared with
240   - * swp_entry, however 0-2nd three LSB still hold protection values.
241   - * That means three protection bits are reserved for both PTE and SWAP
242   - * entry at the most three LSBs.
  236 + * The kernel PTE entry holds an arch-dependent swp_entry structure under
  237 + * certain situations. In other words, in such situations some portion of
  238 + * the PTE bits are used as a swp_entry. In the PPC implementation, the
  239 + * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
  240 + * hold protection values. That means the three protection bits are
  241 + * reserved for both PTE and SWAP entry at the most significant three
  242 + * LSBs.
243 243 *
244   - * There are three protection bits available for SWAP entry;
  244 + * There are three protection bits available for SWAP entry:
245 245 * _PAGE_PRESENT
246 246 * _PAGE_FILE
247 247 * _PAGE_HASHPTE (if HW has)