Cleanup the mess in cpu_cache_init.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Cleanup the mess in cpu_cache_init.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle
1 parent 942d042d17
Showing 12 changed files with 102 additions and 88 deletions Side-by-side Diff
arch/mips/kernel/cpu-probe.c
arch/mips/mm/c-r3k.c
arch/mips/mm/c-r4k.c
arch/mips/mm/c-sb1.c
arch/mips/mm/c-tx39.c
arch/mips/mm/cache.c
include/asm-mips/cpu-features.h
include/asm-mips/cpu.h
include/asm-mips/mach-ip22/cpu-feature-overrides.h
include/asm-mips/mach-mips/cpu-feature-overrides.h
include/asm-mips/mach-rm200/cpu-feature-overrides.h
include/asm-mips/mach-sim/cpu-feature-overrides.h
@@ -191,7 +191,7 @@
 	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 }
  
-#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
+#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 		| MIPS_CPU_COUNTER)
  
 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
@@ -200,7 +200,8 @@
 	case PRID_IMP_R2000:
 		c->cputype = CPU_R2000;
 		c->isa_level = MIPS_CPU_ISA_I;
-		c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
+		c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
+		             MIPS_CPU_NOFPUEX;
 		if (__cpu_has_fpu())
 			c->options |= MIPS_CPU_FPU;
 		c->tlbsize = 64;
@@ -214,7 +215,8 @@
 		else
 			c->cputype = CPU_R3000;
 		c->isa_level = MIPS_CPU_ISA_I;
-		c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
+		c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
+		             MIPS_CPU_NOFPUEX;
 		if (__cpu_has_fpu())
 			c->options |= MIPS_CPU_FPU;
 		c->tlbsize = 64;
@@ -297,7 +299,7 @@
 	#endif
 	case PRID_IMP_TX39:
 		c->isa_level = MIPS_CPU_ISA_I;
-		c->options = MIPS_CPU_TLB;
+		c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
  
 		if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 			c->cputype = CPU_TX3927;
@@ -441,7 +443,7 @@
 	config0 = read_c0_config();
  
 	if (((config0 & MIPS_CONF_MT) >> 7) == 1)
-		c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB;
+		c->options |= MIPS_CPU_TLB;
 	isa = (config0 & MIPS_CONF_AT) >> 13;
 	switch (isa) {
 	case 0:
@@ -516,8 +518,8 @@
 static inline void decode_configs(struct cpuinfo_mips *c)
 {
 	/* MIPS32 or MIPS64 compliant CPU.  */
-	c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
-		     MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
+	c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
+	             MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
  
 	c->scache.flags = MIPS_CACHE_NOT_PRESENT;
  
@@ -603,6 +605,15 @@
 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 {
 	decode_configs(c);
+
+	/*
+	 * For historical reasons the SB1 comes with it's own variant of
+	 * cache code which eventually will be folded into c-r4k.c.  Until
+	 * then we pretend it's got it's own cache architecture.
+	 */
+	c->options &= MIPS_CPU_4K_CACHE;
+	c->options |= MIPS_CPU_SB1_CACHE;
+
 	switch (c->processor_id & 0xff00) {
 	case PRID_IMP_SB1:
 		c->cputype = CPU_SB1;
@@ -319,7 +319,7 @@
 	r3k_flush_dcache_range(start, start + size);
 }
  
-void __init ld_mmu_r23000(void)
+void __init r3k_cache_init(void)
 {
 	extern void build_clear_page(void);
 	extern void build_copy_page(void);
@@ -1221,7 +1221,7 @@
 	}
 }
  
-void __init ld_mmu_r4xx0(void)
+void __init r4k_cache_init(void)
 {
 	extern void build_clear_page(void);
 	extern void build_copy_page(void);
@@ -496,7 +496,7 @@
  * memory management function pointers, as well as initialize
  * the caches and tlbs
  */
-void ld_mmu_sb1(void)
+void sb1_cache_init(void)
 {
 	extern char except_vec2_sb1;
 	extern char handle_vec2_sb1;
@@ -410,7 +410,7 @@
 	}
 }
  
-void __init ld_mmu_tx39(void)
+void __init tx39_cache_init(void)
 {
 	extern void build_clear_page(void);
 	extern void build_copy_page(void);
@@ -104,59 +104,49 @@
 	}
 }
  
-extern void ld_mmu_r23000(void);
-extern void ld_mmu_r4xx0(void);
-extern void ld_mmu_tx39(void);
-extern void ld_mmu_r6000(void);
-extern void ld_mmu_tfp(void);
-extern void ld_mmu_andes(void);
-extern void ld_mmu_sb1(void);
+#define __weak __attribute__((weak))
  
+static char cache_panic[] __initdata = "Yeee, unsupported cache architecture.";
+
 void __init cpu_cache_init(void)
 {
-	if (cpu_has_4ktlb) {
-#if defined(CONFIG_CPU_R4X00)  || defined(CONFIG_CPU_VR41XX) || \
-    defined(CONFIG_CPU_R4300)  || defined(CONFIG_CPU_R5000)  || \
-    defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432)  || \
-    defined(CONFIG_CPU_R5500)  || defined(CONFIG_CPU_MIPS32_R1) || \
-    defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \
-    defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
-		ld_mmu_r4xx0();
-#endif
-	} else switch (current_cpu_data.cputype) {
-#ifdef CONFIG_CPU_R3000
-	case CPU_R2000:
-	case CPU_R3000:
-	case CPU_R3000A:
-	case CPU_R3081E:
-		ld_mmu_r23000();
-		break;
-#endif
-#ifdef CONFIG_CPU_TX39XX
-	case CPU_TX3912:
-	case CPU_TX3922:
-	case CPU_TX3927:
-		ld_mmu_tx39();
-		break;
-#endif
-#ifdef CONFIG_CPU_R10000
-	case CPU_R10000:
-	case CPU_R12000:
-		ld_mmu_r4xx0();
-		break;
-#endif
-#ifdef CONFIG_CPU_SB1
-	case CPU_SB1:
-		ld_mmu_sb1();
-		break;
-#endif
+	if (cpu_has_3k_cache) {
+		extern void __weak r3k_cache_init(void);
  
-	case CPU_R8000:
-		panic("R8000 is unsupported");
-		break;
+		r3k_cache_init();
+		return;
+	}
+	if (cpu_has_6k_cache) {
+		extern void __weak r6k_cache_init(void);
  
-	default:
-		panic("Yeee, unsupported cache architecture.");
+		r6k_cache_init();
+		return;
 	}
+	if (cpu_has_4k_cache) {
+		extern void __weak r4k_cache_init(void);
+
+		r4k_cache_init();
+		return;
+	}
+	if (cpu_has_8k_cache) {
+		extern void __weak r8k_cache_init(void);
+
+		r8k_cache_init();
+		return;
+	}
+	if (cpu_has_tx39_cache) {
+		extern void __weak tx39_cache_init(void);
+
+		tx39_cache_init();
+		return;
+	}
+	if (cpu_has_sb1_cache) {
+		extern void __weak sb1_cache_init(void);
+
+		sb1_cache_init();
+		return;
+	}
+
+	panic(cache_panic);
 }
@@ -25,8 +25,19 @@
 #ifndef cpu_has_4kex
 #define cpu_has_4kex		(cpu_data[0].options & MIPS_CPU_4KEX)
 #endif
-#ifndef cpu_has_4ktlb
-#define cpu_has_4ktlb		(cpu_data[0].options & MIPS_CPU_4KTLB)
+#ifndef cpu_has_3k_cache
+#define cpu_has_3k_cache	(cpu_data[0].options & MIPS_CPU_3K_CACHE)
+#endif
+#define cpu_has_6k_cache	0
+#define cpu_has_8k_cache	0
+#ifndef cpu_has_4k_cache
+#define cpu_has_4k_cache	(cpu_data[0].options & MIPS_CPU_4K_CACHE)
+#endif
+#ifndef cpu_has_tx39_cache
+#define cpu_has_tx39_cache	(cpu_data[0].options & MIPS_CPU_TX39_CACHE)
+#endif
+#ifndef cpu_has_sb1_cache
+#define cpu_has_sb1_cache	(cpu_data[0].options & MIPS_CPU_SB1_CACHE)
 #endif
 #ifndef cpu_has_fpu
 #define cpu_has_fpu		(cpu_data[0].options & MIPS_CPU_FPU)
@@ -217,25 +217,27 @@
  * CPU Option encodings
  */
 #define MIPS_CPU_TLB		0x00000001 /* CPU has TLB */
-/* Leave a spare bit for variant MMU types... */
-#define MIPS_CPU_4KEX		0x00000004 /* "R4K" exception model */
-#define MIPS_CPU_4KTLB		0x00000008 /* "R4K" TLB handler */
-#define MIPS_CPU_FPU		0x00000010 /* CPU has FPU */
-#define MIPS_CPU_32FPR		0x00000020 /* 32 dbl. prec. FP registers */
-#define MIPS_CPU_COUNTER	0x00000040 /* Cycle count/compare */
-#define MIPS_CPU_WATCH		0x00000080 /* watchpoint registers */
-#define MIPS_CPU_DIVEC		0x00000200 /* dedicated interrupt vector */
-#define MIPS_CPU_VCE		0x00000400 /* virt. coherence conflict possible */
-#define MIPS_CPU_CACHE_CDEX_P	0x00000800 /* Create_Dirty_Exclusive CACHE op */
-#define MIPS_CPU_CACHE_CDEX_S	0x00001000 /* ... same for seconary cache ... */
-#define MIPS_CPU_MCHECK		0x00002000 /* Machine check exception */
-#define MIPS_CPU_EJTAG		0x00004000 /* EJTAG exception */
-#define MIPS_CPU_NOFPUEX	0x00008000 /* no FPU exception */
-#define MIPS_CPU_LLSC		0x00010000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_SUBSET_CACHES	0x00020000 /* P-cache subset enforced */
-#define MIPS_CPU_PREFETCH	0x00040000 /* CPU has usable prefetch */
-#define MIPS_CPU_VINT		0x00080000 /* CPU supports MIPSR2 vectored interrupts */
-#define MIPS_CPU_VEIC		0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
+#define MIPS_CPU_4KEX		0x00000002 /* "R4K" exception model */
+#define MIPS_CPU_3K_CACHE	0x00000004 /* R3000-style caches */
+#define MIPS_CPU_4K_CACHE	0x00000008 /* R4000-style caches */
+#define MIPS_CPU_TX39_CACHE	0x00000010 /* TX3900-style caches */
+#define MIPS_CPU_SB1_CACHE	0x00000020 /* SB1-style caches */
+#define MIPS_CPU_FPU		0x00000040 /* CPU has FPU */
+#define MIPS_CPU_32FPR		0x00000080 /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER	0x00000100 /* Cycle count/compare */
+#define MIPS_CPU_WATCH		0x00000200 /* watchpoint registers */
+#define MIPS_CPU_DIVEC		0x00000400 /* dedicated interrupt vector */
+#define MIPS_CPU_VCE		0x00000800 /* virt. coherence conflict possible */
+#define MIPS_CPU_CACHE_CDEX_P	0x00001000 /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_CACHE_CDEX_S	0x00002000 /* ... same for seconary cache ... */
+#define MIPS_CPU_MCHECK		0x00004000 /* Machine check exception */
+#define MIPS_CPU_EJTAG		0x00008000 /* EJTAG exception */
+#define MIPS_CPU_NOFPUEX	0x00010000 /* no FPU exception */
+#define MIPS_CPU_LLSC		0x00020000 /* CPU has ll/sc instructions */
+#define MIPS_CPU_SUBSET_CACHES	0x00040000 /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH	0x00080000 /* CPU has usable prefetch */
+#define MIPS_CPU_VINT		0x00100000 /* CPU supports MIPSR2 vectored interrupts */
+#define MIPS_CPU_VEIC		0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
  
 /*
  * CPU ASE encodings
@@ -13,7 +13,7 @@
  */
 #define cpu_has_tlb		1
 #define cpu_has_4kex		1
-#define cpu_has_4ktlb		1
+#define cpu_has_4kcache		1
 #define cpu_has_fpu		1
 #define cpu_has_32fpr		1
 #define cpu_has_counter		1
@@ -17,7 +17,7 @@
 #ifdef CONFIG_CPU_MIPS32_R1
 #define cpu_has_tlb		1
 #define cpu_has_4kex		1
-#define cpu_has_4ktlb		1
+#define cpu_has_4kcache		1
 /* #define cpu_has_fpu		? */
 /* #define cpu_has_32fpr	? */
 #define cpu_has_counter		1
@@ -43,7 +43,7 @@
 #ifdef CONFIG_CPU_MIPS64_R1
 #define cpu_has_tlb		1
 #define cpu_has_4kex		1
-#define cpu_has_4ktlb		1
+#define cpu_has_4kcache		1
 /* #define cpu_has_fpu		? */
 /* #define cpu_has_32fpr	? */
 #define cpu_has_counter		1
@@ -14,7 +14,7 @@
  
 #define cpu_has_tlb		1
 #define cpu_has_4kex		1
-#define cpu_has_4ktlb		1
+#define cpu_has_4kcache		1
 #define cpu_has_fpu		1
 #define cpu_has_32fpr		1
 #define cpu_has_counter		1
@@ -16,7 +16,7 @@
 #ifdef CONFIG_CPU_MIPS32
 #define cpu_has_tlb		1
 #define cpu_has_4kex		1
-#define cpu_has_4ktlb		1
+#define cpu_has_4kcache		1
 #define cpu_has_fpu		0
 /* #define cpu_has_32fpr	? */
 #define cpu_has_counter		1
@@ -41,7 +41,7 @@
 #ifdef CONFIG_CPU_MIPS64
 #define cpu_has_tlb		1
 #define cpu_has_4kex		1
-#define cpu_has_4ktlb		1
+#define cpu_has_4kcache		1
 /* #define cpu_has_fpu		? */
 /* #define cpu_has_32fpr	? */
 #define cpu_has_counter		1
...	...	@@ -191,7 +191,7 @@
191	191	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
192	192	}
193	193
194		-#define R4K_OPTS (MIPS_CPU_TLB \| MIPS_CPU_4KEX \| MIPS_CPU_4KTLB \
	194	+#define R4K_OPTS (MIPS_CPU_TLB \| MIPS_CPU_4KEX \| MIPS_CPU_4K_CACHE \
195	195	\| MIPS_CPU_COUNTER)
196	196
197	197	static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
...	...	@@ -200,7 +200,8 @@
200	200	case PRID_IMP_R2000:
201	201	c->cputype = CPU_R2000;
202	202	c->isa_level = MIPS_CPU_ISA_I;
203		- c->options = MIPS_CPU_TLB \| MIPS_CPU_NOFPUEX;
	203	+ c->options = MIPS_CPU_TLB \| MIPS_CPU_3K_CACHE \|
	204	+ MIPS_CPU_NOFPUEX;
204	205	if (__cpu_has_fpu())
205	206	c->options \|= MIPS_CPU_FPU;
206	207	c->tlbsize = 64;
...	...	@@ -214,7 +215,8 @@
214	215	else
215	216	c->cputype = CPU_R3000;
216	217	c->isa_level = MIPS_CPU_ISA_I;
217		- c->options = MIPS_CPU_TLB \| MIPS_CPU_NOFPUEX;
	218	+ c->options = MIPS_CPU_TLB \| MIPS_CPU_3K_CACHE \|
	219	+ MIPS_CPU_NOFPUEX;
218	220	if (__cpu_has_fpu())
219	221	c->options \|= MIPS_CPU_FPU;
220	222	c->tlbsize = 64;
...	...	@@ -297,7 +299,7 @@
297	299	#endif
298	300	case PRID_IMP_TX39:
299	301	c->isa_level = MIPS_CPU_ISA_I;
300		- c->options = MIPS_CPU_TLB;
	302	+ c->options = MIPS_CPU_TLB \| MIPS_CPU_TX39_CACHE;
301	303
302	304	if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
303	305	c->cputype = CPU_TX3927;
...	...	@@ -441,7 +443,7 @@
441	443	config0 = read_c0_config();
442	444
443	445	if (((config0 & MIPS_CONF_MT) >> 7) == 1)
444		- c->options \|= MIPS_CPU_TLB \| MIPS_CPU_4KTLB;
	446	+ c->options \|= MIPS_CPU_TLB;
445	447	isa = (config0 & MIPS_CONF_AT) >> 13;
446	448	switch (isa) {
447	449	case 0:
...	...	@@ -516,8 +518,8 @@
516	518	static inline void decode_configs(struct cpuinfo_mips *c)
517	519	{
518	520	/* MIPS32 or MIPS64 compliant CPU. */
519		- c->options = MIPS_CPU_4KEX \| MIPS_CPU_COUNTER \| MIPS_CPU_DIVEC \|
520		- MIPS_CPU_LLSC \| MIPS_CPU_MCHECK;
	521	+ c->options = MIPS_CPU_4KEX \| MIPS_CPU_4K_CACHE \| MIPS_CPU_COUNTER \|
	522	+ MIPS_CPU_DIVEC \| MIPS_CPU_LLSC \| MIPS_CPU_MCHECK;
521	523
522	524	c->scache.flags = MIPS_CACHE_NOT_PRESENT;
523	525
...	...	@@ -603,6 +605,15 @@
603	605	static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
604	606	{
605	607	decode_configs(c);
	608	+
	609	+ /*
	610	+ * For historical reasons the SB1 comes with it's own variant of
	611	+ * cache code which eventually will be folded into c-r4k.c. Until
	612	+ * then we pretend it's got it's own cache architecture.
	613	+ */
	614	+ c->options &= MIPS_CPU_4K_CACHE;
	615	+ c->options \|= MIPS_CPU_SB1_CACHE;
	616	+
606	617	switch (c->processor_id & 0xff00) {
607	618	case PRID_IMP_SB1:
608	619	c->cputype = CPU_SB1;
...	...	@@ -319,7 +319,7 @@
319	319	r3k_flush_dcache_range(start, start + size);
320	320	}
321	321
322		-void __init ld_mmu_r23000(void)
	322	+void __init r3k_cache_init(void)
323	323	{
324	324	extern void build_clear_page(void);
325	325	extern void build_copy_page(void);
...	...	@@ -1221,7 +1221,7 @@
1221	1221	}
1222	1222	}
1223	1223
1224		-void __init ld_mmu_r4xx0(void)
	1224	+void __init r4k_cache_init(void)
1225	1225	{
1226	1226	extern void build_clear_page(void);
1227	1227	extern void build_copy_page(void);
...	...	@@ -496,7 +496,7 @@
496	496	* memory management function pointers, as well as initialize
497	497	* the caches and tlbs
498	498	*/
499		-void ld_mmu_sb1(void)
	499	+void sb1_cache_init(void)
500	500	{
501	501	extern char except_vec2_sb1;
502	502	extern char handle_vec2_sb1;
...	...	@@ -410,7 +410,7 @@
410	410	}
411	411	}
412	412
413		-void __init ld_mmu_tx39(void)
	413	+void __init tx39_cache_init(void)
414	414	{
415	415	extern void build_clear_page(void);
416	416	extern void build_copy_page(void);
...	...	@@ -104,59 +104,49 @@
104	104	}
105	105	}
106	106
107		-extern void ld_mmu_r23000(void);
108		-extern void ld_mmu_r4xx0(void);
109		-extern void ld_mmu_tx39(void);
110		-extern void ld_mmu_r6000(void);
111		-extern void ld_mmu_tfp(void);
112		-extern void ld_mmu_andes(void);
113		-extern void ld_mmu_sb1(void);
	107	+#define __weak __attribute__((weak))
114	108
	109	+static char cache_panic[] __initdata = "Yeee, unsupported cache architecture.";
	110	+
115	111	void __init cpu_cache_init(void)
116	112	{
117		- if (cpu_has_4ktlb) {
118		-#if defined(CONFIG_CPU_R4X00) \|\| defined(CONFIG_CPU_VR41XX) \|\| \
119		- defined(CONFIG_CPU_R4300) \|\| defined(CONFIG_CPU_R5000) \|\| \
120		- defined(CONFIG_CPU_NEVADA) \|\| defined(CONFIG_CPU_R5432) \|\| \
121		- defined(CONFIG_CPU_R5500) \|\| defined(CONFIG_CPU_MIPS32_R1) \|\| \
122		- defined(CONFIG_CPU_MIPS64_R1) \|\| defined(CONFIG_CPU_TX49XX) \|\| \
123		- defined(CONFIG_CPU_RM7000) \|\| defined(CONFIG_CPU_RM9000)
124		- ld_mmu_r4xx0();
125		-#endif
126		- } else switch (current_cpu_data.cputype) {
127		-#ifdef CONFIG_CPU_R3000
128		- case CPU_R2000:
129		- case CPU_R3000:
130		- case CPU_R3000A:
131		- case CPU_R3081E:
132		- ld_mmu_r23000();
133		- break;
134		-#endif
135		-#ifdef CONFIG_CPU_TX39XX
136		- case CPU_TX3912:
137		- case CPU_TX3922:
138		- case CPU_TX3927:
139		- ld_mmu_tx39();
140		- break;
141		-#endif
142		-#ifdef CONFIG_CPU_R10000
143		- case CPU_R10000:
144		- case CPU_R12000:
145		- ld_mmu_r4xx0();
146		- break;
147		-#endif
148		-#ifdef CONFIG_CPU_SB1
149		- case CPU_SB1:
150		- ld_mmu_sb1();
151		- break;
152		-#endif
	113	+ if (cpu_has_3k_cache) {
	114	+ extern void __weak r3k_cache_init(void);
153	115
154		- case CPU_R8000:
155		- panic("R8000 is unsupported");
156		- break;
	116	+ r3k_cache_init();
	117	+ return;
	118	+ }
	119	+ if (cpu_has_6k_cache) {
	120	+ extern void __weak r6k_cache_init(void);
157	121
158		- default:
159		- panic("Yeee, unsupported cache architecture.");
	122	+ r6k_cache_init();
	123	+ return;
160	124	}
	125	+ if (cpu_has_4k_cache) {
	126	+ extern void __weak r4k_cache_init(void);
	127	+
	128	+ r4k_cache_init();
	129	+ return;
	130	+ }
	131	+ if (cpu_has_8k_cache) {
	132	+ extern void __weak r8k_cache_init(void);
	133	+
	134	+ r8k_cache_init();
	135	+ return;
	136	+ }
	137	+ if (cpu_has_tx39_cache) {
	138	+ extern void __weak tx39_cache_init(void);
	139	+
	140	+ tx39_cache_init();
	141	+ return;
	142	+ }
	143	+ if (cpu_has_sb1_cache) {
	144	+ extern void __weak sb1_cache_init(void);
	145	+
	146	+ sb1_cache_init();
	147	+ return;
	148	+ }
	149	+
	150	+ panic(cache_panic);
161	151	}
...	...	@@ -25,8 +25,19 @@
25	25	#ifndef cpu_has_4kex
26	26	#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
27	27	#endif
28		-#ifndef cpu_has_4ktlb
29		-#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
	28	+#ifndef cpu_has_3k_cache
	29	+#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
	30	+#endif
	31	+#define cpu_has_6k_cache 0
	32	+#define cpu_has_8k_cache 0
	33	+#ifndef cpu_has_4k_cache
	34	+#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
	35	+#endif
	36	+#ifndef cpu_has_tx39_cache
	37	+#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
	38	+#endif
	39	+#ifndef cpu_has_sb1_cache
	40	+#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
30	41	#endif
31	42	#ifndef cpu_has_fpu
32	43	#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
...	...	@@ -217,25 +217,27 @@
217	217	* CPU Option encodings
218	218	*/
219	219	#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
220		-/* Leave a spare bit for variant MMU types... */
221		-#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */
222		-#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */
223		-#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */
224		-#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */
225		-#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */
226		-#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */
227		-#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
228		-#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
229		-#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
230		-#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
231		-#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
232		-#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
233		-#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
234		-#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
235		-#define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */
236		-#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
237		-#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
238		-#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
	220	+#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
	221	+#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
	222	+#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
	223	+#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
	224	+#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */
	225	+#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */
	226	+#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */
	227	+#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */
	228	+#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */
	229	+#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */
	230	+#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */
	231	+#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */
	232	+#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */
	233	+#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */
	234	+#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */
	235	+#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */
	236	+#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */
	237	+#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */
	238	+#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
	239	+#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
	240	+#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
239	241
240	242	/*
241	243	* CPU ASE encodings
...	...	@@ -13,7 +13,7 @@
13	13	*/
14	14	#define cpu_has_tlb 1
15	15	#define cpu_has_4kex 1
16		-#define cpu_has_4ktlb 1
	16	+#define cpu_has_4kcache 1
17	17	#define cpu_has_fpu 1
18	18	#define cpu_has_32fpr 1
19	19	#define cpu_has_counter 1
...	...	@@ -17,7 +17,7 @@
17	17	#ifdef CONFIG_CPU_MIPS32_R1
18	18	#define cpu_has_tlb 1
19	19	#define cpu_has_4kex 1
20		-#define cpu_has_4ktlb 1
	20	+#define cpu_has_4kcache 1
21	21	/* #define cpu_has_fpu ? */
22	22	/* #define cpu_has_32fpr ? */
23	23	#define cpu_has_counter 1
...	...	@@ -43,7 +43,7 @@
43	43	#ifdef CONFIG_CPU_MIPS64_R1
44	44	#define cpu_has_tlb 1
45	45	#define cpu_has_4kex 1
46		-#define cpu_has_4ktlb 1
	46	+#define cpu_has_4kcache 1
47	47	/* #define cpu_has_fpu ? */
48	48	/* #define cpu_has_32fpr ? */
49	49	#define cpu_has_counter 1