dmaengine: at_hdmac: simplify device selection from platform data or DT

Using a configuration structure simplify the finding of SoC dependent parameters. Both platform data and device tree ids are using these structures. This will separate data from code and remove the need for an enum. Idea from Grant Likely. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>

dmaengine: at_hdmac: simplify device selection from platform data or DT
Using a configuration structure simplify the finding of SoC dependent parameters. Both platform data and device tree ids are using these structures. This will separate data from code and remove the need for an enum. Idea from Grant Likely. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Nicolas Ferre · Vinod Koul
1 parent dcc817346d
Showing 2 changed files with 31 additions and 39 deletions Side-by-side Diff
drivers/dma/at_hdmac.c
drivers/dma/at_hdmac_regs.h
@@ -1177,14 +1177,22 @@
  
 /*--  Module Management  -----------------------------------------------*/
  
+/* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
+static struct at_dma_platform_data at91sam9rl_config = {
+	.nr_channels = 2,
+};
+static struct at_dma_platform_data at91sam9g45_config = {
+	.nr_channels = 8,
+};
+
 #if defined(CONFIG_OF)
 static const struct of_device_id atmel_dma_dt_ids[] = {
 	{
 		.compatible = "atmel,at91sam9rl-dma",
-		.data = (void *)ATDMA_DEVTYPE_SAM9RL
+		.data = &at91sam9rl_config,
 	}, {
 		.compatible = "atmel,at91sam9g45-dma",
-		.data = (void *)ATDMA_DEVTYPE_SAM9G45
+		.data = &at91sam9g45_config,
 	}, {
 		/* sentinel */
 	}
  
  
  
  
@@ -1196,26 +1204,27 @@
 static const struct platform_device_id atdma_devtypes[] = {
 	{
 		.name = "at91sam9rl_dma",
-		.driver_data = ATDMA_DEVTYPE_SAM9RL,
+		.driver_data = (unsigned long) &at91sam9rl_config,
 	}, {
 		.name = "at91sam9g45_dma",
-		.driver_data = ATDMA_DEVTYPE_SAM9G45,
+		.driver_data = (unsigned long) &at91sam9g45_config,
 	}, {
 		/* sentinel */
 	}
 };
  
-static inline enum atdma_devtype __init at_dma_get_driver_data(
-					struct platform_device *pdev)
+static inline struct at_dma_platform_data * __init at_dma_get_driver_data(
+						struct platform_device *pdev)
 {
 	if (pdev->dev.of_node) {
 		const struct of_device_id *match;
 		match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
 		if (match == NULL)
-			return ATDMA_DEVTYPE_UNDEFINED;
-		return (enum atdma_devtype)match->data;
+			return NULL;
+		return match->data;
 	}
-	return platform_get_device_id(pdev)->driver_data;
+	return (struct at_dma_platform_data *)
+			platform_get_device_id(pdev)->driver_data;
 }
  
 /**
  
  
  
@@ -1242,27 +1251,18 @@
 	int			irq;
 	int			err;
 	int			i;
-	u32                     nr_channels;
-	dma_cap_mask_t          cap_mask = {};
-	enum atdma_devtype	atdmatype;
+	struct at_dma_platform_data *plat_dat;
  
-	dma_cap_set(DMA_MEMCPY, cap_mask);
+	/* setup platform data for each SoC */
+	dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
+	dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
+	dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
  
 	/* get DMA parameters from controller type */
-	atdmatype = at_dma_get_driver_data(pdev);
+	plat_dat = at_dma_get_driver_data(pdev);
+	if (!plat_dat)
+		return -ENODEV;
  
-	switch (atdmatype) {
-	case ATDMA_DEVTYPE_SAM9RL:
-		nr_channels = 2;
-		break;
-	case ATDMA_DEVTYPE_SAM9G45:
-		nr_channels = 8;
-		dma_cap_set(DMA_SLAVE, cap_mask);
-		break;
-	default:
-		return -EINVAL;
-	}
-
 	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!io)
 		return -EINVAL;
  
@@ -1272,15 +1272,14 @@
 		return irq;
  
 	size = sizeof(struct at_dma);
-	size += nr_channels * sizeof(struct at_dma_chan);
+	size += plat_dat->nr_channels * sizeof(struct at_dma_chan);
 	atdma = kzalloc(size, GFP_KERNEL);
 	if (!atdma)
 		return -ENOMEM;
  
 	/* discover transaction capabilities */
-	atdma->dma_common.cap_mask = cap_mask;
-	atdma->all_chan_mask = (1 << nr_channels) - 1;
-	atdma->devtype = atdmatype;
+	atdma->dma_common.cap_mask = plat_dat->cap_mask;
+	atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
  
 	size = resource_size(io);
 	if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
@@ -1326,7 +1325,7 @@
  
 	/* initialize channels related values */
 	INIT_LIST_HEAD(&atdma->dma_common.channels);
-	for (i = 0; i < nr_channels; i++) {
+	for (i = 0; i < plat_dat->nr_channels; i++) {
 		struct at_dma_chan	*atchan = &atdma->chan[i];
  
 		atchan->chan_common.device = &atdma->dma_common;
@@ -1371,7 +1370,7 @@
 	dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
 	  dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
 	  dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)  ? "slave " : "",
-	  nr_channels);
+	  plat_dat->nr_channels);
  
 	dma_async_device_register(&atdma->dma_common);
  
@@ -248,12 +248,6 @@
  
 /*--  Controller  ------------------------------------------------------*/
  
-enum atdma_devtype {
-	ATDMA_DEVTYPE_UNDEFINED = 0,
-	ATDMA_DEVTYPE_SAM9RL,	/* compatible with SAM9RL DMA controller */
-	ATDMA_DEVTYPE_SAM9G45,	/* compatible with SAM9G45 DMA controller */
-};
-
 /**
  * struct at_dma - internal representation of an Atmel HDMA Controller
  * @chan_common: common dmaengine dma_device object members
@@ -267,7 +261,6 @@
  */
 struct at_dma {
 	struct dma_device	dma_common;
-	enum atdma_devtype	devtype;
 	void __iomem		*regs;
 	struct clk		*clk;
 	u32			save_imr;
...	...	@@ -1177,14 +1177,22 @@
1177	1177
1178	1178	/-- Module Management -----------------------------------------------/
1179	1179
	1180	+/* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
	1181	+static struct at_dma_platform_data at91sam9rl_config = {
	1182	+ .nr_channels = 2,
	1183	+};
	1184	+static struct at_dma_platform_data at91sam9g45_config = {
	1185	+ .nr_channels = 8,
	1186	+};
	1187	+
1180	1188	#if defined(CONFIG_OF)
1181	1189	static const struct of_device_id atmel_dma_dt_ids[] = {
1182	1190	{
1183	1191	.compatible = "atmel,at91sam9rl-dma",
1184		- .data = (void *)ATDMA_DEVTYPE_SAM9RL
	1192	+ .data = &at91sam9rl_config,
1185	1193	}, {
1186	1194	.compatible = "atmel,at91sam9g45-dma",
1187		- .data = (void *)ATDMA_DEVTYPE_SAM9G45
	1195	+ .data = &at91sam9g45_config,
1188	1196	}, {
1189	1197	/* sentinel */
1190	1198	}
1191	1199
1192	1200
1193	1201
1194	1202
...	...	@@ -1196,26 +1204,27 @@
1196	1204	static const struct platform_device_id atdma_devtypes[] = {
1197	1205	{
1198	1206	.name = "at91sam9rl_dma",
1199		- .driver_data = ATDMA_DEVTYPE_SAM9RL,
	1207	+ .driver_data = (unsigned long) &at91sam9rl_config,
1200	1208	}, {
1201	1209	.name = "at91sam9g45_dma",
1202		- .driver_data = ATDMA_DEVTYPE_SAM9G45,
	1210	+ .driver_data = (unsigned long) &at91sam9g45_config,
1203	1211	}, {
1204	1212	/* sentinel */
1205	1213	}
1206	1214	};
1207	1215
1208		-static inline enum atdma_devtype __init at_dma_get_driver_data(
1209		- struct platform_device *pdev)
	1216	+static inline struct at_dma_platform_data * __init at_dma_get_driver_data(
	1217	+ struct platform_device *pdev)
1210	1218	{
1211	1219	if (pdev->dev.of_node) {
1212	1220	const struct of_device_id *match;
1213	1221	match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
1214	1222	if (match == NULL)
1215		- return ATDMA_DEVTYPE_UNDEFINED;
1216		- return (enum atdma_devtype)match->data;
	1223	+ return NULL;
	1224	+ return match->data;
1217	1225	}
1218		- return platform_get_device_id(pdev)->driver_data;
	1226	+ return (struct at_dma_platform_data *)
	1227	+ platform_get_device_id(pdev)->driver_data;
1219	1228	}
1220	1229
1221	1230	/**
1222	1231
1223	1232
1224	1233
...	...	@@ -1242,27 +1251,18 @@
1242	1251	int irq;
1243	1252	int err;
1244	1253	int i;
1245		- u32 nr_channels;
1246		- dma_cap_mask_t cap_mask = {};
1247		- enum atdma_devtype atdmatype;
	1254	+ struct at_dma_platform_data *plat_dat;
1248	1255
1249		- dma_cap_set(DMA_MEMCPY, cap_mask);
	1256	+ /* setup platform data for each SoC */
	1257	+ dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
	1258	+ dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
	1259	+ dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
1250	1260
1251	1261	/* get DMA parameters from controller type */
1252		- atdmatype = at_dma_get_driver_data(pdev);
	1262	+ plat_dat = at_dma_get_driver_data(pdev);
	1263	+ if (!plat_dat)
	1264	+ return -ENODEV;
1253	1265
1254		- switch (atdmatype) {
1255		- case ATDMA_DEVTYPE_SAM9RL:
1256		- nr_channels = 2;
1257		- break;
1258		- case ATDMA_DEVTYPE_SAM9G45:
1259		- nr_channels = 8;
1260		- dma_cap_set(DMA_SLAVE, cap_mask);
1261		- break;
1262		- default:
1263		- return -EINVAL;
1264		- }
1265		-
1266	1266	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1267	1267	if (!io)
1268	1268	return -EINVAL;
1269	1269
...	...	@@ -1272,15 +1272,14 @@
1272	1272	return irq;
1273	1273
1274	1274	size = sizeof(struct at_dma);
1275		- size += nr_channels * sizeof(struct at_dma_chan);
	1275	+ size += plat_dat->nr_channels * sizeof(struct at_dma_chan);
1276	1276	atdma = kzalloc(size, GFP_KERNEL);
1277	1277	if (!atdma)
1278	1278	return -ENOMEM;
1279	1279
1280	1280	/* discover transaction capabilities */
1281		- atdma->dma_common.cap_mask = cap_mask;
1282		- atdma->all_chan_mask = (1 << nr_channels) - 1;
1283		- atdma->devtype = atdmatype;
	1281	+ atdma->dma_common.cap_mask = plat_dat->cap_mask;
	1282	+ atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
1284	1283
1285	1284	size = resource_size(io);
1286	1285	if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
...	...	@@ -1326,7 +1325,7 @@
1326	1325
1327	1326	/* initialize channels related values */
1328	1327	INIT_LIST_HEAD(&atdma->dma_common.channels);
1329		- for (i = 0; i < nr_channels; i++) {
	1328	+ for (i = 0; i < plat_dat->nr_channels; i++) {
1330	1329	struct at_dma_chan *atchan = &atdma->chan[i];
1331	1330
1332	1331	atchan->chan_common.device = &atdma->dma_common;
...	...	@@ -1371,7 +1370,7 @@
1371	1370	dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
1372	1371	dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
1373	1372	dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
1374		- nr_channels);
	1373	+ plat_dat->nr_channels);
1375	1374
1376	1375	dma_async_device_register(&atdma->dma_common);
1377	1376
...	...	@@ -248,12 +248,6 @@
248	248
249	249	/-- Controller ------------------------------------------------------/
250	250
251		-enum atdma_devtype {
252		- ATDMA_DEVTYPE_UNDEFINED = 0,
253		- ATDMA_DEVTYPE_SAM9RL, /* compatible with SAM9RL DMA controller */
254		- ATDMA_DEVTYPE_SAM9G45, /* compatible with SAM9G45 DMA controller */
255		-};
256		-
257	251	/**
258	252	* struct at_dma - internal representation of an Atmel HDMA Controller
259	253	* @chan_common: common dmaengine dma_device object members
...	...	@@ -267,7 +261,6 @@
267	261	*/
268	262	struct at_dma {
269	263	struct dma_device dma_common;
270		- enum atdma_devtype devtype;
271	264	void __iomem *regs;
272	265	struct clk *clk;
273	266	u32 save_imr;