Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit 032ec49f5351e9cb242b1a1c367d14415043ab95

Authored by Felipe Balbi 2011-11-24 21:46:26 +0800

Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches

usb: musb: drop useless board_mode usage

we are compiling the driver always with full OTG
capabilities, so that board_mode trick becomes
useless.

Signed-off-by: Felipe Balbi <balbi@ti.com>

Showing 11 changed files with 159 additions and 334 deletions Inline Diff

drivers/usb/musb/am35x.c
drivers/usb/musb/blackfin.c
drivers/usb/musb/da8xx.c
drivers/usb/musb/davinci.c
drivers/usb/musb/musb_core.c
drivers/usb/musb/musb_core.h
drivers/usb/musb/musb_dsps.c
drivers/usb/musb/musb_gadget.c
drivers/usb/musb/musb_virthub.c
drivers/usb/musb/omap2430.c
drivers/usb/musb/tusb6010.c

drivers/usb/musb/am35x.c

Diff comments View file @ 032ec49

 /*
  * Texas Instruments AM35x "glue layer"
  *
  * Copyright (c) 2010, by Texas Instruments
  *
  * Based on the DA8xx "glue layer" code.
  * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
  *
  * This file is part of the Inventra Controller Driver for Linux.
  *
  * The Inventra Controller Driver for Linux is free software; you
  * can redistribute it and/or modify it under the terms of the GNU
  * General Public License version 2 as published by the Free Software
  * Foundation.
  *
  * The Inventra Controller Driver for Linux is distributed in
  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  * without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  * License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with The Inventra Controller Driver for Linux ; if not,
  * write to the Free Software Foundation, Inc., 59 Temple Place,
  * Suite 330, Boston, MA  02111-1307  USA
  *
  */
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <plat/usb.h>
 #include "musb_core.h"
 /*
  * AM35x specific definitions
  */
 /* USB 2.0 OTG module registers */
 #define USB_REVISION_REG	0x00
 #define USB_CTRL_REG		0x04
 #define USB_STAT_REG		0x08
 #define USB_EMULATION_REG	0x0c
 /* 0x10 Reserved */
 #define USB_AUTOREQ_REG		0x14
 #define USB_SRP_FIX_TIME_REG	0x18
 #define USB_TEARDOWN_REG	0x1c
 #define EP_INTR_SRC_REG		0x20
 #define EP_INTR_SRC_SET_REG	0x24
 #define EP_INTR_SRC_CLEAR_REG	0x28
 #define EP_INTR_MASK_REG	0x2c
 #define EP_INTR_MASK_SET_REG	0x30
 #define EP_INTR_MASK_CLEAR_REG	0x34
 #define EP_INTR_SRC_MASKED_REG	0x38
 #define CORE_INTR_SRC_REG	0x40
 #define CORE_INTR_SRC_SET_REG	0x44
 #define CORE_INTR_SRC_CLEAR_REG	0x48
 #define CORE_INTR_MASK_REG	0x4c
 #define CORE_INTR_MASK_SET_REG	0x50
 #define CORE_INTR_MASK_CLEAR_REG 0x54
 #define CORE_INTR_SRC_MASKED_REG 0x58
 /* 0x5c Reserved */
 #define USB_END_OF_INTR_REG	0x60
 /* Control register bits */
 #define AM35X_SOFT_RESET_MASK	1
 /* USB interrupt register bits */
 #define AM35X_INTR_USB_SHIFT	16
 #define AM35X_INTR_USB_MASK	(0x1ff << AM35X_INTR_USB_SHIFT)
 #define AM35X_INTR_DRVVBUS	0x100
 #define AM35X_INTR_RX_SHIFT	16
 #define AM35X_INTR_TX_SHIFT	0
 #define AM35X_TX_EP_MASK	0xffff		/* EP0 + 15 Tx EPs */
 #define AM35X_RX_EP_MASK	0xfffe		/* 15 Rx EPs */
 #define AM35X_TX_INTR_MASK	(AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
 #define AM35X_RX_INTR_MASK	(AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
 #define USB_MENTOR_CORE_OFFSET	0x400
 struct am35x_glue {
 	struct device		*dev;
 	struct platform_device	*musb;
 	struct clk		*phy_clk;
 	struct clk		*clk;
 };
 #define glue_to_musb(g)		platform_get_drvdata(g->musb)
 /*
  * am35x_musb_enable - enable interrupts
  */
 static void am35x_musb_enable(struct musb *musb)
 {
 	void __iomem *reg_base = musb->ctrl_base;
 	u32 epmask;
 	/* Workaround: setup IRQs through both register sets. */
 	epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
 	       ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
 	musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
 	musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
 	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
-	if (is_otg_enabled(musb))
+	musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
-		musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
+			AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
-			    AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
 }
 /*
  * am35x_musb_disable - disable HDRC and flush interrupts
  */
 static void am35x_musb_disable(struct musb *musb)
 {
 	void __iomem *reg_base = musb->ctrl_base;
 	musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
 	musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
 			 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
 	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 }
 #define portstate(stmt)		stmt
 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
 {
 	WARN_ON(is_on && is_peripheral_active(musb));
 }
 #define	POLL_SECONDS	2
 static struct timer_list otg_workaround;
 static void otg_timer(unsigned long _musb)
 {
 	struct musb		*musb = (void *)_musb;
 	void __iomem		*mregs = musb->mregs;
 	u8			devctl;
 	unsigned long		flags;
 	/*
 	 * We poll because AM35x's won't expose several OTG-critical
 	 * status change events (from the transceiver) otherwise.
 	 */
 	devctl = musb_readb(mregs, MUSB_DEVCTL);
 	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
 		otg_state_string(musb->xceiv->state));
 	spin_lock_irqsave(&musb->lock, flags);
 	switch (musb->xceiv->state) {
 	case OTG_STATE_A_WAIT_BCON:
 		devctl &= ~MUSB_DEVCTL_SESSION;
 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 		if (devctl & MUSB_DEVCTL_BDEVICE) {
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 			MUSB_DEV_MODE(musb);
 		} else {
 			musb->xceiv->state = OTG_STATE_A_IDLE;
 			MUSB_HST_MODE(musb);
 		}
 		break;
 	case OTG_STATE_A_WAIT_VFALL:
 		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 		musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
 			    MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
 		break;
 	case OTG_STATE_B_IDLE:
-		if (!is_peripheral_enabled(musb))
-			break;
 		devctl = musb_readb(mregs, MUSB_DEVCTL);
 		if (devctl & MUSB_DEVCTL_BDEVICE)
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 		else
 			musb->xceiv->state = OTG_STATE_A_IDLE;
 		break;
 	default:
 		break;
 	}
 	spin_unlock_irqrestore(&musb->lock, flags);
 }
 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
 {
 	static unsigned long last_timer;
-	if (!is_otg_enabled(musb))
-		return;
 	if (timeout == 0)
 		timeout = jiffies + msecs_to_jiffies(3);
 	/* Never idle if active, or when VBUS timeout is not set as host */
 	if (musb->is_active || (musb->a_wait_bcon == 0 &&
 				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
 		dev_dbg(musb->controller, "%s active, deleting timer\n",
 			otg_state_string(musb->xceiv->state));
 		del_timer(&otg_workaround);
 		last_timer = jiffies;
 		return;
 	}
 	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
 		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
 		return;
 	}
 	last_timer = timeout;
 	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
 		otg_state_string(musb->xceiv->state),
 		jiffies_to_msecs(timeout - jiffies));
 	mod_timer(&otg_workaround, timeout);
 }
 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
 {
 	struct musb  *musb = hci;
 	void __iomem *reg_base = musb->ctrl_base;
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
 	struct usb_otg *otg = musb->xceiv->otg;
 	unsigned long flags;
 	irqreturn_t ret = IRQ_NONE;
 	u32 epintr, usbintr;
 	spin_lock_irqsave(&musb->lock, flags);
 	/* Get endpoint interrupts */
 	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
 	if (epintr) {
 		musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
 		musb->int_rx =
 			(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
 		musb->int_tx =
 			(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
 	}
 	/* Get usb core interrupts */
 	usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
 	if (!usbintr && !epintr)
 		goto eoi;
 	if (usbintr) {
 		musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
 		musb->int_usb =
 			(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
 	}
 	/*
 	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
 	 * AM35x's missing ID change IRQ.  We need an ID change IRQ to
 	 * switch appropriately between halves of the OTG state machine.
 	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
 	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
 	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
 	 */
 	if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
 		int drvvbus = musb_readl(reg_base, USB_STAT_REG);
 		void __iomem *mregs = musb->mregs;
 		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
 		int err;
-		err = is_host_enabled(musb) && (musb->int_usb &
+		err = musb->int_usb & MUSB_INTR_VBUSERROR;
-						MUSB_INTR_VBUSERROR);
 		if (err) {
 			/*
 			 * The Mentor core doesn't debounce VBUS as needed
 			 * to cope with device connect current spikes. This
 			 * means it's not uncommon for bus-powered devices
 			 * to get VBUS errors during enumeration.
 			 *
 			 * This is a workaround, but newer RTL from Mentor
 			 * seems to allow a better one: "re"-starting sessions
 			 * without waiting for VBUS to stop registering in
 			 * devctl.
 			 */
 			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 			WARNING("VBUS error workaround (delay coming)\n");
-		} else if (is_host_enabled(musb) && drvvbus) {
+		} else if (drvvbus) {
 			MUSB_HST_MODE(musb);
 			otg->default_a = 1;
 			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
 			del_timer(&otg_workaround);
 		} else {
 			musb->is_active = 0;
 			MUSB_DEV_MODE(musb);
 			otg->default_a = 0;
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
 		}
 		/* NOTE: this must complete power-on within 100 ms. */
 		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 				drvvbus ? "on" : "off",
 				otg_state_string(musb->xceiv->state),
 				err ? " ERROR" : "",
 				devctl);
 		ret = IRQ_HANDLED;
 	}
 	if (musb->int_tx || musb->int_rx || musb->int_usb)
 		ret |= musb_interrupt(musb);
 eoi:
 	/* EOI needs to be written for the IRQ to be re-asserted. */
 	if (ret == IRQ_HANDLED || epintr || usbintr) {
 		/* clear level interrupt */
 		if (data->clear_irq)
 			data->clear_irq();
 		/* write EOI */
 		musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 	}
 	/* Poll for ID change */
-	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
+	if (musb->xceiv->state == OTG_STATE_B_IDLE)
 		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return ret;
 }
 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
 {
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
 	int     retval = 0;
 	if (data->set_mode)
 		data->set_mode(musb_mode);
 	else
 		retval = -EIO;
 	return retval;
 }
 static int am35x_musb_init(struct musb *musb)
 {
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
 	void __iomem *reg_base = musb->ctrl_base;
 	u32 rev;
 	musb->mregs += USB_MENTOR_CORE_OFFSET;
 	/* Returns zero if e.g. not clocked */
 	rev = musb_readl(reg_base, USB_REVISION_REG);
 	if (!rev)
 		return -ENODEV;
 	usb_nop_xceiv_register();
 	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
 	if (IS_ERR_OR_NULL(musb->xceiv))
 		return -ENODEV;
-	if (is_host_enabled(musb))
+	setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
-		setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
 	/* Reset the musb */
 	if (data->reset)
 		data->reset();
 	/* Reset the controller */
 	musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
 	/* Start the on-chip PHY and its PLL. */
 	if (data->set_phy_power)
 		data->set_phy_power(1);
 	msleep(5);
 	musb->isr = am35x_musb_interrupt;
 	/* clear level interrupt */
 	if (data->clear_irq)
 		data->clear_irq();
 	return 0;
 }
 static int am35x_musb_exit(struct musb *musb)
 {
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
-	if (is_host_enabled(musb))
+	del_timer_sync(&otg_workaround);
-		del_timer_sync(&otg_workaround);
 	/* Shutdown the on-chip PHY and its PLL. */
 	if (data->set_phy_power)
 		data->set_phy_power(0);
 	usb_put_phy(musb->xceiv);
 	usb_nop_xceiv_unregister();
 	return 0;
 }
 /* AM35x supports only 32bit read operation */
 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 {
 	void __iomem *fifo = hw_ep->fifo;
 	u32		val;
 	int		i;
 	/* Read for 32bit-aligned destination address */
 	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
 		readsl(fifo, dst, len >> 2);
 		dst += len & ~0x03;
 		len &= 0x03;
 	}
 	/*
 	 * Now read the remaining 1 to 3 byte or complete length if
 	 * unaligned address.
 	 */
 	if (len > 4) {
 		for (i = 0; i < (len >> 2); i++) {
 			*(u32 *) dst = musb_readl(fifo, 0);
 			dst += 4;
 		}
 		len &= 0x03;
 	}
 	if (len > 0) {
 		val = musb_readl(fifo, 0);
 		memcpy(dst, &val, len);
 	}
 }
 static const struct musb_platform_ops am35x_ops = {
 	.init		= am35x_musb_init,
 	.exit		= am35x_musb_exit,
 	.enable		= am35x_musb_enable,
 	.disable	= am35x_musb_disable,
 	.set_mode	= am35x_musb_set_mode,
 	.try_idle	= am35x_musb_try_idle,
 	.set_vbus	= am35x_musb_set_vbus,
 };
 static u64 am35x_dmamask = DMA_BIT_MASK(32);
 static int __devinit am35x_probe(struct platform_device *pdev)
 {
 	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
 	struct platform_device		*musb;
 	struct am35x_glue		*glue;
 	struct clk			*phy_clk;
 	struct clk			*clk;
 	int				ret = -ENOMEM;
 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 	if (!glue) {
 		dev_err(&pdev->dev, "failed to allocate glue context\n");
 		goto err0;
 	}
 	musb = platform_device_alloc("musb-hdrc", -1);
 	if (!musb) {
 		dev_err(&pdev->dev, "failed to allocate musb device\n");
 		goto err1;
 	}
 	phy_clk = clk_get(&pdev->dev, "fck");
 	if (IS_ERR(phy_clk)) {
 		dev_err(&pdev->dev, "failed to get PHY clock\n");
 		ret = PTR_ERR(phy_clk);
 		goto err2;
 	}
 	clk = clk_get(&pdev->dev, "ick");
 	if (IS_ERR(clk)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
 		ret = PTR_ERR(clk);
 		goto err3;
 	}
 	ret = clk_enable(phy_clk);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to enable PHY clock\n");
 		goto err4;
 	}
 	ret = clk_enable(clk);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to enable clock\n");
 		goto err5;
 	}
 	musb->dev.parent		= &pdev->dev;
 	musb->dev.dma_mask		= &am35x_dmamask;
 	musb->dev.coherent_dma_mask	= am35x_dmamask;
 	glue->dev			= &pdev->dev;
 	glue->musb			= musb;
 	glue->phy_clk			= phy_clk;
 	glue->clk			= clk;
 	pdata->platform_ops		= &am35x_ops;
 	platform_set_drvdata(pdev, glue);
 	ret = platform_device_add_resources(musb, pdev->resource,
 			pdev->num_resources);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add resources\n");
 		goto err6;
 	}
 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add platform_data\n");
 		goto err6;
 	}
 	ret = platform_device_add(musb);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register musb device\n");
 		goto err6;
 	}
 	return 0;
 err6:
 	clk_disable(clk);
 err5:
 	clk_disable(phy_clk);
 err4:
 	clk_put(clk);
 err3:
 	clk_put(phy_clk);
 err2:
 	platform_device_put(musb);
 err1:
 	kfree(glue);
 err0:
 	return ret;
 }
 static int __devexit am35x_remove(struct platform_device *pdev)
 {
 	struct am35x_glue	*glue = platform_get_drvdata(pdev);
 	platform_device_del(glue->musb);
 	platform_device_put(glue->musb);
 	clk_disable(glue->clk);
 	clk_disable(glue->phy_clk);
 	clk_put(glue->clk);
 	clk_put(glue->phy_clk);
 	kfree(glue);
 	return 0;
 }
 #ifdef CONFIG_PM
 static int am35x_suspend(struct device *dev)
 {
 	struct am35x_glue	*glue = dev_get_drvdata(dev);
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
 	/* Shutdown the on-chip PHY and its PLL. */
 	if (data->set_phy_power)
 		data->set_phy_power(0);
 	clk_disable(glue->phy_clk);
 	clk_disable(glue->clk);
 	return 0;
 }
 static int am35x_resume(struct device *dev)
 {
 	struct am35x_glue	*glue = dev_get_drvdata(dev);
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
 	int			ret;
 	/* Start the on-chip PHY and its PLL. */
 	if (data->set_phy_power)
 		data->set_phy_power(1);
 	ret = clk_enable(glue->phy_clk);
 	if (ret) {
 		dev_err(dev, "failed to enable PHY clock\n");
 		return ret;
 	}
 	ret = clk_enable(glue->clk);
 	if (ret) {
 		dev_err(dev, "failed to enable clock\n");
 		return ret;
 	}
 	return 0;
 }
 static struct dev_pm_ops am35x_pm_ops = {
 	.suspend	= am35x_suspend,
 	.resume		= am35x_resume,
 };
 #define DEV_PM_OPS	&am35x_pm_ops
 #else
 #define DEV_PM_OPS	NULL
 #endif
 static struct platform_driver am35x_driver = {
 	.probe		= am35x_probe,
 	.remove		= __devexit_p(am35x_remove),
 	.driver		= {
 		.name	= "musb-am35x",
 		.pm	= DEV_PM_OPS,
 	},
 };
 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
 MODULE_LICENSE("GPL v2");
 static int __init am35x_init(void)
 {
 	return platform_driver_register(&am35x_driver);
 }
 module_init(am35x_init);
 static void __exit am35x_exit(void)
 {
 	platform_driver_unregister(&am35x_driver);
 }
 module_exit(am35x_exit);

drivers/usb/musb/blackfin.c

Diff comments View file @ 032ec49

1	/*	1	/*
2	* MUSB OTG controller driver for Blackfin Processors	2	* MUSB OTG controller driver for Blackfin Processors
3	*	3	*
4	* Copyright 2006-2008 Analog Devices Inc.	4	* Copyright 2006-2008 Analog Devices Inc.
5	*	5	*
6	* Enter bugs at http://blackfin.uclinux.org/	6	* Enter bugs at http://blackfin.uclinux.org/
7	*	7	*
8	* Licensed under the GPL-2 or later.	8	* Licensed under the GPL-2 or later.
9	*/	9	*/
10		10
11	#include <linux/module.h>	11	#include <linux/module.h>
12	#include <linux/kernel.h>	12	#include <linux/kernel.h>
13	#include <linux/sched.h>	13	#include <linux/sched.h>
14	#include <linux/init.h>	14	#include <linux/init.h>
15	#include <linux/list.h>	15	#include <linux/list.h>
16	#include <linux/gpio.h>	16	#include <linux/gpio.h>
17	#include <linux/io.h>	17	#include <linux/io.h>
18	#include <linux/err.h>	18	#include <linux/err.h>
19	#include <linux/platform_device.h>	19	#include <linux/platform_device.h>
20	#include <linux/dma-mapping.h>	20	#include <linux/dma-mapping.h>
21	#include <linux/prefetch.h>	21	#include <linux/prefetch.h>
22		22
23	#include <asm/cacheflush.h>	23	#include <asm/cacheflush.h>
24		24
25	#include "musb_core.h"	25	#include "musb_core.h"
26	#include "musbhsdma.h"	26	#include "musbhsdma.h"
27	#include "blackfin.h"	27	#include "blackfin.h"
28		28
29	struct bfin_glue {	29	struct bfin_glue {
30	struct device *dev;	30	struct device *dev;
31	struct platform_device *musb;	31	struct platform_device *musb;
32	};	32	};
33	#define glue_to_musb(g) platform_get_drvdata(g->musb)	33	#define glue_to_musb(g) platform_get_drvdata(g->musb)
34		34
35	/*	35	/*
36	* Load an endpoint's FIFO	36	* Load an endpoint's FIFO
37	*/	37	*/
38	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)	38	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
39	{	39	{
40	struct musb *musb = hw_ep->musb;	40	struct musb *musb = hw_ep->musb;
41	void __iomem *fifo = hw_ep->fifo;	41	void __iomem *fifo = hw_ep->fifo;
42	void __iomem *epio = hw_ep->regs;	42	void __iomem *epio = hw_ep->regs;
43	u8 epnum = hw_ep->epnum;	43	u8 epnum = hw_ep->epnum;
44		44
45	prefetch((u8 *)src);	45	prefetch((u8 *)src);
46		46
47	musb_writew(epio, MUSB_TXCOUNT, len);	47	musb_writew(epio, MUSB_TXCOUNT, len);
48		48
49	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",	49	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
50	hw_ep->epnum, fifo, len, src, epio);	50	hw_ep->epnum, fifo, len, src, epio);
51		51
52	dump_fifo_data(src, len);	52	dump_fifo_data(src, len);
53		53
54	if (!ANOMALY_05000380 && epnum != 0) {	54	if (!ANOMALY_05000380 && epnum != 0) {
55	u16 dma_reg;	55	u16 dma_reg;
56		56
57	flush_dcache_range((unsigned long)src,	57	flush_dcache_range((unsigned long)src,
58	(unsigned long)(src + len));	58	(unsigned long)(src + len));
59		59
60	/* Setup DMA address register */	60	/* Setup DMA address register */
61	dma_reg = (u32)src;	61	dma_reg = (u32)src;
62	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);	62	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
63	SSYNC();	63	SSYNC();
64		64
65	dma_reg = (u32)src >> 16;	65	dma_reg = (u32)src >> 16;
66	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);	66	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
67	SSYNC();	67	SSYNC();
68		68
69	/* Setup DMA count register */	69	/* Setup DMA count register */
70	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);	70	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
71	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);	71	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
72	SSYNC();	72	SSYNC();
73		73
74	/* Enable the DMA */	74	/* Enable the DMA */
75	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA \| DIRECTION;	75	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA \| DIRECTION;
76	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);	76	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
77	SSYNC();	77	SSYNC();
78		78
79	/* Wait for compelete */	79	/* Wait for compelete */
80	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))	80	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
81	cpu_relax();	81	cpu_relax();
82		82
83	/* acknowledge dma interrupt */	83	/* acknowledge dma interrupt */
84	bfin_write_USB_DMA_INTERRUPT(1 << epnum);	84	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
85	SSYNC();	85	SSYNC();
86		86
87	/* Reset DMA */	87	/* Reset DMA */
88	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);	88	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
89	SSYNC();	89	SSYNC();
90	} else {	90	} else {
91	SSYNC();	91	SSYNC();
92		92
93	if (unlikely((unsigned long)src & 0x01))	93	if (unlikely((unsigned long)src & 0x01))
94	outsw_8((unsigned long)fifo, src, (len + 1) >> 1);	94	outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
95	else	95	else
96	outsw((unsigned long)fifo, src, (len + 1) >> 1);	96	outsw((unsigned long)fifo, src, (len + 1) >> 1);
97	}	97	}
98	}	98	}
99	/*	99	/*
100	* Unload an endpoint's FIFO	100	* Unload an endpoint's FIFO
101	*/	101	*/
102	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)	102	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
103	{	103	{
104	struct musb *musb = hw_ep->musb;	104	struct musb *musb = hw_ep->musb;
105	void __iomem *fifo = hw_ep->fifo;	105	void __iomem *fifo = hw_ep->fifo;
106	u8 epnum = hw_ep->epnum;	106	u8 epnum = hw_ep->epnum;
107		107
108	if (ANOMALY_05000467 && epnum != 0) {	108	if (ANOMALY_05000467 && epnum != 0) {
109	u16 dma_reg;	109	u16 dma_reg;
110		110
111	invalidate_dcache_range((unsigned long)dst,	111	invalidate_dcache_range((unsigned long)dst,
112	(unsigned long)(dst + len));	112	(unsigned long)(dst + len));
113		113
114	/* Setup DMA address register */	114	/* Setup DMA address register */
115	dma_reg = (u32)dst;	115	dma_reg = (u32)dst;
116	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);	116	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
117	SSYNC();	117	SSYNC();
118		118
119	dma_reg = (u32)dst >> 16;	119	dma_reg = (u32)dst >> 16;
120	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);	120	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
121	SSYNC();	121	SSYNC();
122		122
123	/* Setup DMA count register */	123	/* Setup DMA count register */
124	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);	124	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
125	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);	125	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
126	SSYNC();	126	SSYNC();
127		127
128	/* Enable the DMA */	128	/* Enable the DMA */
129	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;	129	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;
130	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);	130	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
131	SSYNC();	131	SSYNC();
132		132
133	/* Wait for compelete */	133	/* Wait for compelete */
134	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))	134	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
135	cpu_relax();	135	cpu_relax();
136		136
137	/* acknowledge dma interrupt */	137	/* acknowledge dma interrupt */
138	bfin_write_USB_DMA_INTERRUPT(1 << epnum);	138	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
139	SSYNC();	139	SSYNC();
140		140
141	/* Reset DMA */	141	/* Reset DMA */
142	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);	142	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
143	SSYNC();	143	SSYNC();
144	} else {	144	} else {
145	SSYNC();	145	SSYNC();
146	/* Read the last byte of packet with odd size from address fifo + 4	146	/* Read the last byte of packet with odd size from address fifo + 4
147	* to trigger 1 byte access to EP0 FIFO.	147	* to trigger 1 byte access to EP0 FIFO.
148	*/	148	*/
149	if (len == 1)	149	if (len == 1)
150	*dst = (u8)inw((unsigned long)fifo + 4);	150	*dst = (u8)inw((unsigned long)fifo + 4);
151	else {	151	else {
152	if (unlikely((unsigned long)dst & 0x01))	152	if (unlikely((unsigned long)dst & 0x01))
153	insw_8((unsigned long)fifo, dst, len >> 1);	153	insw_8((unsigned long)fifo, dst, len >> 1);
154	else	154	else
155	insw((unsigned long)fifo, dst, len >> 1);	155	insw((unsigned long)fifo, dst, len >> 1);
156		156
157	if (len & 0x01)	157	if (len & 0x01)
158	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);	158	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
159	}	159	}
160	}	160	}
161	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",	161	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
162	'R', hw_ep->epnum, fifo, len, dst);	162	'R', hw_ep->epnum, fifo, len, dst);
163		163
164	dump_fifo_data(dst, len);	164	dump_fifo_data(dst, len);
165	}	165	}
166		166
167	static irqreturn_t blackfin_interrupt(int irq, void *__hci)	167	static irqreturn_t blackfin_interrupt(int irq, void *__hci)
168	{	168	{
169	unsigned long flags;	169	unsigned long flags;
170	irqreturn_t retval = IRQ_NONE;	170	irqreturn_t retval = IRQ_NONE;
171	struct musb *musb = __hci;	171	struct musb *musb = __hci;
172		172
173	spin_lock_irqsave(&musb->lock, flags);	173	spin_lock_irqsave(&musb->lock, flags);
174		174
175	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);	175	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
176	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);	176	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
177	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);	177	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
178		178
179	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {	179	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {
180	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);	180	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
181	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);	181	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
182	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);	182	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
183	retval = musb_interrupt(musb);	183	retval = musb_interrupt(musb);
184	}	184	}
185		185
186	/* Start sampling ID pin, when plug is removed from MUSB */	186	/* Start sampling ID pin, when plug is removed from MUSB */
187	if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE	187	if ((musb->xceiv->state == OTG_STATE_B_IDLE
188	\|\| musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) \|\|	188	\|\| musb->xceiv->state == OTG_STATE_A_WAIT_BCON) \|\|
189	(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {	189	(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
190	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);	190	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
191	musb->a_wait_bcon = TIMER_DELAY;	191	musb->a_wait_bcon = TIMER_DELAY;
192	}	192	}
193		193
194	spin_unlock_irqrestore(&musb->lock, flags);	194	spin_unlock_irqrestore(&musb->lock, flags);
195		195
196	return retval;	196	return retval;
197	}	197	}
198		198
199	static void musb_conn_timer_handler(unsigned long _musb)	199	static void musb_conn_timer_handler(unsigned long _musb)
200	{	200	{
201	struct musb musb = (void )_musb;	201	struct musb musb = (void )_musb;
202	unsigned long flags;	202	unsigned long flags;
203	u16 val;	203	u16 val;
204	static u8 toggle;	204	static u8 toggle;
205		205
206	spin_lock_irqsave(&musb->lock, flags);	206	spin_lock_irqsave(&musb->lock, flags);
207	switch (musb->xceiv->state) {	207	switch (musb->xceiv->state) {
208	case OTG_STATE_A_IDLE:	208	case OTG_STATE_A_IDLE:
209	case OTG_STATE_A_WAIT_BCON:	209	case OTG_STATE_A_WAIT_BCON:
210	/* Start a new session */	210	/* Start a new session */
211	val = musb_readw(musb->mregs, MUSB_DEVCTL);	211	val = musb_readw(musb->mregs, MUSB_DEVCTL);
212	val &= ~MUSB_DEVCTL_SESSION;	212	val &= ~MUSB_DEVCTL_SESSION;
213	musb_writew(musb->mregs, MUSB_DEVCTL, val);	213	musb_writew(musb->mregs, MUSB_DEVCTL, val);
214	val \|= MUSB_DEVCTL_SESSION;	214	val \|= MUSB_DEVCTL_SESSION;
215	musb_writew(musb->mregs, MUSB_DEVCTL, val);	215	musb_writew(musb->mregs, MUSB_DEVCTL, val);
216	/* Check if musb is host or peripheral. */	216	/* Check if musb is host or peripheral. */
217	val = musb_readw(musb->mregs, MUSB_DEVCTL);	217	val = musb_readw(musb->mregs, MUSB_DEVCTL);
218		218
219	if (!(val & MUSB_DEVCTL_BDEVICE)) {	219	if (!(val & MUSB_DEVCTL_BDEVICE)) {
220	gpio_set_value(musb->config->gpio_vrsel, 1);	220	gpio_set_value(musb->config->gpio_vrsel, 1);
221	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;	221	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
222	} else {	222	} else {
223	gpio_set_value(musb->config->gpio_vrsel, 0);	223	gpio_set_value(musb->config->gpio_vrsel, 0);
224	/* Ignore VBUSERROR and SUSPEND IRQ */	224	/* Ignore VBUSERROR and SUSPEND IRQ */
225	val = musb_readb(musb->mregs, MUSB_INTRUSBE);	225	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
226	val &= ~MUSB_INTR_VBUSERROR;	226	val &= ~MUSB_INTR_VBUSERROR;
227	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);	227	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
228		228
229	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;	229	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
230	musb_writeb(musb->mregs, MUSB_INTRUSB, val);	230	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
231	if (is_otg_enabled(musb))	231	musb->xceiv->state = OTG_STATE_B_IDLE;
232	musb->xceiv->state = OTG_STATE_B_IDLE;
233	else
234	musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
235	}	232	}
236	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);	233	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
237	break;	234	break;
238	case OTG_STATE_B_IDLE:	235	case OTG_STATE_B_IDLE:
239		236	/*
240	if (!is_peripheral_enabled(musb))	237	* Start a new session. It seems that MUSB needs taking
241	break;
242	/* Start a new session. It seems that MUSB needs taking
243	* some time to recognize the type of the plug inserted?	238	* some time to recognize the type of the plug inserted?
244	*/	239	*/
245	val = musb_readw(musb->mregs, MUSB_DEVCTL);	240	val = musb_readw(musb->mregs, MUSB_DEVCTL);
246	val \|= MUSB_DEVCTL_SESSION;	241	val \|= MUSB_DEVCTL_SESSION;
247	musb_writew(musb->mregs, MUSB_DEVCTL, val);	242	musb_writew(musb->mregs, MUSB_DEVCTL, val);
248	val = musb_readw(musb->mregs, MUSB_DEVCTL);	243	val = musb_readw(musb->mregs, MUSB_DEVCTL);
249		244
250	if (!(val & MUSB_DEVCTL_BDEVICE)) {	245	if (!(val & MUSB_DEVCTL_BDEVICE)) {
251	gpio_set_value(musb->config->gpio_vrsel, 1);	246	gpio_set_value(musb->config->gpio_vrsel, 1);
252	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;	247	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
253	} else {	248	} else {
254	gpio_set_value(musb->config->gpio_vrsel, 0);	249	gpio_set_value(musb->config->gpio_vrsel, 0);
255		250
256	/* Ignore VBUSERROR and SUSPEND IRQ */	251	/* Ignore VBUSERROR and SUSPEND IRQ */
257	val = musb_readb(musb->mregs, MUSB_INTRUSBE);	252	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
258	val &= ~MUSB_INTR_VBUSERROR;	253	val &= ~MUSB_INTR_VBUSERROR;
259	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);	254	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
260		255
261	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;	256	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
262	musb_writeb(musb->mregs, MUSB_INTRUSB, val);	257	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
263		258
264	/* Toggle the Soft Conn bit, so that we can response to	259	/* Toggle the Soft Conn bit, so that we can response to
265	* the inserting of either A-plug or B-plug.	260	* the inserting of either A-plug or B-plug.
266	*/	261	*/
267	if (toggle) {	262	if (toggle) {
268	val = musb_readb(musb->mregs, MUSB_POWER);	263	val = musb_readb(musb->mregs, MUSB_POWER);
269	val &= ~MUSB_POWER_SOFTCONN;	264	val &= ~MUSB_POWER_SOFTCONN;
270	musb_writeb(musb->mregs, MUSB_POWER, val);	265	musb_writeb(musb->mregs, MUSB_POWER, val);
271	toggle = 0;	266	toggle = 0;
272	} else {	267	} else {
273	val = musb_readb(musb->mregs, MUSB_POWER);	268	val = musb_readb(musb->mregs, MUSB_POWER);
274	val \|= MUSB_POWER_SOFTCONN;	269	val \|= MUSB_POWER_SOFTCONN;
275	musb_writeb(musb->mregs, MUSB_POWER, val);	270	musb_writeb(musb->mregs, MUSB_POWER, val);
276	toggle = 1;	271	toggle = 1;
277	}	272	}
278	/* The delay time is set to 1/4 second by default,	273	/* The delay time is set to 1/4 second by default,
279	* shortening it, if accelerating A-plug detection	274	* shortening it, if accelerating A-plug detection
280	* is needed in OTG mode.	275	* is needed in OTG mode.
281	*/	276	*/
282	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);	277	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
283	}	278	}
284	break;	279	break;
285	default:	280	default:
286	dev_dbg(musb->controller, "%s state not handled\n",	281	dev_dbg(musb->controller, "%s state not handled\n",
287	otg_state_string(musb->xceiv->state));	282	otg_state_string(musb->xceiv->state));
288	break;	283	break;
289	}	284	}
290	spin_unlock_irqrestore(&musb->lock, flags);	285	spin_unlock_irqrestore(&musb->lock, flags);
291		286
292	dev_dbg(musb->controller, "state is %s\n",	287	dev_dbg(musb->controller, "state is %s\n",
293	otg_state_string(musb->xceiv->state));	288	otg_state_string(musb->xceiv->state));
294	}	289	}
295		290
296	static void bfin_musb_enable(struct musb *musb)	291	static void bfin_musb_enable(struct musb *musb)
297	{	292	{
298	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {	293	/* REVISIT is this really correct ? */
299	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
300	musb->a_wait_bcon = TIMER_DELAY;
301	}
302	}	294	}
303		295
304	static void bfin_musb_disable(struct musb *musb)	296	static void bfin_musb_disable(struct musb *musb)
305	{	297	{
306	}	298	}
307		299
308	static void bfin_musb_set_vbus(struct musb *musb, int is_on)	300	static void bfin_musb_set_vbus(struct musb *musb, int is_on)
309	{	301	{
310	int value = musb->config->gpio_vrsel_active;	302	int value = musb->config->gpio_vrsel_active;
311	if (!is_on)	303	if (!is_on)
312	value = !value;	304	value = !value;
313	gpio_set_value(musb->config->gpio_vrsel, value);	305	gpio_set_value(musb->config->gpio_vrsel, value);
314		306
315	dev_dbg(musb->controller, "VBUS %s, devctl %02x "	307	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
316	/* otg %3x conf %08x prcm %08x */ "\n",	308	/* otg %3x conf %08x prcm %08x */ "\n",
317	otg_state_string(musb->xceiv->state),	309	otg_state_string(musb->xceiv->state),
318	musb_readb(musb->mregs, MUSB_DEVCTL));	310	musb_readb(musb->mregs, MUSB_DEVCTL));
319	}	311	}
320		312
321	static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)	313	static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
322	{	314	{
323	return 0;	315	return 0;
324	}	316	}
325		317
326	static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
327	{
328	if (!is_otg_enabled(musb) && is_host_enabled(musb))
329	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
330	}
331
332	static int bfin_musb_vbus_status(struct musb *musb)	318	static int bfin_musb_vbus_status(struct musb *musb)
333	{	319	{
334	return 0;	320	return 0;
335	}	321	}
336		322
337	static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)	323	static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
338	{	324	{
339	return -EIO;	325	return -EIO;
340	}	326	}
341		327
342	static int bfin_musb_adjust_channel_params(struct dma_channel *channel,	328	static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
343	u16 packet_sz, u8 *mode,	329	u16 packet_sz, u8 *mode,
344	dma_addr_t dma_addr, u32 len)	330	dma_addr_t dma_addr, u32 len)
345	{	331	{
346	struct musb_dma_channel *musb_channel = channel->private_data;	332	struct musb_dma_channel *musb_channel = channel->private_data;
347		333
348	/*	334	/*
349	* Anomaly 05000450 might cause data corruption when using DMA	335	* Anomaly 05000450 might cause data corruption when using DMA
350	* MODE 1 transmits with short packet. So to work around this,	336	* MODE 1 transmits with short packet. So to work around this,
351	* we truncate all MODE 1 transfers down to a multiple of the	337	* we truncate all MODE 1 transfers down to a multiple of the
352	* max packet size, and then do the last short packet transfer	338	* max packet size, and then do the last short packet transfer
353	* (if there is any) using MODE 0.	339	* (if there is any) using MODE 0.
354	*/	340	*/
355	if (ANOMALY_05000450) {	341	if (ANOMALY_05000450) {
356	if (musb_channel->transmit && *mode == 1)	342	if (musb_channel->transmit && *mode == 1)
357	len = len - (*len % packet_sz);	343	len = len - (*len % packet_sz);
358	}	344	}
359		345
360	return 0;	346	return 0;
361	}	347	}
362		348
363	static void bfin_musb_reg_init(struct musb *musb)	349	static void bfin_musb_reg_init(struct musb *musb)
364	{	350	{
365	if (ANOMALY_05000346) {	351	if (ANOMALY_05000346) {
366	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);	352	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
367	SSYNC();	353	SSYNC();
368	}	354	}
369		355
370	if (ANOMALY_05000347) {	356	if (ANOMALY_05000347) {
371	bfin_write_USB_APHY_CNTRL(0x0);	357	bfin_write_USB_APHY_CNTRL(0x0);
372	SSYNC();	358	SSYNC();
373	}	359	}
374		360
375	/* Configure PLL oscillator register */	361	/* Configure PLL oscillator register */
376	bfin_write_USB_PLLOSC_CTRL(0x3080 \|	362	bfin_write_USB_PLLOSC_CTRL(0x3080 \|
377	((480/musb->config->clkin) << 1));	363	((480/musb->config->clkin) << 1));
378	SSYNC();	364	SSYNC();
379		365
380	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);	366	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
381	SSYNC();	367	SSYNC();
382		368
383	bfin_write_USB_EP_NI0_RXMAXP(64);	369	bfin_write_USB_EP_NI0_RXMAXP(64);
384	SSYNC();	370	SSYNC();
385		371
386	bfin_write_USB_EP_NI0_TXMAXP(64);	372	bfin_write_USB_EP_NI0_TXMAXP(64);
387	SSYNC();	373	SSYNC();
388		374
389	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/	375	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
390	bfin_write_USB_GLOBINTR(0x7);	376	bfin_write_USB_GLOBINTR(0x7);
391	SSYNC();	377	SSYNC();
392		378
393	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|	379	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|
394	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|	380	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|
395	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|	381	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|
396	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|	382	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|
397	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);	383	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);
398	SSYNC();	384	SSYNC();
399	}	385	}
400		386
401	static int bfin_musb_init(struct musb *musb)	387	static int bfin_musb_init(struct musb *musb)
402	{	388	{
403		389
404	/*	390	/*
405	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE	391	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
406	* and OTG HOST modes, while rev 1.1 and greater require PE7 to	392	* and OTG HOST modes, while rev 1.1 and greater require PE7 to
407	* be low for DEVICE mode and high for HOST mode. We set it high	393	* be low for DEVICE mode and high for HOST mode. We set it high
408	* here because we are in host mode	394	* here because we are in host mode
409	*/	395	*/
410		396
411	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {	397	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
412	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",	398	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
413	musb->config->gpio_vrsel);	399	musb->config->gpio_vrsel);
414	return -ENODEV;	400	return -ENODEV;
415	}	401	}
416	gpio_direction_output(musb->config->gpio_vrsel, 0);	402	gpio_direction_output(musb->config->gpio_vrsel, 0);
417		403
418	usb_nop_xceiv_register();	404	usb_nop_xceiv_register();
419	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);	405	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
420	if (IS_ERR_OR_NULL(musb->xceiv)) {	406	if (IS_ERR_OR_NULL(musb->xceiv)) {
421	gpio_free(musb->config->gpio_vrsel);	407	gpio_free(musb->config->gpio_vrsel);
422	return -ENODEV;	408	return -ENODEV;
423	}	409	}
424		410
425	bfin_musb_reg_init(musb);	411	bfin_musb_reg_init(musb);
426		412
427	if (is_host_enabled(musb)) {	413	setup_timer(&musb_conn_timer, musb_conn_timer_handler,
428	setup_timer(&musb_conn_timer,	414	(unsigned long) musb);
429	musb_conn_timer_handler, (unsigned long) musb);
430	}
431	if (is_peripheral_enabled(musb))
432	musb->xceiv->set_power = bfin_musb_set_power;
433		415
		416	musb->xceiv->set_power = bfin_musb_set_power;
		417
434	musb->isr = blackfin_interrupt;	418	musb->isr = blackfin_interrupt;
435	musb->double_buffer_not_ok = true;	419	musb->double_buffer_not_ok = true;
436		420
437	return 0;	421	return 0;
438	}	422	}
439		423
440	static int bfin_musb_exit(struct musb *musb)	424	static int bfin_musb_exit(struct musb *musb)
441	{	425	{
442	gpio_free(musb->config->gpio_vrsel);	426	gpio_free(musb->config->gpio_vrsel);
443		427
444	usb_put_phy(musb->xceiv);	428	usb_put_phy(musb->xceiv);
445	usb_nop_xceiv_unregister();	429	usb_nop_xceiv_unregister();
446	return 0;	430	return 0;
447	}	431	}
448		432
449	static const struct musb_platform_ops bfin_ops = {	433	static const struct musb_platform_ops bfin_ops = {
450	.init = bfin_musb_init,	434	.init = bfin_musb_init,
451	.exit = bfin_musb_exit,	435	.exit = bfin_musb_exit,
452		436
453	.enable = bfin_musb_enable,	437	.enable = bfin_musb_enable,
454	.disable = bfin_musb_disable,	438	.disable = bfin_musb_disable,
455		439
456	.set_mode = bfin_musb_set_mode,	440	.set_mode = bfin_musb_set_mode,
457	.try_idle = bfin_musb_try_idle,
458		441
459	.vbus_status = bfin_musb_vbus_status,	442	.vbus_status = bfin_musb_vbus_status,
460	.set_vbus = bfin_musb_set_vbus,	443	.set_vbus = bfin_musb_set_vbus,
461		444
462	.adjust_channel_params = bfin_musb_adjust_channel_params,	445	.adjust_channel_params = bfin_musb_adjust_channel_params,
463	};	446	};
464		447
465	static u64 bfin_dmamask = DMA_BIT_MASK(32);	448	static u64 bfin_dmamask = DMA_BIT_MASK(32);
466		449
467	static int __devinit bfin_probe(struct platform_device *pdev)	450	static int __devinit bfin_probe(struct platform_device *pdev)
468	{	451	{
469	struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;	452	struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
470	struct platform_device *musb;	453	struct platform_device *musb;
471	struct bfin_glue *glue;	454	struct bfin_glue *glue;
472		455
473	int ret = -ENOMEM;	456	int ret = -ENOMEM;
474		457
475	glue = kzalloc(sizeof(*glue), GFP_KERNEL);	458	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
476	if (!glue) {	459	if (!glue) {
477	dev_err(&pdev->dev, "failed to allocate glue context\n");	460	dev_err(&pdev->dev, "failed to allocate glue context\n");
478	goto err0;	461	goto err0;
479	}	462	}
480		463
481	musb = platform_device_alloc("musb-hdrc", -1);	464	musb = platform_device_alloc("musb-hdrc", -1);
482	if (!musb) {	465	if (!musb) {
483	dev_err(&pdev->dev, "failed to allocate musb device\n");	466	dev_err(&pdev->dev, "failed to allocate musb device\n");
484	goto err1;	467	goto err1;
485	}	468	}
486		469
487	musb->dev.parent = &pdev->dev;	470	musb->dev.parent = &pdev->dev;
488	musb->dev.dma_mask = &bfin_dmamask;	471	musb->dev.dma_mask = &bfin_dmamask;
489	musb->dev.coherent_dma_mask = bfin_dmamask;	472	musb->dev.coherent_dma_mask = bfin_dmamask;
490		473
491	glue->dev = &pdev->dev;	474	glue->dev = &pdev->dev;
492	glue->musb = musb;	475	glue->musb = musb;
493		476
494	pdata->platform_ops = &bfin_ops;	477	pdata->platform_ops = &bfin_ops;
495		478
496	platform_set_drvdata(pdev, glue);	479	platform_set_drvdata(pdev, glue);
497		480
498	ret = platform_device_add_resources(musb, pdev->resource,	481	ret = platform_device_add_resources(musb, pdev->resource,
499	pdev->num_resources);	482	pdev->num_resources);
500	if (ret) {	483	if (ret) {
501	dev_err(&pdev->dev, "failed to add resources\n");	484	dev_err(&pdev->dev, "failed to add resources\n");
502	goto err2;	485	goto err2;
503	}	486	}
504		487
505	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));	488	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
506	if (ret) {	489	if (ret) {
507	dev_err(&pdev->dev, "failed to add platform_data\n");	490	dev_err(&pdev->dev, "failed to add platform_data\n");
508	goto err2;	491	goto err2;
509	}	492	}
510		493
511	ret = platform_device_add(musb);	494	ret = platform_device_add(musb);
512	if (ret) {	495	if (ret) {
513	dev_err(&pdev->dev, "failed to register musb device\n");	496	dev_err(&pdev->dev, "failed to register musb device\n");
514	goto err2;	497	goto err2;
515	}	498	}
516		499
517	return 0;	500	return 0;
518		501
519	err2:	502	err2:
520	platform_device_put(musb);	503	platform_device_put(musb);
521		504
522	err1:	505	err1:
523	kfree(glue);	506	kfree(glue);
524		507
525	err0:	508	err0:
526	return ret;	509	return ret;
527	}	510	}
528		511
529	static int __devexit bfin_remove(struct platform_device *pdev)	512	static int __devexit bfin_remove(struct platform_device *pdev)
530	{	513	{
531	struct bfin_glue *glue = platform_get_drvdata(pdev);	514	struct bfin_glue *glue = platform_get_drvdata(pdev);
532		515
533	platform_device_del(glue->musb);	516	platform_device_del(glue->musb);
534	platform_device_put(glue->musb);	517	platform_device_put(glue->musb);
535	kfree(glue);	518	kfree(glue);
536		519
537	return 0;	520	return 0;
538	}	521	}
539		522
540	#ifdef CONFIG_PM	523	#ifdef CONFIG_PM
541	static int bfin_suspend(struct device *dev)	524	static int bfin_suspend(struct device *dev)
542	{	525	{
543	struct bfin_glue *glue = dev_get_drvdata(dev);	526	struct bfin_glue *glue = dev_get_drvdata(dev);
544	struct musb *musb = glue_to_musb(glue);	527	struct musb *musb = glue_to_musb(glue);
545		528
546	if (is_host_active(musb))	529	if (is_host_active(musb))
547	/*	530	/*
548	* During hibernate gpio_vrsel will change from high to low	531	* During hibernate gpio_vrsel will change from high to low
549	* low which will generate wakeup event resume the system	532	* low which will generate wakeup event resume the system
550	* immediately. Set it to 0 before hibernate to avoid this	533	* immediately. Set it to 0 before hibernate to avoid this
551	* wakeup event.	534	* wakeup event.
552	*/	535	*/
553	gpio_set_value(musb->config->gpio_vrsel, 0);	536	gpio_set_value(musb->config->gpio_vrsel, 0);
554		537
555	return 0;	538	return 0;
556	}	539	}
557		540
558	static int bfin_resume(struct device *dev)	541	static int bfin_resume(struct device *dev)
559	{	542	{
560	struct bfin_glue *glue = dev_get_drvdata(dev);	543	struct bfin_glue *glue = dev_get_drvdata(dev);
561	struct musb *musb = glue_to_musb(glue);	544	struct musb *musb = glue_to_musb(glue);
562		545
563	bfin_musb_reg_init(musb);	546	bfin_musb_reg_init(musb);
564		547
565	return 0;	548	return 0;
566	}	549	}
567		550
568	static struct dev_pm_ops bfin_pm_ops = {	551	static struct dev_pm_ops bfin_pm_ops = {
569	.suspend = bfin_suspend,	552	.suspend = bfin_suspend,
570	.resume = bfin_resume,	553	.resume = bfin_resume,
571	};	554	};
572		555
573	#define DEV_PM_OPS &bfin_pm_ops	556	#define DEV_PM_OPS &bfin_pm_ops
574	#else	557	#else
575	#define DEV_PM_OPS NULL	558	#define DEV_PM_OPS NULL
576	#endif	559	#endif
577		560
578	static struct platform_driver bfin_driver = {	561	static struct platform_driver bfin_driver = {
579	.probe = bfin_probe,	562	.probe = bfin_probe,
580	.remove = __exit_p(bfin_remove),	563	.remove = __exit_p(bfin_remove),
581	.driver = {	564	.driver = {
582	.name = "musb-blackfin",	565	.name = "musb-blackfin",
583	.pm = DEV_PM_OPS,	566	.pm = DEV_PM_OPS,
584	},	567	},
585	};	568	};
586		569
587	MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");	570	MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
588	MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");	571	MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
589	MODULE_LICENSE("GPL v2");	572	MODULE_LICENSE("GPL v2");
590		573
591	static int __init bfin_init(void)	574	static int __init bfin_init(void)
592	{	575	{
593	return platform_driver_register(&bfin_driver);	576	return platform_driver_register(&bfin_driver);
594	}	577	}
595	module_init(bfin_init);	578	module_init(bfin_init);
596		579
597	static void __exit bfin_exit(void)	580	static void __exit bfin_exit(void)
598	{	581	{
599	platform_driver_unregister(&bfin_driver);	582	platform_driver_unregister(&bfin_driver);
600	}	583	}

drivers/usb/musb/da8xx.c

Diff comments View file @ 032ec49

 /*
  * Texas Instruments DA8xx/OMAP-L1x "glue layer"
  *
  * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  *
  * Based on the DaVinci "glue layer" code.
  * Copyright (C) 2005-2006 by Texas Instruments
  *
  * This file is part of the Inventra Controller Driver for Linux.
  *
  * The Inventra Controller Driver for Linux is free software; you
  * can redistribute it and/or modify it under the terms of the GNU
  * General Public License version 2 as published by the Free Software
  * Foundation.
  *
  * The Inventra Controller Driver for Linux is distributed in
  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  * without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  * License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with The Inventra Controller Driver for Linux ; if not,
  * write to the Free Software Foundation, Inc., 59 Temple Place,
  * Suite 330, Boston, MA  02111-1307  USA
  *
  */
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <mach/da8xx.h>
 #include <mach/usb.h>
 #include "musb_core.h"
 /*
  * DA8XX specific definitions
  */
 /* USB 2.0 OTG module registers */
 #define DA8XX_USB_REVISION_REG	0x00
 #define DA8XX_USB_CTRL_REG	0x04
 #define DA8XX_USB_STAT_REG	0x08
 #define DA8XX_USB_EMULATION_REG 0x0c
 #define DA8XX_USB_MODE_REG	0x10	/* Transparent, CDC, [Generic] RNDIS */
 #define DA8XX_USB_AUTOREQ_REG	0x14
 #define DA8XX_USB_SRP_FIX_TIME_REG 0x18
 #define DA8XX_USB_TEARDOWN_REG	0x1c
 #define DA8XX_USB_INTR_SRC_REG	0x20
 #define DA8XX_USB_INTR_SRC_SET_REG 0x24
 #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
 #define DA8XX_USB_INTR_MASK_REG 0x2c
 #define DA8XX_USB_INTR_MASK_SET_REG 0x30
 #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
 #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
 #define DA8XX_USB_END_OF_INTR_REG 0x3c
 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
 /* Control register bits */
 #define DA8XX_SOFT_RESET_MASK	1
 #define DA8XX_USB_TX_EP_MASK	0x1f		/* EP0 + 4 Tx EPs */
 #define DA8XX_USB_RX_EP_MASK	0x1e		/* 4 Rx EPs */
 /* USB interrupt register bits */
 #define DA8XX_INTR_USB_SHIFT	16
 #define DA8XX_INTR_USB_MASK	(0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
 					/* interrupts and DRVVBUS interrupt */
 #define DA8XX_INTR_DRVVBUS	0x100
 #define DA8XX_INTR_RX_SHIFT	8
 #define DA8XX_INTR_RX_MASK	(DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
 #define DA8XX_INTR_TX_SHIFT	0
 #define DA8XX_INTR_TX_MASK	(DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
 #define DA8XX_MENTOR_CORE_OFFSET 0x400
 #define CFGCHIP2	IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
 struct da8xx_glue {
 	struct device		*dev;
 	struct platform_device	*musb;
 	struct clk		*clk;
 };
 /*
  * REVISIT (PM): we should be able to keep the PHY in low power mode most
  * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
  * and, when in host mode, autosuspending idle root ports... PHY_PLLON
  * (overriding SUSPENDM?) then likely needs to stay off.
  */
 static inline void phy_on(void)
 {
 	u32 cfgchip2 = __raw_readl(CFGCHIP2);
 	/*
 	 * Start the on-chip PHY and its PLL.
 	 */
 	cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
 	cfgchip2 |= CFGCHIP2_PHY_PLLON;
 	__raw_writel(cfgchip2, CFGCHIP2);
 	pr_info("Waiting for USB PHY clock good...\n");
 	while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
 		cpu_relax();
 }
 static inline void phy_off(void)
 {
 	u32 cfgchip2 = __raw_readl(CFGCHIP2);
 	/*
 	 * Ensure that USB 1.1 reference clock is not being sourced from
 	 * USB 2.0 PHY.  Otherwise do not power down the PHY.
 	 */
 	if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
 	     (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
 		pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
 			   "can't power it down\n");
 		return;
 	}
 	/*
 	 * Power down the on-chip PHY.
 	 */
 	cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
 	__raw_writel(cfgchip2, CFGCHIP2);
 }
 /*
  * Because we don't set CTRL.UINT, it's "important" to:
  *	- not read/write INTRUSB/INTRUSBE (except during
  *	  initial setup, as a workaround);
  *	- use INTSET/INTCLR instead.
  */
 /**
  * da8xx_musb_enable - enable interrupts
  */
 static void da8xx_musb_enable(struct musb *musb)
 {
 	void __iomem *reg_base = musb->ctrl_base;
 	u32 mask;
 	/* Workaround: setup IRQs through both register sets. */
 	mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
 	       ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
 	       DA8XX_INTR_USB_MASK;
 	musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
 	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
-	if (is_otg_enabled(musb))
+	musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
-		musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
+			DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
-			    DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
 }
 /**
  * da8xx_musb_disable - disable HDRC and flush interrupts
  */
 static void da8xx_musb_disable(struct musb *musb)
 {
 	void __iomem *reg_base = musb->ctrl_base;
 	musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
 		    DA8XX_INTR_USB_MASK |
 		    DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
 	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 	musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
 }
 #define portstate(stmt)		stmt
 static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
 {
 	WARN_ON(is_on && is_peripheral_active(musb));
 }
 #define	POLL_SECONDS	2
 static struct timer_list otg_workaround;
 static void otg_timer(unsigned long _musb)
 {
 	struct musb		*musb = (void *)_musb;
 	void __iomem		*mregs = musb->mregs;
 	u8			devctl;
 	unsigned long		flags;
 	/*
 	 * We poll because DaVinci's won't expose several OTG-critical
 	 * status change events (from the transceiver) otherwise.
 	 */
 	devctl = musb_readb(mregs, MUSB_DEVCTL);
 	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
 		otg_state_string(musb->xceiv->state));
 	spin_lock_irqsave(&musb->lock, flags);
 	switch (musb->xceiv->state) {
 	case OTG_STATE_A_WAIT_BCON:
 		devctl &= ~MUSB_DEVCTL_SESSION;
 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 		if (devctl & MUSB_DEVCTL_BDEVICE) {
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 			MUSB_DEV_MODE(musb);
 		} else {
 			musb->xceiv->state = OTG_STATE_A_IDLE;
 			MUSB_HST_MODE(musb);
 		}
 		break;
 	case OTG_STATE_A_WAIT_VFALL:
 		/*
 		 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
 		 * RTL seems to mis-handle session "start" otherwise (or in
 		 * our case "recover"), in routine "VBUS was valid by the time
 		 * VBUSERR got reported during enumeration" cases.
 		 */
 		if (devctl & MUSB_DEVCTL_VBUS) {
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 			break;
 		}
 		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 		musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
 			    MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
 		break;
 	case OTG_STATE_B_IDLE:
-		if (!is_peripheral_enabled(musb))
-			break;
 		/*
 		 * There's no ID-changed IRQ, so we have no good way to tell
 		 * when to switch to the A-Default state machine (by setting
 		 * the DEVCTL.Session bit).
 		 *
 		 * Workaround:  whenever we're in B_IDLE, try setting the
 		 * session flag every few seconds.  If it works, ID was
 		 * grounded and we're now in the A-Default state machine.
 		 *
 		 * NOTE: setting the session flag is _supposed_ to trigger
 		 * SRP but clearly it doesn't.
 		 */
 		musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
 		devctl = musb_readb(mregs, MUSB_DEVCTL);
 		if (devctl & MUSB_DEVCTL_BDEVICE)
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 		else
 			musb->xceiv->state = OTG_STATE_A_IDLE;
 		break;
 	default:
 		break;
 	}
 	spin_unlock_irqrestore(&musb->lock, flags);
 }
 static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
 {
 	static unsigned long last_timer;
-	if (!is_otg_enabled(musb))
-		return;
 	if (timeout == 0)
 		timeout = jiffies + msecs_to_jiffies(3);
 	/* Never idle if active, or when VBUS timeout is not set as host */
 	if (musb->is_active || (musb->a_wait_bcon == 0 &&
 				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
 		dev_dbg(musb->controller, "%s active, deleting timer\n",
 			otg_state_string(musb->xceiv->state));
 		del_timer(&otg_workaround);
 		last_timer = jiffies;
 		return;
 	}
 	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
 		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
 		return;
 	}
 	last_timer = timeout;
 	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
 		otg_state_string(musb->xceiv->state),
 		jiffies_to_msecs(timeout - jiffies));
 	mod_timer(&otg_workaround, timeout);
 }
 static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
 {
 	struct musb		*musb = hci;
 	void __iomem		*reg_base = musb->ctrl_base;
 	struct usb_otg		*otg = musb->xceiv->otg;
 	unsigned long		flags;
 	irqreturn_t		ret = IRQ_NONE;
 	u32			status;
 	spin_lock_irqsave(&musb->lock, flags);
 	/*
 	 * NOTE: DA8XX shadows the Mentor IRQs.  Don't manage them through
 	 * the Mentor registers (except for setup), use the TI ones and EOI.
 	 */
 	/* Acknowledge and handle non-CPPI interrupts */
 	status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
 	if (!status)
 		goto eoi;
 	musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
 	dev_dbg(musb->controller, "USB IRQ %08x\n", status);
 	musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
 	musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
 	musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
 	/*
 	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
 	 * DA8xx's missing ID change IRQ.  We need an ID change IRQ to
 	 * switch appropriately between halves of the OTG state machine.
 	 * Managing DEVCTL.Session per Mentor docs requires that we know its
 	 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
 	 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
 	 */
 	if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
 		int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
 		void __iomem *mregs = musb->mregs;
 		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
 		int err;
-		err = is_host_enabled(musb) && (musb->int_usb &
+		err = musb->int_usb & USB_INTR_VBUSERROR;
-						MUSB_INTR_VBUSERROR);
 		if (err) {
 			/*
 			 * The Mentor core doesn't debounce VBUS as needed
 			 * to cope with device connect current spikes. This
 			 * means it's not uncommon for bus-powered devices
 			 * to get VBUS errors during enumeration.
 			 *
 			 * This is a workaround, but newer RTL from Mentor
 			 * seems to allow a better one: "re"-starting sessions
 			 * without waiting for VBUS to stop registering in
 			 * devctl.
 			 */
 			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 			WARNING("VBUS error workaround (delay coming)\n");
-		} else if (is_host_enabled(musb) && drvvbus) {
+		} else if (drvvbus) {
 			MUSB_HST_MODE(musb);
 			otg->default_a = 1;
 			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
 			del_timer(&otg_workaround);
 		} else {
 			musb->is_active = 0;
 			MUSB_DEV_MODE(musb);
 			otg->default_a = 0;
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
 		}
 		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 				drvvbus ? "on" : "off",
 				otg_state_string(musb->xceiv->state),
 				err ? " ERROR" : "",
 				devctl);
 		ret = IRQ_HANDLED;
 	}
 	if (musb->int_tx || musb->int_rx || musb->int_usb)
 		ret |= musb_interrupt(musb);
  eoi:
 	/* EOI needs to be written for the IRQ to be re-asserted. */
 	if (ret == IRQ_HANDLED || status)
 		musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
 	/* Poll for ID change */
-	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
+	if (musb->xceiv->state == OTG_STATE_B_IDLE)
 		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return ret;
 }
 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
 {
 	u32 cfgchip2 = __raw_readl(CFGCHIP2);
 	cfgchip2 &= ~CFGCHIP2_OTGMODE;
 	switch (musb_mode) {
 	case MUSB_HOST:		/* Force VBUS valid, ID = 0 */
 		cfgchip2 |= CFGCHIP2_FORCE_HOST;
 		break;
 	case MUSB_PERIPHERAL:	/* Force VBUS valid, ID = 1 */
 		cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
 		break;
 	case MUSB_OTG:		/* Don't override the VBUS/ID comparators */
 		cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
 		break;
 	default:
 		dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
 	}
 	__raw_writel(cfgchip2, CFGCHIP2);
 	return 0;
 }
 static int da8xx_musb_init(struct musb *musb)
 {
 	void __iomem *reg_base = musb->ctrl_base;
 	u32 rev;
 	musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
 	/* Returns zero if e.g. not clocked */
 	rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
 	if (!rev)
 		goto fail;
 	usb_nop_xceiv_register();
 	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
 	if (IS_ERR_OR_NULL(musb->xceiv))
 		goto fail;
-	if (is_host_enabled(musb))
+	setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
-		setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
 	/* Reset the controller */
 	musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
 	/* Start the on-chip PHY and its PLL. */
 	phy_on();
 	msleep(5);
 	/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
 	pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
 		 rev, __raw_readl(CFGCHIP2),
 		 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
 	musb->isr = da8xx_musb_interrupt;
 	return 0;
 fail:
 	return -ENODEV;
 }
 static int da8xx_musb_exit(struct musb *musb)
 {
-	if (is_host_enabled(musb))
+	del_timer_sync(&otg_workaround);
-		del_timer_sync(&otg_workaround);
 	phy_off();
 	usb_put_phy(musb->xceiv);
 	usb_nop_xceiv_unregister();
 	return 0;
 }
 static const struct musb_platform_ops da8xx_ops = {
 	.init		= da8xx_musb_init,
 	.exit		= da8xx_musb_exit,
 	.enable		= da8xx_musb_enable,
 	.disable	= da8xx_musb_disable,
 	.set_mode	= da8xx_musb_set_mode,
 	.try_idle	= da8xx_musb_try_idle,
 	.set_vbus	= da8xx_musb_set_vbus,
 };
 static u64 da8xx_dmamask = DMA_BIT_MASK(32);
 static int __devinit da8xx_probe(struct platform_device *pdev)
 {
 	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
 	struct platform_device		*musb;
 	struct da8xx_glue		*glue;
 	struct clk			*clk;
 	int				ret = -ENOMEM;
 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 	if (!glue) {
 		dev_err(&pdev->dev, "failed to allocate glue context\n");
 		goto err0;
 	}
 	musb = platform_device_alloc("musb-hdrc", -1);
 	if (!musb) {
 		dev_err(&pdev->dev, "failed to allocate musb device\n");
 		goto err1;
 	}
 	clk = clk_get(&pdev->dev, "usb20");
 	if (IS_ERR(clk)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
 		ret = PTR_ERR(clk);
 		goto err2;
 	}
 	ret = clk_enable(clk);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to enable clock\n");
 		goto err3;
 	}
 	musb->dev.parent		= &pdev->dev;
 	musb->dev.dma_mask		= &da8xx_dmamask;
 	musb->dev.coherent_dma_mask	= da8xx_dmamask;
 	glue->dev			= &pdev->dev;
 	glue->musb			= musb;
 	glue->clk			= clk;
 	pdata->platform_ops		= &da8xx_ops;
 	platform_set_drvdata(pdev, glue);
 	ret = platform_device_add_resources(musb, pdev->resource,
 			pdev->num_resources);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add resources\n");
 		goto err4;
 	}
 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add platform_data\n");
 		goto err4;
 	}
 	ret = platform_device_add(musb);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register musb device\n");
 		goto err4;
 	}
 	return 0;
 err4:
 	clk_disable(clk);
 err3:
 	clk_put(clk);
 err2:
 	platform_device_put(musb);
 err1:
 	kfree(glue);
 err0:
 	return ret;
 }
 static int __devexit da8xx_remove(struct platform_device *pdev)
 {
 	struct da8xx_glue		*glue = platform_get_drvdata(pdev);
 	platform_device_del(glue->musb);
 	platform_device_put(glue->musb);
 	clk_disable(glue->clk);
 	clk_put(glue->clk);
 	kfree(glue);
 	return 0;
 }
 static struct platform_driver da8xx_driver = {
 	.probe		= da8xx_probe,
 	.remove		= __devexit_p(da8xx_remove),
 	.driver		= {
 		.name	= "musb-da8xx",
 	},
 };
 MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
 MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
 MODULE_LICENSE("GPL v2");
 static int __init da8xx_init(void)
 {
 	return platform_driver_register(&da8xx_driver);
 }
 module_init(da8xx_init);
 static void __exit da8xx_exit(void)
 {
 	platform_driver_unregister(&da8xx_driver);
 }
 module_exit(da8xx_exit);

drivers/usb/musb/davinci.c

Diff comments View file @ 032ec49

 /*
  * Copyright (C) 2005-2006 by Texas Instruments
  *
  * This file is part of the Inventra Controller Driver for Linux.
  *
  * The Inventra Controller Driver for Linux is free software; you
  * can redistribute it and/or modify it under the terms of the GNU
  * General Public License version 2 as published by the Free Software
  * Foundation.
  *
  * The Inventra Controller Driver for Linux is distributed in
  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  * without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  * License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with The Inventra Controller Driver for Linux ; if not,
  * write to the Free Software Foundation, Inc., 59 Temple Place,
  * Suite 330, Boston, MA  02111-1307  USA
  *
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <mach/cputype.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include "musb_core.h"
 #ifdef CONFIG_MACH_DAVINCI_EVM
 #define GPIO_nVBUS_DRV		160
 #endif
 #include "davinci.h"
 #include "cppi_dma.h"
 #define USB_PHY_CTRL	IO_ADDRESS(USBPHY_CTL_PADDR)
 #define DM355_DEEPSLEEP	IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
 struct davinci_glue {
 	struct device		*dev;
 	struct platform_device	*musb;
 	struct clk		*clk;
 };
 /* REVISIT (PM) we should be able to keep the PHY in low power mode most
  * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
  * and, when in host mode, autosuspending idle root ports... PHYPLLON
  * (overriding SUSPENDM?) then likely needs to stay off.
  */
 static inline void phy_on(void)
 {
 	u32	phy_ctrl = __raw_readl(USB_PHY_CTRL);
 	/* power everything up; start the on-chip PHY and its PLL */
 	phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
 	phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
 	__raw_writel(phy_ctrl, USB_PHY_CTRL);
 	/* wait for PLL to lock before proceeding */
 	while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
 		cpu_relax();
 }
 static inline void phy_off(void)
 {
 	u32	phy_ctrl = __raw_readl(USB_PHY_CTRL);
 	/* powerdown the on-chip PHY, its PLL, and the OTG block */
 	phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
 	phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
 	__raw_writel(phy_ctrl, USB_PHY_CTRL);
 }
 static int dma_off = 1;
 static void davinci_musb_enable(struct musb *musb)
 {
 	u32	tmp, old, val;
 	/* workaround:  setup irqs through both register sets */
 	tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
 			<< DAVINCI_USB_TXINT_SHIFT;
 	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
 	old = tmp;
 	tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
 			<< DAVINCI_USB_RXINT_SHIFT;
 	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
 	tmp |= old;
 	val = ~MUSB_INTR_SOF;
 	tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
 	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
 	if (is_dma_capable() && !dma_off)
 		printk(KERN_WARNING "%s %s: dma not reactivated\n",
 				__FILE__, __func__);
 	else
 		dma_off = 0;
 	/* force a DRVVBUS irq so we can start polling for ID change */
-	if (is_otg_enabled(musb))
+	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
-		musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
 			DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
 }
 /*
  * Disable the HDRC and flush interrupts
  */
 static void davinci_musb_disable(struct musb *musb)
 {
 	/* because we don't set CTRLR.UINT, "important" to:
 	 *  - not read/write INTRUSB/INTRUSBE
 	 *  - (except during initial setup, as workaround)
 	 *  - use INTSETR/INTCLRR instead
 	 */
 	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
 			  DAVINCI_USB_USBINT_MASK
 			| DAVINCI_USB_TXINT_MASK
 			| DAVINCI_USB_RXINT_MASK);
 	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 	musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
 	if (is_dma_capable() && !dma_off)
 		WARNING("dma still active\n");
 }
 #define	portstate(stmt)		stmt
 /*
  * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
  * which doesn't wire DRVVBUS to the FET that switches it.  Unclear
  * if that's a problem with the DM6446 chip or just with that board.
  *
  * In either case, the DM355 EVM automates DRVVBUS the normal way,
  * when J10 is out, and TI documents it as handling OTG.
  */
 #ifdef CONFIG_MACH_DAVINCI_EVM
 static int vbus_state = -1;
 /* I2C operations are always synchronous, and require a task context.
  * With unloaded systems, using the shared workqueue seems to suffice
  * to satisfy the 100msec A_WAIT_VRISE timeout...
  */
 static void evm_deferred_drvvbus(struct work_struct *ignored)
 {
 	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
 	vbus_state = !vbus_state;
 }
 #endif	/* EVM */
 static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate)
 {
 #ifdef CONFIG_MACH_DAVINCI_EVM
 	if (is_on)
 		is_on = 1;
 	if (vbus_state == is_on)
 		return;
 	vbus_state = !is_on;		/* 0/1 vs "-1 == unknown/init" */
 	if (machine_is_davinci_evm()) {
 		static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
 		if (immediate)
 			gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
 		else
 			schedule_work(&evm_vbus_work);
 	}
 	if (immediate)
 		vbus_state = is_on;
 #endif
 }
 static void davinci_musb_set_vbus(struct musb *musb, int is_on)
 {
 	WARN_ON(is_on && is_peripheral_active(musb));
 	davinci_musb_source_power(musb, is_on, 0);
 }
 #define	POLL_SECONDS	2
 static struct timer_list otg_workaround;
 static void otg_timer(unsigned long _musb)
 {
 	struct musb		*musb = (void *)_musb;
 	void __iomem		*mregs = musb->mregs;
 	u8			devctl;
 	unsigned long		flags;
 	/* We poll because DaVinci's won't expose several OTG-critical
 	* status change events (from the transceiver) otherwise.
 	 */
 	devctl = musb_readb(mregs, MUSB_DEVCTL);
 	dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
 		otg_state_string(musb->xceiv->state));
 	spin_lock_irqsave(&musb->lock, flags);
 	switch (musb->xceiv->state) {
 	case OTG_STATE_A_WAIT_VFALL:
 		/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
 		 * seems to mis-handle session "start" otherwise (or in our
 		 * case "recover"), in routine "VBUS was valid by the time
 		 * VBUSERR got reported during enumeration" cases.
 		 */
 		if (devctl & MUSB_DEVCTL_VBUS) {
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 			break;
 		}
 		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 		musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
 			MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
 		break;
 	case OTG_STATE_B_IDLE:
-		if (!is_peripheral_enabled(musb))
+		/*
-			break;
+		 * There's no ID-changed IRQ, so we have no good way to tell
-		/* There's no ID-changed IRQ, so we have no good way to tell
 		 * when to switch to the A-Default state machine (by setting
 		 * the DEVCTL.SESSION flag).
 		 *
 		 * Workaround:  whenever we're in B_IDLE, try setting the
 		 * session flag every few seconds.  If it works, ID was
 		 * grounded and we're now in the A-Default state machine.
 		 *
 		 * NOTE setting the session flag is _supposed_ to trigger
 		 * SRP, but clearly it doesn't.
 		 */
 		musb_writeb(mregs, MUSB_DEVCTL,
 				devctl | MUSB_DEVCTL_SESSION);
 		devctl = musb_readb(mregs, MUSB_DEVCTL);
 		if (devctl & MUSB_DEVCTL_BDEVICE)
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 		else
 			musb->xceiv->state = OTG_STATE_A_IDLE;
 		break;
 	default:
 		break;
 	}
 	spin_unlock_irqrestore(&musb->lock, flags);
 }
 static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
 {
 	unsigned long	flags;
 	irqreturn_t	retval = IRQ_NONE;
 	struct musb	*musb = __hci;
 	struct usb_otg	*otg = musb->xceiv->otg;
 	void __iomem	*tibase = musb->ctrl_base;
 	struct cppi	*cppi;
 	u32		tmp;
 	spin_lock_irqsave(&musb->lock, flags);
 	/* NOTE: DaVinci shadows the Mentor IRQs.  Don't manage them through
 	 * the Mentor registers (except for setup), use the TI ones and EOI.
 	 *
 	 * Docs describe irq "vector" registers associated with the CPPI and
 	 * USB EOI registers.  These hold a bitmask corresponding to the
 	 * current IRQ, not an irq handler address.  Would using those bits
 	 * resolve some of the races observed in this dispatch code??
 	 */
 	/* CPPI interrupts share the same IRQ line, but have their own
 	 * mask, state, "vector", and EOI registers.
 	 */
 	cppi = container_of(musb->dma_controller, struct cppi, controller);
 	if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
 		retval = cppi_interrupt(irq, __hci);
 	/* ack and handle non-CPPI interrupts */
 	tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
 	musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
 	dev_dbg(musb->controller, "IRQ %08x\n", tmp);
 	musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
 			>> DAVINCI_USB_RXINT_SHIFT;
 	musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
 			>> DAVINCI_USB_TXINT_SHIFT;
 	musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
 			>> DAVINCI_USB_USBINT_SHIFT;
 	/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
 	 * DaVinci's missing ID change IRQ.  We need an ID change IRQ to
 	 * switch appropriately between halves of the OTG state machine.
 	 * Managing DEVCTL.SESSION per Mentor docs requires we know its
 	 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
 	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
 	 */
 	if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
 		int	drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
 		void __iomem *mregs = musb->mregs;
 		u8	devctl = musb_readb(mregs, MUSB_DEVCTL);
 		int	err = musb->int_usb & MUSB_INTR_VBUSERROR;
-		err = is_host_enabled(musb)
+		err = musb->int_usb & MUSB_INTR_VBUSERROR;
-				&& (musb->int_usb & MUSB_INTR_VBUSERROR);
 		if (err) {
 			/* The Mentor core doesn't debounce VBUS as needed
 			 * to cope with device connect current spikes. This
 			 * means it's not uncommon for bus-powered devices
 			 * to get VBUS errors during enumeration.
 			 *
 			 * This is a workaround, but newer RTL from Mentor
 			 * seems to allow a better one: "re"starting sessions
 			 * without waiting (on EVM, a **long** time) for VBUS
 			 * to stop registering in devctl.
 			 */
 			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 			WARNING("VBUS error workaround (delay coming)\n");
-		} else if (is_host_enabled(musb) && drvvbus) {
+		} else if (drvvbus) {
 			MUSB_HST_MODE(musb);
 			otg->default_a = 1;
 			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
 			del_timer(&otg_workaround);
 		} else {
 			musb->is_active = 0;
 			MUSB_DEV_MODE(musb);
 			otg->default_a = 0;
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
 		}
 		/* NOTE:  this must complete poweron within 100 msec
 		 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
 		 */
 		davinci_musb_source_power(musb, drvvbus, 0);
 		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 				drvvbus ? "on" : "off",
 				otg_state_string(musb->xceiv->state),
 				err ? " ERROR" : "",
 				devctl);
 		retval = IRQ_HANDLED;
 	}
 	if (musb->int_tx || musb->int_rx || musb->int_usb)
 		retval |= musb_interrupt(musb);
 	/* irq stays asserted until EOI is written */
 	musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
 	/* poll for ID change */
-	if (is_otg_enabled(musb)
+	if (musb->xceiv->state == OTG_STATE_B_IDLE)
-			&& musb->xceiv->state == OTG_STATE_B_IDLE)
 		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return retval;
 }
 static int davinci_musb_set_mode(struct musb *musb, u8 mode)
 {
 	/* EVM can't do this (right?) */
 	return -EIO;
 }
 static int davinci_musb_init(struct musb *musb)
 {
 	void __iomem	*tibase = musb->ctrl_base;
 	u32		revision;
 	usb_nop_xceiv_register();
 	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
 	if (IS_ERR_OR_NULL(musb->xceiv))
 		goto unregister;
 	musb->mregs += DAVINCI_BASE_OFFSET;
 	/* returns zero if e.g. not clocked */
 	revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
 	if (revision == 0)
 		goto fail;
-	if (is_host_enabled(musb))
+	setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
-		setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
 	davinci_musb_source_power(musb, 0, 1);
 	/* dm355 EVM swaps D+/D- for signal integrity, and
 	 * is clocked from the main 24 MHz crystal.
 	 */
 	if (machine_is_davinci_dm355_evm()) {
 		u32	phy_ctrl = __raw_readl(USB_PHY_CTRL);
 		phy_ctrl &= ~(3 << 9);
 		phy_ctrl |= USBPHY_DATAPOL;
 		__raw_writel(phy_ctrl, USB_PHY_CTRL);
 	}
 	/* On dm355, the default-A state machine needs DRVVBUS control.
 	 * If we won't be a host, there's no need to turn it on.
 	 */
 	if (cpu_is_davinci_dm355()) {
 		u32	deepsleep = __raw_readl(DM355_DEEPSLEEP);
-		if (is_host_enabled(musb)) {
+		deepsleep &= ~DRVVBUS_FORCE;
-			deepsleep &= ~DRVVBUS_OVERRIDE;
-		} else {
-			deepsleep &= ~DRVVBUS_FORCE;
-			deepsleep |= DRVVBUS_OVERRIDE;
-		}
 		__raw_writel(deepsleep, DM355_DEEPSLEEP);
 	}
 	/* reset the controller */
 	musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
 	/* start the on-chip PHY and its PLL */
 	phy_on();
 	msleep(5);
 	/* NOTE:  irqs are in mixed mode, not bypass to pure-musb */
 	pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
 		revision, __raw_readl(USB_PHY_CTRL),
 		musb_readb(tibase, DAVINCI_USB_CTRL_REG));
 	musb->isr = davinci_musb_interrupt;
 	return 0;
 fail:
 	usb_put_phy(musb->xceiv);
 unregister:
 	usb_nop_xceiv_unregister();
 	return -ENODEV;
 }
 static int davinci_musb_exit(struct musb *musb)
 {
-	if (is_host_enabled(musb))
+	del_timer_sync(&otg_workaround);
-		del_timer_sync(&otg_workaround);
 	/* force VBUS off */
 	if (cpu_is_davinci_dm355()) {
 		u32	deepsleep = __raw_readl(DM355_DEEPSLEEP);
 		deepsleep &= ~DRVVBUS_FORCE;
 		deepsleep |= DRVVBUS_OVERRIDE;
 		__raw_writel(deepsleep, DM355_DEEPSLEEP);
 	}
 	davinci_musb_source_power(musb, 0 /*off*/, 1);
 	/* delay, to avoid problems with module reload */
-	if (is_host_enabled(musb) && musb->xceiv->otg->default_a) {
+	if (musb->xceiv->otg->default_a) {
 		int	maxdelay = 30;
 		u8	devctl, warn = 0;
 		/* if there's no peripheral connected, this can take a
 		 * long time to fall, especially on EVM with huge C133.
 		 */
 		do {
 			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 			if (!(devctl & MUSB_DEVCTL_VBUS))
 				break;
 			if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
 				warn = devctl & MUSB_DEVCTL_VBUS;
 				dev_dbg(musb->controller, "VBUS %d\n",
 					warn >> MUSB_DEVCTL_VBUS_SHIFT);
 			}
 			msleep(1000);
 			maxdelay--;
 		} while (maxdelay > 0);
 		/* in OTG mode, another host might be connected */
 		if (devctl & MUSB_DEVCTL_VBUS)
 			dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
 	}
 	phy_off();
 	usb_put_phy(musb->xceiv);
 	usb_nop_xceiv_unregister();
 	return 0;
 }
 static const struct musb_platform_ops davinci_ops = {
 	.init		= davinci_musb_init,
 	.exit		= davinci_musb_exit,
 	.enable		= davinci_musb_enable,
 	.disable	= davinci_musb_disable,
 	.set_mode	= davinci_musb_set_mode,
 	.set_vbus	= davinci_musb_set_vbus,
 };
 static u64 davinci_dmamask = DMA_BIT_MASK(32);
 static int __devinit davinci_probe(struct platform_device *pdev)
 {
 	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
 	struct platform_device		*musb;
 	struct davinci_glue		*glue;
 	struct clk			*clk;
 	int				ret = -ENOMEM;
 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 	if (!glue) {
 		dev_err(&pdev->dev, "failed to allocate glue context\n");
 		goto err0;
 	}
 	musb = platform_device_alloc("musb-hdrc", -1);
 	if (!musb) {
 		dev_err(&pdev->dev, "failed to allocate musb device\n");
 		goto err1;
 	}
 	clk = clk_get(&pdev->dev, "usb");
 	if (IS_ERR(clk)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
 		ret = PTR_ERR(clk);
 		goto err2;
 	}
 	ret = clk_enable(clk);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to enable clock\n");
 		goto err3;
 	}
 	musb->dev.parent		= &pdev->dev;
 	musb->dev.dma_mask		= &davinci_dmamask;
 	musb->dev.coherent_dma_mask	= davinci_dmamask;
 	glue->dev			= &pdev->dev;
 	glue->musb			= musb;
 	glue->clk			= clk;
 	pdata->platform_ops		= &davinci_ops;
 	platform_set_drvdata(pdev, glue);
 	ret = platform_device_add_resources(musb, pdev->resource,
 			pdev->num_resources);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add resources\n");
 		goto err4;
 	}
 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add platform_data\n");
 		goto err4;
 	}
 	ret = platform_device_add(musb);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register musb device\n");
 		goto err4;
 	}
 	return 0;
 err4:
 	clk_disable(clk);
 err3:
 	clk_put(clk);
 err2:
 	platform_device_put(musb);
 err1:
 	kfree(glue);
 err0:
 	return ret;
 }
 static int __devexit davinci_remove(struct platform_device *pdev)
 {
 	struct davinci_glue		*glue = platform_get_drvdata(pdev);
 	platform_device_del(glue->musb);
 	platform_device_put(glue->musb);
 	clk_disable(glue->clk);
 	clk_put(glue->clk);
 	kfree(glue);
 	return 0;
 }
 static struct platform_driver davinci_driver = {
 	.probe		= davinci_probe,
 	.remove		= __devexit_p(davinci_remove),
 	.driver		= {
 		.name	= "musb-davinci",
 	},
 };
 MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 MODULE_LICENSE("GPL v2");
 static int __init davinci_init(void)
 {
 	return platform_driver_register(&davinci_driver);
 }
 module_init(davinci_init);
 static void __exit davinci_exit(void)
 {
 	platform_driver_unregister(&davinci_driver);
 }
 module_exit(davinci_exit);

drivers/usb/musb/musb_core.c

Diff comments View file @ 032ec49

1	/*	1	/*
2	* MUSB OTG driver core code	2	* MUSB OTG driver core code
3	*	3	*
4	* Copyright 2005 Mentor Graphics Corporation	4	* Copyright 2005 Mentor Graphics Corporation
5	* Copyright (C) 2005-2006 by Texas Instruments	5	* Copyright (C) 2005-2006 by Texas Instruments
6	* Copyright (C) 2006-2007 Nokia Corporation	6	* Copyright (C) 2006-2007 Nokia Corporation
7	*	7	*
8	* This program is free software; you can redistribute it and/or	8	* This program is free software; you can redistribute it and/or
9	* modify it under the terms of the GNU General Public License	9	* modify it under the terms of the GNU General Public License
10	* version 2 as published by the Free Software Foundation.	10	* version 2 as published by the Free Software Foundation.
11	*	11	*
12	* This program is distributed in the hope that it will be useful, but	12	* This program is distributed in the hope that it will be useful, but
13	* WITHOUT ANY WARRANTY; without even the implied warranty of	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15	* General Public License for more details.	15	* General Public License for more details.
16	*	16	*
17	* You should have received a copy of the GNU General Public License	17	* You should have received a copy of the GNU General Public License
18	* along with this program; if not, write to the Free Software	18	* along with this program; if not, write to the Free Software
19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20	* 02110-1301 USA	20	* 02110-1301 USA
21	*	21	*
22	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED	22	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF	23	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN	24	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,	25	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	26	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF	27	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON	28	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	29	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	30	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	31	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32	*	32	*
33	*/	33	*/
34		34
35	/*	35	/*
36	* Inventra (Multipoint) Dual-Role Controller Driver for Linux.	36	* Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37	*	37	*
38	* This consists of a Host Controller Driver (HCD) and a peripheral	38	* This consists of a Host Controller Driver (HCD) and a peripheral
39	* controller driver implementing the "Gadget" API; OTG support is	39	* controller driver implementing the "Gadget" API; OTG support is
40	* in the works. These are normal Linux-USB controller drivers which	40	* in the works. These are normal Linux-USB controller drivers which
41	* use IRQs and have no dedicated thread.	41	* use IRQs and have no dedicated thread.
42	*	42	*
43	* This version of the driver has only been used with products from	43	* This version of the driver has only been used with products from
44	* Texas Instruments. Those products integrate the Inventra logic	44	* Texas Instruments. Those products integrate the Inventra logic
45	* with other DMA, IRQ, and bus modules, as well as other logic that	45	* with other DMA, IRQ, and bus modules, as well as other logic that
46	* needs to be reflected in this driver.	46	* needs to be reflected in this driver.
47	*	47	*
48	*	48	*
49	* NOTE: the original Mentor code here was pretty much a collection	49	* NOTE: the original Mentor code here was pretty much a collection
50	* of mechanisms that don't seem to have been fully integrated/working	50	* of mechanisms that don't seem to have been fully integrated/working
51	* for any Linux kernel version. This version aims at Linux 2.6.now,	51	* for any Linux kernel version. This version aims at Linux 2.6.now,
52	* Key open issues include:	52	* Key open issues include:
53	*	53	*
54	* - Lack of host-side transaction scheduling, for all transfer types.	54	* - Lack of host-side transaction scheduling, for all transfer types.
55	* The hardware doesn't do it; instead, software must.	55	* The hardware doesn't do it; instead, software must.
56	*	56	*
57	* This is not an issue for OTG devices that don't support external	57	* This is not an issue for OTG devices that don't support external
58	* hubs, but for more "normal" USB hosts it's a user issue that the	58	* hubs, but for more "normal" USB hosts it's a user issue that the
59	* "multipoint" support doesn't scale in the expected ways. That	59	* "multipoint" support doesn't scale in the expected ways. That
60	* includes DaVinci EVM in a common non-OTG mode.	60	* includes DaVinci EVM in a common non-OTG mode.
61	*	61	*
62	* * Control and bulk use dedicated endpoints, and there's as	62	* * Control and bulk use dedicated endpoints, and there's as
63	* yet no mechanism to either (a) reclaim the hardware when	63	* yet no mechanism to either (a) reclaim the hardware when
64	* peripherals are NAKing, which gets complicated with bulk	64	* peripherals are NAKing, which gets complicated with bulk
65	* endpoints, or (b) use more than a single bulk endpoint in	65	* endpoints, or (b) use more than a single bulk endpoint in
66	* each direction.	66	* each direction.
67	*	67	*
68	* RESULT: one device may be perceived as blocking another one.	68	* RESULT: one device may be perceived as blocking another one.
69	*	69	*
70	* * Interrupt and isochronous will dynamically allocate endpoint	70	* * Interrupt and isochronous will dynamically allocate endpoint
71	* hardware, but (a) there's no record keeping for bandwidth;	71	* hardware, but (a) there's no record keeping for bandwidth;
72	* (b) in the common case that few endpoints are available, there	72	* (b) in the common case that few endpoints are available, there
73	* is no mechanism to reuse endpoints to talk to multiple devices.	73	* is no mechanism to reuse endpoints to talk to multiple devices.
74	*	74	*
75	* RESULT: At one extreme, bandwidth can be overcommitted in	75	* RESULT: At one extreme, bandwidth can be overcommitted in
76	* some hardware configurations, no faults will be reported.	76	* some hardware configurations, no faults will be reported.
77	* At the other extreme, the bandwidth capabilities which do	77	* At the other extreme, the bandwidth capabilities which do
78	* exist tend to be severely undercommitted. You can't yet hook	78	* exist tend to be severely undercommitted. You can't yet hook
79	* up both a keyboard and a mouse to an external USB hub.	79	* up both a keyboard and a mouse to an external USB hub.
80	*/	80	*/
81		81
82	/*	82	/*
83	* This gets many kinds of configuration information:	83	* This gets many kinds of configuration information:
84	* - Kconfig for everything user-configurable	84	* - Kconfig for everything user-configurable
85	* - platform_device for addressing, irq, and platform_data	85	* - platform_device for addressing, irq, and platform_data
86	* - platform_data is mostly for board-specific informarion	86	* - platform_data is mostly for board-specific informarion
87	* (plus recentrly, SOC or family details)	87	* (plus recentrly, SOC or family details)
88	*	88	*
89	* Most of the conditional compilation will (someday) vanish.	89	* Most of the conditional compilation will (someday) vanish.
90	*/	90	*/
91		91
92	#include <linux/module.h>	92	#include <linux/module.h>
93	#include <linux/kernel.h>	93	#include <linux/kernel.h>
94	#include <linux/sched.h>	94	#include <linux/sched.h>
95	#include <linux/slab.h>	95	#include <linux/slab.h>
96	#include <linux/init.h>	96	#include <linux/init.h>
97	#include <linux/list.h>	97	#include <linux/list.h>
98	#include <linux/kobject.h>	98	#include <linux/kobject.h>
99	#include <linux/prefetch.h>	99	#include <linux/prefetch.h>
100	#include <linux/platform_device.h>	100	#include <linux/platform_device.h>
101	#include <linux/io.h>	101	#include <linux/io.h>
102		102
103	#include "musb_core.h"	103	#include "musb_core.h"
104		104
105	#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)	105	#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106		106
107		107
108	#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"	108	#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109	#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"	109	#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110		110
111	#define MUSB_VERSION "6.0"	111	#define MUSB_VERSION "6.0"
112		112
113	#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION	113	#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114		114
115	#define MUSB_DRIVER_NAME "musb-hdrc"	115	#define MUSB_DRIVER_NAME "musb-hdrc"
116	const char musb_driver_name[] = MUSB_DRIVER_NAME;	116	const char musb_driver_name[] = MUSB_DRIVER_NAME;
117		117
118	MODULE_DESCRIPTION(DRIVER_INFO);	118	MODULE_DESCRIPTION(DRIVER_INFO);
119	MODULE_AUTHOR(DRIVER_AUTHOR);	119	MODULE_AUTHOR(DRIVER_AUTHOR);
120	MODULE_LICENSE("GPL");	120	MODULE_LICENSE("GPL");
121	MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);	121	MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122		122
123		123
124	/-------------------------------------------------------------------------/	124	/-------------------------------------------------------------------------/
125		125
126	static inline struct musb dev_to_musb(struct device dev)	126	static inline struct musb dev_to_musb(struct device dev)
127	{	127	{
128	return dev_get_drvdata(dev);	128	return dev_get_drvdata(dev);
129	}	129	}
130		130
131	/-------------------------------------------------------------------------/	131	/-------------------------------------------------------------------------/
132		132
133	#ifndef CONFIG_BLACKFIN	133	#ifndef CONFIG_BLACKFIN
134	static int musb_ulpi_read(struct usb_phy *phy, u32 offset)	134	static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135	{	135	{
136	void __iomem *addr = phy->io_priv;	136	void __iomem *addr = phy->io_priv;
137	int i = 0;	137	int i = 0;
138	u8 r;	138	u8 r;
139	u8 power;	139	u8 power;
140	int ret;	140	int ret;
141		141
142	pm_runtime_get_sync(phy->io_dev);	142	pm_runtime_get_sync(phy->io_dev);
143		143
144	/* Make sure the transceiver is not in low power mode */	144	/* Make sure the transceiver is not in low power mode */
145	power = musb_readb(addr, MUSB_POWER);	145	power = musb_readb(addr, MUSB_POWER);
146	power &= ~MUSB_POWER_SUSPENDM;	146	power &= ~MUSB_POWER_SUSPENDM;
147	musb_writeb(addr, MUSB_POWER, power);	147	musb_writeb(addr, MUSB_POWER, power);
148		148
149	/* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the	149	/* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150	* ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.	150	* ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151	*/	151	*/
152		152
153	musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);	153	musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154	musb_writeb(addr, MUSB_ULPI_REG_CONTROL,	154	musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155	MUSB_ULPI_REG_REQ \| MUSB_ULPI_RDN_WR);	155	MUSB_ULPI_REG_REQ \| MUSB_ULPI_RDN_WR);
156		156
157	while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)	157	while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158	& MUSB_ULPI_REG_CMPLT)) {	158	& MUSB_ULPI_REG_CMPLT)) {
159	i++;	159	i++;
160	if (i == 10000) {	160	if (i == 10000) {
161	ret = -ETIMEDOUT;	161	ret = -ETIMEDOUT;
162	goto out;	162	goto out;
163	}	163	}
164		164
165	}	165	}
166	r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);	166	r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167	r &= ~MUSB_ULPI_REG_CMPLT;	167	r &= ~MUSB_ULPI_REG_CMPLT;
168	musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);	168	musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169		169
170	ret = musb_readb(addr, MUSB_ULPI_REG_DATA);	170	ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171		171
172	out:	172	out:
173	pm_runtime_put(phy->io_dev);	173	pm_runtime_put(phy->io_dev);
174		174
175	return ret;	175	return ret;
176	}	176	}
177		177
178	static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)	178	static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179	{	179	{
180	void __iomem *addr = phy->io_priv;	180	void __iomem *addr = phy->io_priv;
181	int i = 0;	181	int i = 0;
182	u8 r = 0;	182	u8 r = 0;
183	u8 power;	183	u8 power;
184	int ret = 0;	184	int ret = 0;
185		185
186	pm_runtime_get_sync(phy->io_dev);	186	pm_runtime_get_sync(phy->io_dev);
187		187
188	/* Make sure the transceiver is not in low power mode */	188	/* Make sure the transceiver is not in low power mode */
189	power = musb_readb(addr, MUSB_POWER);	189	power = musb_readb(addr, MUSB_POWER);
190	power &= ~MUSB_POWER_SUSPENDM;	190	power &= ~MUSB_POWER_SUSPENDM;
191	musb_writeb(addr, MUSB_POWER, power);	191	musb_writeb(addr, MUSB_POWER, power);
192		192
193	musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);	193	musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194	musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);	194	musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195	musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);	195	musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196		196
197	while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)	197	while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198	& MUSB_ULPI_REG_CMPLT)) {	198	& MUSB_ULPI_REG_CMPLT)) {
199	i++;	199	i++;
200	if (i == 10000) {	200	if (i == 10000) {
201	ret = -ETIMEDOUT;	201	ret = -ETIMEDOUT;
202	goto out;	202	goto out;
203	}	203	}
204	}	204	}
205		205
206	r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);	206	r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207	r &= ~MUSB_ULPI_REG_CMPLT;	207	r &= ~MUSB_ULPI_REG_CMPLT;
208	musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);	208	musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209		209
210	out:	210	out:
211	pm_runtime_put(phy->io_dev);	211	pm_runtime_put(phy->io_dev);
212		212
213	return ret;	213	return ret;
214	}	214	}
215	#else	215	#else
216	#define musb_ulpi_read NULL	216	#define musb_ulpi_read NULL
217	#define musb_ulpi_write NULL	217	#define musb_ulpi_write NULL
218	#endif	218	#endif
219		219
220	static struct usb_phy_io_ops musb_ulpi_access = {	220	static struct usb_phy_io_ops musb_ulpi_access = {
221	.read = musb_ulpi_read,	221	.read = musb_ulpi_read,
222	.write = musb_ulpi_write,	222	.write = musb_ulpi_write,
223	};	223	};
224		224
225	/-------------------------------------------------------------------------/	225	/-------------------------------------------------------------------------/
226		226
227	#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)	227	#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
228		228
229	/*	229	/*
230	* Load an endpoint's FIFO	230	* Load an endpoint's FIFO
231	*/	231	*/
232	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)	232	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
233	{	233	{
234	struct musb *musb = hw_ep->musb;	234	struct musb *musb = hw_ep->musb;
235	void __iomem *fifo = hw_ep->fifo;	235	void __iomem *fifo = hw_ep->fifo;
236		236
237	if (unlikely(len == 0))	237	if (unlikely(len == 0))
238	return;	238	return;
239		239
240	prefetch((u8 *)src);	240	prefetch((u8 *)src);
241		241
242	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",	242	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
243	'T', hw_ep->epnum, fifo, len, src);	243	'T', hw_ep->epnum, fifo, len, src);
244		244
245	/* we can't assume unaligned reads work */	245	/* we can't assume unaligned reads work */
246	if (likely((0x01 & (unsigned long) src) == 0)) {	246	if (likely((0x01 & (unsigned long) src) == 0)) {
247	u16 index = 0;	247	u16 index = 0;
248		248
249	/* best case is 32bit-aligned source address */	249	/* best case is 32bit-aligned source address */
250	if ((0x02 & (unsigned long) src) == 0) {	250	if ((0x02 & (unsigned long) src) == 0) {
251	if (len >= 4) {	251	if (len >= 4) {
252	writesl(fifo, src + index, len >> 2);	252	writesl(fifo, src + index, len >> 2);
253	index += len & ~0x03;	253	index += len & ~0x03;
254	}	254	}
255	if (len & 0x02) {	255	if (len & 0x02) {
256	musb_writew(fifo, 0, (u16 )&src[index]);	256	musb_writew(fifo, 0, (u16 )&src[index]);
257	index += 2;	257	index += 2;
258	}	258	}
259	} else {	259	} else {
260	if (len >= 2) {	260	if (len >= 2) {
261	writesw(fifo, src + index, len >> 1);	261	writesw(fifo, src + index, len >> 1);
262	index += len & ~0x01;	262	index += len & ~0x01;
263	}	263	}
264	}	264	}
265	if (len & 0x01)	265	if (len & 0x01)
266	musb_writeb(fifo, 0, src[index]);	266	musb_writeb(fifo, 0, src[index]);
267	} else {	267	} else {
268	/* byte aligned */	268	/* byte aligned */
269	writesb(fifo, src, len);	269	writesb(fifo, src, len);
270	}	270	}
271	}	271	}
272		272
273	#if !defined(CONFIG_USB_MUSB_AM35X)	273	#if !defined(CONFIG_USB_MUSB_AM35X)
274	/*	274	/*
275	* Unload an endpoint's FIFO	275	* Unload an endpoint's FIFO
276	*/	276	*/
277	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)	277	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
278	{	278	{
279	struct musb *musb = hw_ep->musb;	279	struct musb *musb = hw_ep->musb;
280	void __iomem *fifo = hw_ep->fifo;	280	void __iomem *fifo = hw_ep->fifo;
281		281
282	if (unlikely(len == 0))	282	if (unlikely(len == 0))
283	return;	283	return;
284		284
285	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",	285	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
286	'R', hw_ep->epnum, fifo, len, dst);	286	'R', hw_ep->epnum, fifo, len, dst);
287		287
288	/* we can't assume unaligned writes work */	288	/* we can't assume unaligned writes work */
289	if (likely((0x01 & (unsigned long) dst) == 0)) {	289	if (likely((0x01 & (unsigned long) dst) == 0)) {
290	u16 index = 0;	290	u16 index = 0;
291		291
292	/* best case is 32bit-aligned destination address */	292	/* best case is 32bit-aligned destination address */
293	if ((0x02 & (unsigned long) dst) == 0) {	293	if ((0x02 & (unsigned long) dst) == 0) {
294	if (len >= 4) {	294	if (len >= 4) {
295	readsl(fifo, dst, len >> 2);	295	readsl(fifo, dst, len >> 2);
296	index = len & ~0x03;	296	index = len & ~0x03;
297	}	297	}
298	if (len & 0x02) {	298	if (len & 0x02) {
299	(u16 )&dst[index] = musb_readw(fifo, 0);	299	(u16 )&dst[index] = musb_readw(fifo, 0);
300	index += 2;	300	index += 2;
301	}	301	}
302	} else {	302	} else {
303	if (len >= 2) {	303	if (len >= 2) {
304	readsw(fifo, dst, len >> 1);	304	readsw(fifo, dst, len >> 1);
305	index = len & ~0x01;	305	index = len & ~0x01;
306	}	306	}
307	}	307	}
308	if (len & 0x01)	308	if (len & 0x01)
309	dst[index] = musb_readb(fifo, 0);	309	dst[index] = musb_readb(fifo, 0);
310	} else {	310	} else {
311	/* byte aligned */	311	/* byte aligned */
312	readsb(fifo, dst, len);	312	readsb(fifo, dst, len);
313	}	313	}
314	}	314	}
315	#endif	315	#endif
316		316
317	#endif /* normal PIO */	317	#endif /* normal PIO */
318		318
319		319
320	/-------------------------------------------------------------------------/	320	/-------------------------------------------------------------------------/
321		321
322	/* for high speed test mode; see USB 2.0 spec 7.1.20 */	322	/* for high speed test mode; see USB 2.0 spec 7.1.20 */
323	static const u8 musb_test_packet[53] = {	323	static const u8 musb_test_packet[53] = {
324	/* implicit SYNC then DATA0 to start */	324	/* implicit SYNC then DATA0 to start */
325		325
326	/* JKJKJKJK x9 */	326	/* JKJKJKJK x9 */
327	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	327	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
328	/* JJKKJJKK x8 */	328	/* JJKKJJKK x8 */
329	0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,	329	0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
330	/* JJJJKKKK x8 */	330	/* JJJJKKKK x8 */
331	0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,	331	0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
332	/* JJJJJJJKKKKKKK x8 */	332	/* JJJJJJJKKKKKKK x8 */
333	0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	333	0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
334	/* JJJJJJJK x8 */	334	/* JJJJJJJK x8 */
335	0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,	335	0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
336	/* JKKKKKKK x10, JK */	336	/* JKKKKKKK x10, JK */
337	0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e	337	0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
338		338
339	/* implicit CRC16 then EOP to end */	339	/* implicit CRC16 then EOP to end */
340	};	340	};
341		341
342	void musb_load_testpacket(struct musb *musb)	342	void musb_load_testpacket(struct musb *musb)
343	{	343	{
344	void __iomem *regs = musb->endpoints[0].regs;	344	void __iomem *regs = musb->endpoints[0].regs;
345		345
346	musb_ep_select(musb->mregs, 0);	346	musb_ep_select(musb->mregs, 0);
347	musb_write_fifo(musb->control_ep,	347	musb_write_fifo(musb->control_ep,
348	sizeof(musb_test_packet), musb_test_packet);	348	sizeof(musb_test_packet), musb_test_packet);
349	musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);	349	musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
350	}	350	}
351		351
352	/-------------------------------------------------------------------------/	352	/-------------------------------------------------------------------------/
353		353
354	/*	354	/*
355	* Handles OTG hnp timeouts, such as b_ase0_brst	355	* Handles OTG hnp timeouts, such as b_ase0_brst
356	*/	356	*/
357	static void musb_otg_timer_func(unsigned long data)	357	static void musb_otg_timer_func(unsigned long data)
358	{	358	{
359	struct musb musb = (struct musb )data;	359	struct musb musb = (struct musb )data;
360	unsigned long flags;	360	unsigned long flags;
361		361
362	spin_lock_irqsave(&musb->lock, flags);	362	spin_lock_irqsave(&musb->lock, flags);
363	switch (musb->xceiv->state) {	363	switch (musb->xceiv->state) {
364	case OTG_STATE_B_WAIT_ACON:	364	case OTG_STATE_B_WAIT_ACON:
365	dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");	365	dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
366	musb_g_disconnect(musb);	366	musb_g_disconnect(musb);
367	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;	367	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
368	musb->is_active = 0;	368	musb->is_active = 0;
369	break;	369	break;
370	case OTG_STATE_A_SUSPEND:	370	case OTG_STATE_A_SUSPEND:
371	case OTG_STATE_A_WAIT_BCON:	371	case OTG_STATE_A_WAIT_BCON:
372	dev_dbg(musb->controller, "HNP: %s timeout\n",	372	dev_dbg(musb->controller, "HNP: %s timeout\n",
373	otg_state_string(musb->xceiv->state));	373	otg_state_string(musb->xceiv->state));
374	musb_platform_set_vbus(musb, 0);	374	musb_platform_set_vbus(musb, 0);
375	musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;	375	musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
376	break;	376	break;
377	default:	377	default:
378	dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",	378	dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
379	otg_state_string(musb->xceiv->state));	379	otg_state_string(musb->xceiv->state));
380	}	380	}
381	musb->ignore_disconnect = 0;	381	musb->ignore_disconnect = 0;
382	spin_unlock_irqrestore(&musb->lock, flags);	382	spin_unlock_irqrestore(&musb->lock, flags);
383	}	383	}
384		384
385	/*	385	/*
386	* Stops the HNP transition. Caller must take care of locking.	386	* Stops the HNP transition. Caller must take care of locking.
387	*/	387	*/
388	void musb_hnp_stop(struct musb *musb)	388	void musb_hnp_stop(struct musb *musb)
389	{	389	{
390	struct usb_hcd *hcd = musb_to_hcd(musb);	390	struct usb_hcd *hcd = musb_to_hcd(musb);
391	void __iomem *mbase = musb->mregs;	391	void __iomem *mbase = musb->mregs;
392	u8 reg;	392	u8 reg;
393		393
394	dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));	394	dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
395		395
396	switch (musb->xceiv->state) {	396	switch (musb->xceiv->state) {
397	case OTG_STATE_A_PERIPHERAL:	397	case OTG_STATE_A_PERIPHERAL:
398	musb_g_disconnect(musb);	398	musb_g_disconnect(musb);
399	dev_dbg(musb->controller, "HNP: back to %s\n",	399	dev_dbg(musb->controller, "HNP: back to %s\n",
400	otg_state_string(musb->xceiv->state));	400	otg_state_string(musb->xceiv->state));
401	break;	401	break;
402	case OTG_STATE_B_HOST:	402	case OTG_STATE_B_HOST:
403	dev_dbg(musb->controller, "HNP: Disabling HR\n");	403	dev_dbg(musb->controller, "HNP: Disabling HR\n");
404	hcd->self.is_b_host = 0;	404	hcd->self.is_b_host = 0;
405	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;	405	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
406	MUSB_DEV_MODE(musb);	406	MUSB_DEV_MODE(musb);
407	reg = musb_readb(mbase, MUSB_POWER);	407	reg = musb_readb(mbase, MUSB_POWER);
408	reg \|= MUSB_POWER_SUSPENDM;	408	reg \|= MUSB_POWER_SUSPENDM;
409	musb_writeb(mbase, MUSB_POWER, reg);	409	musb_writeb(mbase, MUSB_POWER, reg);
410	/* REVISIT: Start SESSION_REQUEST here? */	410	/* REVISIT: Start SESSION_REQUEST here? */
411	break;	411	break;
412	default:	412	default:
413	dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",	413	dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
414	otg_state_string(musb->xceiv->state));	414	otg_state_string(musb->xceiv->state));
415	}	415	}
416		416
417	/*	417	/*
418	* When returning to A state after HNP, avoid hub_port_rebounce(),	418	* When returning to A state after HNP, avoid hub_port_rebounce(),
419	* which cause occasional OPT A "Did not receive reset after connect"	419	* which cause occasional OPT A "Did not receive reset after connect"
420	* errors.	420	* errors.
421	*/	421	*/
422	musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);	422	musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
423	}	423	}
424		424
425	/*	425	/*
426	* Interrupt Service Routine to record USB "global" interrupts.	426	* Interrupt Service Routine to record USB "global" interrupts.
427	* Since these do not happen often and signify things of	427	* Since these do not happen often and signify things of
428	* paramount importance, it seems OK to check them individually;	428	* paramount importance, it seems OK to check them individually;
429	* the order of the tests is specified in the manual	429	* the order of the tests is specified in the manual
430	*	430	*
431	* @param musb instance pointer	431	* @param musb instance pointer
432	* @param int_usb register contents	432	* @param int_usb register contents
433	* @param devctl	433	* @param devctl
434	* @param power	434	* @param power
435	*/	435	*/
436		436
437	static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,	437	static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
438	u8 devctl, u8 power)	438	u8 devctl, u8 power)
439	{	439	{
440	struct usb_otg *otg = musb->xceiv->otg;	440	struct usb_otg *otg = musb->xceiv->otg;
441	irqreturn_t handled = IRQ_NONE;	441	irqreturn_t handled = IRQ_NONE;
442		442
443	dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,	443	dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
444	int_usb);	444	int_usb);
445		445
446	/* in host mode, the peripheral may issue remote wakeup.	446	/* in host mode, the peripheral may issue remote wakeup.
447	* in peripheral mode, the host may resume the link.	447	* in peripheral mode, the host may resume the link.
448	* spurious RESUME irqs happen too, paired with SUSPEND.	448	* spurious RESUME irqs happen too, paired with SUSPEND.
449	*/	449	*/
450	if (int_usb & MUSB_INTR_RESUME) {	450	if (int_usb & MUSB_INTR_RESUME) {
451	handled = IRQ_HANDLED;	451	handled = IRQ_HANDLED;
452	dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));	452	dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
453		453
454	if (devctl & MUSB_DEVCTL_HM) {	454	if (devctl & MUSB_DEVCTL_HM) {
455	void __iomem *mbase = musb->mregs;	455	void __iomem *mbase = musb->mregs;
456		456
457	switch (musb->xceiv->state) {	457	switch (musb->xceiv->state) {
458	case OTG_STATE_A_SUSPEND:	458	case OTG_STATE_A_SUSPEND:
459	/* remote wakeup? later, GetPortStatus	459	/* remote wakeup? later, GetPortStatus
460	* will stop RESUME signaling	460	* will stop RESUME signaling
461	*/	461	*/
462		462
463	if (power & MUSB_POWER_SUSPENDM) {	463	if (power & MUSB_POWER_SUSPENDM) {
464	/* spurious */	464	/* spurious */
465	musb->int_usb &= ~MUSB_INTR_SUSPEND;	465	musb->int_usb &= ~MUSB_INTR_SUSPEND;
466	dev_dbg(musb->controller, "Spurious SUSPENDM\n");	466	dev_dbg(musb->controller, "Spurious SUSPENDM\n");
467	break;	467	break;
468	}	468	}
469		469
470	power &= ~MUSB_POWER_SUSPENDM;	470	power &= ~MUSB_POWER_SUSPENDM;
471	musb_writeb(mbase, MUSB_POWER,	471	musb_writeb(mbase, MUSB_POWER,
472	power \| MUSB_POWER_RESUME);	472	power \| MUSB_POWER_RESUME);
473		473
474	musb->port1_status \|=	474	musb->port1_status \|=
475	(USB_PORT_STAT_C_SUSPEND << 16)	475	(USB_PORT_STAT_C_SUSPEND << 16)
476	\| MUSB_PORT_STAT_RESUME;	476	\| MUSB_PORT_STAT_RESUME;
477	musb->rh_timer = jiffies	477	musb->rh_timer = jiffies
478	+ msecs_to_jiffies(20);	478	+ msecs_to_jiffies(20);
479		479
480	musb->xceiv->state = OTG_STATE_A_HOST;	480	musb->xceiv->state = OTG_STATE_A_HOST;
481	musb->is_active = 1;	481	musb->is_active = 1;
482	usb_hcd_resume_root_hub(musb_to_hcd(musb));	482	usb_hcd_resume_root_hub(musb_to_hcd(musb));
483	break;	483	break;
484	case OTG_STATE_B_WAIT_ACON:	484	case OTG_STATE_B_WAIT_ACON:
485	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;	485	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
486	musb->is_active = 1;	486	musb->is_active = 1;
487	MUSB_DEV_MODE(musb);	487	MUSB_DEV_MODE(musb);
488	break;	488	break;
489	default:	489	default:
490	WARNING("bogus %s RESUME (%s)\n",	490	WARNING("bogus %s RESUME (%s)\n",
491	"host",	491	"host",
492	otg_state_string(musb->xceiv->state));	492	otg_state_string(musb->xceiv->state));
493	}	493	}
494	} else {	494	} else {
495	switch (musb->xceiv->state) {	495	switch (musb->xceiv->state) {
496	case OTG_STATE_A_SUSPEND:	496	case OTG_STATE_A_SUSPEND:
497	/* possibly DISCONNECT is upcoming */	497	/* possibly DISCONNECT is upcoming */
498	musb->xceiv->state = OTG_STATE_A_HOST;	498	musb->xceiv->state = OTG_STATE_A_HOST;
499	usb_hcd_resume_root_hub(musb_to_hcd(musb));	499	usb_hcd_resume_root_hub(musb_to_hcd(musb));
500	break;	500	break;
501	case OTG_STATE_B_WAIT_ACON:	501	case OTG_STATE_B_WAIT_ACON:
502	case OTG_STATE_B_PERIPHERAL:	502	case OTG_STATE_B_PERIPHERAL:
503	/* disconnect while suspended? we may	503	/* disconnect while suspended? we may
504	* not get a disconnect irq...	504	* not get a disconnect irq...
505	*/	505	*/
506	if ((devctl & MUSB_DEVCTL_VBUS)	506	if ((devctl & MUSB_DEVCTL_VBUS)
507	!= (3 << MUSB_DEVCTL_VBUS_SHIFT)	507	!= (3 << MUSB_DEVCTL_VBUS_SHIFT)
508	) {	508	) {
509	musb->int_usb \|= MUSB_INTR_DISCONNECT;	509	musb->int_usb \|= MUSB_INTR_DISCONNECT;
510	musb->int_usb &= ~MUSB_INTR_SUSPEND;	510	musb->int_usb &= ~MUSB_INTR_SUSPEND;
511	break;	511	break;
512	}	512	}
513	musb_g_resume(musb);	513	musb_g_resume(musb);
514	break;	514	break;
515	case OTG_STATE_B_IDLE:	515	case OTG_STATE_B_IDLE:
516	musb->int_usb &= ~MUSB_INTR_SUSPEND;	516	musb->int_usb &= ~MUSB_INTR_SUSPEND;
517	break;	517	break;
518	default:	518	default:
519	WARNING("bogus %s RESUME (%s)\n",	519	WARNING("bogus %s RESUME (%s)\n",
520	"peripheral",	520	"peripheral",
521	otg_state_string(musb->xceiv->state));	521	otg_state_string(musb->xceiv->state));
522	}	522	}
523	}	523	}
524	}	524	}
525		525
526	/* see manual for the order of the tests */	526	/* see manual for the order of the tests */
527	if (int_usb & MUSB_INTR_SESSREQ) {	527	if (int_usb & MUSB_INTR_SESSREQ) {
528	void __iomem *mbase = musb->mregs;	528	void __iomem *mbase = musb->mregs;
529		529
530	if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS	530	if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
531	&& (devctl & MUSB_DEVCTL_BDEVICE)) {	531	&& (devctl & MUSB_DEVCTL_BDEVICE)) {
532	dev_dbg(musb->controller, "SessReq while on B state\n");	532	dev_dbg(musb->controller, "SessReq while on B state\n");
533	return IRQ_HANDLED;	533	return IRQ_HANDLED;
534	}	534	}
535		535
536	dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",	536	dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
537	otg_state_string(musb->xceiv->state));	537	otg_state_string(musb->xceiv->state));
538		538
539	/* IRQ arrives from ID pin sense or (later, if VBUS power	539	/* IRQ arrives from ID pin sense or (later, if VBUS power
540	* is removed) SRP. responses are time critical:	540	* is removed) SRP. responses are time critical:
541	* - turn on VBUS (with silicon-specific mechanism)	541	* - turn on VBUS (with silicon-specific mechanism)
542	* - go through A_WAIT_VRISE	542	* - go through A_WAIT_VRISE
543	* - ... to A_WAIT_BCON.	543	* - ... to A_WAIT_BCON.
544	* a_wait_vrise_tmout triggers VBUS_ERROR transitions	544	* a_wait_vrise_tmout triggers VBUS_ERROR transitions
545	*/	545	*/
546	musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);	546	musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
547	musb->ep0_stage = MUSB_EP0_START;	547	musb->ep0_stage = MUSB_EP0_START;
548	musb->xceiv->state = OTG_STATE_A_IDLE;	548	musb->xceiv->state = OTG_STATE_A_IDLE;
549	MUSB_HST_MODE(musb);	549	MUSB_HST_MODE(musb);
550	musb_platform_set_vbus(musb, 1);	550	musb_platform_set_vbus(musb, 1);
551		551
552	handled = IRQ_HANDLED;	552	handled = IRQ_HANDLED;
553	}	553	}
554		554
555	if (int_usb & MUSB_INTR_VBUSERROR) {	555	if (int_usb & MUSB_INTR_VBUSERROR) {
556	int ignore = 0;	556	int ignore = 0;
557		557
558	/* During connection as an A-Device, we may see a short	558	/* During connection as an A-Device, we may see a short
559	* current spikes causing voltage drop, because of cable	559	* current spikes causing voltage drop, because of cable
560	* and peripheral capacitance combined with vbus draw.	560	* and peripheral capacitance combined with vbus draw.
561	* (So: less common with truly self-powered devices, where	561	* (So: less common with truly self-powered devices, where
562	* vbus doesn't act like a power supply.)	562	* vbus doesn't act like a power supply.)
563	*	563	*
564	* Such spikes are short; usually less than ~500 usec, max	564	* Such spikes are short; usually less than ~500 usec, max
565	* of ~2 msec. That is, they're not sustained overcurrent	565	* of ~2 msec. That is, they're not sustained overcurrent
566	* errors, though they're reported using VBUSERROR irqs.	566	* errors, though they're reported using VBUSERROR irqs.
567	*	567	*
568	* Workarounds: (a) hardware: use self powered devices.	568	* Workarounds: (a) hardware: use self powered devices.
569	* (b) software: ignore non-repeated VBUS errors.	569	* (b) software: ignore non-repeated VBUS errors.
570	*	570	*
571	* REVISIT: do delays from lots of DEBUG_KERNEL checks	571	* REVISIT: do delays from lots of DEBUG_KERNEL checks
572	* make trouble here, keeping VBUS < 4.4V ?	572	* make trouble here, keeping VBUS < 4.4V ?
573	*/	573	*/
574	switch (musb->xceiv->state) {	574	switch (musb->xceiv->state) {
575	case OTG_STATE_A_HOST:	575	case OTG_STATE_A_HOST:
576	/* recovery is dicey once we've gotten past the	576	/* recovery is dicey once we've gotten past the
577	* initial stages of enumeration, but if VBUS	577	* initial stages of enumeration, but if VBUS
578	* stayed ok at the other end of the link, and	578	* stayed ok at the other end of the link, and
579	* another reset is due (at least for high speed,	579	* another reset is due (at least for high speed,
580	* to redo the chirp etc), it might work OK...	580	* to redo the chirp etc), it might work OK...
581	*/	581	*/
582	case OTG_STATE_A_WAIT_BCON:	582	case OTG_STATE_A_WAIT_BCON:
583	case OTG_STATE_A_WAIT_VRISE:	583	case OTG_STATE_A_WAIT_VRISE:
584	if (musb->vbuserr_retry) {	584	if (musb->vbuserr_retry) {
585	void __iomem *mbase = musb->mregs;	585	void __iomem *mbase = musb->mregs;
586		586
587	musb->vbuserr_retry--;	587	musb->vbuserr_retry--;
588	ignore = 1;	588	ignore = 1;
589	devctl \|= MUSB_DEVCTL_SESSION;	589	devctl \|= MUSB_DEVCTL_SESSION;
590	musb_writeb(mbase, MUSB_DEVCTL, devctl);	590	musb_writeb(mbase, MUSB_DEVCTL, devctl);
591	} else {	591	} else {
592	musb->port1_status \|=	592	musb->port1_status \|=
593	USB_PORT_STAT_OVERCURRENT	593	USB_PORT_STAT_OVERCURRENT
594	\| (USB_PORT_STAT_C_OVERCURRENT << 16);	594	\| (USB_PORT_STAT_C_OVERCURRENT << 16);
595	}	595	}
596	break;	596	break;
597	default:	597	default:
598	break;	598	break;
599	}	599	}
600		600
601	dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",	601	dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
602	otg_state_string(musb->xceiv->state),	602	otg_state_string(musb->xceiv->state),
603	devctl,	603	devctl,
604	({ char *s;	604	({ char *s;
605	switch (devctl & MUSB_DEVCTL_VBUS) {	605	switch (devctl & MUSB_DEVCTL_VBUS) {
606	case 0 << MUSB_DEVCTL_VBUS_SHIFT:	606	case 0 << MUSB_DEVCTL_VBUS_SHIFT:
607	s = "<SessEnd"; break;	607	s = "<SessEnd"; break;
608	case 1 << MUSB_DEVCTL_VBUS_SHIFT:	608	case 1 << MUSB_DEVCTL_VBUS_SHIFT:
609	s = "<AValid"; break;	609	s = "<AValid"; break;
610	case 2 << MUSB_DEVCTL_VBUS_SHIFT:	610	case 2 << MUSB_DEVCTL_VBUS_SHIFT:
611	s = "<VBusValid"; break;	611	s = "<VBusValid"; break;
612	/* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */	612	/* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
613	default:	613	default:
614	s = "VALID"; break;	614	s = "VALID"; break;
615	}; s; }),	615	}; s; }),
616	VBUSERR_RETRY_COUNT - musb->vbuserr_retry,	616	VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
617	musb->port1_status);	617	musb->port1_status);
618		618
619	/* go through A_WAIT_VFALL then start a new session */	619	/* go through A_WAIT_VFALL then start a new session */
620	if (!ignore)	620	if (!ignore)
621	musb_platform_set_vbus(musb, 0);	621	musb_platform_set_vbus(musb, 0);
622	handled = IRQ_HANDLED;	622	handled = IRQ_HANDLED;
623	}	623	}
624		624
625	if (int_usb & MUSB_INTR_SUSPEND) {	625	if (int_usb & MUSB_INTR_SUSPEND) {
626	dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",	626	dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
627	otg_state_string(musb->xceiv->state), devctl, power);	627	otg_state_string(musb->xceiv->state), devctl, power);
628	handled = IRQ_HANDLED;	628	handled = IRQ_HANDLED;
629		629
630	switch (musb->xceiv->state) {	630	switch (musb->xceiv->state) {
631	case OTG_STATE_A_PERIPHERAL:	631	case OTG_STATE_A_PERIPHERAL:
632	/* We also come here if the cable is removed, since	632	/* We also come here if the cable is removed, since
633	* this silicon doesn't report ID-no-longer-grounded.	633	* this silicon doesn't report ID-no-longer-grounded.
634	*	634	*
635	* We depend on T(a_wait_bcon) to shut us down, and	635	* We depend on T(a_wait_bcon) to shut us down, and
636	* hope users don't do anything dicey during this	636	* hope users don't do anything dicey during this
637	* undesired detour through A_WAIT_BCON.	637	* undesired detour through A_WAIT_BCON.
638	*/	638	*/
639	musb_hnp_stop(musb);	639	musb_hnp_stop(musb);
640	usb_hcd_resume_root_hub(musb_to_hcd(musb));	640	usb_hcd_resume_root_hub(musb_to_hcd(musb));
641	musb_root_disconnect(musb);	641	musb_root_disconnect(musb);
642	musb_platform_try_idle(musb, jiffies	642	musb_platform_try_idle(musb, jiffies
643	+ msecs_to_jiffies(musb->a_wait_bcon	643	+ msecs_to_jiffies(musb->a_wait_bcon
644	? : OTG_TIME_A_WAIT_BCON));	644	? : OTG_TIME_A_WAIT_BCON));
645		645
646	break;	646	break;
647	case OTG_STATE_B_IDLE:	647	case OTG_STATE_B_IDLE:
648	if (!musb->is_active)	648	if (!musb->is_active)
649	break;	649	break;
650	case OTG_STATE_B_PERIPHERAL:	650	case OTG_STATE_B_PERIPHERAL:
651	musb_g_suspend(musb);	651	musb_g_suspend(musb);
652	musb->is_active = is_otg_enabled(musb)	652	musb->is_active = otg->gadget->b_hnp_enable;
653	&& otg->gadget->b_hnp_enable;
654	if (musb->is_active) {	653	if (musb->is_active) {
655	musb->xceiv->state = OTG_STATE_B_WAIT_ACON;	654	musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
656	dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");	655	dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
657	mod_timer(&musb->otg_timer, jiffies	656	mod_timer(&musb->otg_timer, jiffies
658	+ msecs_to_jiffies(	657	+ msecs_to_jiffies(
659	OTG_TIME_B_ASE0_BRST));	658	OTG_TIME_B_ASE0_BRST));
660	}	659	}
661	break;	660	break;
662	case OTG_STATE_A_WAIT_BCON:	661	case OTG_STATE_A_WAIT_BCON:
663	if (musb->a_wait_bcon != 0)	662	if (musb->a_wait_bcon != 0)
664	musb_platform_try_idle(musb, jiffies	663	musb_platform_try_idle(musb, jiffies
665	+ msecs_to_jiffies(musb->a_wait_bcon));	664	+ msecs_to_jiffies(musb->a_wait_bcon));
666	break;	665	break;
667	case OTG_STATE_A_HOST:	666	case OTG_STATE_A_HOST:
668	musb->xceiv->state = OTG_STATE_A_SUSPEND;	667	musb->xceiv->state = OTG_STATE_A_SUSPEND;
669	musb->is_active = is_otg_enabled(musb)	668	musb->is_active = otg->host->b_hnp_enable;
670	&& otg->host->b_hnp_enable;
671	break;	669	break;
672	case OTG_STATE_B_HOST:	670	case OTG_STATE_B_HOST:
673	/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */	671	/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
674	dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");	672	dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
675	break;	673	break;
676	default:	674	default:
677	/* "should not happen" */	675	/* "should not happen" */
678	musb->is_active = 0;	676	musb->is_active = 0;
679	break;	677	break;
680	}	678	}
681	}	679	}
682		680
683	if (int_usb & MUSB_INTR_CONNECT) {	681	if (int_usb & MUSB_INTR_CONNECT) {
684	struct usb_hcd *hcd = musb_to_hcd(musb);	682	struct usb_hcd *hcd = musb_to_hcd(musb);
685		683
686	handled = IRQ_HANDLED;	684	handled = IRQ_HANDLED;
687	musb->is_active = 1;	685	musb->is_active = 1;
688		686
689	musb->ep0_stage = MUSB_EP0_START;	687	musb->ep0_stage = MUSB_EP0_START;
690		688
691	/* flush endpoints when transitioning from Device Mode */	689	/* flush endpoints when transitioning from Device Mode */
692	if (is_peripheral_active(musb)) {	690	if (is_peripheral_active(musb)) {
693	/* REVISIT HNP; just force disconnect */	691	/* REVISIT HNP; just force disconnect */
694	}	692	}
695	musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);	693	musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
696	musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);	694	musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
697	musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);	695	musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
698	musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED	696	musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
699	\|USB_PORT_STAT_HIGH_SPEED	697	\|USB_PORT_STAT_HIGH_SPEED
700	\|USB_PORT_STAT_ENABLE	698	\|USB_PORT_STAT_ENABLE
701	);	699	);
702	musb->port1_status \|= USB_PORT_STAT_CONNECTION	700	musb->port1_status \|= USB_PORT_STAT_CONNECTION
703	\|(USB_PORT_STAT_C_CONNECTION << 16);	701	\|(USB_PORT_STAT_C_CONNECTION << 16);
704		702
705	/* high vs full speed is just a guess until after reset */	703	/* high vs full speed is just a guess until after reset */
706	if (devctl & MUSB_DEVCTL_LSDEV)	704	if (devctl & MUSB_DEVCTL_LSDEV)
707	musb->port1_status \|= USB_PORT_STAT_LOW_SPEED;	705	musb->port1_status \|= USB_PORT_STAT_LOW_SPEED;
708		706
709	/* indicate new connection to OTG machine */	707	/* indicate new connection to OTG machine */
710	switch (musb->xceiv->state) {	708	switch (musb->xceiv->state) {
711	case OTG_STATE_B_PERIPHERAL:	709	case OTG_STATE_B_PERIPHERAL:
712	if (int_usb & MUSB_INTR_SUSPEND) {	710	if (int_usb & MUSB_INTR_SUSPEND) {
713	dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");	711	dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
714	int_usb &= ~MUSB_INTR_SUSPEND;	712	int_usb &= ~MUSB_INTR_SUSPEND;
715	goto b_host;	713	goto b_host;
716	} else	714	} else
717	dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");	715	dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
718	break;	716	break;
719	case OTG_STATE_B_WAIT_ACON:	717	case OTG_STATE_B_WAIT_ACON:
720	dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");	718	dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
721	b_host:	719	b_host:
722	musb->xceiv->state = OTG_STATE_B_HOST;	720	musb->xceiv->state = OTG_STATE_B_HOST;
723	hcd->self.is_b_host = 1;	721	hcd->self.is_b_host = 1;
724	musb->ignore_disconnect = 0;	722	musb->ignore_disconnect = 0;
725	del_timer(&musb->otg_timer);	723	del_timer(&musb->otg_timer);
726	break;	724	break;
727	default:	725	default:
728	if ((devctl & MUSB_DEVCTL_VBUS)	726	if ((devctl & MUSB_DEVCTL_VBUS)
729	== (3 << MUSB_DEVCTL_VBUS_SHIFT)) {	727	== (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
730	musb->xceiv->state = OTG_STATE_A_HOST;	728	musb->xceiv->state = OTG_STATE_A_HOST;
731	hcd->self.is_b_host = 0;	729	hcd->self.is_b_host = 0;
732	}	730	}
733	break;	731	break;
734	}	732	}
735		733
736	/* poke the root hub */	734	/* poke the root hub */
737	MUSB_HST_MODE(musb);	735	MUSB_HST_MODE(musb);
738	if (hcd->status_urb)	736	if (hcd->status_urb)
739	usb_hcd_poll_rh_status(hcd);	737	usb_hcd_poll_rh_status(hcd);
740	else	738	else
741	usb_hcd_resume_root_hub(hcd);	739	usb_hcd_resume_root_hub(hcd);
742		740
743	dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",	741	dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
744	otg_state_string(musb->xceiv->state), devctl);	742	otg_state_string(musb->xceiv->state), devctl);
745	}	743	}
746		744
747	if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {	745	if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
748	dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",	746	dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
749	otg_state_string(musb->xceiv->state),	747	otg_state_string(musb->xceiv->state),
750	MUSB_MODE(musb), devctl);	748	MUSB_MODE(musb), devctl);
751	handled = IRQ_HANDLED;	749	handled = IRQ_HANDLED;
752		750
753	switch (musb->xceiv->state) {	751	switch (musb->xceiv->state) {
754	case OTG_STATE_A_HOST:	752	case OTG_STATE_A_HOST:
755	case OTG_STATE_A_SUSPEND:	753	case OTG_STATE_A_SUSPEND:
756	usb_hcd_resume_root_hub(musb_to_hcd(musb));	754	usb_hcd_resume_root_hub(musb_to_hcd(musb));
757	musb_root_disconnect(musb);	755	musb_root_disconnect(musb);
758	if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))	756	if (musb->a_wait_bcon != 0)
759	musb_platform_try_idle(musb, jiffies	757	musb_platform_try_idle(musb, jiffies
760	+ msecs_to_jiffies(musb->a_wait_bcon));	758	+ msecs_to_jiffies(musb->a_wait_bcon));
761	break;	759	break;
762	case OTG_STATE_B_HOST:	760	case OTG_STATE_B_HOST:
763	/* REVISIT this behaves for "real disconnect"	761	/* REVISIT this behaves for "real disconnect"
764	* cases; make sure the other transitions from	762	* cases; make sure the other transitions from
765	* from B_HOST act right too. The B_HOST code	763	* from B_HOST act right too. The B_HOST code
766	* in hnp_stop() is currently not used...	764	* in hnp_stop() is currently not used...
767	*/	765	*/
768	musb_root_disconnect(musb);	766	musb_root_disconnect(musb);
769	musb_to_hcd(musb)->self.is_b_host = 0;	767	musb_to_hcd(musb)->self.is_b_host = 0;
770	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;	768	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
771	MUSB_DEV_MODE(musb);	769	MUSB_DEV_MODE(musb);
772	musb_g_disconnect(musb);	770	musb_g_disconnect(musb);
773	break;	771	break;
774	case OTG_STATE_A_PERIPHERAL:	772	case OTG_STATE_A_PERIPHERAL:
775	musb_hnp_stop(musb);	773	musb_hnp_stop(musb);
776	musb_root_disconnect(musb);	774	musb_root_disconnect(musb);
777	/* FALLTHROUGH */	775	/* FALLTHROUGH */
778	case OTG_STATE_B_WAIT_ACON:	776	case OTG_STATE_B_WAIT_ACON:
779	/* FALLTHROUGH */	777	/* FALLTHROUGH */
780	case OTG_STATE_B_PERIPHERAL:	778	case OTG_STATE_B_PERIPHERAL:
781	case OTG_STATE_B_IDLE:	779	case OTG_STATE_B_IDLE:
782	musb_g_disconnect(musb);	780	musb_g_disconnect(musb);
783	break;	781	break;
784	default:	782	default:
785	WARNING("unhandled DISCONNECT transition (%s)\n",	783	WARNING("unhandled DISCONNECT transition (%s)\n",
786	otg_state_string(musb->xceiv->state));	784	otg_state_string(musb->xceiv->state));
787	break;	785	break;
788	}	786	}
789	}	787	}
790		788
791	/* mentor saves a bit: bus reset and babble share the same irq.	789	/* mentor saves a bit: bus reset and babble share the same irq.
792	* only host sees babble; only peripheral sees bus reset.	790	* only host sees babble; only peripheral sees bus reset.
793	*/	791	*/
794	if (int_usb & MUSB_INTR_RESET) {	792	if (int_usb & MUSB_INTR_RESET) {
795	handled = IRQ_HANDLED;	793	handled = IRQ_HANDLED;
796	if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {	794	if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
797	/*	795	/*
798	* Looks like non-HS BABBLE can be ignored, but	796	* Looks like non-HS BABBLE can be ignored, but
799	* HS BABBLE is an error condition. For HS the solution	797	* HS BABBLE is an error condition. For HS the solution
800	* is to avoid babble in the first place and fix what	798	* is to avoid babble in the first place and fix what
801	* caused BABBLE. When HS BABBLE happens we can only	799	* caused BABBLE. When HS BABBLE happens we can only
802	* stop the session.	800	* stop the session.
803	*/	801	*/
804	if (devctl & (MUSB_DEVCTL_FSDEV \| MUSB_DEVCTL_LSDEV))	802	if (devctl & (MUSB_DEVCTL_FSDEV \| MUSB_DEVCTL_LSDEV))
805	dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);	803	dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
806	else {	804	else {
807	ERR("Stopping host session -- babble\n");	805	ERR("Stopping host session -- babble\n");
808	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);	806	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
809	}	807	}
810	} else if (is_peripheral_capable()) {	808	} else if (is_peripheral_capable()) {
811	dev_dbg(musb->controller, "BUS RESET as %s\n",	809	dev_dbg(musb->controller, "BUS RESET as %s\n",
812	otg_state_string(musb->xceiv->state));	810	otg_state_string(musb->xceiv->state));
813	switch (musb->xceiv->state) {	811	switch (musb->xceiv->state) {
814	case OTG_STATE_A_SUSPEND:	812	case OTG_STATE_A_SUSPEND:
815	/* We need to ignore disconnect on suspend	813	/* We need to ignore disconnect on suspend
816	* otherwise tusb 2.0 won't reconnect after a	814	* otherwise tusb 2.0 won't reconnect after a
817	* power cycle, which breaks otg compliance.	815	* power cycle, which breaks otg compliance.
818	*/	816	*/
819	musb->ignore_disconnect = 1;	817	musb->ignore_disconnect = 1;
820	musb_g_reset(musb);	818	musb_g_reset(musb);
821	/* FALLTHROUGH */	819	/* FALLTHROUGH */
822	case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */	820	case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
823	/* never use invalid T(a_wait_bcon) */	821	/* never use invalid T(a_wait_bcon) */
824	dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",	822	dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
825	otg_state_string(musb->xceiv->state),	823	otg_state_string(musb->xceiv->state),
826	TA_WAIT_BCON(musb));	824	TA_WAIT_BCON(musb));
827	mod_timer(&musb->otg_timer, jiffies	825	mod_timer(&musb->otg_timer, jiffies
828	+ msecs_to_jiffies(TA_WAIT_BCON(musb)));	826	+ msecs_to_jiffies(TA_WAIT_BCON(musb)));
829	break;	827	break;
830	case OTG_STATE_A_PERIPHERAL:	828	case OTG_STATE_A_PERIPHERAL:
831	musb->ignore_disconnect = 0;	829	musb->ignore_disconnect = 0;
832	del_timer(&musb->otg_timer);	830	del_timer(&musb->otg_timer);
833	musb_g_reset(musb);	831	musb_g_reset(musb);
834	break;	832	break;
835	case OTG_STATE_B_WAIT_ACON:	833	case OTG_STATE_B_WAIT_ACON:
836	dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",	834	dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
837	otg_state_string(musb->xceiv->state));	835	otg_state_string(musb->xceiv->state));
838	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;	836	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
839	musb_g_reset(musb);	837	musb_g_reset(musb);
840	break;	838	break;
841	case OTG_STATE_B_IDLE:	839	case OTG_STATE_B_IDLE:
842	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;	840	musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
843	/* FALLTHROUGH */	841	/* FALLTHROUGH */
844	case OTG_STATE_B_PERIPHERAL:	842	case OTG_STATE_B_PERIPHERAL:
845	musb_g_reset(musb);	843	musb_g_reset(musb);
846	break;	844	break;
847	default:	845	default:
848	dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",	846	dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
849	otg_state_string(musb->xceiv->state));	847	otg_state_string(musb->xceiv->state));
850	}	848	}
851	}	849	}
852	}	850	}
853		851
854	#if 0	852	#if 0
855	/* REVISIT ... this would be for multiplexing periodic endpoints, or	853	/* REVISIT ... this would be for multiplexing periodic endpoints, or
856	* supporting transfer phasing to prevent exceeding ISO bandwidth	854	* supporting transfer phasing to prevent exceeding ISO bandwidth
857	* limits of a given frame or microframe.	855	* limits of a given frame or microframe.
858	*	856	*
859	* It's not needed for peripheral side, which dedicates endpoints;	857	* It's not needed for peripheral side, which dedicates endpoints;
860	* though it _might_ use SOF irqs for other purposes.	858	* though it _might_ use SOF irqs for other purposes.
861	*	859	*
862	* And it's not currently needed for host side, which also dedicates	860	* And it's not currently needed for host side, which also dedicates
863	* endpoints, relies on TX/RX interval registers, and isn't claimed	861	* endpoints, relies on TX/RX interval registers, and isn't claimed
864	* to support ISO transfers yet.	862	* to support ISO transfers yet.
865	*/	863	*/
866	if (int_usb & MUSB_INTR_SOF) {	864	if (int_usb & MUSB_INTR_SOF) {
867	void __iomem *mbase = musb->mregs;	865	void __iomem *mbase = musb->mregs;
868	struct musb_hw_ep *ep;	866	struct musb_hw_ep *ep;
869	u8 epnum;	867	u8 epnum;
870	u16 frame;	868	u16 frame;
871		869
872	dev_dbg(musb->controller, "START_OF_FRAME\n");	870	dev_dbg(musb->controller, "START_OF_FRAME\n");
873	handled = IRQ_HANDLED;	871	handled = IRQ_HANDLED;
874		872
875	/* start any periodic Tx transfers waiting for current frame */	873	/* start any periodic Tx transfers waiting for current frame */
876	frame = musb_readw(mbase, MUSB_FRAME);	874	frame = musb_readw(mbase, MUSB_FRAME);
877	ep = musb->endpoints;	875	ep = musb->endpoints;
878	for (epnum = 1; (epnum < musb->nr_endpoints)	876	for (epnum = 1; (epnum < musb->nr_endpoints)
879	&& (musb->epmask >= (1 << epnum));	877	&& (musb->epmask >= (1 << epnum));
880	epnum++, ep++) {	878	epnum++, ep++) {
881	/*	879	/*
882	* FIXME handle framecounter wraps (12 bits)	880	* FIXME handle framecounter wraps (12 bits)
883	* eliminate duplicated StartUrb logic	881	* eliminate duplicated StartUrb logic
884	*/	882	*/
885	if (ep->dwWaitFrame >= frame) {	883	if (ep->dwWaitFrame >= frame) {
886	ep->dwWaitFrame = 0;	884	ep->dwWaitFrame = 0;
887	pr_debug("SOF --> periodic TX%s on %d\n",	885	pr_debug("SOF --> periodic TX%s on %d\n",
888	ep->tx_channel ? " DMA" : "",	886	ep->tx_channel ? " DMA" : "",
889	epnum);	887	epnum);
890	if (!ep->tx_channel)	888	if (!ep->tx_channel)
891	musb_h_tx_start(musb, epnum);	889	musb_h_tx_start(musb, epnum);
892	else	890	else
893	cppi_hostdma_start(musb, epnum);	891	cppi_hostdma_start(musb, epnum);
894	}	892	}
895	} /* end of for loop */	893	} /* end of for loop */
896	}	894	}
897	#endif	895	#endif
898		896
899	schedule_work(&musb->irq_work);	897	schedule_work(&musb->irq_work);
900		898
901	return handled;	899	return handled;
902	}	900	}
903		901
904	/-------------------------------------------------------------------------/	902	/-------------------------------------------------------------------------/
905		903
906	/*	904	/*
907	* Program the HDRC to start (enable interrupts, dma, etc.).	905	* Program the HDRC to start (enable interrupts, dma, etc.).
908	*/	906	*/
909	void musb_start(struct musb *musb)	907	void musb_start(struct musb *musb)
910	{	908	{
911	void __iomem *regs = musb->mregs;	909	void __iomem *regs = musb->mregs;
912	u8 devctl = musb_readb(regs, MUSB_DEVCTL);	910	u8 devctl = musb_readb(regs, MUSB_DEVCTL);
913		911
914	dev_dbg(musb->controller, "<== devctl %02x\n", devctl);	912	dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
915		913
916	/* Set INT enable registers, enable interrupts */	914	/* Set INT enable registers, enable interrupts */
917	musb_writew(regs, MUSB_INTRTXE, musb->epmask);	915	musb_writew(regs, MUSB_INTRTXE, musb->epmask);
918	musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);	916	musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
919	musb_writeb(regs, MUSB_INTRUSBE, 0xf7);	917	musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
920		918
921	musb_writeb(regs, MUSB_TESTMODE, 0);	919	musb_writeb(regs, MUSB_TESTMODE, 0);
922		920
923	/* put into basic highspeed mode and start session */	921	/* put into basic highspeed mode and start session */
924	musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE	922	musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
925	\| MUSB_POWER_HSENAB	923	\| MUSB_POWER_HSENAB
926	/* ENSUSPEND wedges tusb */	924	/* ENSUSPEND wedges tusb */
927	/* \| MUSB_POWER_ENSUSPEND */	925	/* \| MUSB_POWER_ENSUSPEND */
928	);	926	);
929		927
930	musb->is_active = 0;	928	musb->is_active = 0;
931	devctl = musb_readb(regs, MUSB_DEVCTL);	929	devctl = musb_readb(regs, MUSB_DEVCTL);
932	devctl &= ~MUSB_DEVCTL_SESSION;	930	devctl &= ~MUSB_DEVCTL_SESSION;
933		931
934	if (is_otg_enabled(musb)) {	932	/* session started after:
935	/* session started after:	933	* (a) ID-grounded irq, host mode;
936	* (a) ID-grounded irq, host mode;	934	* (b) vbus present/connect IRQ, peripheral mode;
937	* (b) vbus present/connect IRQ, peripheral mode;	935	* (c) peripheral initiates, using SRP
938	* (c) peripheral initiates, using SRP	936	*/
939	*/	937	if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
940	if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)	938	musb->is_active = 1;
941	musb->is_active = 1;	939	else
942	else
943	devctl \|= MUSB_DEVCTL_SESSION;
944
945	} else if (is_host_enabled(musb)) {
946	/* assume ID pin is hard-wired to ground */
947	devctl \|= MUSB_DEVCTL_SESSION;	940	devctl \|= MUSB_DEVCTL_SESSION;
948		941
949	} else /* peripheral is enabled */ {
950	if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
951	musb->is_active = 1;
952	}
953	musb_platform_enable(musb);	942	musb_platform_enable(musb);
954	musb_writeb(regs, MUSB_DEVCTL, devctl);	943	musb_writeb(regs, MUSB_DEVCTL, devctl);
955	}	944	}
956		945
957		946
958	static void musb_generic_disable(struct musb *musb)	947	static void musb_generic_disable(struct musb *musb)
959	{	948	{
960	void __iomem *mbase = musb->mregs;	949	void __iomem *mbase = musb->mregs;
961	u16 temp;	950	u16 temp;
962		951
963	/* disable interrupts */	952	/* disable interrupts */
964	musb_writeb(mbase, MUSB_INTRUSBE, 0);	953	musb_writeb(mbase, MUSB_INTRUSBE, 0);
965	musb_writew(mbase, MUSB_INTRTXE, 0);	954	musb_writew(mbase, MUSB_INTRTXE, 0);
966	musb_writew(mbase, MUSB_INTRRXE, 0);	955	musb_writew(mbase, MUSB_INTRRXE, 0);
967		956
968	/* off */	957	/* off */
969	musb_writeb(mbase, MUSB_DEVCTL, 0);	958	musb_writeb(mbase, MUSB_DEVCTL, 0);
970		959
971	/* flush pending interrupts */	960	/* flush pending interrupts */
972	temp = musb_readb(mbase, MUSB_INTRUSB);	961	temp = musb_readb(mbase, MUSB_INTRUSB);
973	temp = musb_readw(mbase, MUSB_INTRTX);	962	temp = musb_readw(mbase, MUSB_INTRTX);
974	temp = musb_readw(mbase, MUSB_INTRRX);	963	temp = musb_readw(mbase, MUSB_INTRRX);
975		964
976	}	965	}
977		966
978	/*	967	/*
979	* Make the HDRC stop (disable interrupts, etc.);	968	* Make the HDRC stop (disable interrupts, etc.);
980	* reversible by musb_start	969	* reversible by musb_start
981	* called on gadget driver unregister	970	* called on gadget driver unregister
982	* with controller locked, irqs blocked	971	* with controller locked, irqs blocked
983	* acts as a NOP unless some role activated the hardware	972	* acts as a NOP unless some role activated the hardware
984	*/	973	*/
985	void musb_stop(struct musb *musb)	974	void musb_stop(struct musb *musb)
986	{	975	{
987	/* stop IRQs, timers, ... */	976	/* stop IRQs, timers, ... */
988	musb_platform_disable(musb);	977	musb_platform_disable(musb);
989	musb_generic_disable(musb);	978	musb_generic_disable(musb);
990	dev_dbg(musb->controller, "HDRC disabled\n");	979	dev_dbg(musb->controller, "HDRC disabled\n");
991		980
992	/* FIXME	981	/* FIXME
993	* - mark host and/or peripheral drivers unusable/inactive	982	* - mark host and/or peripheral drivers unusable/inactive
994	* - disable DMA (and enable it in HdrcStart)	983	* - disable DMA (and enable it in HdrcStart)
995	* - make sure we can musb_start() after musb_stop(); with	984	* - make sure we can musb_start() after musb_stop(); with
996	* OTG mode, gadget driver module rmmod/modprobe cycles that	985	* OTG mode, gadget driver module rmmod/modprobe cycles that
997	* - ...	986	* - ...
998	*/	987	*/
999	musb_platform_try_idle(musb, 0);	988	musb_platform_try_idle(musb, 0);
1000	}	989	}
1001		990
1002	static void musb_shutdown(struct platform_device *pdev)	991	static void musb_shutdown(struct platform_device *pdev)
1003	{	992	{
1004	struct musb *musb = dev_to_musb(&pdev->dev);	993	struct musb *musb = dev_to_musb(&pdev->dev);
1005	unsigned long flags;	994	unsigned long flags;
1006		995
1007	pm_runtime_get_sync(musb->controller);	996	pm_runtime_get_sync(musb->controller);
1008		997
1009	musb_gadget_cleanup(musb);	998	musb_gadget_cleanup(musb);
1010		999
1011	spin_lock_irqsave(&musb->lock, flags);	1000	spin_lock_irqsave(&musb->lock, flags);
1012	musb_platform_disable(musb);	1001	musb_platform_disable(musb);
1013	musb_generic_disable(musb);	1002	musb_generic_disable(musb);
1014	spin_unlock_irqrestore(&musb->lock, flags);	1003	spin_unlock_irqrestore(&musb->lock, flags);
1015		1004
1016	if (!is_otg_enabled(musb) && is_host_enabled(musb))
1017	usb_remove_hcd(musb_to_hcd(musb));
1018	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);	1005	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1019	musb_platform_exit(musb);	1006	musb_platform_exit(musb);
1020		1007
1021	pm_runtime_put(musb->controller);	1008	pm_runtime_put(musb->controller);
1022	/* FIXME power down */	1009	/* FIXME power down */
1023	}	1010	}
1024		1011
1025		1012
1026	/-------------------------------------------------------------------------/	1013	/-------------------------------------------------------------------------/
1027		1014
1028	/*	1015	/*
1029	* The silicon either has hard-wired endpoint configurations, or else	1016	* The silicon either has hard-wired endpoint configurations, or else
1030	* "dynamic fifo" sizing. The driver has support for both, though at this	1017	* "dynamic fifo" sizing. The driver has support for both, though at this
1031	* writing only the dynamic sizing is very well tested. Since we switched	1018	* writing only the dynamic sizing is very well tested. Since we switched
1032	* away from compile-time hardware parameters, we can no longer rely on	1019	* away from compile-time hardware parameters, we can no longer rely on
1033	* dead code elimination to leave only the relevant one in the object file.	1020	* dead code elimination to leave only the relevant one in the object file.
1034	*	1021	*
1035	* We don't currently use dynamic fifo setup capability to do anything	1022	* We don't currently use dynamic fifo setup capability to do anything
1036	* more than selecting one of a bunch of predefined configurations.	1023	* more than selecting one of a bunch of predefined configurations.
1037	*/	1024	*/
1038	#if defined(CONFIG_USB_MUSB_TUSB6010) \	1025	#if defined(CONFIG_USB_MUSB_TUSB6010) \
1039	\|\| defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \	1026	\|\| defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1040	\|\| defined(CONFIG_USB_MUSB_OMAP2PLUS) \	1027	\|\| defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1041	\|\| defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \	1028	\|\| defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1042	\|\| defined(CONFIG_USB_MUSB_AM35X) \	1029	\|\| defined(CONFIG_USB_MUSB_AM35X) \
1043	\|\| defined(CONFIG_USB_MUSB_AM35X_MODULE) \	1030	\|\| defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1044	\|\| defined(CONFIG_USB_MUSB_DSPS) \	1031	\|\| defined(CONFIG_USB_MUSB_DSPS) \
1045	\|\| defined(CONFIG_USB_MUSB_DSPS_MODULE)	1032	\|\| defined(CONFIG_USB_MUSB_DSPS_MODULE)
1046	static ushort __devinitdata fifo_mode = 4;	1033	static ushort __devinitdata fifo_mode = 4;
1047	#elif defined(CONFIG_USB_MUSB_UX500) \	1034	#elif defined(CONFIG_USB_MUSB_UX500) \
1048	\|\| defined(CONFIG_USB_MUSB_UX500_MODULE)	1035	\|\| defined(CONFIG_USB_MUSB_UX500_MODULE)
1049	static ushort __devinitdata fifo_mode = 5;	1036	static ushort __devinitdata fifo_mode = 5;
1050	#else	1037	#else
1051	static ushort __devinitdata fifo_mode = 2;	1038	static ushort __devinitdata fifo_mode = 2;
1052	#endif	1039	#endif
1053		1040
1054	/* "modprobe ... fifo_mode=1" etc */	1041	/* "modprobe ... fifo_mode=1" etc */
1055	module_param(fifo_mode, ushort, 0);	1042	module_param(fifo_mode, ushort, 0);
1056	MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");	1043	MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1057		1044
1058	/*	1045	/*
1059	* tables defining fifo_mode values. define more if you like.	1046	* tables defining fifo_mode values. define more if you like.
1060	* for host side, make sure both halves of ep1 are set up.	1047	* for host side, make sure both halves of ep1 are set up.
1061	*/	1048	*/
1062		1049
1063	/* mode 0 - fits in 2KB */	1050	/* mode 0 - fits in 2KB */
1064	static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {	1051	static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
1065	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },	1052	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1066	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },	1053	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1067	{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },	1054	{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1068	{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },	1055	{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1069	{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },	1056	{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1070	};	1057	};
1071		1058
1072	/* mode 1 - fits in 4KB */	1059	/* mode 1 - fits in 4KB */
1073	static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {	1060	static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
1074	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },	1061	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1075	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },	1062	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1076	{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },	1063	{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1077	{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },	1064	{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1078	{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },	1065	{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1079	};	1066	};
1080		1067
1081	/* mode 2 - fits in 4KB */	1068	/* mode 2 - fits in 4KB */
1082	static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {	1069	static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
1083	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },	1070	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1084	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },	1071	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1085	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },	1072	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1086	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },	1073	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1087	{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },	1074	{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1088	{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },	1075	{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1089	};	1076	};
1090		1077
1091	/* mode 3 - fits in 4KB */	1078	/* mode 3 - fits in 4KB */
1092	static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {	1079	static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
1093	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },	1080	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1094	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },	1081	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1095	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },	1082	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1096	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },	1083	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1097	{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },	1084	{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1098	{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },	1085	{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1099	};	1086	};
1100		1087
1101	/* mode 4 - fits in 16KB */	1088	/* mode 4 - fits in 16KB */
1102	static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {	1089	static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
1103	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },	1090	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1104	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },	1091	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1105	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },	1092	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1106	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },	1093	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1107	{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },	1094	{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1108	{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },	1095	{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1109	{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },	1096	{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1110	{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },	1097	{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1111	{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },	1098	{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1112	{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },	1099	{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1113	{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },	1100	{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1114	{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },	1101	{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1115	{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },	1102	{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1116	{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },	1103	{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1117	{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },	1104	{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1118	{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },	1105	{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1119	{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },	1106	{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1120	{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },	1107	{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1121	{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },	1108	{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1122	{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },	1109	{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1123	{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },	1110	{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1124	{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },	1111	{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1125	{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },	1112	{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1126	{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },	1113	{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1127	{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },	1114	{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1128	{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },	1115	{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1129	{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },	1116	{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1130	};	1117	};
1131		1118
1132	/* mode 5 - fits in 8KB */	1119	/* mode 5 - fits in 8KB */
1133	static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {	1120	static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
1134	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },	1121	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1135	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },	1122	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1136	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },	1123	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1137	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },	1124	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1138	{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },	1125	{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1139	{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },	1126	{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1140	{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },	1127	{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1141	{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },	1128	{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1142	{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },	1129	{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1143	{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },	1130	{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1144	{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },	1131	{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1145	{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },	1132	{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1146	{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },	1133	{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1147	{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },	1134	{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1148	{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },	1135	{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1149	{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },	1136	{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1150	{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },	1137	{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1151	{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },	1138	{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1152	{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },	1139	{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1153	{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },	1140	{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1154	{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },	1141	{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1155	{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },	1142	{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1156	{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },	1143	{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1157	{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },	1144	{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1158	{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },	1145	{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1159	{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },	1146	{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1160	{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },	1147	{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1161	};	1148	};
1162		1149
1163	/*	1150	/*
1164	* configure a fifo; for non-shared endpoints, this may be called	1151	* configure a fifo; for non-shared endpoints, this may be called
1165	* once for a tx fifo and once for an rx fifo.	1152	* once for a tx fifo and once for an rx fifo.
1166	*	1153	*
1167	* returns negative errno or offset for next fifo.	1154	* returns negative errno or offset for next fifo.
1168	*/	1155	*/
1169	static int __devinit	1156	static int __devinit
1170	fifo_setup(struct musb musb, struct musb_hw_ep hw_ep,	1157	fifo_setup(struct musb musb, struct musb_hw_ep hw_ep,
1171	const struct musb_fifo_cfg *cfg, u16 offset)	1158	const struct musb_fifo_cfg *cfg, u16 offset)
1172	{	1159	{
1173	void __iomem *mbase = musb->mregs;	1160	void __iomem *mbase = musb->mregs;
1174	int size = 0;	1161	int size = 0;
1175	u16 maxpacket = cfg->maxpacket;	1162	u16 maxpacket = cfg->maxpacket;
1176	u16 c_off = offset >> 3;	1163	u16 c_off = offset >> 3;
1177	u8 c_size;	1164	u8 c_size;
1178		1165
1179	/* expect hw_ep has already been zero-initialized */	1166	/* expect hw_ep has already been zero-initialized */
1180		1167
1181	size = ffs(max(maxpacket, (u16) 8)) - 1;	1168	size = ffs(max(maxpacket, (u16) 8)) - 1;
1182	maxpacket = 1 << size;	1169	maxpacket = 1 << size;
1183		1170
1184	c_size = size - 3;	1171	c_size = size - 3;
1185	if (cfg->mode == BUF_DOUBLE) {	1172	if (cfg->mode == BUF_DOUBLE) {
1186	if ((offset + (maxpacket << 1)) >	1173	if ((offset + (maxpacket << 1)) >
1187	(1 << (musb->config->ram_bits + 2)))	1174	(1 << (musb->config->ram_bits + 2)))
1188	return -EMSGSIZE;	1175	return -EMSGSIZE;
1189	c_size \|= MUSB_FIFOSZ_DPB;	1176	c_size \|= MUSB_FIFOSZ_DPB;
1190	} else {	1177	} else {
1191	if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))	1178	if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1192	return -EMSGSIZE;	1179	return -EMSGSIZE;
1193	}	1180	}
1194		1181
1195	/* configure the FIFO */	1182	/* configure the FIFO */
1196	musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);	1183	musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1197		1184
1198	/* EP0 reserved endpoint for control, bidirectional;	1185	/* EP0 reserved endpoint for control, bidirectional;
1199	* EP1 reserved for bulk, two unidirection halves.	1186	* EP1 reserved for bulk, two unidirection halves.
1200	*/	1187	*/
1201	if (hw_ep->epnum == 1)	1188	if (hw_ep->epnum == 1)
1202	musb->bulk_ep = hw_ep;	1189	musb->bulk_ep = hw_ep;
1203	/* REVISIT error check: be sure ep0 can both rx and tx ... */	1190	/* REVISIT error check: be sure ep0 can both rx and tx ... */
1204	switch (cfg->style) {	1191	switch (cfg->style) {
1205	case FIFO_TX:	1192	case FIFO_TX:
1206	musb_write_txfifosz(mbase, c_size);	1193	musb_write_txfifosz(mbase, c_size);
1207	musb_write_txfifoadd(mbase, c_off);	1194	musb_write_txfifoadd(mbase, c_off);
1208	hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);	1195	hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1209	hw_ep->max_packet_sz_tx = maxpacket;	1196	hw_ep->max_packet_sz_tx = maxpacket;
1210	break;	1197	break;
1211	case FIFO_RX:	1198	case FIFO_RX:
1212	musb_write_rxfifosz(mbase, c_size);	1199	musb_write_rxfifosz(mbase, c_size);
1213	musb_write_rxfifoadd(mbase, c_off);	1200	musb_write_rxfifoadd(mbase, c_off);
1214	hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);	1201	hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1215	hw_ep->max_packet_sz_rx = maxpacket;	1202	hw_ep->max_packet_sz_rx = maxpacket;
1216	break;	1203	break;
1217	case FIFO_RXTX:	1204	case FIFO_RXTX:
1218	musb_write_txfifosz(mbase, c_size);	1205	musb_write_txfifosz(mbase, c_size);
1219	musb_write_txfifoadd(mbase, c_off);	1206	musb_write_txfifoadd(mbase, c_off);
1220	hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);	1207	hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1221	hw_ep->max_packet_sz_rx = maxpacket;	1208	hw_ep->max_packet_sz_rx = maxpacket;
1222		1209
1223	musb_write_rxfifosz(mbase, c_size);	1210	musb_write_rxfifosz(mbase, c_size);
1224	musb_write_rxfifoadd(mbase, c_off);	1211	musb_write_rxfifoadd(mbase, c_off);
1225	hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;	1212	hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1226	hw_ep->max_packet_sz_tx = maxpacket;	1213	hw_ep->max_packet_sz_tx = maxpacket;
1227		1214
1228	hw_ep->is_shared_fifo = true;	1215	hw_ep->is_shared_fifo = true;
1229	break;	1216	break;
1230	}	1217	}
1231		1218
1232	/* NOTE rx and tx endpoint irqs aren't managed separately,	1219	/* NOTE rx and tx endpoint irqs aren't managed separately,
1233	* which happens to be ok	1220	* which happens to be ok
1234	*/	1221	*/
1235	musb->epmask \|= (1 << hw_ep->epnum);	1222	musb->epmask \|= (1 << hw_ep->epnum);
1236		1223
1237	return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));	1224	return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1238	}	1225	}
1239		1226
1240	static struct musb_fifo_cfg __devinitdata ep0_cfg = {	1227	static struct musb_fifo_cfg __devinitdata ep0_cfg = {
1241	.style = FIFO_RXTX, .maxpacket = 64,	1228	.style = FIFO_RXTX, .maxpacket = 64,
1242	};	1229	};
1243		1230
1244	static int __devinit ep_config_from_table(struct musb *musb)	1231	static int __devinit ep_config_from_table(struct musb *musb)
1245	{	1232	{
1246	const struct musb_fifo_cfg *cfg;	1233	const struct musb_fifo_cfg *cfg;
1247	unsigned i, n;	1234	unsigned i, n;
1248	int offset;	1235	int offset;
1249	struct musb_hw_ep *hw_ep = musb->endpoints;	1236	struct musb_hw_ep *hw_ep = musb->endpoints;
1250		1237
1251	if (musb->config->fifo_cfg) {	1238	if (musb->config->fifo_cfg) {
1252	cfg = musb->config->fifo_cfg;	1239	cfg = musb->config->fifo_cfg;
1253	n = musb->config->fifo_cfg_size;	1240	n = musb->config->fifo_cfg_size;
1254	goto done;	1241	goto done;
1255	}	1242	}
1256		1243
1257	switch (fifo_mode) {	1244	switch (fifo_mode) {
1258	default:	1245	default:
1259	fifo_mode = 0;	1246	fifo_mode = 0;
1260	/* FALLTHROUGH */	1247	/* FALLTHROUGH */
1261	case 0:	1248	case 0:
1262	cfg = mode_0_cfg;	1249	cfg = mode_0_cfg;
1263	n = ARRAY_SIZE(mode_0_cfg);	1250	n = ARRAY_SIZE(mode_0_cfg);
1264	break;	1251	break;
1265	case 1:	1252	case 1:
1266	cfg = mode_1_cfg;	1253	cfg = mode_1_cfg;
1267	n = ARRAY_SIZE(mode_1_cfg);	1254	n = ARRAY_SIZE(mode_1_cfg);
1268	break;	1255	break;
1269	case 2:	1256	case 2:
1270	cfg = mode_2_cfg;	1257	cfg = mode_2_cfg;
1271	n = ARRAY_SIZE(mode_2_cfg);	1258	n = ARRAY_SIZE(mode_2_cfg);
1272	break;	1259	break;
1273	case 3:	1260	case 3:
1274	cfg = mode_3_cfg;	1261	cfg = mode_3_cfg;
1275	n = ARRAY_SIZE(mode_3_cfg);	1262	n = ARRAY_SIZE(mode_3_cfg);
1276	break;	1263	break;
1277	case 4:	1264	case 4:
1278	cfg = mode_4_cfg;	1265	cfg = mode_4_cfg;
1279	n = ARRAY_SIZE(mode_4_cfg);	1266	n = ARRAY_SIZE(mode_4_cfg);
1280	break;	1267	break;
1281	case 5:	1268	case 5:
1282	cfg = mode_5_cfg;	1269	cfg = mode_5_cfg;
1283	n = ARRAY_SIZE(mode_5_cfg);	1270	n = ARRAY_SIZE(mode_5_cfg);
1284	break;	1271	break;
1285	}	1272	}
1286		1273
1287	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",	1274	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1288	musb_driver_name, fifo_mode);	1275	musb_driver_name, fifo_mode);
1289		1276
1290		1277
1291	done:	1278	done:
1292	offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);	1279	offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1293	/* assert(offset > 0) */	1280	/* assert(offset > 0) */
1294		1281
1295	/* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would	1282	/* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1296	* be better than static musb->config->num_eps and DYN_FIFO_SIZE...	1283	* be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1297	*/	1284	*/
1298		1285
1299	for (i = 0; i < n; i++) {	1286	for (i = 0; i < n; i++) {
1300	u8 epn = cfg->hw_ep_num;	1287	u8 epn = cfg->hw_ep_num;
1301		1288
1302	if (epn >= musb->config->num_eps) {	1289	if (epn >= musb->config->num_eps) {
1303	pr_debug("%s: invalid ep %d\n",	1290	pr_debug("%s: invalid ep %d\n",
1304	musb_driver_name, epn);	1291	musb_driver_name, epn);
1305	return -EINVAL;	1292	return -EINVAL;
1306	}	1293	}
1307	offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);	1294	offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1308	if (offset < 0) {	1295	if (offset < 0) {
1309	pr_debug("%s: mem overrun, ep %d\n",	1296	pr_debug("%s: mem overrun, ep %d\n",
1310	musb_driver_name, epn);	1297	musb_driver_name, epn);
1311	return -EINVAL;	1298	return -EINVAL;
1312	}	1299	}
1313	epn++;	1300	epn++;
1314	musb->nr_endpoints = max(epn, musb->nr_endpoints);	1301	musb->nr_endpoints = max(epn, musb->nr_endpoints);
1315	}	1302	}
1316		1303
1317	printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",	1304	printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1318	musb_driver_name,	1305	musb_driver_name,
1319	n + 1, musb->config->num_eps * 2 - 1,	1306	n + 1, musb->config->num_eps * 2 - 1,
1320	offset, (1 << (musb->config->ram_bits + 2)));	1307	offset, (1 << (musb->config->ram_bits + 2)));
1321		1308
1322	if (!musb->bulk_ep) {	1309	if (!musb->bulk_ep) {
1323	pr_debug("%s: missing bulk\n", musb_driver_name);	1310	pr_debug("%s: missing bulk\n", musb_driver_name);
1324	return -EINVAL;	1311	return -EINVAL;
1325	}	1312	}
1326		1313
1327	return 0;	1314	return 0;
1328	}	1315	}
1329		1316
1330		1317
1331	/*	1318	/*
1332	* ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false	1319	* ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1333	* @param musb the controller	1320	* @param musb the controller
1334	*/	1321	*/
1335	static int __devinit ep_config_from_hw(struct musb *musb)	1322	static int __devinit ep_config_from_hw(struct musb *musb)
1336	{	1323	{
1337	u8 epnum = 0;	1324	u8 epnum = 0;
1338	struct musb_hw_ep *hw_ep;	1325	struct musb_hw_ep *hw_ep;
1339	void __iomem *mbase = musb->mregs;	1326	void __iomem *mbase = musb->mregs;
1340	int ret = 0;	1327	int ret = 0;
1341		1328
1342	dev_dbg(musb->controller, "<== static silicon ep config\n");	1329	dev_dbg(musb->controller, "<== static silicon ep config\n");
1343		1330
1344	/* FIXME pick up ep0 maxpacket size */	1331	/* FIXME pick up ep0 maxpacket size */
1345		1332
1346	for (epnum = 1; epnum < musb->config->num_eps; epnum++) {	1333	for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1347	musb_ep_select(mbase, epnum);	1334	musb_ep_select(mbase, epnum);
1348	hw_ep = musb->endpoints + epnum;	1335	hw_ep = musb->endpoints + epnum;
1349		1336
1350	ret = musb_read_fifosize(musb, hw_ep, epnum);	1337	ret = musb_read_fifosize(musb, hw_ep, epnum);
1351	if (ret < 0)	1338	if (ret < 0)
1352	break;	1339	break;
1353		1340
1354	/* FIXME set up hw_ep->{rx,tx}_double_buffered */	1341	/* FIXME set up hw_ep->{rx,tx}_double_buffered */
1355		1342
1356	/* pick an RX/TX endpoint for bulk */	1343	/* pick an RX/TX endpoint for bulk */
1357	if (hw_ep->max_packet_sz_tx < 512	1344	if (hw_ep->max_packet_sz_tx < 512
1358	\|\| hw_ep->max_packet_sz_rx < 512)	1345	\|\| hw_ep->max_packet_sz_rx < 512)
1359	continue;	1346	continue;
1360		1347
1361	/* REVISIT: this algorithm is lazy, we should at least	1348	/* REVISIT: this algorithm is lazy, we should at least
1362	* try to pick a double buffered endpoint.	1349	* try to pick a double buffered endpoint.
1363	*/	1350	*/
1364	if (musb->bulk_ep)	1351	if (musb->bulk_ep)
1365	continue;	1352	continue;
1366	musb->bulk_ep = hw_ep;	1353	musb->bulk_ep = hw_ep;
1367	}	1354	}
1368		1355
1369	if (!musb->bulk_ep) {	1356	if (!musb->bulk_ep) {
1370	pr_debug("%s: missing bulk\n", musb_driver_name);	1357	pr_debug("%s: missing bulk\n", musb_driver_name);
1371	return -EINVAL;	1358	return -EINVAL;
1372	}	1359	}
1373		1360
1374	return 0;	1361	return 0;
1375	}	1362	}
1376		1363
1377	enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };	1364	enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1378		1365
1379	/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;	1366	/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1380	* configure endpoints, or take their config from silicon	1367	* configure endpoints, or take their config from silicon
1381	*/	1368	*/
1382	static int __devinit musb_core_init(u16 musb_type, struct musb *musb)	1369	static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
1383	{	1370	{
1384	u8 reg;	1371	u8 reg;
1385	char *type;	1372	char *type;
1386	char aInfo[90], aRevision[32], aDate[12];	1373	char aInfo[90], aRevision[32], aDate[12];
1387	void __iomem *mbase = musb->mregs;	1374	void __iomem *mbase = musb->mregs;
1388	int status = 0;	1375	int status = 0;
1389	int i;	1376	int i;
1390		1377
1391	/* log core options (read using indexed model) */	1378	/* log core options (read using indexed model) */
1392	reg = musb_read_configdata(mbase);	1379	reg = musb_read_configdata(mbase);
1393		1380
1394	strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");	1381	strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1395	if (reg & MUSB_CONFIGDATA_DYNFIFO) {	1382	if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1396	strcat(aInfo, ", dyn FIFOs");	1383	strcat(aInfo, ", dyn FIFOs");
1397	musb->dyn_fifo = true;	1384	musb->dyn_fifo = true;
1398	}	1385	}
1399	if (reg & MUSB_CONFIGDATA_MPRXE) {	1386	if (reg & MUSB_CONFIGDATA_MPRXE) {
1400	strcat(aInfo, ", bulk combine");	1387	strcat(aInfo, ", bulk combine");
1401	musb->bulk_combine = true;	1388	musb->bulk_combine = true;
1402	}	1389	}
1403	if (reg & MUSB_CONFIGDATA_MPTXE) {	1390	if (reg & MUSB_CONFIGDATA_MPTXE) {
1404	strcat(aInfo, ", bulk split");	1391	strcat(aInfo, ", bulk split");
1405	musb->bulk_split = true;	1392	musb->bulk_split = true;
1406	}	1393	}
1407	if (reg & MUSB_CONFIGDATA_HBRXE) {	1394	if (reg & MUSB_CONFIGDATA_HBRXE) {
1408	strcat(aInfo, ", HB-ISO Rx");	1395	strcat(aInfo, ", HB-ISO Rx");
1409	musb->hb_iso_rx = true;	1396	musb->hb_iso_rx = true;
1410	}	1397	}
1411	if (reg & MUSB_CONFIGDATA_HBTXE) {	1398	if (reg & MUSB_CONFIGDATA_HBTXE) {
1412	strcat(aInfo, ", HB-ISO Tx");	1399	strcat(aInfo, ", HB-ISO Tx");
1413	musb->hb_iso_tx = true;	1400	musb->hb_iso_tx = true;
1414	}	1401	}
1415	if (reg & MUSB_CONFIGDATA_SOFTCONE)	1402	if (reg & MUSB_CONFIGDATA_SOFTCONE)
1416	strcat(aInfo, ", SoftConn");	1403	strcat(aInfo, ", SoftConn");
1417		1404
1418	printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",	1405	printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1419	musb_driver_name, reg, aInfo);	1406	musb_driver_name, reg, aInfo);
1420		1407
1421	aDate[0] = 0;	1408	aDate[0] = 0;
1422	if (MUSB_CONTROLLER_MHDRC == musb_type) {	1409	if (MUSB_CONTROLLER_MHDRC == musb_type) {
1423	musb->is_multipoint = 1;	1410	musb->is_multipoint = 1;
1424	type = "M";	1411	type = "M";
1425	} else {	1412	} else {
1426	musb->is_multipoint = 0;	1413	musb->is_multipoint = 0;
1427	type = "";	1414	type = "";
1428	#ifndef CONFIG_USB_OTG_BLACKLIST_HUB	1415	#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1429	printk(KERN_ERR	1416	printk(KERN_ERR
1430	"%s: kernel must blacklist external hubs\n",	1417	"%s: kernel must blacklist external hubs\n",
1431	musb_driver_name);	1418	musb_driver_name);
1432	#endif	1419	#endif
1433	}	1420	}
1434		1421
1435	/* log release info */	1422	/* log release info */
1436	musb->hwvers = musb_read_hwvers(mbase);	1423	musb->hwvers = musb_read_hwvers(mbase);
1437	snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),	1424	snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1438	MUSB_HWVERS_MINOR(musb->hwvers),	1425	MUSB_HWVERS_MINOR(musb->hwvers),
1439	(musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");	1426	(musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1440	printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",	1427	printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1441	musb_driver_name, type, aRevision, aDate);	1428	musb_driver_name, type, aRevision, aDate);
1442		1429
1443	/* configure ep0 */	1430	/* configure ep0 */
1444	musb_configure_ep0(musb);	1431	musb_configure_ep0(musb);
1445		1432
1446	/* discover endpoint configuration */	1433	/* discover endpoint configuration */
1447	musb->nr_endpoints = 1;	1434	musb->nr_endpoints = 1;
1448	musb->epmask = 1;	1435	musb->epmask = 1;
1449		1436
1450	if (musb->dyn_fifo)	1437	if (musb->dyn_fifo)
1451	status = ep_config_from_table(musb);	1438	status = ep_config_from_table(musb);
1452	else	1439	else
1453	status = ep_config_from_hw(musb);	1440	status = ep_config_from_hw(musb);
1454		1441
1455	if (status < 0)	1442	if (status < 0)
1456	return status;	1443	return status;
1457		1444
1458	/* finish init, and print endpoint config */	1445	/* finish init, and print endpoint config */
1459	for (i = 0; i < musb->nr_endpoints; i++) {	1446	for (i = 0; i < musb->nr_endpoints; i++) {
1460	struct musb_hw_ep *hw_ep = musb->endpoints + i;	1447	struct musb_hw_ep *hw_ep = musb->endpoints + i;
1461		1448
1462	hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;	1449	hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1463	#if defined(CONFIG_USB_MUSB_TUSB6010) \|\| defined (CONFIG_USB_MUSB_TUSB6010_MODULE)	1450	#if defined(CONFIG_USB_MUSB_TUSB6010) \|\| defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1464	hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);	1451	hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1465	hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);	1452	hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1466	hw_ep->fifo_sync_va =	1453	hw_ep->fifo_sync_va =
1467	musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);	1454	musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1468		1455
1469	if (i == 0)	1456	if (i == 0)
1470	hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;	1457	hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1471	else	1458	else
1472	hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);	1459	hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1473	#endif	1460	#endif
1474		1461
1475	hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;	1462	hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1476	hw_ep->target_regs = musb_read_target_reg_base(i, mbase);	1463	hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1477	hw_ep->rx_reinit = 1;	1464	hw_ep->rx_reinit = 1;
1478	hw_ep->tx_reinit = 1;	1465	hw_ep->tx_reinit = 1;
1479		1466
1480	if (hw_ep->max_packet_sz_tx) {	1467	if (hw_ep->max_packet_sz_tx) {
1481	dev_dbg(musb->controller,	1468	dev_dbg(musb->controller,
1482	"%s: hw_ep %d%s, %smax %d\n",	1469	"%s: hw_ep %d%s, %smax %d\n",
1483	musb_driver_name, i,	1470	musb_driver_name, i,
1484	hw_ep->is_shared_fifo ? "shared" : "tx",	1471	hw_ep->is_shared_fifo ? "shared" : "tx",
1485	hw_ep->tx_double_buffered	1472	hw_ep->tx_double_buffered
1486	? "doublebuffer, " : "",	1473	? "doublebuffer, " : "",
1487	hw_ep->max_packet_sz_tx);	1474	hw_ep->max_packet_sz_tx);
1488	}	1475	}
1489	if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {	1476	if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1490	dev_dbg(musb->controller,	1477	dev_dbg(musb->controller,
1491	"%s: hw_ep %d%s, %smax %d\n",	1478	"%s: hw_ep %d%s, %smax %d\n",
1492	musb_driver_name, i,	1479	musb_driver_name, i,
1493	"rx",	1480	"rx",
1494	hw_ep->rx_double_buffered	1481	hw_ep->rx_double_buffered
1495	? "doublebuffer, " : "",	1482	? "doublebuffer, " : "",
1496	hw_ep->max_packet_sz_rx);	1483	hw_ep->max_packet_sz_rx);
1497	}	1484	}
1498	if (!(hw_ep->max_packet_sz_tx \|\| hw_ep->max_packet_sz_rx))	1485	if (!(hw_ep->max_packet_sz_tx \|\| hw_ep->max_packet_sz_rx))
1499	dev_dbg(musb->controller, "hw_ep %d not configured\n", i);	1486	dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1500	}	1487	}
1501		1488
1502	return 0;	1489	return 0;
1503	}	1490	}
1504		1491
1505	/-------------------------------------------------------------------------/	1492	/-------------------------------------------------------------------------/
1506		1493
1507	#if defined(CONFIG_SOC_OMAP2430) \|\| defined(CONFIG_SOC_OMAP3430) \|\| \	1494	#if defined(CONFIG_SOC_OMAP2430) \|\| defined(CONFIG_SOC_OMAP3430) \|\| \
1508	defined(CONFIG_ARCH_OMAP4) \|\| defined(CONFIG_ARCH_U8500)	1495	defined(CONFIG_ARCH_OMAP4) \|\| defined(CONFIG_ARCH_U8500)
1509		1496
1510	static irqreturn_t generic_interrupt(int irq, void *__hci)	1497	static irqreturn_t generic_interrupt(int irq, void *__hci)
1511	{	1498	{
1512	unsigned long flags;	1499	unsigned long flags;
1513	irqreturn_t retval = IRQ_NONE;	1500	irqreturn_t retval = IRQ_NONE;
1514	struct musb *musb = __hci;	1501	struct musb *musb = __hci;
1515		1502
1516	spin_lock_irqsave(&musb->lock, flags);	1503	spin_lock_irqsave(&musb->lock, flags);
1517		1504
1518	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);	1505	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1519	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);	1506	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1520	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);	1507	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1521		1508
1522	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx)	1509	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx)
1523	retval = musb_interrupt(musb);	1510	retval = musb_interrupt(musb);
1524		1511
1525	spin_unlock_irqrestore(&musb->lock, flags);	1512	spin_unlock_irqrestore(&musb->lock, flags);
1526		1513
1527	return retval;	1514	return retval;
1528	}	1515	}
1529		1516
1530	#else	1517	#else
1531	#define generic_interrupt NULL	1518	#define generic_interrupt NULL
1532	#endif	1519	#endif
1533		1520
1534	/*	1521	/*
1535	* handle all the irqs defined by the HDRC core. for now we expect: other	1522	* handle all the irqs defined by the HDRC core. for now we expect: other
1536	* irq sources (phy, dma, etc) will be handled first, musb->int_* values	1523	* irq sources (phy, dma, etc) will be handled first, musb->int_* values
1537	* will be assigned, and the irq will already have been acked.	1524	* will be assigned, and the irq will already have been acked.
1538	*	1525	*
1539	* called in irq context with spinlock held, irqs blocked	1526	* called in irq context with spinlock held, irqs blocked
1540	*/	1527	*/
1541	irqreturn_t musb_interrupt(struct musb *musb)	1528	irqreturn_t musb_interrupt(struct musb *musb)
1542	{	1529	{
1543	irqreturn_t retval = IRQ_NONE;	1530	irqreturn_t retval = IRQ_NONE;
1544	u8 devctl, power;	1531	u8 devctl, power;
1545	int ep_num;	1532	int ep_num;
1546	u32 reg;	1533	u32 reg;
1547		1534
1548	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);	1535	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1549	power = musb_readb(musb->mregs, MUSB_POWER);	1536	power = musb_readb(musb->mregs, MUSB_POWER);
1550		1537
1551	dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",	1538	dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1552	(devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",	1539	(devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1553	musb->int_usb, musb->int_tx, musb->int_rx);	1540	musb->int_usb, musb->int_tx, musb->int_rx);
1554		1541
1555	/* the core can interrupt us for multiple reasons; docs have	1542	/* the core can interrupt us for multiple reasons; docs have
1556	* a generic interrupt flowchart to follow	1543	* a generic interrupt flowchart to follow
1557	*/	1544	*/
1558	if (musb->int_usb)	1545	if (musb->int_usb)
1559	retval \|= musb_stage0_irq(musb, musb->int_usb,	1546	retval \|= musb_stage0_irq(musb, musb->int_usb,
1560	devctl, power);	1547	devctl, power);
1561		1548
1562	/* "stage 1" is handling endpoint irqs */	1549	/* "stage 1" is handling endpoint irqs */
1563		1550
1564	/* handle endpoint 0 first */	1551	/* handle endpoint 0 first */
1565	if (musb->int_tx & 1) {	1552	if (musb->int_tx & 1) {
1566	if (devctl & MUSB_DEVCTL_HM)	1553	if (devctl & MUSB_DEVCTL_HM)
1567	retval \|= musb_h_ep0_irq(musb);	1554	retval \|= musb_h_ep0_irq(musb);
1568	else	1555	else
1569	retval \|= musb_g_ep0_irq(musb);	1556	retval \|= musb_g_ep0_irq(musb);
1570	}	1557	}
1571		1558
1572	/* RX on endpoints 1-15 */	1559	/* RX on endpoints 1-15 */
1573	reg = musb->int_rx >> 1;	1560	reg = musb->int_rx >> 1;
1574	ep_num = 1;	1561	ep_num = 1;
1575	while (reg) {	1562	while (reg) {
1576	if (reg & 1) {	1563	if (reg & 1) {
1577	/* musb_ep_select(musb->mregs, ep_num); */	1564	/* musb_ep_select(musb->mregs, ep_num); */
1578	/* REVISIT just retval = ep->rx_irq(...) */	1565	/* REVISIT just retval = ep->rx_irq(...) */
1579	retval = IRQ_HANDLED;	1566	retval = IRQ_HANDLED;
1580	if (devctl & MUSB_DEVCTL_HM) {	1567	if (devctl & MUSB_DEVCTL_HM) {
1581	if (is_host_capable())	1568	if (is_host_capable())
1582	musb_host_rx(musb, ep_num);	1569	musb_host_rx(musb, ep_num);
1583	} else {	1570	} else {
1584	if (is_peripheral_capable())	1571	if (is_peripheral_capable())
1585	musb_g_rx(musb, ep_num);	1572	musb_g_rx(musb, ep_num);
1586	}	1573	}
1587	}	1574	}
1588		1575
1589	reg >>= 1;	1576	reg >>= 1;
1590	ep_num++;	1577	ep_num++;
1591	}	1578	}
1592		1579
1593	/* TX on endpoints 1-15 */	1580	/* TX on endpoints 1-15 */
1594	reg = musb->int_tx >> 1;	1581	reg = musb->int_tx >> 1;
1595	ep_num = 1;	1582	ep_num = 1;
1596	while (reg) {	1583	while (reg) {
1597	if (reg & 1) {	1584	if (reg & 1) {
1598	/* musb_ep_select(musb->mregs, ep_num); */	1585	/* musb_ep_select(musb->mregs, ep_num); */
1599	/* REVISIT just retval \|= ep->tx_irq(...) */	1586	/* REVISIT just retval \|= ep->tx_irq(...) */
1600	retval = IRQ_HANDLED;	1587	retval = IRQ_HANDLED;
1601	if (devctl & MUSB_DEVCTL_HM) {	1588	if (devctl & MUSB_DEVCTL_HM) {
1602	if (is_host_capable())	1589	if (is_host_capable())
1603	musb_host_tx(musb, ep_num);	1590	musb_host_tx(musb, ep_num);
1604	} else {	1591	} else {
1605	if (is_peripheral_capable())	1592	if (is_peripheral_capable())
1606	musb_g_tx(musb, ep_num);	1593	musb_g_tx(musb, ep_num);
1607	}	1594	}
1608	}	1595	}
1609	reg >>= 1;	1596	reg >>= 1;
1610	ep_num++;	1597	ep_num++;
1611	}	1598	}
1612		1599
1613	return retval;	1600	return retval;
1614	}	1601	}
1615	EXPORT_SYMBOL_GPL(musb_interrupt);	1602	EXPORT_SYMBOL_GPL(musb_interrupt);
1616		1603
1617	#ifndef CONFIG_MUSB_PIO_ONLY	1604	#ifndef CONFIG_MUSB_PIO_ONLY
1618	static bool __devinitdata use_dma = 1;	1605	static bool __devinitdata use_dma = 1;
1619		1606
1620	/* "modprobe ... use_dma=0" etc */	1607	/* "modprobe ... use_dma=0" etc */
1621	module_param(use_dma, bool, 0);	1608	module_param(use_dma, bool, 0);
1622	MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");	1609	MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1623		1610
1624	void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)	1611	void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1625	{	1612	{
1626	u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);	1613	u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1627		1614
1628	/* called with controller lock already held */	1615	/* called with controller lock already held */
1629		1616
1630	if (!epnum) {	1617	if (!epnum) {
1631	#ifndef CONFIG_USB_TUSB_OMAP_DMA	1618	#ifndef CONFIG_USB_TUSB_OMAP_DMA
1632	if (!is_cppi_enabled()) {	1619	if (!is_cppi_enabled()) {
1633	/* endpoint 0 */	1620	/* endpoint 0 */
1634	if (devctl & MUSB_DEVCTL_HM)	1621	if (devctl & MUSB_DEVCTL_HM)
1635	musb_h_ep0_irq(musb);	1622	musb_h_ep0_irq(musb);
1636	else	1623	else
1637	musb_g_ep0_irq(musb);	1624	musb_g_ep0_irq(musb);
1638	}	1625	}
1639	#endif	1626	#endif
1640	} else {	1627	} else {
1641	/* endpoints 1..15 */	1628	/* endpoints 1..15 */
1642	if (transmit) {	1629	if (transmit) {
1643	if (devctl & MUSB_DEVCTL_HM) {	1630	if (devctl & MUSB_DEVCTL_HM) {
1644	if (is_host_capable())	1631	if (is_host_capable())
1645	musb_host_tx(musb, epnum);	1632	musb_host_tx(musb, epnum);
1646	} else {	1633	} else {
1647	if (is_peripheral_capable())	1634	if (is_peripheral_capable())
1648	musb_g_tx(musb, epnum);	1635	musb_g_tx(musb, epnum);
1649	}	1636	}
1650	} else {	1637	} else {
1651	/* receive */	1638	/* receive */
1652	if (devctl & MUSB_DEVCTL_HM) {	1639	if (devctl & MUSB_DEVCTL_HM) {
1653	if (is_host_capable())	1640	if (is_host_capable())
1654	musb_host_rx(musb, epnum);	1641	musb_host_rx(musb, epnum);
1655	} else {	1642	} else {
1656	if (is_peripheral_capable())	1643	if (is_peripheral_capable())
1657	musb_g_rx(musb, epnum);	1644	musb_g_rx(musb, epnum);
1658	}	1645	}
1659	}	1646	}
1660	}	1647	}
1661	}	1648	}
1662	EXPORT_SYMBOL_GPL(musb_dma_completion);	1649	EXPORT_SYMBOL_GPL(musb_dma_completion);
1663		1650
1664	#else	1651	#else
1665	#define use_dma 0	1652	#define use_dma 0
1666	#endif	1653	#endif
1667		1654
1668	/-------------------------------------------------------------------------/	1655	/-------------------------------------------------------------------------/
1669		1656
1670	#ifdef CONFIG_SYSFS	1657	#ifdef CONFIG_SYSFS
1671		1658
1672	static ssize_t	1659	static ssize_t
1673	musb_mode_show(struct device dev, struct device_attribute attr, char *buf)	1660	musb_mode_show(struct device dev, struct device_attribute attr, char *buf)
1674	{	1661	{
1675	struct musb *musb = dev_to_musb(dev);	1662	struct musb *musb = dev_to_musb(dev);
1676	unsigned long flags;	1663	unsigned long flags;
1677	int ret = -EINVAL;	1664	int ret = -EINVAL;
1678		1665
1679	spin_lock_irqsave(&musb->lock, flags);	1666	spin_lock_irqsave(&musb->lock, flags);
1680	ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));	1667	ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1681	spin_unlock_irqrestore(&musb->lock, flags);	1668	spin_unlock_irqrestore(&musb->lock, flags);
1682		1669
1683	return ret;	1670	return ret;
1684	}	1671	}
1685		1672
1686	static ssize_t	1673	static ssize_t
1687	musb_mode_store(struct device dev, struct device_attribute attr,	1674	musb_mode_store(struct device dev, struct device_attribute attr,
1688	const char *buf, size_t n)	1675	const char *buf, size_t n)
1689	{	1676	{
1690	struct musb *musb = dev_to_musb(dev);	1677	struct musb *musb = dev_to_musb(dev);
1691	unsigned long flags;	1678	unsigned long flags;
1692	int status;	1679	int status;
1693		1680
1694	spin_lock_irqsave(&musb->lock, flags);	1681	spin_lock_irqsave(&musb->lock, flags);
1695	if (sysfs_streq(buf, "host"))	1682	if (sysfs_streq(buf, "host"))
1696	status = musb_platform_set_mode(musb, MUSB_HOST);	1683	status = musb_platform_set_mode(musb, MUSB_HOST);
1697	else if (sysfs_streq(buf, "peripheral"))	1684	else if (sysfs_streq(buf, "peripheral"))
1698	status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);	1685	status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1699	else if (sysfs_streq(buf, "otg"))	1686	else if (sysfs_streq(buf, "otg"))
1700	status = musb_platform_set_mode(musb, MUSB_OTG);	1687	status = musb_platform_set_mode(musb, MUSB_OTG);
1701	else	1688	else
1702	status = -EINVAL;	1689	status = -EINVAL;
1703	spin_unlock_irqrestore(&musb->lock, flags);	1690	spin_unlock_irqrestore(&musb->lock, flags);
1704		1691
1705	return (status == 0) ? n : status;	1692	return (status == 0) ? n : status;
1706	}	1693	}
1707	static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);	1694	static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1708		1695
1709	static ssize_t	1696	static ssize_t
1710	musb_vbus_store(struct device dev, struct device_attribute attr,	1697	musb_vbus_store(struct device dev, struct device_attribute attr,
1711	const char *buf, size_t n)	1698	const char *buf, size_t n)
1712	{	1699	{
1713	struct musb *musb = dev_to_musb(dev);	1700	struct musb *musb = dev_to_musb(dev);
1714	unsigned long flags;	1701	unsigned long flags;
1715	unsigned long val;	1702	unsigned long val;
1716		1703
1717	if (sscanf(buf, "%lu", &val) < 1) {	1704	if (sscanf(buf, "%lu", &val) < 1) {
1718	dev_err(dev, "Invalid VBUS timeout ms value\n");	1705	dev_err(dev, "Invalid VBUS timeout ms value\n");
1719	return -EINVAL;	1706	return -EINVAL;
1720	}	1707	}
1721		1708
1722	spin_lock_irqsave(&musb->lock, flags);	1709	spin_lock_irqsave(&musb->lock, flags);
1723	/* force T(a_wait_bcon) to be zero/unlimited OR valid */	1710	/* force T(a_wait_bcon) to be zero/unlimited OR valid */
1724	musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;	1711	musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1725	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)	1712	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1726	musb->is_active = 0;	1713	musb->is_active = 0;
1727	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));	1714	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1728	spin_unlock_irqrestore(&musb->lock, flags);	1715	spin_unlock_irqrestore(&musb->lock, flags);
1729		1716
1730	return n;	1717	return n;
1731	}	1718	}
1732		1719
1733	static ssize_t	1720	static ssize_t
1734	musb_vbus_show(struct device dev, struct device_attribute attr, char *buf)	1721	musb_vbus_show(struct device dev, struct device_attribute attr, char *buf)
1735	{	1722	{
1736	struct musb *musb = dev_to_musb(dev);	1723	struct musb *musb = dev_to_musb(dev);
1737	unsigned long flags;	1724	unsigned long flags;
1738	unsigned long val;	1725	unsigned long val;
1739	int vbus;	1726	int vbus;
1740		1727
1741	spin_lock_irqsave(&musb->lock, flags);	1728	spin_lock_irqsave(&musb->lock, flags);
1742	val = musb->a_wait_bcon;	1729	val = musb->a_wait_bcon;
1743	/* FIXME get_vbus_status() is normally #defined as false...	1730	/* FIXME get_vbus_status() is normally #defined as false...
1744	* and is effectively TUSB-specific.	1731	* and is effectively TUSB-specific.
1745	*/	1732	*/
1746	vbus = musb_platform_get_vbus_status(musb);	1733	vbus = musb_platform_get_vbus_status(musb);
1747	spin_unlock_irqrestore(&musb->lock, flags);	1734	spin_unlock_irqrestore(&musb->lock, flags);
1748		1735
1749	return sprintf(buf, "Vbus %s, timeout %lu msec\n",	1736	return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1750	vbus ? "on" : "off", val);	1737	vbus ? "on" : "off", val);
1751	}	1738	}
1752	static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);	1739	static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1753		1740
1754	/* Gadget drivers can't know that a host is connected so they might want	1741	/* Gadget drivers can't know that a host is connected so they might want
1755	* to start SRP, but users can. This allows userspace to trigger SRP.	1742	* to start SRP, but users can. This allows userspace to trigger SRP.
1756	*/	1743	*/
1757	static ssize_t	1744	static ssize_t
1758	musb_srp_store(struct device dev, struct device_attribute attr,	1745	musb_srp_store(struct device dev, struct device_attribute attr,
1759	const char *buf, size_t n)	1746	const char *buf, size_t n)
1760	{	1747	{
1761	struct musb *musb = dev_to_musb(dev);	1748	struct musb *musb = dev_to_musb(dev);
1762	unsigned short srp;	1749	unsigned short srp;
1763		1750
1764	if (sscanf(buf, "%hu", &srp) != 1	1751	if (sscanf(buf, "%hu", &srp) != 1
1765	\|\| (srp != 1)) {	1752	\|\| (srp != 1)) {
1766	dev_err(dev, "SRP: Value must be 1\n");	1753	dev_err(dev, "SRP: Value must be 1\n");
1767	return -EINVAL;	1754	return -EINVAL;
1768	}	1755	}
1769		1756
1770	if (srp == 1)	1757	if (srp == 1)
1771	musb_g_wakeup(musb);	1758	musb_g_wakeup(musb);
1772		1759
1773	return n;	1760	return n;
1774	}	1761	}
1775	static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);	1762	static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1776		1763
1777	static struct attribute *musb_attributes[] = {	1764	static struct attribute *musb_attributes[] = {
1778	&dev_attr_mode.attr,	1765	&dev_attr_mode.attr,
1779	&dev_attr_vbus.attr,	1766	&dev_attr_vbus.attr,
1780	&dev_attr_srp.attr,	1767	&dev_attr_srp.attr,
1781	NULL	1768	NULL
1782	};	1769	};
1783		1770
1784	static const struct attribute_group musb_attr_group = {	1771	static const struct attribute_group musb_attr_group = {
1785	.attrs = musb_attributes,	1772	.attrs = musb_attributes,
1786	};	1773	};
1787		1774
1788	#endif /* sysfs */	1775	#endif /* sysfs */
1789		1776
1790	/* Only used to provide driver mode change events */	1777	/* Only used to provide driver mode change events */
1791	static void musb_irq_work(struct work_struct *data)	1778	static void musb_irq_work(struct work_struct *data)
1792	{	1779	{
1793	struct musb *musb = container_of(data, struct musb, irq_work);	1780	struct musb *musb = container_of(data, struct musb, irq_work);
1794	static int old_state;	1781	static int old_state;
1795		1782
1796	if (musb->xceiv->state != old_state) {	1783	if (musb->xceiv->state != old_state) {
1797	old_state = musb->xceiv->state;	1784	old_state = musb->xceiv->state;
1798	sysfs_notify(&musb->controller->kobj, NULL, "mode");	1785	sysfs_notify(&musb->controller->kobj, NULL, "mode");
1799	}	1786	}
1800	}	1787	}
1801		1788
1802	/* --------------------------------------------------------------------------	1789	/* --------------------------------------------------------------------------
1803	* Init support	1790	* Init support
1804	*/	1791	*/
1805		1792
1806	static struct musb *__devinit	1793	static struct musb *__devinit
1807	allocate_instance(struct device *dev,	1794	allocate_instance(struct device *dev,
1808	struct musb_hdrc_config config, void __iomem mbase)	1795	struct musb_hdrc_config config, void __iomem mbase)
1809	{	1796	{
1810	struct musb *musb;	1797	struct musb *musb;
1811	struct musb_hw_ep *ep;	1798	struct musb_hw_ep *ep;
1812	int epnum;	1799	int epnum;
1813	struct usb_hcd *hcd;	1800	struct usb_hcd *hcd;
1814		1801
1815	hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));	1802	hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1816	if (!hcd)	1803	if (!hcd)
1817	return NULL;	1804	return NULL;
1818	/* usbcore sets dev->driver_data to hcd, and sometimes uses that... */	1805	/* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1819		1806
1820	musb = hcd_to_musb(hcd);	1807	musb = hcd_to_musb(hcd);
1821	INIT_LIST_HEAD(&musb->control);	1808	INIT_LIST_HEAD(&musb->control);
1822	INIT_LIST_HEAD(&musb->in_bulk);	1809	INIT_LIST_HEAD(&musb->in_bulk);
1823	INIT_LIST_HEAD(&musb->out_bulk);	1810	INIT_LIST_HEAD(&musb->out_bulk);
1824		1811
1825	hcd->uses_new_polling = 1;	1812	hcd->uses_new_polling = 1;
1826	hcd->has_tt = 1;	1813	hcd->has_tt = 1;
1827		1814
1828	musb->vbuserr_retry = VBUSERR_RETRY_COUNT;	1815	musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1829	musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;	1816	musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1830	dev_set_drvdata(dev, musb);	1817	dev_set_drvdata(dev, musb);
1831	musb->mregs = mbase;	1818	musb->mregs = mbase;
1832	musb->ctrl_base = mbase;	1819	musb->ctrl_base = mbase;
1833	musb->nIrq = -ENODEV;	1820	musb->nIrq = -ENODEV;
1834	musb->config = config;	1821	musb->config = config;
1835	BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);	1822	BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1836	for (epnum = 0, ep = musb->endpoints;	1823	for (epnum = 0, ep = musb->endpoints;
1837	epnum < musb->config->num_eps;	1824	epnum < musb->config->num_eps;
1838	epnum++, ep++) {	1825	epnum++, ep++) {
1839	ep->musb = musb;	1826	ep->musb = musb;
1840	ep->epnum = epnum;	1827	ep->epnum = epnum;
1841	}	1828	}
1842		1829
1843	musb->controller = dev;	1830	musb->controller = dev;
1844		1831
1845	return musb;	1832	return musb;
1846	}	1833	}
1847		1834
1848	static void musb_free(struct musb *musb)	1835	static void musb_free(struct musb *musb)
1849	{	1836	{
1850	/* this has multiple entry modes. it handles fault cleanup after	1837	/* this has multiple entry modes. it handles fault cleanup after
1851	* probe(), where things may be partially set up, as well as rmmod	1838	* probe(), where things may be partially set up, as well as rmmod
1852	* cleanup after everything's been de-activated.	1839	* cleanup after everything's been de-activated.
1853	*/	1840	*/
1854		1841
1855	#ifdef CONFIG_SYSFS	1842	#ifdef CONFIG_SYSFS
1856	sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);	1843	sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1857	#endif	1844	#endif
1858		1845
1859	if (musb->nIrq >= 0) {	1846	if (musb->nIrq >= 0) {
1860	if (musb->irq_wake)	1847	if (musb->irq_wake)
1861	disable_irq_wake(musb->nIrq);	1848	disable_irq_wake(musb->nIrq);
1862	free_irq(musb->nIrq, musb);	1849	free_irq(musb->nIrq, musb);
1863	}	1850	}
1864	if (is_dma_capable() && musb->dma_controller) {	1851	if (is_dma_capable() && musb->dma_controller) {
1865	struct dma_controller *c = musb->dma_controller;	1852	struct dma_controller *c = musb->dma_controller;
1866		1853
1867	(void) c->stop(c);	1854	(void) c->stop(c);
1868	dma_controller_destroy(c);	1855	dma_controller_destroy(c);
1869	}	1856	}
1870		1857
1871	usb_put_hcd(musb_to_hcd(musb));	1858	usb_put_hcd(musb_to_hcd(musb));
1872	}	1859	}
1873		1860
1874	/*	1861	/*
1875	* Perform generic per-controller initialization.	1862	* Perform generic per-controller initialization.
1876	*	1863	*
1877	* @pDevice: the controller (already clocked, etc)	1864	* @pDevice: the controller (already clocked, etc)
1878	* @nIrq: irq	1865	* @nIrq: irq
1879	* @mregs: virtual address of controller registers,	1866	* @mregs: virtual address of controller registers,
1880	* not yet corrected for platform-specific offsets	1867	* not yet corrected for platform-specific offsets
1881	*/	1868	*/
1882	static int __devinit	1869	static int __devinit
1883	musb_init_controller(struct device dev, int nIrq, void __iomem ctrl)	1870	musb_init_controller(struct device dev, int nIrq, void __iomem ctrl)
1884	{	1871	{
1885	int status;	1872	int status;
1886	struct musb *musb;	1873	struct musb *musb;
1887	struct musb_hdrc_platform_data *plat = dev->platform_data;	1874	struct musb_hdrc_platform_data *plat = dev->platform_data;
		1875	struct usb_hcd *hcd;
1888		1876
1889	/* The driver might handle more features than the board; OK.	1877	/* The driver might handle more features than the board; OK.
1890	* Fail when the board needs a feature that's not enabled.	1878	* Fail when the board needs a feature that's not enabled.
1891	*/	1879	*/
1892	if (!plat) {	1880	if (!plat) {
1893	dev_dbg(dev, "no platform_data?\n");	1881	dev_dbg(dev, "no platform_data?\n");
1894	status = -ENODEV;	1882	status = -ENODEV;
1895	goto fail0;	1883	goto fail0;
1896	}	1884	}
1897		1885
1898	/* allocate */	1886	/* allocate */
1899	musb = allocate_instance(dev, plat->config, ctrl);	1887	musb = allocate_instance(dev, plat->config, ctrl);
1900	if (!musb) {	1888	if (!musb) {
1901	status = -ENOMEM;	1889	status = -ENOMEM;
1902	goto fail0;	1890	goto fail0;
1903	}	1891	}
1904		1892
1905	pm_runtime_use_autosuspend(musb->controller);	1893	pm_runtime_use_autosuspend(musb->controller);
1906	pm_runtime_set_autosuspend_delay(musb->controller, 200);	1894	pm_runtime_set_autosuspend_delay(musb->controller, 200);
1907	pm_runtime_enable(musb->controller);	1895	pm_runtime_enable(musb->controller);
1908		1896
1909	spin_lock_init(&musb->lock);	1897	spin_lock_init(&musb->lock);
1910	musb->board_mode = plat->mode;
1911	musb->board_set_power = plat->set_power;	1898	musb->board_set_power = plat->set_power;
1912	musb->min_power = plat->min_power;	1899	musb->min_power = plat->min_power;
1913	musb->ops = plat->platform_ops;	1900	musb->ops = plat->platform_ops;
1914		1901
1915	/* The musb_platform_init() call:	1902	/* The musb_platform_init() call:
1916	* - adjusts musb->mregs and musb->isr if needed,	1903	* - adjusts musb->mregs and musb->isr if needed,
1917	* - may initialize an integrated tranceiver	1904	* - may initialize an integrated tranceiver
1918	* - initializes musb->xceiv, usually by otg_get_phy()	1905	* - initializes musb->xceiv, usually by otg_get_phy()
1919	* - stops powering VBUS	1906	* - stops powering VBUS
1920	*	1907	*
1921	* There are various transceiver configurations. Blackfin,	1908	* There are various transceiver configurations. Blackfin,
1922	* DaVinci, TUSB60x0, and others integrate them. OMAP3 uses	1909	* DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1923	* external/discrete ones in various flavors (twl4030 family,	1910	* external/discrete ones in various flavors (twl4030 family,
1924	* isp1504, non-OTG, etc) mostly hooking up through ULPI.	1911	* isp1504, non-OTG, etc) mostly hooking up through ULPI.
1925	*/	1912	*/
1926	musb->isr = generic_interrupt;	1913	musb->isr = generic_interrupt;
1927	status = musb_platform_init(musb);	1914	status = musb_platform_init(musb);
1928	if (status < 0)	1915	if (status < 0)
1929	goto fail1;	1916	goto fail1;
1930		1917
1931	if (!musb->isr) {	1918	if (!musb->isr) {
1932	status = -ENODEV;	1919	status = -ENODEV;
1933	goto fail2;	1920	goto fail2;
1934	}	1921	}
1935		1922
1936	if (!musb->xceiv->io_ops) {	1923	if (!musb->xceiv->io_ops) {
1937	musb->xceiv->io_dev = musb->controller;	1924	musb->xceiv->io_dev = musb->controller;
1938	musb->xceiv->io_priv = musb->mregs;	1925	musb->xceiv->io_priv = musb->mregs;
1939	musb->xceiv->io_ops = &musb_ulpi_access;	1926	musb->xceiv->io_ops = &musb_ulpi_access;
1940	}	1927	}
1941		1928
1942	pm_runtime_get_sync(musb->controller);	1929	pm_runtime_get_sync(musb->controller);
1943		1930
1944	#ifndef CONFIG_MUSB_PIO_ONLY	1931	#ifndef CONFIG_MUSB_PIO_ONLY
1945	if (use_dma && dev->dma_mask) {	1932	if (use_dma && dev->dma_mask) {
1946	struct dma_controller *c;	1933	struct dma_controller *c;
1947		1934
1948	c = dma_controller_create(musb, musb->mregs);	1935	c = dma_controller_create(musb, musb->mregs);
1949	musb->dma_controller = c;	1936	musb->dma_controller = c;
1950	if (c)	1937	if (c)
1951	(void) c->start(c);	1938	(void) c->start(c);
1952	}	1939	}
1953	#endif	1940	#endif
1954	/* ideally this would be abstracted in platform setup */	1941	/* ideally this would be abstracted in platform setup */
1955	if (!is_dma_capable() \|\| !musb->dma_controller)	1942	if (!is_dma_capable() \|\| !musb->dma_controller)
1956	dev->dma_mask = NULL;	1943	dev->dma_mask = NULL;
1957		1944
1958	/* be sure interrupts are disabled before connecting ISR */	1945	/* be sure interrupts are disabled before connecting ISR */
1959	musb_platform_disable(musb);	1946	musb_platform_disable(musb);
1960	musb_generic_disable(musb);	1947	musb_generic_disable(musb);
1961		1948
1962	/* setup musb parts of the core (especially endpoints) */	1949	/* setup musb parts of the core (especially endpoints) */
1963	status = musb_core_init(plat->config->multipoint	1950	status = musb_core_init(plat->config->multipoint
1964	? MUSB_CONTROLLER_MHDRC	1951	? MUSB_CONTROLLER_MHDRC
1965	: MUSB_CONTROLLER_HDRC, musb);	1952	: MUSB_CONTROLLER_HDRC, musb);
1966	if (status < 0)	1953	if (status < 0)
1967	goto fail3;	1954	goto fail3;
1968		1955
1969	setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);	1956	setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1970		1957
1971	/* Init IRQ workqueue before request_irq */	1958	/* Init IRQ workqueue before request_irq */
1972	INIT_WORK(&musb->irq_work, musb_irq_work);	1959	INIT_WORK(&musb->irq_work, musb_irq_work);
1973		1960
1974	/* attach to the IRQ */	1961	/* attach to the IRQ */
1975	if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {	1962	if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1976	dev_err(dev, "request_irq %d failed!\n", nIrq);	1963	dev_err(dev, "request_irq %d failed!\n", nIrq);
1977	status = -ENODEV;	1964	status = -ENODEV;
1978	goto fail3;	1965	goto fail3;
1979	}	1966	}
1980	musb->nIrq = nIrq;	1967	musb->nIrq = nIrq;
1981	/* FIXME this handles wakeup irqs wrong */	1968	/* FIXME this handles wakeup irqs wrong */
1982	if (enable_irq_wake(nIrq) == 0) {	1969	if (enable_irq_wake(nIrq) == 0) {
1983	musb->irq_wake = 1;	1970	musb->irq_wake = 1;
1984	device_init_wakeup(dev, 1);	1971	device_init_wakeup(dev, 1);
1985	} else {	1972	} else {
1986	musb->irq_wake = 0;	1973	musb->irq_wake = 0;
1987	}	1974	}
1988		1975
1989	/* host side needs more setup */	1976	/* host side needs more setup */
1990	if (is_host_enabled(musb)) {	1977	hcd = musb_to_hcd(musb);
1991	struct usb_hcd *hcd = musb_to_hcd(musb);	1978	otg_set_host(musb->xceiv->otg, &hcd->self);
		1979	hcd->self.otg_port = 1;
		1980	musb->xceiv->otg->host = &hcd->self;
		1981	hcd->power_budget = 2 * (plat->power ? : 250);
1992		1982
1993	otg_set_host(musb->xceiv->otg, &hcd->self);	1983	/* program PHY to use external vBus if required */
1994		1984	if (plat->extvbus) {
1995	if (is_otg_enabled(musb))	1985	u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1996	hcd->self.otg_port = 1;	1986	busctl \|= MUSB_ULPI_USE_EXTVBUS;
1997	musb->xceiv->otg->host = &hcd->self;	1987	musb_write_ulpi_buscontrol(musb->mregs, busctl);
1998	hcd->power_budget = 2 * (plat->power ? : 250);
1999
2000	/* program PHY to use external vBus if required */
2001	if (plat->extvbus) {
2002	u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2003	busctl \|= MUSB_ULPI_USE_EXTVBUS;
2004	musb_write_ulpi_buscontrol(musb->mregs, busctl);
2005	}
2006	}	1988	}
2007		1989
2008	/* For the host-only role, we can activate right away.	1990	MUSB_DEV_MODE(musb);
2009	* (We expect the ID pin to be forcibly grounded!!)	1991	musb->xceiv->otg->default_a = 0;
2010	* Otherwise, wait till the gadget driver hooks up.	1992	musb->xceiv->state = OTG_STATE_B_IDLE;
2011	*/
2012	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2013	struct usb_hcd *hcd = musb_to_hcd(musb);
2014		1993
2015	MUSB_HST_MODE(musb);	1994	status = musb_gadget_setup(musb);
2016	musb->xceiv->otg->default_a = 1;
2017	musb->xceiv->state = OTG_STATE_A_IDLE;
2018		1995
2019	status = usb_add_hcd(musb_to_hcd(musb), 0, 0);
2020
2021	hcd->self.uses_pio_for_control = 1;
2022	dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2023	"HOST", status,
2024	musb_readb(musb->mregs, MUSB_DEVCTL),
2025	(musb_readb(musb->mregs, MUSB_DEVCTL)
2026	& MUSB_DEVCTL_BDEVICE
2027	? 'B' : 'A'));
2028
2029	} else /* peripheral is enabled */ {
2030	MUSB_DEV_MODE(musb);
2031	musb->xceiv->otg->default_a = 0;
2032	musb->xceiv->state = OTG_STATE_B_IDLE;
2033
2034	status = musb_gadget_setup(musb);
2035
2036	dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2037	is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2038	status,
2039	musb_readb(musb->mregs, MUSB_DEVCTL));
2040
2041	}
2042	if (status < 0)	1996	if (status < 0)
2043	goto fail3;	1997	goto fail3;
2044		1998
2045	status = musb_init_debugfs(musb);	1999	status = musb_init_debugfs(musb);
2046	if (status < 0)	2000	if (status < 0)
2047	goto fail4;	2001	goto fail4;
2048		2002
2049	#ifdef CONFIG_SYSFS	2003	#ifdef CONFIG_SYSFS
2050	status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);	2004	status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2051	if (status)	2005	if (status)
2052	goto fail5;	2006	goto fail5;
2053	#endif	2007	#endif
2054		2008
2055	pm_runtime_put(musb->controller);	2009	pm_runtime_put(musb->controller);
2056		2010
2057	dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2058	({char *s;
2059	switch (musb->board_mode) {
2060	case MUSB_HOST: s = "Host"; break;
2061	case MUSB_PERIPHERAL: s = "Peripheral"; break;
2062	default: s = "OTG"; break;
2063	}; s; }),
2064	ctrl,
2065	(is_dma_capable() && musb->dma_controller)
2066	? "DMA" : "PIO",
2067	musb->nIrq);
2068
2069	return 0;	2011	return 0;
2070		2012
2071	fail5:	2013	fail5:
2072	musb_exit_debugfs(musb);	2014	musb_exit_debugfs(musb);
2073		2015
2074	fail4:	2016	fail4:
2075	if (!is_otg_enabled(musb) && is_host_enabled(musb))	2017	musb_gadget_cleanup(musb);
2076	usb_remove_hcd(musb_to_hcd(musb));
2077	else
2078	musb_gadget_cleanup(musb);
2079		2018
2080	fail3:	2019	fail3:
2081	pm_runtime_put_sync(musb->controller);	2020	pm_runtime_put_sync(musb->controller);
2082		2021
2083	fail2:	2022	fail2:
2084	if (musb->irq_wake)	2023	if (musb->irq_wake)
2085	device_init_wakeup(dev, 0);	2024	device_init_wakeup(dev, 0);
2086	musb_platform_exit(musb);	2025	musb_platform_exit(musb);
2087		2026
2088	fail1:	2027	fail1:
2089	dev_err(musb->controller,	2028	dev_err(musb->controller,
2090	"musb_init_controller failed with status %d\n", status);	2029	"musb_init_controller failed with status %d\n", status);
2091		2030
2092	musb_free(musb);	2031	musb_free(musb);
2093		2032
2094	fail0:	2033	fail0:
2095		2034
2096	return status;	2035	return status;
2097		2036
2098	}	2037	}
2099		2038
2100	/-------------------------------------------------------------------------/	2039	/-------------------------------------------------------------------------/
2101		2040
2102	/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just	2041	/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2103	* bridge to a platform device; this driver then suffices.	2042	* bridge to a platform device; this driver then suffices.
2104	*/	2043	*/
2105		2044
2106	#ifndef CONFIG_MUSB_PIO_ONLY	2045	#ifndef CONFIG_MUSB_PIO_ONLY
2107	static u64 *orig_dma_mask;	2046	static u64 *orig_dma_mask;
2108	#endif	2047	#endif
2109		2048
2110	static int __devinit musb_probe(struct platform_device *pdev)	2049	static int __devinit musb_probe(struct platform_device *pdev)
2111	{	2050	{
2112	struct device *dev = &pdev->dev;	2051	struct device *dev = &pdev->dev;
2113	int irq = platform_get_irq_byname(pdev, "mc");	2052	int irq = platform_get_irq_byname(pdev, "mc");
2114	int status;	2053	int status;
2115	struct resource *iomem;	2054	struct resource *iomem;
2116	void __iomem *base;	2055	void __iomem *base;
2117		2056
2118	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);	2057	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2119	if (!iomem \|\| irq <= 0)	2058	if (!iomem \|\| irq <= 0)
2120	return -ENODEV;	2059	return -ENODEV;
2121		2060
2122	base = ioremap(iomem->start, resource_size(iomem));	2061	base = ioremap(iomem->start, resource_size(iomem));
2123	if (!base) {	2062	if (!base) {
2124	dev_err(dev, "ioremap failed\n");	2063	dev_err(dev, "ioremap failed\n");
2125	return -ENOMEM;	2064	return -ENOMEM;
2126	}	2065	}
2127		2066
2128	#ifndef CONFIG_MUSB_PIO_ONLY	2067	#ifndef CONFIG_MUSB_PIO_ONLY
2129	/* clobbered by use_dma=n */	2068	/* clobbered by use_dma=n */
2130	orig_dma_mask = dev->dma_mask;	2069	orig_dma_mask = dev->dma_mask;
2131	#endif	2070	#endif
2132	status = musb_init_controller(dev, irq, base);	2071	status = musb_init_controller(dev, irq, base);
2133	if (status < 0)	2072	if (status < 0)
2134	iounmap(base);	2073	iounmap(base);
2135		2074
2136	return status;	2075	return status;
2137	}	2076	}
2138		2077
2139	static int __devexit musb_remove(struct platform_device *pdev)	2078	static int __devexit musb_remove(struct platform_device *pdev)
2140	{	2079	{
2141	struct musb *musb = dev_to_musb(&pdev->dev);	2080	struct musb *musb = dev_to_musb(&pdev->dev);
2142	void __iomem *ctrl_base = musb->ctrl_base;	2081	void __iomem *ctrl_base = musb->ctrl_base;
2143		2082
2144	/* this gets called on rmmod.	2083	/* this gets called on rmmod.
2145	* - Host mode: host may still be active	2084	* - Host mode: host may still be active
2146	* - Peripheral mode: peripheral is deactivated (or never-activated)	2085	* - Peripheral mode: peripheral is deactivated (or never-activated)
2147	* - OTG mode: both roles are deactivated (or never-activated)	2086	* - OTG mode: both roles are deactivated (or never-activated)
2148	*/	2087	*/
2149	musb_exit_debugfs(musb);	2088	musb_exit_debugfs(musb);
2150	musb_shutdown(pdev);	2089	musb_shutdown(pdev);
2151		2090
2152	musb_free(musb);	2091	musb_free(musb);
2153	iounmap(ctrl_base);	2092	iounmap(ctrl_base);
2154	device_init_wakeup(&pdev->dev, 0);	2093	device_init_wakeup(&pdev->dev, 0);
2155	#ifndef CONFIG_MUSB_PIO_ONLY	2094	#ifndef CONFIG_MUSB_PIO_ONLY
2156	pdev->dev.dma_mask = orig_dma_mask;	2095	pdev->dev.dma_mask = orig_dma_mask;
2157	#endif	2096	#endif
2158	return 0;	2097	return 0;
2159	}	2098	}
2160		2099
2161	#ifdef CONFIG_PM	2100	#ifdef CONFIG_PM
2162		2101
2163	static void musb_save_context(struct musb *musb)	2102	static void musb_save_context(struct musb *musb)
2164	{	2103	{
2165	int i;	2104	int i;
2166	void __iomem *musb_base = musb->mregs;	2105	void __iomem *musb_base = musb->mregs;
2167	void __iomem *epio;	2106	void __iomem *epio;
2168		2107
2169	if (is_host_enabled(musb)) {	2108	musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2170	musb->context.frame = musb_readw(musb_base, MUSB_FRAME);	2109	musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2171	musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);	2110	musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2172	musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2173	}
2174	musb->context.power = musb_readb(musb_base, MUSB_POWER);	2111	musb->context.power = musb_readb(musb_base, MUSB_POWER);
2175	musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);	2112	musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2176	musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);	2113	musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2177	musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);	2114	musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2178	musb->context.index = musb_readb(musb_base, MUSB_INDEX);	2115	musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2179	musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);	2116	musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2180		2117
2181	for (i = 0; i < musb->config->num_eps; ++i) {	2118	for (i = 0; i < musb->config->num_eps; ++i) {
2182	struct musb_hw_ep *hw_ep;	2119	struct musb_hw_ep *hw_ep;
2183		2120
2184	hw_ep = &musb->endpoints[i];	2121	hw_ep = &musb->endpoints[i];
2185	if (!hw_ep)	2122	if (!hw_ep)
2186	continue;	2123	continue;
2187		2124
2188	epio = hw_ep->regs;	2125	epio = hw_ep->regs;
2189	if (!epio)	2126	if (!epio)
2190	continue;	2127	continue;
2191		2128
2192	musb_writeb(musb_base, MUSB_INDEX, i);	2129	musb_writeb(musb_base, MUSB_INDEX, i);
2193	musb->context.index_regs[i].txmaxp =	2130	musb->context.index_regs[i].txmaxp =
2194	musb_readw(epio, MUSB_TXMAXP);	2131	musb_readw(epio, MUSB_TXMAXP);
2195	musb->context.index_regs[i].txcsr =	2132	musb->context.index_regs[i].txcsr =
2196	musb_readw(epio, MUSB_TXCSR);	2133	musb_readw(epio, MUSB_TXCSR);
2197	musb->context.index_regs[i].rxmaxp =	2134	musb->context.index_regs[i].rxmaxp =
2198	musb_readw(epio, MUSB_RXMAXP);	2135	musb_readw(epio, MUSB_RXMAXP);
2199	musb->context.index_regs[i].rxcsr =	2136	musb->context.index_regs[i].rxcsr =
2200	musb_readw(epio, MUSB_RXCSR);	2137	musb_readw(epio, MUSB_RXCSR);
2201		2138
2202	if (musb->dyn_fifo) {	2139	if (musb->dyn_fifo) {
2203	musb->context.index_regs[i].txfifoadd =	2140	musb->context.index_regs[i].txfifoadd =
2204	musb_read_txfifoadd(musb_base);	2141	musb_read_txfifoadd(musb_base);
2205	musb->context.index_regs[i].rxfifoadd =	2142	musb->context.index_regs[i].rxfifoadd =
2206	musb_read_rxfifoadd(musb_base);	2143	musb_read_rxfifoadd(musb_base);
2207	musb->context.index_regs[i].txfifosz =	2144	musb->context.index_regs[i].txfifosz =
2208	musb_read_txfifosz(musb_base);	2145	musb_read_txfifosz(musb_base);
2209	musb->context.index_regs[i].rxfifosz =	2146	musb->context.index_regs[i].rxfifosz =
2210	musb_read_rxfifosz(musb_base);	2147	musb_read_rxfifosz(musb_base);
2211	}	2148	}
2212	if (is_host_enabled(musb)) {
2213	musb->context.index_regs[i].txtype =
2214	musb_readb(epio, MUSB_TXTYPE);
2215	musb->context.index_regs[i].txinterval =
2216	musb_readb(epio, MUSB_TXINTERVAL);
2217	musb->context.index_regs[i].rxtype =
2218	musb_readb(epio, MUSB_RXTYPE);
2219	musb->context.index_regs[i].rxinterval =
2220	musb_readb(epio, MUSB_RXINTERVAL);
2221		2149
2222	musb->context.index_regs[i].txfunaddr =	2150	musb->context.index_regs[i].txtype =
2223	musb_read_txfunaddr(musb_base, i);	2151	musb_readb(epio, MUSB_TXTYPE);
2224	musb->context.index_regs[i].txhubaddr =	2152	musb->context.index_regs[i].txinterval =
2225	musb_read_txhubaddr(musb_base, i);	2153	musb_readb(epio, MUSB_TXINTERVAL);
2226	musb->context.index_regs[i].txhubport =	2154	musb->context.index_regs[i].rxtype =
2227	musb_read_txhubport(musb_base, i);	2155	musb_readb(epio, MUSB_RXTYPE);
		2156	musb->context.index_regs[i].rxinterval =
		2157	musb_readb(epio, MUSB_RXINTERVAL);
2228		2158
2229	musb->context.index_regs[i].rxfunaddr =	2159	musb->context.index_regs[i].txfunaddr =
2230	musb_read_rxfunaddr(musb_base, i);	2160	musb_read_txfunaddr(musb_base, i);
2231	musb->context.index_regs[i].rxhubaddr =	2161	musb->context.index_regs[i].txhubaddr =
2232	musb_read_rxhubaddr(musb_base, i);	2162	musb_read_txhubaddr(musb_base, i);
2233	musb->context.index_regs[i].rxhubport =	2163	musb->context.index_regs[i].txhubport =
2234	musb_read_rxhubport(musb_base, i);	2164	musb_read_txhubport(musb_base, i);
2235	}	2165
		2166	musb->context.index_regs[i].rxfunaddr =
		2167	musb_read_rxfunaddr(musb_base, i);
		2168	musb->context.index_regs[i].rxhubaddr =
		2169	musb_read_rxhubaddr(musb_base, i);
		2170	musb->context.index_regs[i].rxhubport =
		2171	musb_read_rxhubport(musb_base, i);
2236	}	2172	}
2237	}	2173	}
2238		2174
2239	static void musb_restore_context(struct musb *musb)	2175	static void musb_restore_context(struct musb *musb)
2240	{	2176	{
2241	int i;	2177	int i;
2242	void __iomem *musb_base = musb->mregs;	2178	void __iomem *musb_base = musb->mregs;
2243	void __iomem *ep_target_regs;	2179	void __iomem *ep_target_regs;
2244	void __iomem *epio;	2180	void __iomem *epio;
2245		2181
2246	if (is_host_enabled(musb)) {	2182	musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2247	musb_writew(musb_base, MUSB_FRAME, musb->context.frame);	2183	musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2248	musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);	2184	musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2249	musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2250	}
2251	musb_writeb(musb_base, MUSB_POWER, musb->context.power);	2185	musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2252	musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);	2186	musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2253	musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);	2187	musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2254	musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);	2188	musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2255	musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);	2189	musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2256		2190
2257	for (i = 0; i < musb->config->num_eps; ++i) {	2191	for (i = 0; i < musb->config->num_eps; ++i) {
2258	struct musb_hw_ep *hw_ep;	2192	struct musb_hw_ep *hw_ep;
2259		2193
2260	hw_ep = &musb->endpoints[i];	2194	hw_ep = &musb->endpoints[i];
2261	if (!hw_ep)	2195	if (!hw_ep)
2262	continue;	2196	continue;
2263		2197
2264	epio = hw_ep->regs;	2198	epio = hw_ep->regs;
2265	if (!epio)	2199	if (!epio)
2266	continue;	2200	continue;
2267		2201
2268	musb_writeb(musb_base, MUSB_INDEX, i);	2202	musb_writeb(musb_base, MUSB_INDEX, i);
2269	musb_writew(epio, MUSB_TXMAXP,	2203	musb_writew(epio, MUSB_TXMAXP,
2270	musb->context.index_regs[i].txmaxp);	2204	musb->context.index_regs[i].txmaxp);
2271	musb_writew(epio, MUSB_TXCSR,	2205	musb_writew(epio, MUSB_TXCSR,
2272	musb->context.index_regs[i].txcsr);	2206	musb->context.index_regs[i].txcsr);
2273	musb_writew(epio, MUSB_RXMAXP,	2207	musb_writew(epio, MUSB_RXMAXP,
2274	musb->context.index_regs[i].rxmaxp);	2208	musb->context.index_regs[i].rxmaxp);
2275	musb_writew(epio, MUSB_RXCSR,	2209	musb_writew(epio, MUSB_RXCSR,
2276	musb->context.index_regs[i].rxcsr);	2210	musb->context.index_regs[i].rxcsr);
2277		2211
2278	if (musb->dyn_fifo) {	2212	if (musb->dyn_fifo) {
2279	musb_write_txfifosz(musb_base,	2213	musb_write_txfifosz(musb_base,
2280	musb->context.index_regs[i].txfifosz);	2214	musb->context.index_regs[i].txfifosz);
2281	musb_write_rxfifosz(musb_base,	2215	musb_write_rxfifosz(musb_base,
2282	musb->context.index_regs[i].rxfifosz);	2216	musb->context.index_regs[i].rxfifosz);
2283	musb_write_txfifoadd(musb_base,	2217	musb_write_txfifoadd(musb_base,
2284	musb->context.index_regs[i].txfifoadd);	2218	musb->context.index_regs[i].txfifoadd);
2285	musb_write_rxfifoadd(musb_base,	2219	musb_write_rxfifoadd(musb_base,
2286	musb->context.index_regs[i].rxfifoadd);	2220	musb->context.index_regs[i].rxfifoadd);
2287	}	2221	}
2288		2222
2289	if (is_host_enabled(musb)) {	2223	musb_writeb(epio, MUSB_TXTYPE,
2290	musb_writeb(epio, MUSB_TXTYPE,
2291	musb->context.index_regs[i].txtype);	2224	musb->context.index_regs[i].txtype);
2292	musb_writeb(epio, MUSB_TXINTERVAL,	2225	musb_writeb(epio, MUSB_TXINTERVAL,
2293	musb->context.index_regs[i].txinterval);	2226	musb->context.index_regs[i].txinterval);
2294	musb_writeb(epio, MUSB_RXTYPE,	2227	musb_writeb(epio, MUSB_RXTYPE,
2295	musb->context.index_regs[i].rxtype);	2228	musb->context.index_regs[i].rxtype);
2296	musb_writeb(epio, MUSB_RXINTERVAL,	2229	musb_writeb(epio, MUSB_RXINTERVAL,
2297		2230
2298	musb->context.index_regs[i].rxinterval);	2231	musb->context.index_regs[i].rxinterval);
2299	musb_write_txfunaddr(musb_base, i,	2232	musb_write_txfunaddr(musb_base, i,
2300	musb->context.index_regs[i].txfunaddr);	2233	musb->context.index_regs[i].txfunaddr);
2301	musb_write_txhubaddr(musb_base, i,	2234	musb_write_txhubaddr(musb_base, i,
2302	musb->context.index_regs[i].txhubaddr);	2235	musb->context.index_regs[i].txhubaddr);
2303	musb_write_txhubport(musb_base, i,	2236	musb_write_txhubport(musb_base, i,
2304	musb->context.index_regs[i].txhubport);	2237	musb->context.index_regs[i].txhubport);
2305		2238
2306	ep_target_regs =	2239	ep_target_regs =
2307	musb_read_target_reg_base(i, musb_base);	2240	musb_read_target_reg_base(i, musb_base);
2308		2241
2309	musb_write_rxfunaddr(ep_target_regs,	2242	musb_write_rxfunaddr(ep_target_regs,
2310	musb->context.index_regs[i].rxfunaddr);	2243	musb->context.index_regs[i].rxfunaddr);
2311	musb_write_rxhubaddr(ep_target_regs,	2244	musb_write_rxhubaddr(ep_target_regs,
2312	musb->context.index_regs[i].rxhubaddr);	2245	musb->context.index_regs[i].rxhubaddr);
2313	musb_write_rxhubport(ep_target_regs,	2246	musb_write_rxhubport(ep_target_regs,
2314	musb->context.index_regs[i].rxhubport);	2247	musb->context.index_regs[i].rxhubport);
2315	}
2316	}	2248	}
2317	musb_writeb(musb_base, MUSB_INDEX, musb->context.index);	2249	musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2318	}	2250	}
2319		2251
2320	static int musb_suspend(struct device *dev)	2252	static int musb_suspend(struct device *dev)
2321	{	2253	{
2322	struct musb *musb = dev_to_musb(dev);	2254	struct musb *musb = dev_to_musb(dev);
2323	unsigned long flags;	2255	unsigned long flags;
2324		2256
2325	spin_lock_irqsave(&musb->lock, flags);	2257	spin_lock_irqsave(&musb->lock, flags);
2326		2258
2327	if (is_peripheral_active(musb)) {	2259	if (is_peripheral_active(musb)) {
2328	/* FIXME force disconnect unless we know USB will wake	2260	/* FIXME force disconnect unless we know USB will wake
2329	* the system up quickly enough to respond ...	2261	* the system up quickly enough to respond ...
2330	*/	2262	*/
2331	} else if (is_host_active(musb)) {	2263	} else if (is_host_active(musb)) {
2332	/* we know all the children are suspended; sometimes	2264	/* we know all the children are suspended; sometimes
2333	* they will even be wakeup-enabled.	2265	* they will even be wakeup-enabled.
2334	*/	2266	*/
2335	}	2267	}
2336		2268
2337	spin_unlock_irqrestore(&musb->lock, flags);	2269	spin_unlock_irqrestore(&musb->lock, flags);
2338	return 0;	2270	return 0;
2339	}	2271	}
2340		2272
2341	static int musb_resume_noirq(struct device *dev)	2273	static int musb_resume_noirq(struct device *dev)
2342	{	2274	{
2343	/* for static cmos like DaVinci, register values were preserved	2275	/* for static cmos like DaVinci, register values were preserved
2344	* unless for some reason the whole soc powered down or the USB	2276	* unless for some reason the whole soc powered down or the USB
2345	* module got reset through the PSC (vs just being disabled).	2277	* module got reset through the PSC (vs just being disabled).
2346	*/	2278	*/
2347	return 0;	2279	return 0;
2348	}	2280	}
2349		2281
2350	static int musb_runtime_suspend(struct device *dev)	2282	static int musb_runtime_suspend(struct device *dev)
2351	{	2283	{
2352	struct musb *musb = dev_to_musb(dev);	2284	struct musb *musb = dev_to_musb(dev);
2353		2285
2354	musb_save_context(musb);	2286	musb_save_context(musb);
2355		2287
2356	return 0;	2288	return 0;
2357	}	2289	}
2358		2290
2359	static int musb_runtime_resume(struct device *dev)	2291	static int musb_runtime_resume(struct device *dev)
2360	{	2292	{
2361	struct musb *musb = dev_to_musb(dev);	2293	struct musb *musb = dev_to_musb(dev);
2362	static int first = 1;	2294	static int first = 1;
2363		2295
2364	/*	2296	/*
2365	* When pm_runtime_get_sync called for the first time in driver	2297	* When pm_runtime_get_sync called for the first time in driver
2366	* init, some of the structure is still not initialized which is	2298	* init, some of the structure is still not initialized which is
2367	* used in restore function. But clock needs to be	2299	* used in restore function. But clock needs to be
2368	* enabled before any register access, so	2300	* enabled before any register access, so
2369	* pm_runtime_get_sync has to be called.	2301	* pm_runtime_get_sync has to be called.
2370	* Also context restore without save does not make	2302	* Also context restore without save does not make
2371	* any sense	2303	* any sense
2372	*/	2304	*/
2373	if (!first)	2305	if (!first)
2374	musb_restore_context(musb);	2306	musb_restore_context(musb);
2375	first = 0;	2307	first = 0;
2376		2308
2377	return 0;	2309	return 0;
2378	}	2310	}
2379		2311
2380	static const struct dev_pm_ops musb_dev_pm_ops = {	2312	static const struct dev_pm_ops musb_dev_pm_ops = {
2381	.suspend = musb_suspend,	2313	.suspend = musb_suspend,
2382	.resume_noirq = musb_resume_noirq,	2314	.resume_noirq = musb_resume_noirq,
2383	.runtime_suspend = musb_runtime_suspend,	2315	.runtime_suspend = musb_runtime_suspend,
2384	.runtime_resume = musb_runtime_resume,	2316	.runtime_resume = musb_runtime_resume,
2385	};	2317	};
2386		2318
2387	#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)	2319	#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2388	#else	2320	#else
2389	#define MUSB_DEV_PM_OPS NULL	2321	#define MUSB_DEV_PM_OPS NULL
2390	#endif	2322	#endif
2391		2323
2392	static struct platform_driver musb_driver = {	2324	static struct platform_driver musb_driver = {
2393	.driver = {	2325	.driver = {
2394	.name = (char *)musb_driver_name,	2326	.name = (char *)musb_driver_name,
2395	.bus = &platform_bus_type,	2327	.bus = &platform_bus_type,
2396	.owner = THIS_MODULE,	2328	.owner = THIS_MODULE,
2397	.pm = MUSB_DEV_PM_OPS,	2329	.pm = MUSB_DEV_PM_OPS,
2398	},	2330	},
2399	.probe = musb_probe,	2331	.probe = musb_probe,
2400	.remove = __devexit_p(musb_remove),	2332	.remove = __devexit_p(musb_remove),
2401	.shutdown = musb_shutdown,	2333	.shutdown = musb_shutdown,
2402	};	2334	};
2403		2335
2404	/-------------------------------------------------------------------------/	2336	/-------------------------------------------------------------------------/
2405		2337
2406	static int __init musb_init(void)	2338	static int __init musb_init(void)
2407	{	2339	{
2408	if (usb_disabled())	2340	if (usb_disabled())
2409	return 0;	2341	return 0;
2410		2342
2411	pr_info("%s: version " MUSB_VERSION ", "	2343	pr_info("%s: version " MUSB_VERSION ", "
2412	"?dma?"	2344	"?dma?"
2413	", "	2345	", "

drivers/usb/musb/musb_core.h

Diff comments View file @ 032ec49

 /*
  * MUSB OTG driver defines
  *
  * Copyright 2005 Mentor Graphics Corporation
  * Copyright (C) 2005-2006 by Texas Instruments
  * Copyright (C) 2006-2007 Nokia Corporation
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  * General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  *
  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  */
 #ifndef __MUSB_CORE_H__
 #define __MUSB_CORE_H__
 #include <linux/slab.h>
 #include <linux/list.h>
 #include <linux/interrupt.h>
 #include <linux/errno.h>
 #include <linux/timer.h>
 #include <linux/device.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/musb.h>
 struct musb;
 struct musb_hw_ep;
 struct musb_ep;
 /* Helper defines for struct musb->hwvers */
 #define MUSB_HWVERS_MAJOR(x)	((x >> 10) & 0x1f)
 #define MUSB_HWVERS_MINOR(x)	(x & 0x3ff)
 #define MUSB_HWVERS_RC		0x8000
 #define MUSB_HWVERS_1300	0x52C
 #define MUSB_HWVERS_1400	0x590
 #define MUSB_HWVERS_1800	0x720
 #define MUSB_HWVERS_1900	0x784
 #define MUSB_HWVERS_2000	0x800
 #include "musb_debug.h"
 #include "musb_dma.h"
 #include "musb_io.h"
 #include "musb_regs.h"
 #include "musb_gadget.h"
 #include <linux/usb/hcd.h>
 #include "musb_host.h"
-#define	is_peripheral_enabled(musb)	((musb)->board_mode != MUSB_HOST)
-#define	is_host_enabled(musb)		((musb)->board_mode != MUSB_PERIPHERAL)
-#define	is_otg_enabled(musb)		((musb)->board_mode == MUSB_OTG)
 /* NOTE:  otg and peripheral-only state machines start at B_IDLE.
  * OTG or host-only go to A_IDLE when ID is sensed.
  */
 #define is_peripheral_active(m)		(!(m)->is_host)
 #define is_host_active(m)		((m)->is_host)
 #ifdef CONFIG_PROC_FS
 #include <linux/fs.h>
 #define MUSB_CONFIG_PROC_FS
 #endif
 /****************************** PERIPHERAL ROLE *****************************/
 #define	is_peripheral_capable()	(1)
 extern irqreturn_t musb_g_ep0_irq(struct musb *);
 extern void musb_g_tx(struct musb *, u8);
 extern void musb_g_rx(struct musb *, u8);
 extern void musb_g_reset(struct musb *);
 extern void musb_g_suspend(struct musb *);
 extern void musb_g_resume(struct musb *);
 extern void musb_g_wakeup(struct musb *);
 extern void musb_g_disconnect(struct musb *);
 /****************************** HOST ROLE ***********************************/
 #define	is_host_capable()	(1)
 extern irqreturn_t musb_h_ep0_irq(struct musb *);
 extern void musb_host_tx(struct musb *, u8);
 extern void musb_host_rx(struct musb *, u8);
 /****************************** CONSTANTS ********************************/
 #ifndef MUSB_C_NUM_EPS
 #define MUSB_C_NUM_EPS ((u8)16)
 #endif
 #ifndef MUSB_MAX_END0_PACKET
 #define MUSB_MAX_END0_PACKET ((u16)MUSB_EP0_FIFOSIZE)
 #endif
 /* host side ep0 states */
 enum musb_h_ep0_state {
 	MUSB_EP0_IDLE,
 	MUSB_EP0_START,			/* expect ack of setup */
 	MUSB_EP0_IN,			/* expect IN DATA */
 	MUSB_EP0_OUT,			/* expect ack of OUT DATA */
 	MUSB_EP0_STATUS,		/* expect ack of STATUS */
 } __attribute__ ((packed));
 /* peripheral side ep0 states */
 enum musb_g_ep0_state {
 	MUSB_EP0_STAGE_IDLE,		/* idle, waiting for SETUP */
 	MUSB_EP0_STAGE_SETUP,		/* received SETUP */
 	MUSB_EP0_STAGE_TX,		/* IN data */
 	MUSB_EP0_STAGE_RX,		/* OUT data */
 	MUSB_EP0_STAGE_STATUSIN,	/* (after OUT data) */
 	MUSB_EP0_STAGE_STATUSOUT,	/* (after IN data) */
 	MUSB_EP0_STAGE_ACKWAIT,		/* after zlp, before statusin */
 } __attribute__ ((packed));
 /*
  * OTG protocol constants.  See USB OTG 1.3 spec,
  * sections 5.5 "Device Timings" and 6.6.5 "Timers".
  */
 #define OTG_TIME_A_WAIT_VRISE	100		/* msec (max) */
 #define OTG_TIME_A_WAIT_BCON	1100		/* min 1 second */
 #define OTG_TIME_A_AIDL_BDIS	200		/* min 200 msec */
 #define OTG_TIME_B_ASE0_BRST	100		/* min 3.125 ms */
 /*************************** REGISTER ACCESS ********************************/
 /* Endpoint registers (other than dynfifo setup) can be accessed either
  * directly with the "flat" model, or after setting up an index register.
  */
 #if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
 		|| defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
 		|| defined(CONFIG_ARCH_OMAP4)
 /* REVISIT indexed access seemed to
  * misbehave (on DaVinci) for at least peripheral IN ...
  */
 #define	MUSB_FLAT_REG
 #endif
 /* TUSB mapping: "flat" plus ep0 special cases */
 #if defined(CONFIG_USB_MUSB_TUSB6010) || \
 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
 #define musb_ep_select(_mbase, _epnum) \
 	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
 #define	MUSB_EP_OFFSET			MUSB_TUSB_OFFSET
 /* "flat" mapping: each endpoint has its own i/o address */
 #elif	defined(MUSB_FLAT_REG)
 #define musb_ep_select(_mbase, _epnum)	(((void)(_mbase)), ((void)(_epnum)))
 #define	MUSB_EP_OFFSET			MUSB_FLAT_OFFSET
 /* "indexed" mapping: INDEX register controls register bank select */
 #else
 #define musb_ep_select(_mbase, _epnum) \
 	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
 #define	MUSB_EP_OFFSET			MUSB_INDEXED_OFFSET
 #endif
 /****************************** FUNCTIONS ********************************/
 #define MUSB_HST_MODE(_musb)\
 	{ (_musb)->is_host = true; }
 #define MUSB_DEV_MODE(_musb) \
 	{ (_musb)->is_host = false; }
 #define test_devctl_hst_mode(_x) \
 	(musb_readb((_x)->mregs, MUSB_DEVCTL)&MUSB_DEVCTL_HM)
 #define MUSB_MODE(musb) ((musb)->is_host ? "Host" : "Peripheral")
 /******************************** TYPES *************************************/
 /**
  * struct musb_platform_ops - Operations passed to musb_core by HW glue layer
  * @init:	turns on clocks, sets up platform-specific registers, etc
  * @exit:	undoes @init
  * @set_mode:	forcefully changes operating mode
  * @try_ilde:	tries to idle the IP
  * @vbus_status: returns vbus status if possible
  * @set_vbus:	forces vbus status
  * @adjust_channel_params: pre check for standard dma channel_program func
  */
 struct musb_platform_ops {
 	int	(*init)(struct musb *musb);
 	int	(*exit)(struct musb *musb);
 	void	(*enable)(struct musb *musb);
 	void	(*disable)(struct musb *musb);
 	int	(*set_mode)(struct musb *musb, u8 mode);
 	void	(*try_idle)(struct musb *musb, unsigned long timeout);
 	int	(*vbus_status)(struct musb *musb);
 	void	(*set_vbus)(struct musb *musb, int on);
 	int	(*adjust_channel_params)(struct dma_channel *channel,
 				u16 packet_sz, u8 *mode,
 				dma_addr_t *dma_addr, u32 *len);
 };
 /*
  * struct musb_hw_ep - endpoint hardware (bidirectional)
  *
  * Ordered slightly for better cacheline locality.
  */
 struct musb_hw_ep {
 	struct musb		*musb;
 	void __iomem		*fifo;
 	void __iomem		*regs;
 #if defined(CONFIG_USB_MUSB_TUSB6010) || \
 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
 	void __iomem		*conf;
 #endif
 	/* index in musb->endpoints[]  */
 	u8			epnum;
 	/* hardware configuration, possibly dynamic */
 	bool			is_shared_fifo;
 	bool			tx_double_buffered;
 	bool			rx_double_buffered;
 	u16			max_packet_sz_tx;
 	u16			max_packet_sz_rx;
 	struct dma_channel	*tx_channel;
 	struct dma_channel	*rx_channel;
 #if defined(CONFIG_USB_MUSB_TUSB6010) || \
 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
 	/* TUSB has "asynchronous" and "synchronous" dma modes */
 	dma_addr_t		fifo_async;
 	dma_addr_t		fifo_sync;
 	void __iomem		*fifo_sync_va;
 #endif
 	void __iomem		*target_regs;
 	/* currently scheduled peripheral endpoint */
 	struct musb_qh		*in_qh;
 	struct musb_qh		*out_qh;
 	u8			rx_reinit;
 	u8			tx_reinit;
 	/* peripheral side */
 	struct musb_ep		ep_in;			/* TX */
 	struct musb_ep		ep_out;			/* RX */
 };
 static inline struct musb_request *next_in_request(struct musb_hw_ep *hw_ep)
 {
 	return next_request(&hw_ep->ep_in);
 }
 static inline struct musb_request *next_out_request(struct musb_hw_ep *hw_ep)
 {
 	return next_request(&hw_ep->ep_out);
 }
 struct musb_csr_regs {
 	/* FIFO registers */
 	u16 txmaxp, txcsr, rxmaxp, rxcsr;
 	u16 rxfifoadd, txfifoadd;
 	u8 txtype, txinterval, rxtype, rxinterval;
 	u8 rxfifosz, txfifosz;
 	u8 txfunaddr, txhubaddr, txhubport;
 	u8 rxfunaddr, rxhubaddr, rxhubport;
 };
 struct musb_context_registers {
 	u8 power;
 	u16 intrtxe, intrrxe;
 	u8 intrusbe;
 	u16 frame;
 	u8 index, testmode;
 	u8 devctl, busctl, misc;
 	u32 otg_interfsel;
 	struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
 };
 /*
  * struct musb - Driver instance data.
  */
 struct musb {
 	/* device lock */
 	spinlock_t		lock;
 	const struct musb_platform_ops *ops;
 	struct musb_context_registers context;
 	irqreturn_t		(*isr)(int, void *);
 	struct work_struct	irq_work;
 	u16			hwvers;
 /* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
 #define MUSB_PORT_STAT_RESUME	(1 << 31)
 	u32			port1_status;
 	unsigned long		rh_timer;
 	enum musb_h_ep0_state	ep0_stage;
 	/* bulk traffic normally dedicates endpoint hardware, and each
 	 * direction has its own ring of host side endpoints.
 	 * we try to progress the transfer at the head of each endpoint's
 	 * queue until it completes or NAKs too much; then we try the next
 	 * endpoint.
 	 */
 	struct musb_hw_ep	*bulk_ep;
 	struct list_head	control;	/* of musb_qh */
 	struct list_head	in_bulk;	/* of musb_qh */
 	struct list_head	out_bulk;	/* of musb_qh */
 	struct timer_list	otg_timer;
 	struct notifier_block	nb;
 	struct dma_controller	*dma_controller;
 	struct device		*controller;
 	void __iomem		*ctrl_base;
 	void __iomem		*mregs;
 #if defined(CONFIG_USB_MUSB_TUSB6010) || \
 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
 	dma_addr_t		async;
 	dma_addr_t		sync;
 	void __iomem		*sync_va;
 #endif
 	/* passed down from chip/board specific irq handlers */
 	u8			int_usb;
 	u16			int_rx;
 	u16			int_tx;
 	struct usb_phy		*xceiv;
 	int nIrq;
 	unsigned		irq_wake:1;
 	struct musb_hw_ep	 endpoints[MUSB_C_NUM_EPS];
 #define control_ep		endpoints
 #define VBUSERR_RETRY_COUNT	3
 	u16			vbuserr_retry;
 	u16 epmask;
 	u8 nr_endpoints;
-	u8 board_mode;		/* enum musb_mode */
 	int			(*board_set_power)(int state);
 	u8			min_power;	/* vbus for periph, in mA/2 */
 	bool			is_host;
 	int			a_wait_bcon;	/* VBUS timeout in msecs */
 	unsigned long		idle_timeout;	/* Next timeout in jiffies */
 	/* active means connected and not suspended */
 	unsigned		is_active:1;
 	unsigned is_multipoint:1;
 	unsigned ignore_disconnect:1;	/* during bus resets */
 	unsigned		hb_iso_rx:1;	/* high bandwidth iso rx? */
 	unsigned		hb_iso_tx:1;	/* high bandwidth iso tx? */
 	unsigned		dyn_fifo:1;	/* dynamic FIFO supported? */
 	unsigned		bulk_split:1;
 #define	can_bulk_split(musb,type) \
 	(((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split)
 	unsigned		bulk_combine:1;
 #define	can_bulk_combine(musb,type) \
 	(((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine)
 	/* is_suspended means USB B_PERIPHERAL suspend */
 	unsigned		is_suspended:1;
 	/* may_wakeup means remote wakeup is enabled */
 	unsigned		may_wakeup:1;
 	/* is_self_powered is reported in device status and the
 	 * config descriptor.  is_bus_powered means B_PERIPHERAL
 	 * draws some VBUS current; both can be true.
 	 */
 	unsigned		is_self_powered:1;
 	unsigned		is_bus_powered:1;
 	unsigned		set_address:1;
 	unsigned		test_mode:1;
 	unsigned		softconnect:1;
 	u8			address;
 	u8			test_mode_nr;
 	u16			ackpend;		/* ep0 */
 	enum musb_g_ep0_state	ep0_state;
 	struct usb_gadget	g;			/* the gadget */
 	struct usb_gadget_driver *gadget_driver;	/* its driver */
 	/*
 	 * FIXME: Remove this flag.
 	 *
 	 * This is only added to allow Blackfin to work
 	 * with current driver. For some unknown reason
 	 * Blackfin doesn't work with double buffering
 	 * and that's enabled by default.
 	 *
 	 * We added this flag to forcefully disable double
 	 * buffering until we get it working.
 	 */
 	unsigned                double_buffer_not_ok:1;
 	struct musb_hdrc_config	*config;
 #ifdef MUSB_CONFIG_PROC_FS
 	struct proc_dir_entry *proc_entry;
 #endif
 };
 static inline struct musb *gadget_to_musb(struct usb_gadget *g)
 {
 	return container_of(g, struct musb, g);
 }
 #ifdef CONFIG_BLACKFIN
 static inline int musb_read_fifosize(struct musb *musb,
 		struct musb_hw_ep *hw_ep, u8 epnum)
 {
 	musb->nr_endpoints++;
 	musb->epmask |= (1 << epnum);
 	if (epnum < 5) {
 		hw_ep->max_packet_sz_tx = 128;
 		hw_ep->max_packet_sz_rx = 128;
 	} else {
 		hw_ep->max_packet_sz_tx = 1024;
 		hw_ep->max_packet_sz_rx = 1024;
 	}
 	hw_ep->is_shared_fifo = false;
 	return 0;
 }
 static inline void musb_configure_ep0(struct musb *musb)
 {
 	musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
 	musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
 	musb->endpoints[0].is_shared_fifo = true;
 }
 #else
 static inline int musb_read_fifosize(struct musb *musb,
 		struct musb_hw_ep *hw_ep, u8 epnum)
 {
 	void __iomem *mbase = musb->mregs;
 	u8 reg = 0;
 	/* read from core using indexed model */
 	reg = musb_readb(mbase, MUSB_EP_OFFSET(epnum, MUSB_FIFOSIZE));
 	/* 0's returned when no more endpoints */
 	if (!reg)
 		return -ENODEV;
 	musb->nr_endpoints++;
 	musb->epmask |= (1 << epnum);
 	hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
 	/* shared TX/RX FIFO? */
 	if ((reg & 0xf0) == 0xf0) {
 		hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
 		hw_ep->is_shared_fifo = true;
 		return 0;
 	} else {
 		hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
 		hw_ep->is_shared_fifo = false;
 	}
 	return 0;
 }
 static inline void musb_configure_ep0(struct musb *musb)
 {
 	musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
 	musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
 	musb->endpoints[0].is_shared_fifo = true;
 }
 #endif /* CONFIG_BLACKFIN */
 /***************************** Glue it together *****************************/
 extern const char musb_driver_name[];
 extern void musb_start(struct musb *musb);
 extern void musb_stop(struct musb *musb);
 extern void musb_write_fifo(struct musb_hw_ep *ep, u16 len, const u8 *src);
 extern void musb_read_fifo(struct musb_hw_ep *ep, u16 len, u8 *dst);
 extern void musb_load_testpacket(struct musb *);
 extern irqreturn_t musb_interrupt(struct musb *);
 extern void musb_hnp_stop(struct musb *musb);
 static inline void musb_platform_set_vbus(struct musb *musb, int is_on)
 {
 	if (musb->ops->set_vbus)
 		musb->ops->set_vbus(musb, is_on);
 }
 static inline void musb_platform_enable(struct musb *musb)
 {
 	if (musb->ops->enable)
 		musb->ops->enable(musb);
 }
 static inline void musb_platform_disable(struct musb *musb)
 {
 	if (musb->ops->disable)
 		musb->ops->disable(musb);
 }
 static inline int musb_platform_set_mode(struct musb *musb, u8 mode)
 {
 	if (!musb->ops->set_mode)
 		return 0;
 	return musb->ops->set_mode(musb, mode);
 }
 static inline void musb_platform_try_idle(struct musb *musb,
 		unsigned long timeout)
 {
 	if (musb->ops->try_idle)
 		musb->ops->try_idle(musb, timeout);
 }
 static inline int musb_platform_get_vbus_status(struct musb *musb)
 {
 	if (!musb->ops->vbus_status)
 		return 0;
 	return musb->ops->vbus_status(musb);
 }
 static inline int musb_platform_init(struct musb *musb)
 {
 	if (!musb->ops->init)
 		return -EINVAL;
 	return musb->ops->init(musb);
 }
 static inline int musb_platform_exit(struct musb *musb)
 {
 	if (!musb->ops->exit)
 		return -EINVAL;
 	return musb->ops->exit(musb);
 }
 #endif	/* __MUSB_CORE_H__ */

drivers/usb/musb/musb_dsps.c

Diff comments View file @ 032ec49

 /*
  * Texas Instruments DSPS platforms "glue layer"
  *
  * Copyright (C) 2012, by Texas Instruments
  *
  * Based on the am35x "glue layer" code.
  *
  * This file is part of the Inventra Controller Driver for Linux.
  *
  * The Inventra Controller Driver for Linux is free software; you
  * can redistribute it and/or modify it under the terms of the GNU
  * General Public License version 2 as published by the Free Software
  * Foundation.
  *
  * The Inventra Controller Driver for Linux is distributed in
  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  * without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  * License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with The Inventra Controller Driver for Linux ; if not,
  * write to the Free Software Foundation, Inc., 59 Temple Place,
  * Suite 330, Boston, MA  02111-1307  USA
  *
  * musb_dsps.c will be a common file for all the TI DSPS platforms
  * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
  * For now only ti81x is using this and in future davinci.c, am35x.c
  * da8xx.c would be merged to this file after testing.
  */
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/pm_runtime.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_address.h>
 #include <plat/usb.h>
 #include "musb_core.h"
 /**
  * avoid using musb_readx()/musb_writex() as glue layer should not be
  * dependent on musb core layer symbols.
  */
 static inline u8 dsps_readb(const void __iomem *addr, unsigned offset)
 	{ return __raw_readb(addr + offset); }
 static inline u32 dsps_readl(const void __iomem *addr, unsigned offset)
 	{ return __raw_readl(addr + offset); }
 static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data)
 	{ __raw_writeb(data, addr + offset); }
 static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data)
 	{ __raw_writel(data, addr + offset); }
 /**
  * DSPS musb wrapper register offset.
  * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
  * musb ips.
  */
 struct dsps_musb_wrapper {
 	u16	revision;
 	u16	control;
 	u16	status;
 	u16	eoi;
 	u16	epintr_set;
 	u16	epintr_clear;
 	u16	epintr_status;
 	u16	coreintr_set;
 	u16	coreintr_clear;
 	u16	coreintr_status;
 	u16	phy_utmi;
 	u16	mode;
 	/* bit positions for control */
 	unsigned	reset:5;
 	/* bit positions for interrupt */
 	unsigned	usb_shift:5;
 	u32		usb_mask;
 	u32		usb_bitmap;
 	unsigned	drvvbus:5;
 	unsigned	txep_shift:5;
 	u32		txep_mask;
 	u32		txep_bitmap;
 	unsigned	rxep_shift:5;
 	u32		rxep_mask;
 	u32		rxep_bitmap;
 	/* bit positions for phy_utmi */
 	unsigned	otg_disable:5;
 	/* bit positions for mode */
 	unsigned	iddig:5;
 	/* miscellaneous stuff */
 	u32		musb_core_offset;
 	u8		poll_seconds;
 };
 /**
  * DSPS glue structure.
  */
 struct dsps_glue {
 	struct device *dev;
 	struct platform_device *musb;	/* child musb pdev */
 	const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
 	struct timer_list timer;	/* otg_workaround timer */
 };
 /**
  * dsps_musb_enable - enable interrupts
  */
 static void dsps_musb_enable(struct musb *musb)
 {
 	struct device *dev = musb->controller;
 	struct platform_device *pdev = to_platform_device(dev->parent);
 	struct dsps_glue *glue = platform_get_drvdata(pdev);
 	const struct dsps_musb_wrapper *wrp = glue->wrp;
 	void __iomem *reg_base = musb->ctrl_base;
 	u32 epmask, coremask;
 	/* Workaround: setup IRQs through both register sets. */
 	epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
 	       ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
 	coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
 	dsps_writel(reg_base, wrp->epintr_set, epmask);
 	dsps_writel(reg_base, wrp->coreintr_set, coremask);
 	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
-	if (is_otg_enabled(musb))
+	dsps_writel(reg_base, wrp->coreintr_set,
-		dsps_writel(reg_base, wrp->coreintr_set,
+		    (1 << wrp->drvvbus) << wrp->usb_shift);
-			    (1 << wrp->drvvbus) << wrp->usb_shift);
 }
 /**
  * dsps_musb_disable - disable HDRC and flush interrupts
  */
 static void dsps_musb_disable(struct musb *musb)
 {
 	struct device *dev = musb->controller;
 	struct platform_device *pdev = to_platform_device(dev->parent);
 	struct dsps_glue *glue = platform_get_drvdata(pdev);
 	const struct dsps_musb_wrapper *wrp = glue->wrp;
 	void __iomem *reg_base = musb->ctrl_base;
 	dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
 	dsps_writel(reg_base, wrp->epintr_clear,
 			 wrp->txep_bitmap | wrp->rxep_bitmap);
 	dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
 	dsps_writel(reg_base, wrp->eoi, 0);
 }
 static void otg_timer(unsigned long _musb)
 {
 	struct musb *musb = (void *)_musb;
 	void __iomem *mregs = musb->mregs;
 	struct device *dev = musb->controller;
 	struct platform_device *pdev = to_platform_device(dev->parent);
 	struct dsps_glue *glue = platform_get_drvdata(pdev);
 	const struct dsps_musb_wrapper *wrp = glue->wrp;
 	u8 devctl;
 	unsigned long flags;
 	/*
 	 * We poll because DSPS IP's won't expose several OTG-critical
 	 * status change events (from the transceiver) otherwise.
 	 */
 	devctl = dsps_readb(mregs, MUSB_DEVCTL);
 	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
 				otg_state_string(musb->xceiv->state));
 	spin_lock_irqsave(&musb->lock, flags);
 	switch (musb->xceiv->state) {
 	case OTG_STATE_A_WAIT_BCON:
 		devctl &= ~MUSB_DEVCTL_SESSION;
 		dsps_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 		devctl = dsps_readb(musb->mregs, MUSB_DEVCTL);
 		if (devctl & MUSB_DEVCTL_BDEVICE) {
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 			MUSB_DEV_MODE(musb);
 		} else {
 			musb->xceiv->state = OTG_STATE_A_IDLE;
 			MUSB_HST_MODE(musb);
 		}
 		break;
 	case OTG_STATE_A_WAIT_VFALL:
 		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 		dsps_writel(musb->ctrl_base, wrp->coreintr_set,
 			    MUSB_INTR_VBUSERROR << wrp->usb_shift);
 		break;
 	case OTG_STATE_B_IDLE:
-		if (!is_peripheral_enabled(musb))
-			break;
 		devctl = dsps_readb(mregs, MUSB_DEVCTL);
 		if (devctl & MUSB_DEVCTL_BDEVICE)
 			mod_timer(&glue->timer,
 					jiffies + wrp->poll_seconds * HZ);
 		else
 			musb->xceiv->state = OTG_STATE_A_IDLE;
 		break;
 	default:
 		break;
 	}
 	spin_unlock_irqrestore(&musb->lock, flags);
 }
 static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout)
 {
 	struct device *dev = musb->controller;
 	struct platform_device *pdev = to_platform_device(dev->parent);
 	struct dsps_glue *glue = platform_get_drvdata(pdev);
 	static unsigned long last_timer;
-	if (!is_otg_enabled(musb))
-		return;
 	if (timeout == 0)
 		timeout = jiffies + msecs_to_jiffies(3);
 	/* Never idle if active, or when VBUS timeout is not set as host */
 	if (musb->is_active || (musb->a_wait_bcon == 0 &&
 				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
 		dev_dbg(musb->controller, "%s active, deleting timer\n",
 				otg_state_string(musb->xceiv->state));
 		del_timer(&glue->timer);
 		last_timer = jiffies;
 		return;
 	}
 	if (time_after(last_timer, timeout) && timer_pending(&glue->timer)) {
 		dev_dbg(musb->controller,
 			"Longer idle timer already pending, ignoring...\n");
 		return;
 	}
 	last_timer = timeout;
 	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
 		otg_state_string(musb->xceiv->state),
 			jiffies_to_msecs(timeout - jiffies));
 	mod_timer(&glue->timer, timeout);
 }
 static irqreturn_t dsps_interrupt(int irq, void *hci)
 {
 	struct musb  *musb = hci;
 	void __iomem *reg_base = musb->ctrl_base;
 	struct device *dev = musb->controller;
 	struct platform_device *pdev = to_platform_device(dev->parent);
 	struct dsps_glue *glue = platform_get_drvdata(pdev);
 	const struct dsps_musb_wrapper *wrp = glue->wrp;
 	unsigned long flags;
 	irqreturn_t ret = IRQ_NONE;
 	u32 epintr, usbintr;
 	spin_lock_irqsave(&musb->lock, flags);
 	/* Get endpoint interrupts */
 	epintr = dsps_readl(reg_base, wrp->epintr_status);
 	musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
 	musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
 	if (epintr)
 		dsps_writel(reg_base, wrp->epintr_status, epintr);
 	/* Get usb core interrupts */
 	usbintr = dsps_readl(reg_base, wrp->coreintr_status);
 	if (!usbintr && !epintr)
 		goto eoi;
 	musb->int_usb =	(usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
 	if (usbintr)
 		dsps_writel(reg_base, wrp->coreintr_status, usbintr);
 	dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
 			usbintr, epintr);
 	/*
 	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
 	 * DSPS IP's missing ID change IRQ.  We need an ID change IRQ to
 	 * switch appropriately between halves of the OTG state machine.
 	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
 	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
 	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
 	 */
-	if ((usbintr & MUSB_INTR_BABBLE) && is_host_enabled(musb))
+	if (usbintr & MUSB_INTR_BABBLE)
 		pr_info("CAUTION: musb: Babble Interrupt Occured\n");
 	if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
 		int drvvbus = dsps_readl(reg_base, wrp->status);
 		void __iomem *mregs = musb->mregs;
 		u8 devctl = dsps_readb(mregs, MUSB_DEVCTL);
 		int err;
-		err = is_host_enabled(musb) && (musb->int_usb &
+		err = musb->int_usb & MUSB_INTR_VBUSERROR;
-						MUSB_INTR_VBUSERROR);
 		if (err) {
 			/*
 			 * The Mentor core doesn't debounce VBUS as needed
 			 * to cope with device connect current spikes. This
 			 * means it's not uncommon for bus-powered devices
 			 * to get VBUS errors during enumeration.
 			 *
 			 * This is a workaround, but newer RTL from Mentor
 			 * seems to allow a better one: "re"-starting sessions
 			 * without waiting for VBUS to stop registering in
 			 * devctl.
 			 */
 			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 			mod_timer(&glue->timer,
 					jiffies + wrp->poll_seconds * HZ);
 			WARNING("VBUS error workaround (delay coming)\n");
-		} else if (is_host_enabled(musb) && drvvbus) {
+		} else if (drvvbus) {
 			musb->is_active = 1;
 			MUSB_HST_MODE(musb);
 			musb->xceiv->otg->default_a = 1;
 			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 			del_timer(&glue->timer);
 		} else {
 			musb->is_active = 0;
 			MUSB_DEV_MODE(musb);
 			musb->xceiv->otg->default_a = 0;
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 		}
 		/* NOTE: this must complete power-on within 100 ms. */
 		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 				drvvbus ? "on" : "off",
 				otg_state_string(musb->xceiv->state),
 				err ? " ERROR" : "",
 				devctl);
 		ret = IRQ_HANDLED;
 	}
 	if (musb->int_tx || musb->int_rx || musb->int_usb)
 		ret |= musb_interrupt(musb);
  eoi:
 	/* EOI needs to be written for the IRQ to be re-asserted. */
 	if (ret == IRQ_HANDLED || epintr || usbintr)
 		dsps_writel(reg_base, wrp->eoi, 1);
 	/* Poll for ID change */
-	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
+	if (musb->xceiv->state == OTG_STATE_B_IDLE)
 		mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return ret;
 }
 static int dsps_musb_init(struct musb *musb)
 {
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct platform_device *pdev = to_platform_device(dev->parent);
 	struct dsps_glue *glue = platform_get_drvdata(pdev);
 	const struct dsps_musb_wrapper *wrp = glue->wrp;
 	struct omap_musb_board_data *data = plat->board_data;
 	void __iomem *reg_base = musb->ctrl_base;
 	u32 rev, val;
 	int status;
 	/* mentor core register starts at offset of 0x400 from musb base */
 	musb->mregs += wrp->musb_core_offset;
 	/* NOP driver needs change if supporting dual instance */
 	usb_nop_xceiv_register();
 	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
 	if (IS_ERR_OR_NULL(musb->xceiv))
 		return -ENODEV;
 	/* Returns zero if e.g. not clocked */
 	rev = dsps_readl(reg_base, wrp->revision);
 	if (!rev) {
 		status = -ENODEV;
 		goto err0;
 	}
-	if (is_host_enabled(musb))
+	setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
-		setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
 	/* Reset the musb */
 	dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
 	/* Start the on-chip PHY and its PLL. */
 	if (data->set_phy_power)
 		data->set_phy_power(1);
 	musb->isr = dsps_interrupt;
 	/* reset the otgdisable bit, needed for host mode to work */
 	val = dsps_readl(reg_base, wrp->phy_utmi);
 	val &= ~(1 << wrp->otg_disable);
 	dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
 	/* clear level interrupt */
 	dsps_writel(reg_base, wrp->eoi, 0);
 	return 0;
 err0:
 	usb_put_phy(musb->xceiv);
 	usb_nop_xceiv_unregister();
 	return status;
 }
 static int dsps_musb_exit(struct musb *musb)
 {
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
 	struct platform_device *pdev = to_platform_device(dev->parent);
 	struct dsps_glue *glue = platform_get_drvdata(pdev);
-	if (is_host_enabled(musb))
+	del_timer_sync(&glue->timer);
-		del_timer_sync(&glue->timer);
 	/* Shutdown the on-chip PHY and its PLL. */
 	if (data->set_phy_power)
 		data->set_phy_power(0);
 	/* NOP driver needs change if supporting dual instance */
 	usb_put_phy(musb->xceiv);
 	usb_nop_xceiv_unregister();
 	return 0;
 }
 static struct musb_platform_ops dsps_ops = {
 	.init		= dsps_musb_init,
 	.exit		= dsps_musb_exit,
 	.enable		= dsps_musb_enable,
 	.disable	= dsps_musb_disable,
 	.try_idle	= dsps_musb_try_idle,
 };
 static u64 musb_dmamask = DMA_BIT_MASK(32);
 static int __devinit dsps_create_musb_pdev(struct dsps_glue *glue, u8 id)
 {
 	struct device *dev = glue->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct musb_hdrc_platform_data  *pdata = dev->platform_data;
 	struct platform_device	*musb;
 	struct resource *res;
 	struct resource	resources[2];
 	char res_name[10];
 	int ret;
 	/* get memory resource */
 	sprintf(res_name, "musb%d", id);
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
 	if (!res) {
 		dev_err(dev, "%s get mem resource failed\n", res_name);
 		ret = -ENODEV;
 		goto err0;
 	}
 	res->parent = NULL;
 	resources[0] = *res;
 	/* get irq resource */
 	sprintf(res_name, "musb%d-irq", id);
 	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
 	if (!res) {
 		dev_err(dev, "%s get irq resource failed\n", res_name);
 		ret = -ENODEV;
 		goto err0;
 	}
 	strcpy((u8 *)res->name, "mc");
 	res->parent = NULL;
 	resources[1] = *res;
 	/* allocate the child platform device */
 	musb = platform_device_alloc("musb-hdrc", -1);
 	if (!musb) {
 		dev_err(dev, "failed to allocate musb device\n");
 		ret = -ENOMEM;
 		goto err0;
 	}
 	musb->dev.parent		= dev;
 	musb->dev.dma_mask		= &musb_dmamask;
 	musb->dev.coherent_dma_mask	= musb_dmamask;
 	glue->musb			= musb;
 	pdata->platform_ops		= &dsps_ops;
 	ret = platform_device_add_resources(musb, resources, 2);
 	if (ret) {
 		dev_err(dev, "failed to add resources\n");
 		goto err1;
 	}
 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 	if (ret) {
 		dev_err(dev, "failed to add platform_data\n");
 		goto err1;
 	}
 	ret = platform_device_add(musb);
 	if (ret) {
 		dev_err(dev, "failed to register musb device\n");
 		goto err1;
 	}
 	return 0;
 err1:
 	platform_device_put(musb);
 err0:
 	return ret;
 }
 static void __devexit dsps_delete_musb_pdev(struct dsps_glue *glue)
 {
 	platform_device_del(glue->musb);
 	platform_device_put(glue->musb);
 }
 static int __devinit dsps_probe(struct platform_device *pdev)
 {
 	const struct platform_device_id *id = platform_get_device_id(pdev);
 	const struct dsps_musb_wrapper *wrp =
 				(struct dsps_musb_wrapper *)id->driver_data;
 	struct dsps_glue *glue;
 	struct resource *iomem;
 	int ret;
 	/* allocate glue */
 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 	if (!glue) {
 		dev_err(&pdev->dev, "unable to allocate glue memory\n");
 		ret = -ENOMEM;
 		goto err0;
 	}
 	/* get memory resource */
 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!iomem) {
 		dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
 		ret = -ENODEV;
 		goto err1;
 	}
 	glue->dev = &pdev->dev;
 	glue->wrp = kmemdup(wrp, sizeof(*wrp), GFP_KERNEL);
 	if (!glue->wrp) {
 		dev_err(&pdev->dev, "failed to duplicate wrapper struct memory\n");
 		ret = -ENOMEM;
 		goto err1;
 	}
 	platform_set_drvdata(pdev, glue);
 	/* create the child platform device for first instances of musb */
 	ret = dsps_create_musb_pdev(glue, 0);
 	if (ret != 0) {
 		dev_err(&pdev->dev, "failed to create child pdev\n");
 		goto err2;
 	}
 	/* enable the usbss clocks */
 	pm_runtime_enable(&pdev->dev);
 	ret = pm_runtime_get_sync(&pdev->dev);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "pm_runtime_get_sync FAILED");
 		goto err3;
 	}
 	return 0;
 err3:
 	pm_runtime_disable(&pdev->dev);
 err2:
 	kfree(glue->wrp);
 err1:
 	kfree(glue);
 err0:
 	return ret;
 }
 static int __devexit dsps_remove(struct platform_device *pdev)
 {
 	struct dsps_glue *glue = platform_get_drvdata(pdev);
 	/* delete the child platform device */
 	dsps_delete_musb_pdev(glue);
 	/* disable usbss clocks */
 	pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 	kfree(glue->wrp);
 	kfree(glue);
 	return 0;
 }
 #ifdef CONFIG_PM_SLEEP
 static int dsps_suspend(struct device *dev)
 {
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
 	/* Shutdown the on-chip PHY and its PLL. */
 	if (data->set_phy_power)
 		data->set_phy_power(0);
 	return 0;
 }
 static int dsps_resume(struct device *dev)
 {
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
 	/* Start the on-chip PHY and its PLL. */
 	if (data->set_phy_power)
 		data->set_phy_power(1);
 	return 0;
 }
 #endif
 static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
 static const struct dsps_musb_wrapper ti81xx_driver_data __devinitconst = {
 	.revision		= 0x00,
 	.control		= 0x14,
 	.status			= 0x18,
 	.eoi			= 0x24,
 	.epintr_set		= 0x38,
 	.epintr_clear		= 0x40,
 	.epintr_status		= 0x30,
 	.coreintr_set		= 0x3c,
 	.coreintr_clear		= 0x44,
 	.coreintr_status	= 0x34,
 	.phy_utmi		= 0xe0,
 	.mode			= 0xe8,
 	.reset			= 0,
 	.otg_disable		= 21,
 	.iddig			= 8,
 	.usb_shift		= 0,
 	.usb_mask		= 0x1ff,
 	.usb_bitmap		= (0x1ff << 0),
 	.drvvbus		= 8,
 	.txep_shift		= 0,
 	.txep_mask		= 0xffff,
 	.txep_bitmap		= (0xffff << 0),
 	.rxep_shift		= 16,
 	.rxep_mask		= 0xfffe,
 	.rxep_bitmap		= (0xfffe << 16),
 	.musb_core_offset	= 0x400,
 	.poll_seconds		= 2,
 };
 static const struct platform_device_id musb_dsps_id_table[] __devinitconst = {
 	{
 		.name	= "musb-ti81xx",
 		.driver_data	= (kernel_ulong_t) &ti81xx_driver_data,
 	},
 	{  },	/* Terminating Entry */
 };
 MODULE_DEVICE_TABLE(platform, musb_dsps_id_table);
 static const struct of_device_id musb_dsps_of_match[] __devinitconst = {
 	{ .compatible = "musb-ti81xx", },
 	{ .compatible = "ti,ti81xx-musb", },
 	{ .compatible = "ti,am335x-musb", },
 	{  },
 };
 MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
 static struct platform_driver dsps_usbss_driver = {
 	.probe		= dsps_probe,
 	.remove         = __devexit_p(dsps_remove),
 	.driver         = {
 		.name   = "musb-dsps",
 		.pm	= &dsps_pm_ops,
 		.of_match_table	= musb_dsps_of_match,
 	},
 	.id_table	= musb_dsps_id_table,
 };
 MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
 MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
 MODULE_LICENSE("GPL v2");
 static int __init dsps_init(void)
 {
 	return platform_driver_register(&dsps_usbss_driver);
 }
 subsys_initcall(dsps_init);
 static void __exit dsps_exit(void)
 {
 	platform_driver_unregister(&dsps_usbss_driver);
 }
 module_exit(dsps_exit);

drivers/usb/musb/musb_gadget.c

Diff comments View file @ 032ec49

 /*
  * MUSB OTG driver peripheral support
  *
  * Copyright 2005 Mentor Graphics Corporation
  * Copyright (C) 2005-2006 by Texas Instruments
  * Copyright (C) 2006-2007 Nokia Corporation
  * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  * General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  *
  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  */
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/module.h>
 #include <linux/smp.h>
 #include <linux/spinlock.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include "musb_core.h"
 /* MUSB PERIPHERAL status 3-mar-2006:
  *
  * - EP0 seems solid.  It passes both USBCV and usbtest control cases.
  *   Minor glitches:
  *
  *     + remote wakeup to Linux hosts work, but saw USBCV failures;
  *       in one test run (operator error?)
  *     + endpoint halt tests -- in both usbtest and usbcv -- seem
  *       to break when dma is enabled ... is something wrongly
  *       clearing SENDSTALL?
  *
  * - Mass storage behaved ok when last tested.  Network traffic patterns
  *   (with lots of short transfers etc) need retesting; they turn up the
  *   worst cases of the DMA, since short packets are typical but are not
  *   required.
  *
  * - TX/IN
  *     + both pio and dma behave in with network and g_zero tests
  *     + no cppi throughput issues other than no-hw-queueing
  *     + failed with FLAT_REG (DaVinci)
  *     + seems to behave with double buffering, PIO -and- CPPI
  *     + with gadgetfs + AIO, requests got lost?
  *
  * - RX/OUT
  *     + both pio and dma behave in with network and g_zero tests
  *     + dma is slow in typical case (short_not_ok is clear)
  *     + double buffering ok with PIO
  *     + double buffering *FAILS* with CPPI, wrong data bytes sometimes
  *     + request lossage observed with gadgetfs
  *
  * - ISO not tested ... might work, but only weakly isochronous
  *
  * - Gadget driver disabling of softconnect during bind() is ignored; so
  *   drivers can't hold off host requests until userspace is ready.
  *   (Workaround:  they can turn it off later.)
  *
  * - PORTABILITY (assumes PIO works):
  *     + DaVinci, basically works with cppi dma
  *     + OMAP 2430, ditto with mentor dma
  *     + TUSB 6010, platform-specific dma in the works
  */
 /* ----------------------------------------------------------------------- */
 #define is_buffer_mapped(req) (is_dma_capable() && \
 					(req->map_state != UN_MAPPED))
 /* Maps the buffer to dma  */
 static inline void map_dma_buffer(struct musb_request *request,
 			struct musb *musb, struct musb_ep *musb_ep)
 {
 	int compatible = true;
 	struct dma_controller *dma = musb->dma_controller;
 	request->map_state = UN_MAPPED;
 	if (!is_dma_capable() || !musb_ep->dma)
 		return;
 	/* Check if DMA engine can handle this request.
 	 * DMA code must reject the USB request explicitly.
 	 * Default behaviour is to map the request.
 	 */
 	if (dma->is_compatible)
 		compatible = dma->is_compatible(musb_ep->dma,
 				musb_ep->packet_sz, request->request.buf,
 				request->request.length);
 	if (!compatible)
 		return;
 	if (request->request.dma == DMA_ADDR_INVALID) {
 		request->request.dma = dma_map_single(
 				musb->controller,
 				request->request.buf,
 				request->request.length,
 				request->tx
 					? DMA_TO_DEVICE
 					: DMA_FROM_DEVICE);
 		request->map_state = MUSB_MAPPED;
 	} else {
 		dma_sync_single_for_device(musb->controller,
 			request->request.dma,
 			request->request.length,
 			request->tx
 				? DMA_TO_DEVICE
 				: DMA_FROM_DEVICE);
 		request->map_state = PRE_MAPPED;
 	}
 }
 /* Unmap the buffer from dma and maps it back to cpu */
 static inline void unmap_dma_buffer(struct musb_request *request,
 				struct musb *musb)
 {
 	if (!is_buffer_mapped(request))
 		return;
 	if (request->request.dma == DMA_ADDR_INVALID) {
 		dev_vdbg(musb->controller,
 				"not unmapping a never mapped buffer\n");
 		return;
 	}
 	if (request->map_state == MUSB_MAPPED) {
 		dma_unmap_single(musb->controller,
 			request->request.dma,
 			request->request.length,
 			request->tx
 				? DMA_TO_DEVICE
 				: DMA_FROM_DEVICE);
 		request->request.dma = DMA_ADDR_INVALID;
 	} else { /* PRE_MAPPED */
 		dma_sync_single_for_cpu(musb->controller,
 			request->request.dma,
 			request->request.length,
 			request->tx
 				? DMA_TO_DEVICE
 				: DMA_FROM_DEVICE);
 	}
 	request->map_state = UN_MAPPED;
 }
 /*
  * Immediately complete a request.
  *
  * @param request the request to complete
  * @param status the status to complete the request with
  * Context: controller locked, IRQs blocked.
  */
 void musb_g_giveback(
 	struct musb_ep		*ep,
 	struct usb_request	*request,
 	int			status)
 __releases(ep->musb->lock)
 __acquires(ep->musb->lock)
 {
 	struct musb_request	*req;
 	struct musb		*musb;
 	int			busy = ep->busy;
 	req = to_musb_request(request);
 	list_del(&req->list);
 	if (req->request.status == -EINPROGRESS)
 		req->request.status = status;
 	musb = req->musb;
 	ep->busy = 1;
 	spin_unlock(&musb->lock);
 	unmap_dma_buffer(req, musb);
 	if (request->status == 0)
 		dev_dbg(musb->controller, "%s done request %p,  %d/%d\n",
 				ep->end_point.name, request,
 				req->request.actual, req->request.length);
 	else
 		dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
 				ep->end_point.name, request,
 				req->request.actual, req->request.length,
 				request->status);
 	req->request.complete(&req->ep->end_point, &req->request);
 	spin_lock(&musb->lock);
 	ep->busy = busy;
 }
 /* ----------------------------------------------------------------------- */
 /*
  * Abort requests queued to an endpoint using the status. Synchronous.
  * caller locked controller and blocked irqs, and selected this ep.
  */
 static void nuke(struct musb_ep *ep, const int status)
 {
 	struct musb		*musb = ep->musb;
 	struct musb_request	*req = NULL;
 	void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
 	ep->busy = 1;
 	if (is_dma_capable() && ep->dma) {
 		struct dma_controller	*c = ep->musb->dma_controller;
 		int value;
 		if (ep->is_in) {
 			/*
 			 * The programming guide says that we must not clear
 			 * the DMAMODE bit before DMAENAB, so we only
 			 * clear it in the second write...
 			 */
 			musb_writew(epio, MUSB_TXCSR,
 				    MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
 			musb_writew(epio, MUSB_TXCSR,
 					0 | MUSB_TXCSR_FLUSHFIFO);
 		} else {
 			musb_writew(epio, MUSB_RXCSR,
 					0 | MUSB_RXCSR_FLUSHFIFO);
 			musb_writew(epio, MUSB_RXCSR,
 					0 | MUSB_RXCSR_FLUSHFIFO);
 		}
 		value = c->channel_abort(ep->dma);
 		dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
 				ep->name, value);
 		c->channel_release(ep->dma);
 		ep->dma = NULL;
 	}
 	while (!list_empty(&ep->req_list)) {
 		req = list_first_entry(&ep->req_list, struct musb_request, list);
 		musb_g_giveback(ep, &req->request, status);
 	}
 }
 /* ----------------------------------------------------------------------- */
 /* Data transfers - pure PIO, pure DMA, or mixed mode */
 /*
  * This assumes the separate CPPI engine is responding to DMA requests
  * from the usb core ... sequenced a bit differently from mentor dma.
  */
 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
 {
 	if (can_bulk_split(musb, ep->type))
 		return ep->hw_ep->max_packet_sz_tx;
 	else
 		return ep->packet_sz;
 }
 #ifdef CONFIG_USB_INVENTRA_DMA
 /* Peripheral tx (IN) using Mentor DMA works as follows:
 	Only mode 0 is used for transfers <= wPktSize,
 	mode 1 is used for larger transfers,
 	One of the following happens:
 	- Host sends IN token which causes an endpoint interrupt
 		-> TxAvail
 			-> if DMA is currently busy, exit.
 			-> if queue is non-empty, txstate().
 	- Request is queued by the gadget driver.
 		-> if queue was previously empty, txstate()
 	txstate()
 		-> start
 		  /\	-> setup DMA
 		  |     (data is transferred to the FIFO, then sent out when
 		  |	IN token(s) are recd from Host.
 		  |		-> DMA interrupt on completion
 		  |		   calls TxAvail.
 		  |		      -> stop DMA, ~DMAENAB,
 		  |		      -> set TxPktRdy for last short pkt or zlp
 		  |		      -> Complete Request
 		  |		      -> Continue next request (call txstate)
 		  |___________________________________|
  * Non-Mentor DMA engines can of course work differently, such as by
  * upleveling from irq-per-packet to irq-per-buffer.
  */
 #endif
 /*
  * An endpoint is transmitting data. This can be called either from
  * the IRQ routine or from ep.queue() to kickstart a request on an
  * endpoint.
  *
  * Context: controller locked, IRQs blocked, endpoint selected
  */
 static void txstate(struct musb *musb, struct musb_request *req)
 {
 	u8			epnum = req->epnum;
 	struct musb_ep		*musb_ep;
 	void __iomem		*epio = musb->endpoints[epnum].regs;
 	struct usb_request	*request;
 	u16			fifo_count = 0, csr;
 	int			use_dma = 0;
 	musb_ep = req->ep;
 	/* Check if EP is disabled */
 	if (!musb_ep->desc) {
 		dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
 						musb_ep->end_point.name);
 		return;
 	}
 	/* we shouldn't get here while DMA is active ... but we do ... */
 	if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
 		dev_dbg(musb->controller, "dma pending...\n");
 		return;
 	}
 	/* read TXCSR before */
 	csr = musb_readw(epio, MUSB_TXCSR);
 	request = &req->request;
 	fifo_count = min(max_ep_writesize(musb, musb_ep),
 			(int)(request->length - request->actual));
 	if (csr & MUSB_TXCSR_TXPKTRDY) {
 		dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
 				musb_ep->end_point.name, csr);
 		return;
 	}
 	if (csr & MUSB_TXCSR_P_SENDSTALL) {
 		dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
 				musb_ep->end_point.name, csr);
 		return;
 	}
 	dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
 			epnum, musb_ep->packet_sz, fifo_count,
 			csr);
 #ifndef	CONFIG_MUSB_PIO_ONLY
 	if (is_buffer_mapped(req)) {
 		struct dma_controller	*c = musb->dma_controller;
 		size_t request_size;
 		/* setup DMA, then program endpoint CSR */
 		request_size = min_t(size_t, request->length - request->actual,
 					musb_ep->dma->max_len);
 		use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
 		/* MUSB_TXCSR_P_ISO is still set correctly */
 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
 		{
 			if (request_size < musb_ep->packet_sz)
 				musb_ep->dma->desired_mode = 0;
 			else
 				musb_ep->dma->desired_mode = 1;
 			use_dma = use_dma && c->channel_program(
 					musb_ep->dma, musb_ep->packet_sz,
 					musb_ep->dma->desired_mode,
 					request->dma + request->actual, request_size);
 			if (use_dma) {
 				if (musb_ep->dma->desired_mode == 0) {
 					/*
 					 * We must not clear the DMAMODE bit
 					 * before the DMAENAB bit -- and the
 					 * latter doesn't always get cleared
 					 * before we get here...
 					 */
 					csr &= ~(MUSB_TXCSR_AUTOSET
 						| MUSB_TXCSR_DMAENAB);
 					musb_writew(epio, MUSB_TXCSR, csr
 						| MUSB_TXCSR_P_WZC_BITS);
 					csr &= ~MUSB_TXCSR_DMAMODE;
 					csr |= (MUSB_TXCSR_DMAENAB |
 							MUSB_TXCSR_MODE);
 					/* against programming guide */
 				} else {
 					csr |= (MUSB_TXCSR_DMAENAB
 							| MUSB_TXCSR_DMAMODE
 							| MUSB_TXCSR_MODE);
 					if (!musb_ep->hb_mult)
 						csr |= MUSB_TXCSR_AUTOSET;
 				}
 				csr &= ~MUSB_TXCSR_P_UNDERRUN;
 				musb_writew(epio, MUSB_TXCSR, csr);
 			}
 		}
 #elif defined(CONFIG_USB_TI_CPPI_DMA)
 		/* program endpoint CSR first, then setup DMA */
 		csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
 		csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
 		       MUSB_TXCSR_MODE;
 		musb_writew(epio, MUSB_TXCSR,
 			(MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
 				| csr);
 		/* ensure writebuffer is empty */
 		csr = musb_readw(epio, MUSB_TXCSR);
 		/* NOTE host side sets DMAENAB later than this; both are
 		 * OK since the transfer dma glue (between CPPI and Mentor
 		 * fifos) just tells CPPI it could start.  Data only moves
 		 * to the USB TX fifo when both fifos are ready.
 		 */
 		/* "mode" is irrelevant here; handle terminating ZLPs like
 		 * PIO does, since the hardware RNDIS mode seems unreliable
 		 * except for the last-packet-is-already-short case.
 		 */
 		use_dma = use_dma && c->channel_program(
 				musb_ep->dma, musb_ep->packet_sz,
 				0,
 				request->dma + request->actual,
 				request_size);
 		if (!use_dma) {
 			c->channel_release(musb_ep->dma);
 			musb_ep->dma = NULL;
 			csr &= ~MUSB_TXCSR_DMAENAB;
 			musb_writew(epio, MUSB_TXCSR, csr);
 			/* invariant: prequest->buf is non-null */
 		}
 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
 		use_dma = use_dma && c->channel_program(
 				musb_ep->dma, musb_ep->packet_sz,
 				request->zero,
 				request->dma + request->actual,
 				request_size);
 #endif
 	}
 #endif
 	if (!use_dma) {
 		/*
 		 * Unmap the dma buffer back to cpu if dma channel
 		 * programming fails
 		 */
 		unmap_dma_buffer(req, musb);
 		musb_write_fifo(musb_ep->hw_ep, fifo_count,
 				(u8 *) (request->buf + request->actual));
 		request->actual += fifo_count;
 		csr |= MUSB_TXCSR_TXPKTRDY;
 		csr &= ~MUSB_TXCSR_P_UNDERRUN;
 		musb_writew(epio, MUSB_TXCSR, csr);
 	}
 	/* host may already have the data when this message shows... */
 	dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
 			musb_ep->end_point.name, use_dma ? "dma" : "pio",
 			request->actual, request->length,
 			musb_readw(epio, MUSB_TXCSR),
 			fifo_count,
 			musb_readw(epio, MUSB_TXMAXP));
 }
 /*
  * FIFO state update (e.g. data ready).
  * Called from IRQ,  with controller locked.
  */
 void musb_g_tx(struct musb *musb, u8 epnum)
 {
 	u16			csr;
 	struct musb_request	*req;
 	struct usb_request	*request;
 	u8 __iomem		*mbase = musb->mregs;
 	struct musb_ep		*musb_ep = &musb->endpoints[epnum].ep_in;
 	void __iomem		*epio = musb->endpoints[epnum].regs;
 	struct dma_channel	*dma;
 	musb_ep_select(mbase, epnum);
 	req = next_request(musb_ep);
 	request = &req->request;
 	csr = musb_readw(epio, MUSB_TXCSR);
 	dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
 	dma = is_dma_capable() ? musb_ep->dma : NULL;
 	/*
 	 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
 	 * probably rates reporting as a host error.
 	 */
 	if (csr & MUSB_TXCSR_P_SENTSTALL) {
 		csr |=	MUSB_TXCSR_P_WZC_BITS;
 		csr &= ~MUSB_TXCSR_P_SENTSTALL;
 		musb_writew(epio, MUSB_TXCSR, csr);
 		return;
 	}
 	if (csr & MUSB_TXCSR_P_UNDERRUN) {
 		/* We NAKed, no big deal... little reason to care. */
 		csr |=	 MUSB_TXCSR_P_WZC_BITS;
 		csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
 		musb_writew(epio, MUSB_TXCSR, csr);
 		dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
 				epnum, request);
 	}
 	if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
 		/*
 		 * SHOULD NOT HAPPEN... has with CPPI though, after
 		 * changing SENDSTALL (and other cases); harmless?
 		 */
 		dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
 		return;
 	}
 	if (request) {
 		u8	is_dma = 0;
 		if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
 			is_dma = 1;
 			csr |= MUSB_TXCSR_P_WZC_BITS;
 			csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
 				 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
 			musb_writew(epio, MUSB_TXCSR, csr);
 			/* Ensure writebuffer is empty. */
 			csr = musb_readw(epio, MUSB_TXCSR);
 			request->actual += musb_ep->dma->actual_len;
 			dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
 				epnum, csr, musb_ep->dma->actual_len, request);
 		}
 		/*
 		 * First, maybe a terminating short packet. Some DMA
 		 * engines might handle this by themselves.
 		 */
 		if ((request->zero && request->length
 			&& (request->length % musb_ep->packet_sz == 0)
 			&& (request->actual == request->length))
 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
 			|| (is_dma && (!dma->desired_mode ||
 				(request->actual &
 					(musb_ep->packet_sz - 1))))
 #endif
 		) {
 			/*
 			 * On DMA completion, FIFO may not be
 			 * available yet...
 			 */
 			if (csr & MUSB_TXCSR_TXPKTRDY)
 				return;
 			dev_dbg(musb->controller, "sending zero pkt\n");
 			musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
 					| MUSB_TXCSR_TXPKTRDY);
 			request->zero = 0;
 		}
 		if (request->actual == request->length) {
 			musb_g_giveback(musb_ep, request, 0);
 			/*
 			 * In the giveback function the MUSB lock is
 			 * released and acquired after sometime. During
 			 * this time period the INDEX register could get
 			 * changed by the gadget_queue function especially
 			 * on SMP systems. Reselect the INDEX to be sure
 			 * we are reading/modifying the right registers
 			 */
 			musb_ep_select(mbase, epnum);
 			req = musb_ep->desc ? next_request(musb_ep) : NULL;
 			if (!req) {
 				dev_dbg(musb->controller, "%s idle now\n",
 					musb_ep->end_point.name);
 				return;
 			}
 		}
 		txstate(musb, req);
 	}
 }
 /* ------------------------------------------------------------ */
 #ifdef CONFIG_USB_INVENTRA_DMA
 /* Peripheral rx (OUT) using Mentor DMA works as follows:
 	- Only mode 0 is used.
 	- Request is queued by the gadget class driver.
 		-> if queue was previously empty, rxstate()
 	- Host sends OUT token which causes an endpoint interrupt
 	  /\      -> RxReady
 	  |	      -> if request queued, call rxstate
 	  |		/\	-> setup DMA
 	  |		|	     -> DMA interrupt on completion
 	  |		|		-> RxReady
 	  |		|		      -> stop DMA
 	  |		|		      -> ack the read
 	  |		|		      -> if data recd = max expected
 	  |		|				by the request, or host
 	  |		|				sent a short packet,
 	  |		|				complete the request,
 	  |		|				and start the next one.
 	  |		|_____________________________________|
 	  |					 else just wait for the host
 	  |					    to send the next OUT token.
 	  |__________________________________________________|
  * Non-Mentor DMA engines can of course work differently.
  */
 #endif
 /*
  * Context: controller locked, IRQs blocked, endpoint selected
  */
 static void rxstate(struct musb *musb, struct musb_request *req)
 {
 	const u8		epnum = req->epnum;
 	struct usb_request	*request = &req->request;
 	struct musb_ep		*musb_ep;
 	void __iomem		*epio = musb->endpoints[epnum].regs;
 	unsigned		len = 0;
 	u16			fifo_count;
 	u16			csr = musb_readw(epio, MUSB_RXCSR);
 	struct musb_hw_ep	*hw_ep = &musb->endpoints[epnum];
 	u8			use_mode_1;
 	if (hw_ep->is_shared_fifo)
 		musb_ep = &hw_ep->ep_in;
 	else
 		musb_ep = &hw_ep->ep_out;
 	fifo_count = musb_ep->packet_sz;
 	/* Check if EP is disabled */
 	if (!musb_ep->desc) {
 		dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
 						musb_ep->end_point.name);
 		return;
 	}
 	/* We shouldn't get here while DMA is active, but we do... */
 	if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
 		dev_dbg(musb->controller, "DMA pending...\n");
 		return;
 	}
 	if (csr & MUSB_RXCSR_P_SENDSTALL) {
 		dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
 		    musb_ep->end_point.name, csr);
 		return;
 	}
 	if (is_cppi_enabled() && is_buffer_mapped(req)) {
 		struct dma_controller	*c = musb->dma_controller;
 		struct dma_channel	*channel = musb_ep->dma;
 		/* NOTE:  CPPI won't actually stop advancing the DMA
 		 * queue after short packet transfers, so this is almost
 		 * always going to run as IRQ-per-packet DMA so that
 		 * faults will be handled correctly.
 		 */
 		if (c->channel_program(channel,
 				musb_ep->packet_sz,
 				!request->short_not_ok,
 				request->dma + request->actual,
 				request->length - request->actual)) {
 			/* make sure that if an rxpkt arrived after the irq,
 			 * the cppi engine will be ready to take it as soon
 			 * as DMA is enabled
 			 */
 			csr &= ~(MUSB_RXCSR_AUTOCLEAR
 					| MUSB_RXCSR_DMAMODE);
 			csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
 			musb_writew(epio, MUSB_RXCSR, csr);
 			return;
 		}
 	}
 	if (csr & MUSB_RXCSR_RXPKTRDY) {
 		fifo_count = musb_readw(epio, MUSB_RXCOUNT);
 		/*
 		 *  use mode 1 only if we expect data of at least ep packet_sz
 		 *  and have not yet received a short packet
 		 */
 		if ((request->length - request->actual >= musb_ep->packet_sz) &&
 			(fifo_count >= musb_ep->packet_sz))
 			use_mode_1 = 1;
 		else
 			use_mode_1 = 0;
 		if (request->actual < request->length) {
 #ifdef CONFIG_USB_INVENTRA_DMA
 			if (is_buffer_mapped(req)) {
 				struct dma_controller	*c;
 				struct dma_channel	*channel;
 				int			use_dma = 0;
 				c = musb->dma_controller;
 				channel = musb_ep->dma;
 				/* Experimental: Mode1 works with mass storage use cases */
 				if (use_mode_1) {
 					csr |= MUSB_RXCSR_AUTOCLEAR;
 					musb_writew(epio, MUSB_RXCSR, csr);
 					csr |= MUSB_RXCSR_DMAENAB;
 					musb_writew(epio, MUSB_RXCSR, csr);
 					/*
 					 * this special sequence (enabling and then
 					 * disabling MUSB_RXCSR_DMAMODE) is required
 					 * to get DMAReq to activate
 					 */
 					musb_writew(epio, MUSB_RXCSR,
 						csr | MUSB_RXCSR_DMAMODE);
 					musb_writew(epio, MUSB_RXCSR, csr);
 				} else {
 					if (!musb_ep->hb_mult &&
 						musb_ep->hw_ep->rx_double_buffered)
 						csr |= MUSB_RXCSR_AUTOCLEAR;
 					csr |= MUSB_RXCSR_DMAENAB;
 					musb_writew(epio, MUSB_RXCSR, csr);
 				}
 				if (request->actual < request->length) {
 					int transfer_size = 0;
 					if (use_mode_1) {
 						transfer_size = min(request->length - request->actual,
 								channel->max_len);
 						musb_ep->dma->desired_mode = 1;
 					} else {
 						transfer_size = min(request->length - request->actual,
 							(unsigned)fifo_count);
 						musb_ep->dma->desired_mode = 0;
 					}
 					use_dma = c->channel_program(
 							channel,
 							musb_ep->packet_sz,
 							channel->desired_mode,
 							request->dma
 							+ request->actual,
 							transfer_size);
 				}
 				if (use_dma)
 					return;
 			}
 #elif defined(CONFIG_USB_UX500_DMA)
 			if ((is_buffer_mapped(req)) &&
 				(request->actual < request->length)) {
 				struct dma_controller *c;
 				struct dma_channel *channel;
 				int transfer_size = 0;
 				c = musb->dma_controller;
 				channel = musb_ep->dma;
 				/* In case first packet is short */
 				if (fifo_count < musb_ep->packet_sz)
 					transfer_size = fifo_count;
 				else if (request->short_not_ok)
 					transfer_size =	min(request->length -
 							request->actual,
 							channel->max_len);
 				else
 					transfer_size = min(request->length -
 							request->actual,
 							(unsigned)fifo_count);
 				csr &= ~MUSB_RXCSR_DMAMODE;
 				csr |= (MUSB_RXCSR_DMAENAB |
 					MUSB_RXCSR_AUTOCLEAR);
 				musb_writew(epio, MUSB_RXCSR, csr);
 				if (transfer_size <= musb_ep->packet_sz) {
 					musb_ep->dma->desired_mode = 0;
 				} else {
 					musb_ep->dma->desired_mode = 1;
 					/* Mode must be set after DMAENAB */
 					csr |= MUSB_RXCSR_DMAMODE;
 					musb_writew(epio, MUSB_RXCSR, csr);
 				}
 				if (c->channel_program(channel,
 							musb_ep->packet_sz,
 							channel->desired_mode,
 							request->dma
 							+ request->actual,
 							transfer_size))
 					return;
 			}
 #endif	/* Mentor's DMA */
 			len = request->length - request->actual;
 			dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
 					musb_ep->end_point.name,
 					fifo_count, len,
 					musb_ep->packet_sz);
 			fifo_count = min_t(unsigned, len, fifo_count);
 #ifdef	CONFIG_USB_TUSB_OMAP_DMA
 			if (tusb_dma_omap() && is_buffer_mapped(req)) {
 				struct dma_controller *c = musb->dma_controller;
 				struct dma_channel *channel = musb_ep->dma;
 				u32 dma_addr = request->dma + request->actual;
 				int ret;
 				ret = c->channel_program(channel,
 						musb_ep->packet_sz,
 						channel->desired_mode,
 						dma_addr,
 						fifo_count);
 				if (ret)
 					return;
 			}
 #endif
 			/*
 			 * Unmap the dma buffer back to cpu if dma channel
 			 * programming fails. This buffer is mapped if the
 			 * channel allocation is successful
 			 */
 			 if (is_buffer_mapped(req)) {
 				unmap_dma_buffer(req, musb);
 				/*
 				 * Clear DMAENAB and AUTOCLEAR for the
 				 * PIO mode transfer
 				 */
 				csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
 				musb_writew(epio, MUSB_RXCSR, csr);
 			}
 			musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
 					(request->buf + request->actual));
 			request->actual += fifo_count;
 			/* REVISIT if we left anything in the fifo, flush
 			 * it and report -EOVERFLOW
 			 */
 			/* ack the read! */
 			csr |= MUSB_RXCSR_P_WZC_BITS;
 			csr &= ~MUSB_RXCSR_RXPKTRDY;
 			musb_writew(epio, MUSB_RXCSR, csr);
 		}
 	}
 	/* reach the end or short packet detected */
 	if (request->actual == request->length ||
 	    fifo_count < musb_ep->packet_sz)
 		musb_g_giveback(musb_ep, request, 0);
 }
 /*
  * Data ready for a request; called from IRQ
  */
 void musb_g_rx(struct musb *musb, u8 epnum)
 {
 	u16			csr;
 	struct musb_request	*req;
 	struct usb_request	*request;
 	void __iomem		*mbase = musb->mregs;
 	struct musb_ep		*musb_ep;
 	void __iomem		*epio = musb->endpoints[epnum].regs;
 	struct dma_channel	*dma;
 	struct musb_hw_ep	*hw_ep = &musb->endpoints[epnum];
 	if (hw_ep->is_shared_fifo)
 		musb_ep = &hw_ep->ep_in;
 	else
 		musb_ep = &hw_ep->ep_out;
 	musb_ep_select(mbase, epnum);
 	req = next_request(musb_ep);
 	if (!req)
 		return;
 	request = &req->request;
 	csr = musb_readw(epio, MUSB_RXCSR);
 	dma = is_dma_capable() ? musb_ep->dma : NULL;
 	dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
 			csr, dma ? " (dma)" : "", request);
 	if (csr & MUSB_RXCSR_P_SENTSTALL) {
 		csr |= MUSB_RXCSR_P_WZC_BITS;
 		csr &= ~MUSB_RXCSR_P_SENTSTALL;
 		musb_writew(epio, MUSB_RXCSR, csr);
 		return;
 	}
 	if (csr & MUSB_RXCSR_P_OVERRUN) {
 		/* csr |= MUSB_RXCSR_P_WZC_BITS; */
 		csr &= ~MUSB_RXCSR_P_OVERRUN;
 		musb_writew(epio, MUSB_RXCSR, csr);
 		dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
 		if (request->status == -EINPROGRESS)
 			request->status = -EOVERFLOW;
 	}
 	if (csr & MUSB_RXCSR_INCOMPRX) {
 		/* REVISIT not necessarily an error */
 		dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
 	}
 	if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
 		/* "should not happen"; likely RXPKTRDY pending for DMA */
 		dev_dbg(musb->controller, "%s busy, csr %04x\n",
 			musb_ep->end_point.name, csr);
 		return;
 	}
 	if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
 		csr &= ~(MUSB_RXCSR_AUTOCLEAR
 				| MUSB_RXCSR_DMAENAB
 				| MUSB_RXCSR_DMAMODE);
 		musb_writew(epio, MUSB_RXCSR,
 			MUSB_RXCSR_P_WZC_BITS | csr);
 		request->actual += musb_ep->dma->actual_len;
 		dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
 			epnum, csr,
 			musb_readw(epio, MUSB_RXCSR),
 			musb_ep->dma->actual_len, request);
 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
 	defined(CONFIG_USB_UX500_DMA)
 		/* Autoclear doesn't clear RxPktRdy for short packets */
 		if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
 				|| (dma->actual_len
 					& (musb_ep->packet_sz - 1))) {
 			/* ack the read! */
 			csr &= ~MUSB_RXCSR_RXPKTRDY;
 			musb_writew(epio, MUSB_RXCSR, csr);
 		}
 		/* incomplete, and not short? wait for next IN packet */
 		if ((request->actual < request->length)
 				&& (musb_ep->dma->actual_len
 					== musb_ep->packet_sz)) {
 			/* In double buffer case, continue to unload fifo if
  			 * there is Rx packet in FIFO.
  			 **/
 			csr = musb_readw(epio, MUSB_RXCSR);
 			if ((csr & MUSB_RXCSR_RXPKTRDY) &&
 				hw_ep->rx_double_buffered)
 				goto exit;
 			return;
 		}
 #endif
 		musb_g_giveback(musb_ep, request, 0);
 		/*
 		 * In the giveback function the MUSB lock is
 		 * released and acquired after sometime. During
 		 * this time period the INDEX register could get
 		 * changed by the gadget_queue function especially
 		 * on SMP systems. Reselect the INDEX to be sure
 		 * we are reading/modifying the right registers
 		 */
 		musb_ep_select(mbase, epnum);
 		req = next_request(musb_ep);
 		if (!req)
 			return;
 	}
 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
 	defined(CONFIG_USB_UX500_DMA)
 exit:
 #endif
 	/* Analyze request */
 	rxstate(musb, req);
 }
 /* ------------------------------------------------------------ */
 static int musb_gadget_enable(struct usb_ep *ep,
 			const struct usb_endpoint_descriptor *desc)
 {
 	unsigned long		flags;
 	struct musb_ep		*musb_ep;
 	struct musb_hw_ep	*hw_ep;
 	void __iomem		*regs;
 	struct musb		*musb;
 	void __iomem	*mbase;
 	u8		epnum;
 	u16		csr;
 	unsigned	tmp;
 	int		status = -EINVAL;
 	if (!ep || !desc)
 		return -EINVAL;
 	musb_ep = to_musb_ep(ep);
 	hw_ep = musb_ep->hw_ep;
 	regs = hw_ep->regs;
 	musb = musb_ep->musb;
 	mbase = musb->mregs;
 	epnum = musb_ep->current_epnum;
 	spin_lock_irqsave(&musb->lock, flags);
 	if (musb_ep->desc) {
 		status = -EBUSY;
 		goto fail;
 	}
 	musb_ep->type = usb_endpoint_type(desc);
 	/* check direction and (later) maxpacket size against endpoint */
 	if (usb_endpoint_num(desc) != epnum)
 		goto fail;
 	/* REVISIT this rules out high bandwidth periodic transfers */
 	tmp = usb_endpoint_maxp(desc);
 	if (tmp & ~0x07ff) {
 		int ok;
 		if (usb_endpoint_dir_in(desc))
 			ok = musb->hb_iso_tx;
 		else
 			ok = musb->hb_iso_rx;
 		if (!ok) {
 			dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
 			goto fail;
 		}
 		musb_ep->hb_mult = (tmp >> 11) & 3;
 	} else {
 		musb_ep->hb_mult = 0;
 	}
 	musb_ep->packet_sz = tmp & 0x7ff;
 	tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
 	/* enable the interrupts for the endpoint, set the endpoint
 	 * packet size (or fail), set the mode, clear the fifo
 	 */
 	musb_ep_select(mbase, epnum);
 	if (usb_endpoint_dir_in(desc)) {
 		u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
 		if (hw_ep->is_shared_fifo)
 			musb_ep->is_in = 1;
 		if (!musb_ep->is_in)
 			goto fail;
 		if (tmp > hw_ep->max_packet_sz_tx) {
 			dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
 			goto fail;
 		}
 		int_txe |= (1 << epnum);
 		musb_writew(mbase, MUSB_INTRTXE, int_txe);
 		/* REVISIT if can_bulk_split(), use by updating "tmp";
 		 * likewise high bandwidth periodic tx
 		 */
 		/* Set TXMAXP with the FIFO size of the endpoint
 		 * to disable double buffering mode.
 		 */
 		if (musb->double_buffer_not_ok)
 			musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
 		else
 			musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
 					| (musb_ep->hb_mult << 11));
 		csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
 		if (musb_readw(regs, MUSB_TXCSR)
 				& MUSB_TXCSR_FIFONOTEMPTY)
 			csr |= MUSB_TXCSR_FLUSHFIFO;
 		if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
 			csr |= MUSB_TXCSR_P_ISO;
 		/* set twice in case of double buffering */
 		musb_writew(regs, MUSB_TXCSR, csr);
 		/* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
 		musb_writew(regs, MUSB_TXCSR, csr);
 	} else {
 		u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
 		if (hw_ep->is_shared_fifo)
 			musb_ep->is_in = 0;
 		if (musb_ep->is_in)
 			goto fail;
 		if (tmp > hw_ep->max_packet_sz_rx) {
 			dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
 			goto fail;
 		}
 		int_rxe |= (1 << epnum);
 		musb_writew(mbase, MUSB_INTRRXE, int_rxe);
 		/* REVISIT if can_bulk_combine() use by updating "tmp"
 		 * likewise high bandwidth periodic rx
 		 */
 		/* Set RXMAXP with the FIFO size of the endpoint
 		 * to disable double buffering mode.
 		 */
 		if (musb->double_buffer_not_ok)
 			musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
 		else
 			musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
 					| (musb_ep->hb_mult << 11));
 		/* force shared fifo to OUT-only mode */
 		if (hw_ep->is_shared_fifo) {
 			csr = musb_readw(regs, MUSB_TXCSR);
 			csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
 			musb_writew(regs, MUSB_TXCSR, csr);
 		}
 		csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
 		if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
 			csr |= MUSB_RXCSR_P_ISO;
 		else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
 			csr |= MUSB_RXCSR_DISNYET;
 		/* set twice in case of double buffering */
 		musb_writew(regs, MUSB_RXCSR, csr);
 		musb_writew(regs, MUSB_RXCSR, csr);
 	}
 	/* NOTE:  all the I/O code _should_ work fine without DMA, in case
 	 * for some reason you run out of channels here.
 	 */
 	if (is_dma_capable() && musb->dma_controller) {
 		struct dma_controller	*c = musb->dma_controller;
 		musb_ep->dma = c->channel_alloc(c, hw_ep,
 				(desc->bEndpointAddress & USB_DIR_IN));
 	} else
 		musb_ep->dma = NULL;
 	musb_ep->desc = desc;
 	musb_ep->busy = 0;
 	musb_ep->wedged = 0;
 	status = 0;
 	pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
 			musb_driver_name, musb_ep->end_point.name,
 			({ char *s; switch (musb_ep->type) {
 			case USB_ENDPOINT_XFER_BULK:	s = "bulk"; break;
 			case USB_ENDPOINT_XFER_INT:	s = "int"; break;
 			default:			s = "iso"; break;
 			}; s; }),
 			musb_ep->is_in ? "IN" : "OUT",
 			musb_ep->dma ? "dma, " : "",
 			musb_ep->packet_sz);
 	schedule_work(&musb->irq_work);
 fail:
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return status;
 }
 /*
  * Disable an endpoint flushing all requests queued.
  */
 static int musb_gadget_disable(struct usb_ep *ep)
 {
 	unsigned long	flags;
 	struct musb	*musb;
 	u8		epnum;
 	struct musb_ep	*musb_ep;
 	void __iomem	*epio;
 	int		status = 0;
 	musb_ep = to_musb_ep(ep);
 	musb = musb_ep->musb;
 	epnum = musb_ep->current_epnum;
 	epio = musb->endpoints[epnum].regs;
 	spin_lock_irqsave(&musb->lock, flags);
 	musb_ep_select(musb->mregs, epnum);
 	/* zero the endpoint sizes */
 	if (musb_ep->is_in) {
 		u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
 		int_txe &= ~(1 << epnum);
 		musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
 		musb_writew(epio, MUSB_TXMAXP, 0);
 	} else {
 		u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
 		int_rxe &= ~(1 << epnum);
 		musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
 		musb_writew(epio, MUSB_RXMAXP, 0);
 	}
 	musb_ep->desc = NULL;
 	musb_ep->end_point.desc = NULL;
 	/* abort all pending DMA and requests */
 	nuke(musb_ep, -ESHUTDOWN);
 	schedule_work(&musb->irq_work);
 	spin_unlock_irqrestore(&(musb->lock), flags);
 	dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
 	return status;
 }
 /*
  * Allocate a request for an endpoint.
  * Reused by ep0 code.
  */
 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 {
 	struct musb_ep		*musb_ep = to_musb_ep(ep);
 	struct musb		*musb = musb_ep->musb;
 	struct musb_request	*request = NULL;
 	request = kzalloc(sizeof *request, gfp_flags);
 	if (!request) {
 		dev_dbg(musb->controller, "not enough memory\n");
 		return NULL;
 	}
 	request->request.dma = DMA_ADDR_INVALID;
 	request->epnum = musb_ep->current_epnum;
 	request->ep = musb_ep;
 	return &request->request;
 }
 /*
  * Free a request
  * Reused by ep0 code.
  */
 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
 {
 	kfree(to_musb_request(req));
 }
 static LIST_HEAD(buffers);
 struct free_record {
 	struct list_head	list;
 	struct device		*dev;
 	unsigned		bytes;
 	dma_addr_t		dma;
 };
 /*
  * Context: controller locked, IRQs blocked.
  */
 void musb_ep_restart(struct musb *musb, struct musb_request *req)
 {
 	dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
 		req->tx ? "TX/IN" : "RX/OUT",
 		&req->request, req->request.length, req->epnum);
 	musb_ep_select(musb->mregs, req->epnum);
 	if (req->tx)
 		txstate(musb, req);
 	else
 		rxstate(musb, req);
 }
 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
 			gfp_t gfp_flags)
 {
 	struct musb_ep		*musb_ep;
 	struct musb_request	*request;
 	struct musb		*musb;
 	int			status = 0;
 	unsigned long		lockflags;
 	if (!ep || !req)
 		return -EINVAL;
 	if (!req->buf)
 		return -ENODATA;
 	musb_ep = to_musb_ep(ep);
 	musb = musb_ep->musb;
 	request = to_musb_request(req);
 	request->musb = musb;
 	if (request->ep != musb_ep)
 		return -EINVAL;
 	dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
 	/* request is mine now... */
 	request->request.actual = 0;
 	request->request.status = -EINPROGRESS;
 	request->epnum = musb_ep->current_epnum;
 	request->tx = musb_ep->is_in;
 	map_dma_buffer(request, musb, musb_ep);
 	spin_lock_irqsave(&musb->lock, lockflags);
 	/* don't queue if the ep is down */
 	if (!musb_ep->desc) {
 		dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
 				req, ep->name, "disabled");
 		status = -ESHUTDOWN;
 		goto cleanup;
 	}
 	/* add request to the list */
 	list_add_tail(&request->list, &musb_ep->req_list);
 	/* it this is the head of the queue, start i/o ... */
 	if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
 		musb_ep_restart(musb, request);
 cleanup:
 	spin_unlock_irqrestore(&musb->lock, lockflags);
 	return status;
 }
 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
 {
 	struct musb_ep		*musb_ep = to_musb_ep(ep);
 	struct musb_request	*req = to_musb_request(request);
 	struct musb_request	*r;
 	unsigned long		flags;
 	int			status = 0;
 	struct musb		*musb = musb_ep->musb;
 	if (!ep || !request || to_musb_request(request)->ep != musb_ep)
 		return -EINVAL;
 	spin_lock_irqsave(&musb->lock, flags);
 	list_for_each_entry(r, &musb_ep->req_list, list) {
 		if (r == req)
 			break;
 	}
 	if (r != req) {
 		dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
 		status = -EINVAL;
 		goto done;
 	}
 	/* if the hardware doesn't have the request, easy ... */
 	if (musb_ep->req_list.next != &req->list || musb_ep->busy)
 		musb_g_giveback(musb_ep, request, -ECONNRESET);
 	/* ... else abort the dma transfer ... */
 	else if (is_dma_capable() && musb_ep->dma) {
 		struct dma_controller	*c = musb->dma_controller;
 		musb_ep_select(musb->mregs, musb_ep->current_epnum);
 		if (c->channel_abort)
 			status = c->channel_abort(musb_ep->dma);
 		else
 			status = -EBUSY;
 		if (status == 0)
 			musb_g_giveback(musb_ep, request, -ECONNRESET);
 	} else {
 		/* NOTE: by sticking to easily tested hardware/driver states,
 		 * we leave counting of in-flight packets imprecise.
 		 */
 		musb_g_giveback(musb_ep, request, -ECONNRESET);
 	}
 done:
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return status;
 }
 /*
  * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
  * data but will queue requests.
  *
  * exported to ep0 code
  */
 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
 {
 	struct musb_ep		*musb_ep = to_musb_ep(ep);
 	u8			epnum = musb_ep->current_epnum;
 	struct musb		*musb = musb_ep->musb;
 	void __iomem		*epio = musb->endpoints[epnum].regs;
 	void __iomem		*mbase;
 	unsigned long		flags;
 	u16			csr;
 	struct musb_request	*request;
 	int			status = 0;
 	if (!ep)
 		return -EINVAL;
 	mbase = musb->mregs;
 	spin_lock_irqsave(&musb->lock, flags);
 	if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
 		status = -EINVAL;
 		goto done;
 	}
 	musb_ep_select(mbase, epnum);
 	request = next_request(musb_ep);
 	if (value) {
 		if (request) {
 			dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
 			    ep->name);
 			status = -EAGAIN;
 			goto done;
 		}
 		/* Cannot portably stall with non-empty FIFO */
 		if (musb_ep->is_in) {
 			csr = musb_readw(epio, MUSB_TXCSR);
 			if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
 				dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
 				status = -EAGAIN;
 				goto done;
 			}
 		}
 	} else
 		musb_ep->wedged = 0;
 	/* set/clear the stall and toggle bits */
 	dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
 	if (musb_ep->is_in) {
 		csr = musb_readw(epio, MUSB_TXCSR);
 		csr |= MUSB_TXCSR_P_WZC_BITS
 			| MUSB_TXCSR_CLRDATATOG;
 		if (value)
 			csr |= MUSB_TXCSR_P_SENDSTALL;
 		else
 			csr &= ~(MUSB_TXCSR_P_SENDSTALL
 				| MUSB_TXCSR_P_SENTSTALL);
 		csr &= ~MUSB_TXCSR_TXPKTRDY;
 		musb_writew(epio, MUSB_TXCSR, csr);
 	} else {
 		csr = musb_readw(epio, MUSB_RXCSR);
 		csr |= MUSB_RXCSR_P_WZC_BITS
 			| MUSB_RXCSR_FLUSHFIFO
 			| MUSB_RXCSR_CLRDATATOG;
 		if (value)
 			csr |= MUSB_RXCSR_P_SENDSTALL;
 		else
 			csr &= ~(MUSB_RXCSR_P_SENDSTALL
 				| MUSB_RXCSR_P_SENTSTALL);
 		musb_writew(epio, MUSB_RXCSR, csr);
 	}
 	/* maybe start the first request in the queue */
 	if (!musb_ep->busy && !value && request) {
 		dev_dbg(musb->controller, "restarting the request\n");
 		musb_ep_restart(musb, request);
 	}
 done:
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return status;
 }
 /*
  * Sets the halt feature with the clear requests ignored
  */
 static int musb_gadget_set_wedge(struct usb_ep *ep)
 {
 	struct musb_ep		*musb_ep = to_musb_ep(ep);
 	if (!ep)
 		return -EINVAL;
 	musb_ep->wedged = 1;
 	return usb_ep_set_halt(ep);
 }
 static int musb_gadget_fifo_status(struct usb_ep *ep)
 {
 	struct musb_ep		*musb_ep = to_musb_ep(ep);
 	void __iomem		*epio = musb_ep->hw_ep->regs;
 	int			retval = -EINVAL;
 	if (musb_ep->desc && !musb_ep->is_in) {
 		struct musb		*musb = musb_ep->musb;
 		int			epnum = musb_ep->current_epnum;
 		void __iomem		*mbase = musb->mregs;
 		unsigned long		flags;
 		spin_lock_irqsave(&musb->lock, flags);
 		musb_ep_select(mbase, epnum);
 		/* FIXME return zero unless RXPKTRDY is set */
 		retval = musb_readw(epio, MUSB_RXCOUNT);
 		spin_unlock_irqrestore(&musb->lock, flags);
 	}
 	return retval;
 }
 static void musb_gadget_fifo_flush(struct usb_ep *ep)
 {
 	struct musb_ep	*musb_ep = to_musb_ep(ep);
 	struct musb	*musb = musb_ep->musb;
 	u8		epnum = musb_ep->current_epnum;
 	void __iomem	*epio = musb->endpoints[epnum].regs;
 	void __iomem	*mbase;
 	unsigned long	flags;
 	u16		csr, int_txe;
 	mbase = musb->mregs;
 	spin_lock_irqsave(&musb->lock, flags);
 	musb_ep_select(mbase, (u8) epnum);
 	/* disable interrupts */
 	int_txe = musb_readw(mbase, MUSB_INTRTXE);
 	musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
 	if (musb_ep->is_in) {
 		csr = musb_readw(epio, MUSB_TXCSR);
 		if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
 			csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
 			/*
 			 * Setting both TXPKTRDY and FLUSHFIFO makes controller
 			 * to interrupt current FIFO loading, but not flushing
 			 * the already loaded ones.
 			 */
 			csr &= ~MUSB_TXCSR_TXPKTRDY;
 			musb_writew(epio, MUSB_TXCSR, csr);
 			/* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
 			musb_writew(epio, MUSB_TXCSR, csr);
 		}
 	} else {
 		csr = musb_readw(epio, MUSB_RXCSR);
 		csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
 		musb_writew(epio, MUSB_RXCSR, csr);
 		musb_writew(epio, MUSB_RXCSR, csr);
 	}
 	/* re-enable interrupt */
 	musb_writew(mbase, MUSB_INTRTXE, int_txe);
 	spin_unlock_irqrestore(&musb->lock, flags);
 }
 static const struct usb_ep_ops musb_ep_ops = {
 	.enable		= musb_gadget_enable,
 	.disable	= musb_gadget_disable,
 	.alloc_request	= musb_alloc_request,
 	.free_request	= musb_free_request,
 	.queue		= musb_gadget_queue,
 	.dequeue	= musb_gadget_dequeue,
 	.set_halt	= musb_gadget_set_halt,
 	.set_wedge	= musb_gadget_set_wedge,
 	.fifo_status	= musb_gadget_fifo_status,
 	.fifo_flush	= musb_gadget_fifo_flush
 };
 /* ----------------------------------------------------------------------- */
 static int musb_gadget_get_frame(struct usb_gadget *gadget)
 {
 	struct musb	*musb = gadget_to_musb(gadget);
 	return (int)musb_readw(musb->mregs, MUSB_FRAME);
 }
 static int musb_gadget_wakeup(struct usb_gadget *gadget)
 {
 	struct musb	*musb = gadget_to_musb(gadget);
 	void __iomem	*mregs = musb->mregs;
 	unsigned long	flags;
 	int		status = -EINVAL;
 	u8		power, devctl;
 	int		retries;
 	spin_lock_irqsave(&musb->lock, flags);
 	switch (musb->xceiv->state) {
 	case OTG_STATE_B_PERIPHERAL:
 		/* NOTE:  OTG state machine doesn't include B_SUSPENDED;
 		 * that's part of the standard usb 1.1 state machine, and
 		 * doesn't affect OTG transitions.
 		 */
 		if (musb->may_wakeup && musb->is_suspended)
 			break;
 		goto done;
 	case OTG_STATE_B_IDLE:
 		/* Start SRP ... OTG not required. */
 		devctl = musb_readb(mregs, MUSB_DEVCTL);
 		dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
 		devctl |= MUSB_DEVCTL_SESSION;
 		musb_writeb(mregs, MUSB_DEVCTL, devctl);
 		devctl = musb_readb(mregs, MUSB_DEVCTL);
 		retries = 100;
 		while (!(devctl & MUSB_DEVCTL_SESSION)) {
 			devctl = musb_readb(mregs, MUSB_DEVCTL);
 			if (retries-- < 1)
 				break;
 		}
 		retries = 10000;
 		while (devctl & MUSB_DEVCTL_SESSION) {
 			devctl = musb_readb(mregs, MUSB_DEVCTL);
 			if (retries-- < 1)
 				break;
 		}
 		spin_unlock_irqrestore(&musb->lock, flags);
 		otg_start_srp(musb->xceiv->otg);
 		spin_lock_irqsave(&musb->lock, flags);
 		/* Block idling for at least 1s */
 		musb_platform_try_idle(musb,
 			jiffies + msecs_to_jiffies(1 * HZ));
 		status = 0;
 		goto done;
 	default:
 		dev_dbg(musb->controller, "Unhandled wake: %s\n",
 			otg_state_string(musb->xceiv->state));
 		goto done;
 	}
 	status = 0;
 	power = musb_readb(mregs, MUSB_POWER);
 	power |= MUSB_POWER_RESUME;
 	musb_writeb(mregs, MUSB_POWER, power);
 	dev_dbg(musb->controller, "issue wakeup\n");
 	/* FIXME do this next chunk in a timer callback, no udelay */
 	mdelay(2);
 	power = musb_readb(mregs, MUSB_POWER);
 	power &= ~MUSB_POWER_RESUME;
 	musb_writeb(mregs, MUSB_POWER, power);
 done:
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return status;
 }
 static int
 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
 {
 	struct musb	*musb = gadget_to_musb(gadget);
 	musb->is_self_powered = !!is_selfpowered;
 	return 0;
 }
 static void musb_pullup(struct musb *musb, int is_on)
 {
 	u8 power;
 	power = musb_readb(musb->mregs, MUSB_POWER);
 	if (is_on)
 		power |= MUSB_POWER_SOFTCONN;
 	else
 		power &= ~MUSB_POWER_SOFTCONN;
 	/* FIXME if on, HdrcStart; if off, HdrcStop */
 	dev_dbg(musb->controller, "gadget D+ pullup %s\n",
 		is_on ? "on" : "off");
 	musb_writeb(musb->mregs, MUSB_POWER, power);
 }
 #if 0
 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
 {
 	dev_dbg(musb->controller, "<= %s =>\n", __func__);
 	/*
 	 * FIXME iff driver's softconnect flag is set (as it is during probe,
 	 * though that can clear it), just musb_pullup().
 	 */
 	return -EINVAL;
 }
 #endif
 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
 {
 	struct musb	*musb = gadget_to_musb(gadget);
 	if (!musb->xceiv->set_power)
 		return -EOPNOTSUPP;
 	return usb_phy_set_power(musb->xceiv, mA);
 }
 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
 {
 	struct musb	*musb = gadget_to_musb(gadget);
 	unsigned long	flags;
 	is_on = !!is_on;
 	pm_runtime_get_sync(musb->controller);
 	/* NOTE: this assumes we are sensing vbus; we'd rather
 	 * not pullup unless the B-session is active.
 	 */
 	spin_lock_irqsave(&musb->lock, flags);
 	if (is_on != musb->softconnect) {
 		musb->softconnect = is_on;
 		musb_pullup(musb, is_on);
 	}
 	spin_unlock_irqrestore(&musb->lock, flags);
 	pm_runtime_put(musb->controller);
 	return 0;
 }
 static int musb_gadget_start(struct usb_gadget *g,
 		struct usb_gadget_driver *driver);
 static int musb_gadget_stop(struct usb_gadget *g,
 		struct usb_gadget_driver *driver);
 static const struct usb_gadget_ops musb_gadget_operations = {
 	.get_frame		= musb_gadget_get_frame,
 	.wakeup			= musb_gadget_wakeup,
 	.set_selfpowered	= musb_gadget_set_self_powered,
 	/* .vbus_session		= musb_gadget_vbus_session, */
 	.vbus_draw		= musb_gadget_vbus_draw,
 	.pullup			= musb_gadget_pullup,
 	.udc_start		= musb_gadget_start,
 	.udc_stop		= musb_gadget_stop,
 };
 /* ----------------------------------------------------------------------- */
 /* Registration */
 /* Only this registration code "knows" the rule (from USB standards)
  * about there being only one external upstream port.  It assumes
  * all peripheral ports are external...
  */
 static void musb_gadget_release(struct device *dev)
 {
 	/* kref_put(WHAT) */
 	dev_dbg(dev, "%s\n", __func__);
 }
 static void __devinit
 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
 {
 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
 	memset(ep, 0, sizeof *ep);
 	ep->current_epnum = epnum;
 	ep->musb = musb;
 	ep->hw_ep = hw_ep;
 	ep->is_in = is_in;
 	INIT_LIST_HEAD(&ep->req_list);
 	sprintf(ep->name, "ep%d%s", epnum,
 			(!epnum || hw_ep->is_shared_fifo) ? "" : (
 				is_in ? "in" : "out"));
 	ep->end_point.name = ep->name;
 	INIT_LIST_HEAD(&ep->end_point.ep_list);
 	if (!epnum) {
 		ep->end_point.maxpacket = 64;
 		ep->end_point.ops = &musb_g_ep0_ops;
 		musb->g.ep0 = &ep->end_point;
 	} else {
 		if (is_in)
 			ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
 		else
 			ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
 		ep->end_point.ops = &musb_ep_ops;
 		list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
 	}
 }
 /*
  * Initialize the endpoints exposed to peripheral drivers, with backlinks
  * to the rest of the driver state.
  */
 static inline void __devinit musb_g_init_endpoints(struct musb *musb)
 {
 	u8			epnum;
 	struct musb_hw_ep	*hw_ep;
 	unsigned		count = 0;
 	/* initialize endpoint list just once */
 	INIT_LIST_HEAD(&(musb->g.ep_list));
 	for (epnum = 0, hw_ep = musb->endpoints;
 			epnum < musb->nr_endpoints;
 			epnum++, hw_ep++) {
 		if (hw_ep->is_shared_fifo /* || !epnum */) {
 			init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
 			count++;
 		} else {
 			if (hw_ep->max_packet_sz_tx) {
 				init_peripheral_ep(musb, &hw_ep->ep_in,
 							epnum, 1);
 				count++;
 			}
 			if (hw_ep->max_packet_sz_rx) {
 				init_peripheral_ep(musb, &hw_ep->ep_out,
 							epnum, 0);
 				count++;
 			}
 		}
 	}
 }
 /* called once during driver setup to initialize and link into
  * the driver model; memory is zeroed.
  */
 int __devinit musb_gadget_setup(struct musb *musb)
 {
 	int status;
 	/* REVISIT minor race:  if (erroneously) setting up two
 	 * musb peripherals at the same time, only the bus lock
 	 * is probably held.
 	 */
 	musb->g.ops = &musb_gadget_operations;
 	musb->g.max_speed = USB_SPEED_HIGH;
 	musb->g.speed = USB_SPEED_UNKNOWN;
 	/* this "gadget" abstracts/virtualizes the controller */
 	dev_set_name(&musb->g.dev, "gadget");
 	musb->g.dev.parent = musb->controller;
 	musb->g.dev.dma_mask = musb->controller->dma_mask;
 	musb->g.dev.release = musb_gadget_release;
 	musb->g.name = musb_driver_name;
-	if (is_otg_enabled(musb))
+	musb->g.is_otg = 1;
-		musb->g.is_otg = 1;
 	musb_g_init_endpoints(musb);
 	musb->is_active = 0;
 	musb_platform_try_idle(musb, 0);
 	status = device_register(&musb->g.dev);
 	if (status != 0) {
 		put_device(&musb->g.dev);
 		return status;
 	}
 	status = usb_add_gadget_udc(musb->controller, &musb->g);
 	if (status)
 		goto err;
 	return 0;
 err:
 	musb->g.dev.parent = NULL;
 	device_unregister(&musb->g.dev);
 	return status;
 }
 void musb_gadget_cleanup(struct musb *musb)
 {
 	usb_del_gadget_udc(&musb->g);
 	if (musb->g.dev.parent)
 		device_unregister(&musb->g.dev);
 }
 /*
  * Register the gadget driver. Used by gadget drivers when
  * registering themselves with the controller.
  *
  * -EINVAL something went wrong (not driver)
  * -EBUSY another gadget is already using the controller
  * -ENOMEM no memory to perform the operation
  *
  * @param driver the gadget driver
  * @return <0 if error, 0 if everything is fine
  */
 static int musb_gadget_start(struct usb_gadget *g,
 		struct usb_gadget_driver *driver)
 {
 	struct musb		*musb = gadget_to_musb(g);
 	struct usb_otg		*otg = musb->xceiv->otg;
+	struct usb_hcd		*hcd = musb_to_hcd(musb);
 	unsigned long		flags;
-	int			retval = -EINVAL;
+	int			retval = 0;
-	if (driver->max_speed < USB_SPEED_HIGH)
+	if (driver->max_speed < USB_SPEED_HIGH) {
-		goto err0;
+		retval = -EINVAL;
+		goto err;
+	}
 	pm_runtime_get_sync(musb->controller);
 	dev_dbg(musb->controller, "registering driver %s\n", driver->function);
 	musb->softconnect = 0;
 	musb->gadget_driver = driver;
 	spin_lock_irqsave(&musb->lock, flags);
 	musb->is_active = 1;
 	otg_set_peripheral(otg, &musb->g);
 	musb->xceiv->state = OTG_STATE_B_IDLE;
+	spin_unlock_irqrestore(&musb->lock, flags);
-	/*
+	/* REVISIT:  funcall to other code, which also
-	 * FIXME this ignores the softconnect flag.  Drivers are
+	 * handles power budgeting ... this way also
-	 * allowed hold the peripheral inactive until for example
+	 * ensures HdrcStart is indirectly called.
-	 * userspace hooks up printer hardware or DSP codecs, so
-	 * hosts only see fully functional devices.
 	 */
+	retval = usb_add_hcd(hcd, 0, 0);
+	if (retval < 0) {
+		dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
+		goto err;
+	}
-	if (!is_otg_enabled(musb))
+	if ((musb->xceiv->last_event == USB_EVENT_ID)
-		musb_start(musb);
+				&& otg->set_vbus)
+		otg_set_vbus(otg, 1);
-	spin_unlock_irqrestore(&musb->lock, flags);
+	hcd->self.uses_pio_for_control = 1;
-	if (is_otg_enabled(musb)) {
-		struct usb_hcd	*hcd = musb_to_hcd(musb);
-		dev_dbg(musb->controller, "OTG startup...\n");
-		/* REVISIT:  funcall to other code, which also
-		 * handles power budgeting ... this way also
-		 * ensures HdrcStart is indirectly called.
-		 */
-		retval = usb_add_hcd(musb_to_hcd(musb), 0, 0);
-		if (retval < 0) {
-			dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
-			goto err2;
-		}
-		if ((musb->xceiv->last_event == USB_EVENT_ID)
-					&& otg->set_vbus)
-			otg_set_vbus(otg, 1);
-		hcd->self.uses_pio_for_control = 1;
-	}
 	if (musb->xceiv->last_event == USB_EVENT_NONE)
 		pm_runtime_put(musb->controller);
 	return 0;
-err2:
+err:
-	if (!is_otg_enabled(musb))
-		musb_stop(musb);
-err0:
 	return retval;
 }
 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
 {
 	int			i;
 	struct musb_hw_ep	*hw_ep;
 	/* don't disconnect if it's not connected */
 	if (musb->g.speed == USB_SPEED_UNKNOWN)
 		driver = NULL;
 	else
 		musb->g.speed = USB_SPEED_UNKNOWN;
 	/* deactivate the hardware */
 	if (musb->softconnect) {
 		musb->softconnect = 0;
 		musb_pullup(musb, 0);
 	}
 	musb_stop(musb);
 	/* killing any outstanding requests will quiesce the driver;
 	 * then report disconnect
 	 */
 	if (driver) {
 		for (i = 0, hw_ep = musb->endpoints;
 				i < musb->nr_endpoints;
 				i++, hw_ep++) {
 			musb_ep_select(musb->mregs, i);
 			if (hw_ep->is_shared_fifo /* || !epnum */) {
 				nuke(&hw_ep->ep_in, -ESHUTDOWN);
 			} else {
 				if (hw_ep->max_packet_sz_tx)
 					nuke(&hw_ep->ep_in, -ESHUTDOWN);
 				if (hw_ep->max_packet_sz_rx)
 					nuke(&hw_ep->ep_out, -ESHUTDOWN);
 			}
 		}
 	}
 }
 /*
  * Unregister the gadget driver. Used by gadget drivers when
  * unregistering themselves from the controller.
  *
  * @param driver the gadget driver to unregister
  */
 static int musb_gadget_stop(struct usb_gadget *g,
 		struct usb_gadget_driver *driver)
 {
 	struct musb	*musb = gadget_to_musb(g);
 	unsigned long	flags;
 	if (musb->xceiv->last_event == USB_EVENT_NONE)
 		pm_runtime_get_sync(musb->controller);
 	/*
 	 * REVISIT always use otg_set_peripheral() here too;
 	 * this needs to shut down the OTG engine.
 	 */
 	spin_lock_irqsave(&musb->lock, flags);
 	musb_hnp_stop(musb);
 	(void) musb_gadget_vbus_draw(&musb->g, 0);
 	musb->xceiv->state = OTG_STATE_UNDEFINED;
 	stop_activity(musb, driver);
 	otg_set_peripheral(musb->xceiv->otg, NULL);
 	dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
 	musb->is_active = 0;
 	musb_platform_try_idle(musb, 0);
 	spin_unlock_irqrestore(&musb->lock, flags);
-	if (is_otg_enabled(musb)) {
+	usb_remove_hcd(musb_to_hcd(musb));
-		usb_remove_hcd(musb_to_hcd(musb));
+	/*
-		/* FIXME we need to be able to register another
+	 * FIXME we need to be able to register another
-		 * gadget driver here and have everything work;
+	 * gadget driver here and have everything work;
-		 * that currently misbehaves.
+	 * that currently misbehaves.
-		 */
+	 */
-	}
-	if (!is_otg_enabled(musb))
-		musb_stop(musb);
 	pm_runtime_put(musb->controller);
 	return 0;
 }
 /* ----------------------------------------------------------------------- */
 /* lifecycle operations called through plat_uds.c */
 void musb_g_resume(struct musb *musb)
 {
 	musb->is_suspended = 0;
 	switch (musb->xceiv->state) {
 	case OTG_STATE_B_IDLE:
 		break;
 	case OTG_STATE_B_WAIT_ACON:
 	case OTG_STATE_B_PERIPHERAL:
 		musb->is_active = 1;
 		if (musb->gadget_driver && musb->gadget_driver->resume) {
 			spin_unlock(&musb->lock);
 			musb->gadget_driver->resume(&musb->g);
 			spin_lock(&musb->lock);
 		}
 		break;
 	default:
 		WARNING("unhandled RESUME transition (%s)\n",
 				otg_state_string(musb->xceiv->state));
 	}
 }
 /* called when SOF packets stop for 3+ msec */
 void musb_g_suspend(struct musb *musb)
 {
 	u8	devctl;
 	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 	dev_dbg(musb->controller, "devctl %02x\n", devctl);
 	switch (musb->xceiv->state) {
 	case OTG_STATE_B_IDLE:
 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
 			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
 		break;
 	case OTG_STATE_B_PERIPHERAL:
 		musb->is_suspended = 1;
 		if (musb->gadget_driver && musb->gadget_driver->suspend) {
 			spin_unlock(&musb->lock);
 			musb->gadget_driver->suspend(&musb->g);
 			spin_lock(&musb->lock);
 		}
 		break;
 	default:
 		/* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
 		 * A_PERIPHERAL may need care too
 		 */
 		WARNING("unhandled SUSPEND transition (%s)\n",
 				otg_state_string(musb->xceiv->state));
 	}
 }
 /* Called during SRP */
 void musb_g_wakeup(struct musb *musb)
 {
 	musb_gadget_wakeup(&musb->g);
 }
 /* called when VBUS drops below session threshold, and in other cases */
 void musb_g_disconnect(struct musb *musb)
 {
 	void __iomem	*mregs = musb->mregs;
 	u8	devctl = musb_readb(mregs, MUSB_DEVCTL);
 	dev_dbg(musb->controller, "devctl %02x\n", devctl);
 	/* clear HR */
 	musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
 	/* don't draw vbus until new b-default session */
 	(void) musb_gadget_vbus_draw(&musb->g, 0);
 	musb->g.speed = USB_SPEED_UNKNOWN;
 	if (musb->gadget_driver && musb->gadget_driver->disconnect) {
 		spin_unlock(&musb->lock);
 		musb->gadget_driver->disconnect(&musb->g);
 		spin_lock(&musb->lock);
 	}
 	switch (musb->xceiv->state) {
 	default:
 		dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
 			otg_state_string(musb->xceiv->state));
 		musb->xceiv->state = OTG_STATE_A_IDLE;
 		MUSB_HST_MODE(musb);
 		break;
 	case OTG_STATE_A_PERIPHERAL:
 		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 		MUSB_HST_MODE(musb);
 		break;
 	case OTG_STATE_B_WAIT_ACON:
 	case OTG_STATE_B_HOST:
 	case OTG_STATE_B_PERIPHERAL:
 	case OTG_STATE_B_IDLE:
 		musb->xceiv->state = OTG_STATE_B_IDLE;
 		break;
 	case OTG_STATE_B_SRP_INIT:
 		break;
 	}
 	musb->is_active = 0;
 }
 void musb_g_reset(struct musb *musb)
 __releases(musb->lock)
 __acquires(musb->lock)
 {
 	void __iomem	*mbase = musb->mregs;
 	u8		devctl = musb_readb(mbase, MUSB_DEVCTL);
 	u8		power;
 	dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
 			(devctl & MUSB_DEVCTL_BDEVICE)
 				? "B-Device" : "A-Device",
 			musb_readb(mbase, MUSB_FADDR),
 			musb->gadget_driver
 				? musb->gadget_driver->driver.name
 				: NULL
 			);
 	/* report disconnect, if we didn't already (flushing EP state) */
 	if (musb->g.speed != USB_SPEED_UNKNOWN)
 		musb_g_disconnect(musb);
 	/* clear HR */
 	else if (devctl & MUSB_DEVCTL_HR)
 		musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
 	/* what speed did we negotiate? */
 	power = musb_readb(mbase, MUSB_POWER);
 	musb->g.speed = (power & MUSB_POWER_HSMODE)
 			? USB_SPEED_HIGH : USB_SPEED_FULL;
 	/* start in USB_STATE_DEFAULT */
 	musb->is_active = 1;
 	musb->is_suspended = 0;
 	MUSB_DEV_MODE(musb);
 	musb->address = 0;
 	musb->ep0_state = MUSB_EP0_STAGE_SETUP;
 	musb->may_wakeup = 0;
 	musb->g.b_hnp_enable = 0;
 	musb->g.a_alt_hnp_support = 0;
 	musb->g.a_hnp_support = 0;
 	/* Normal reset, as B-Device;
 	 * or else after HNP, as A-Device
 	 */
 	if (devctl & MUSB_DEVCTL_BDEVICE) {
 		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
 		musb->g.is_a_peripheral = 0;
-	} else if (is_otg_enabled(musb)) {
+	} else {

drivers/usb/musb/musb_virthub.c

Diff comments View file @ 032ec49

 /*
  * MUSB OTG driver virtual root hub support
  *
  * Copyright 2005 Mentor Graphics Corporation
  * Copyright (C) 2005-2006 by Texas Instruments
  * Copyright (C) 2006-2007 Nokia Corporation
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  * General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  *
  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/time.h>
 #include <linux/timer.h>
 #include <asm/unaligned.h>
 #include "musb_core.h"
 static void musb_port_suspend(struct musb *musb, bool do_suspend)
 {
 	struct usb_otg	*otg = musb->xceiv->otg;
 	u8		power;
 	void __iomem	*mbase = musb->mregs;
 	if (!is_host_active(musb))
 		return;
 	/* NOTE:  this doesn't necessarily put PHY into low power mode,
 	 * turning off its clock; that's a function of PHY integration and
 	 * MUSB_POWER_ENSUSPEND.  PHY may need a clock (sigh) to detect
 	 * SE0 changing to connect (J) or wakeup (K) states.
 	 */
 	power = musb_readb(mbase, MUSB_POWER);
 	if (do_suspend) {
 		int retries = 10000;
 		power &= ~MUSB_POWER_RESUME;
 		power |= MUSB_POWER_SUSPENDM;
 		musb_writeb(mbase, MUSB_POWER, power);
 		/* Needed for OPT A tests */
 		power = musb_readb(mbase, MUSB_POWER);
 		while (power & MUSB_POWER_SUSPENDM) {
 			power = musb_readb(mbase, MUSB_POWER);
 			if (retries-- < 1)
 				break;
 		}
 		dev_dbg(musb->controller, "Root port suspended, power %02x\n", power);
 		musb->port1_status |= USB_PORT_STAT_SUSPEND;
 		switch (musb->xceiv->state) {
 		case OTG_STATE_A_HOST:
 			musb->xceiv->state = OTG_STATE_A_SUSPEND;
-			musb->is_active = is_otg_enabled(musb)
+			musb->is_active = otg->host->b_hnp_enable;
-					&& otg->host->b_hnp_enable;
 			if (musb->is_active)
 				mod_timer(&musb->otg_timer, jiffies
 					+ msecs_to_jiffies(
 						OTG_TIME_A_AIDL_BDIS));
 			musb_platform_try_idle(musb, 0);
 			break;
 		case OTG_STATE_B_HOST:
 			musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
-			musb->is_active = is_otg_enabled(musb)
+			musb->is_active = otg->host->b_hnp_enable;
-					&& otg->host->b_hnp_enable;
 			musb_platform_try_idle(musb, 0);
 			break;
 		default:
 			dev_dbg(musb->controller, "bogus rh suspend? %s\n",
 				otg_state_string(musb->xceiv->state));
 		}
 	} else if (power & MUSB_POWER_SUSPENDM) {
 		power &= ~MUSB_POWER_SUSPENDM;
 		power |= MUSB_POWER_RESUME;
 		musb_writeb(mbase, MUSB_POWER, power);
 		dev_dbg(musb->controller, "Root port resuming, power %02x\n", power);
 		/* later, GetPortStatus will stop RESUME signaling */
 		musb->port1_status |= MUSB_PORT_STAT_RESUME;
 		musb->rh_timer = jiffies + msecs_to_jiffies(20);
 	}
 }
 static void musb_port_reset(struct musb *musb, bool do_reset)
 {
 	u8		power;
 	void __iomem	*mbase = musb->mregs;
 	if (musb->xceiv->state == OTG_STATE_B_IDLE) {
 		dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
 		musb->port1_status &= ~USB_PORT_STAT_RESET;
 		return;
 	}
 	if (!is_host_active(musb))
 		return;
 	/* NOTE:  caller guarantees it will turn off the reset when
 	 * the appropriate amount of time has passed
 	 */
 	power = musb_readb(mbase, MUSB_POWER);
 	if (do_reset) {
 		/*
 		 * If RESUME is set, we must make sure it stays minimum 20 ms.
 		 * Then we must clear RESUME and wait a bit to let musb start
 		 * generating SOFs. If we don't do this, OPT HS A 6.8 tests
 		 * fail with "Error! Did not receive an SOF before suspend
 		 * detected".
 		 */
 		if (power &  MUSB_POWER_RESUME) {
 			while (time_before(jiffies, musb->rh_timer))
 				msleep(1);
 			musb_writeb(mbase, MUSB_POWER,
 				power & ~MUSB_POWER_RESUME);
 			msleep(1);
 		}
 		musb->ignore_disconnect = true;
 		power &= 0xf0;
 		musb_writeb(mbase, MUSB_POWER,
 				power | MUSB_POWER_RESET);
 		musb->port1_status |= USB_PORT_STAT_RESET;
 		musb->port1_status &= ~USB_PORT_STAT_ENABLE;
 		musb->rh_timer = jiffies + msecs_to_jiffies(50);
 	} else {
 		dev_dbg(musb->controller, "root port reset stopped\n");
 		musb_writeb(mbase, MUSB_POWER,
 				power & ~MUSB_POWER_RESET);
 		musb->ignore_disconnect = false;
 		power = musb_readb(mbase, MUSB_POWER);
 		if (power & MUSB_POWER_HSMODE) {
 			dev_dbg(musb->controller, "high-speed device connected\n");
 			musb->port1_status |= USB_PORT_STAT_HIGH_SPEED;
 		}
 		musb->port1_status &= ~USB_PORT_STAT_RESET;
 		musb->port1_status |= USB_PORT_STAT_ENABLE
 					| (USB_PORT_STAT_C_RESET << 16)
 					| (USB_PORT_STAT_C_ENABLE << 16);
 		usb_hcd_poll_rh_status(musb_to_hcd(musb));
 		musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
 	}
 }
 void musb_root_disconnect(struct musb *musb)
 {
 	struct usb_otg	*otg = musb->xceiv->otg;
 	musb->port1_status = USB_PORT_STAT_POWER
 			| (USB_PORT_STAT_C_CONNECTION << 16);
 	usb_hcd_poll_rh_status(musb_to_hcd(musb));
 	musb->is_active = 0;
 	switch (musb->xceiv->state) {
 	case OTG_STATE_A_SUSPEND:
-		if (is_otg_enabled(musb)
+		if (otg->host->b_hnp_enable) {
-				&& otg->host->b_hnp_enable) {
 			musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
 			musb->g.is_a_peripheral = 1;
 			break;
 		}
 		/* FALLTHROUGH */
 	case OTG_STATE_A_HOST:
 		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 		musb->is_active = 0;
 		break;
 	case OTG_STATE_A_WAIT_VFALL:
 		musb->xceiv->state = OTG_STATE_B_IDLE;
 		break;
 	default:
 		dev_dbg(musb->controller, "host disconnect (%s)\n",
 			otg_state_string(musb->xceiv->state));
 	}
 }
 /*---------------------------------------------------------------------*/
 /* Caller may or may not hold musb->lock */
 int musb_hub_status_data(struct usb_hcd *hcd, char *buf)
 {
 	struct musb	*musb = hcd_to_musb(hcd);
 	int		retval = 0;
 	/* called in_irq() via usb_hcd_poll_rh_status() */
 	if (musb->port1_status & 0xffff0000) {
 		*buf = 0x02;
 		retval = 1;
 	}
 	return retval;
 }
 int musb_hub_control(
 	struct usb_hcd	*hcd,
 	u16		typeReq,
 	u16		wValue,
 	u16		wIndex,
 	char		*buf,
 	u16		wLength)
 {
 	struct musb	*musb = hcd_to_musb(hcd);
 	u32		temp;
 	int		retval = 0;
 	unsigned long	flags;
 	spin_lock_irqsave(&musb->lock, flags);
 	if (unlikely(!HCD_HW_ACCESSIBLE(hcd))) {
 		spin_unlock_irqrestore(&musb->lock, flags);
 		return -ESHUTDOWN;
 	}
 	/* hub features:  always zero, setting is a NOP
 	 * port features: reported, sometimes updated when host is active
 	 * no indicators
 	 */
 	switch (typeReq) {
 	case ClearHubFeature:
 	case SetHubFeature:
 		switch (wValue) {
 		case C_HUB_OVER_CURRENT:
 		case C_HUB_LOCAL_POWER:
 			break;
 		default:
 			goto error;
 		}
 		break;
 	case ClearPortFeature:
 		if ((wIndex & 0xff) != 1)
 			goto error;
 		switch (wValue) {
 		case USB_PORT_FEAT_ENABLE:
 			break;
 		case USB_PORT_FEAT_SUSPEND:
 			musb_port_suspend(musb, false);
 			break;
 		case USB_PORT_FEAT_POWER:
-			if (!(is_otg_enabled(musb) && hcd->self.is_b_host))
+			if (!hcd->self.is_b_host)
 				musb_platform_set_vbus(musb, 0);
 			break;
 		case USB_PORT_FEAT_C_CONNECTION:
 		case USB_PORT_FEAT_C_ENABLE:
 		case USB_PORT_FEAT_C_OVER_CURRENT:
 		case USB_PORT_FEAT_C_RESET:
 		case USB_PORT_FEAT_C_SUSPEND:
 			break;
 		default:
 			goto error;
 		}
 		dev_dbg(musb->controller, "clear feature %d\n", wValue);
 		musb->port1_status &= ~(1 << wValue);
 		break;
 	case GetHubDescriptor:
 		{
 		struct usb_hub_descriptor *desc = (void *)buf;
 		desc->bDescLength = 9;
 		desc->bDescriptorType = 0x29;
 		desc->bNbrPorts = 1;
 		desc->wHubCharacteristics = cpu_to_le16(
 				  0x0001	/* per-port power switching */
 				| 0x0010	/* no overcurrent reporting */
 				);
 		desc->bPwrOn2PwrGood = 5;	/* msec/2 */
 		desc->bHubContrCurrent = 0;
 		/* workaround bogus struct definition */
 		desc->u.hs.DeviceRemovable[0] = 0x02;	/* port 1 */
 		desc->u.hs.DeviceRemovable[1] = 0xff;
 		}
 		break;
 	case GetHubStatus:
 		temp = 0;
 		*(__le32 *) buf = cpu_to_le32(temp);
 		break;
 	case GetPortStatus:
 		if (wIndex != 1)
 			goto error;
 		/* finish RESET signaling? */
 		if ((musb->port1_status & USB_PORT_STAT_RESET)
 				&& time_after_eq(jiffies, musb->rh_timer))
 			musb_port_reset(musb, false);
 		/* finish RESUME signaling? */
 		if ((musb->port1_status & MUSB_PORT_STAT_RESUME)
 				&& time_after_eq(jiffies, musb->rh_timer)) {
 			u8		power;
 			power = musb_readb(musb->mregs, MUSB_POWER);
 			power &= ~MUSB_POWER_RESUME;
 			dev_dbg(musb->controller, "root port resume stopped, power %02x\n",
 					power);
 			musb_writeb(musb->mregs, MUSB_POWER, power);
 			/* ISSUE:  DaVinci (RTL 1.300) disconnects after
 			 * resume of high speed peripherals (but not full
 			 * speed ones).
 			 */
 			musb->is_active = 1;
 			musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
 					| MUSB_PORT_STAT_RESUME);
 			musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
 			usb_hcd_poll_rh_status(musb_to_hcd(musb));
 			/* NOTE: it might really be A_WAIT_BCON ... */
 			musb->xceiv->state = OTG_STATE_A_HOST;
 		}
 		put_unaligned(cpu_to_le32(musb->port1_status
 					& ~MUSB_PORT_STAT_RESUME),
 				(__le32 *) buf);
 		/* port change status is more interesting */
 		dev_dbg(musb->controller, "port status %08x\n",
 				musb->port1_status);
 		break;
 	case SetPortFeature:
 		if ((wIndex & 0xff) != 1)
 			goto error;
 		switch (wValue) {
 		case USB_PORT_FEAT_POWER:
 			/* NOTE: this controller has a strange state machine
 			 * that involves "requesting sessions" according to
 			 * magic side effects from incompletely-described
 			 * rules about startup...
 			 *
 			 * This call is what really starts the host mode; be
 			 * very careful about side effects if you reorder any
 			 * initialization logic, e.g. for OTG, or change any
 			 * logic relating to VBUS power-up.
 			 */
-			if (!(is_otg_enabled(musb) && hcd->self.is_b_host))
+			if (!hcd->self.is_b_host)
 				musb_start(musb);
 			break;
 		case USB_PORT_FEAT_RESET:
 			musb_port_reset(musb, true);
 			break;
 		case USB_PORT_FEAT_SUSPEND:
 			musb_port_suspend(musb, true);
 			break;
 		case USB_PORT_FEAT_TEST:
 			if (unlikely(is_host_active(musb)))
 				goto error;
 			wIndex >>= 8;
 			switch (wIndex) {
 			case 1:
 				pr_debug("TEST_J\n");
 				temp = MUSB_TEST_J;
 				break;
 			case 2:
 				pr_debug("TEST_K\n");
 				temp = MUSB_TEST_K;
 				break;
 			case 3:
 				pr_debug("TEST_SE0_NAK\n");
 				temp = MUSB_TEST_SE0_NAK;
 				break;
 			case 4:
 				pr_debug("TEST_PACKET\n");
 				temp = MUSB_TEST_PACKET;
 				musb_load_testpacket(musb);
 				break;
 			case 5:
 				pr_debug("TEST_FORCE_ENABLE\n");
 				temp = MUSB_TEST_FORCE_HOST
 					| MUSB_TEST_FORCE_HS;
 				musb_writeb(musb->mregs, MUSB_DEVCTL,
 						MUSB_DEVCTL_SESSION);
 				break;
 			case 6:
 				pr_debug("TEST_FIFO_ACCESS\n");
 				temp = MUSB_TEST_FIFO_ACCESS;
 				break;
 			default:
 				goto error;
 			}
 			musb_writeb(musb->mregs, MUSB_TESTMODE, temp);
 			break;
 		default:
 			goto error;
 		}
 		dev_dbg(musb->controller, "set feature %d\n", wValue);
 		musb->port1_status |= 1 << wValue;
 		break;
 	default:
 error:
 		/* "protocol stall" on error */
 		retval = -EPIPE;
 	}
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return retval;
 }

drivers/usb/musb/omap2430.c

Diff comments View file @ 032ec49

 /*
  * Copyright (C) 2005-2007 by Texas Instruments
  * Some code has been taken from tusb6010.c
  * Copyrights for that are attributable to:
  * Copyright (C) 2006 Nokia Corporation
  * Tony Lindgren <tony@atomide.com>
  *
  * This file is part of the Inventra Controller Driver for Linux.
  *
  * The Inventra Controller Driver for Linux is free software; you
  * can redistribute it and/or modify it under the terms of the GNU
  * General Public License version 2 as published by the Free Software
  * Foundation.
  *
  * The Inventra Controller Driver for Linux is distributed in
  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  * without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  * License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with The Inventra Controller Driver for Linux ; if not,
  * write to the Free Software Foundation, Inc., 59 Temple Place,
  * Suite 330, Boston, MA  02111-1307  USA
  *
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/pm_runtime.h>
 #include <linux/err.h>
 #include <linux/usb/musb-omap.h>
 #include "musb_core.h"
 #include "omap2430.h"
 struct omap2430_glue {
 	struct device		*dev;
 	struct platform_device	*musb;
 	enum omap_musb_vbus_id_status status;
 	struct work_struct	omap_musb_mailbox_work;
 };
 #define glue_to_musb(g)		platform_get_drvdata(g->musb)
 struct omap2430_glue		*_glue;
 static struct timer_list musb_idle_timer;
 static void musb_do_idle(unsigned long _musb)
 {
 	struct musb	*musb = (void *)_musb;
 	unsigned long	flags;
 	u8	power;
 	u8	devctl;
 	spin_lock_irqsave(&musb->lock, flags);
 	switch (musb->xceiv->state) {
 	case OTG_STATE_A_WAIT_BCON:
 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 		if (devctl & MUSB_DEVCTL_BDEVICE) {
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 			MUSB_DEV_MODE(musb);
 		} else {
 			musb->xceiv->state = OTG_STATE_A_IDLE;
 			MUSB_HST_MODE(musb);
 		}
 		break;
 	case OTG_STATE_A_SUSPEND:
 		/* finish RESUME signaling? */
 		if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
 			power = musb_readb(musb->mregs, MUSB_POWER);
 			power &= ~MUSB_POWER_RESUME;
 			dev_dbg(musb->controller, "root port resume stopped, power %02x\n", power);
 			musb_writeb(musb->mregs, MUSB_POWER, power);
 			musb->is_active = 1;
 			musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
 						| MUSB_PORT_STAT_RESUME);
 			musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
 			usb_hcd_poll_rh_status(musb_to_hcd(musb));
 			/* NOTE: it might really be A_WAIT_BCON ... */
 			musb->xceiv->state = OTG_STATE_A_HOST;
 		}
 		break;
 	case OTG_STATE_A_HOST:
 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 		if (devctl &  MUSB_DEVCTL_BDEVICE)
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 		else
 			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 	default:
 		break;
 	}
 	spin_unlock_irqrestore(&musb->lock, flags);
 }
 static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
 {
 	unsigned long		default_timeout = jiffies + msecs_to_jiffies(3);
 	static unsigned long	last_timer;
 	if (timeout == 0)
 		timeout = default_timeout;
 	/* Never idle if active, or when VBUS timeout is not set as host */
 	if (musb->is_active || ((musb->a_wait_bcon == 0)
 			&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
 		dev_dbg(musb->controller, "%s active, deleting timer\n",
 			otg_state_string(musb->xceiv->state));
 		del_timer(&musb_idle_timer);
 		last_timer = jiffies;
 		return;
 	}
 	if (time_after(last_timer, timeout)) {
 		if (!timer_pending(&musb_idle_timer))
 			last_timer = timeout;
 		else {
 			dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
 			return;
 		}
 	}
 	last_timer = timeout;
 	dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
 		otg_state_string(musb->xceiv->state),
 		(unsigned long)jiffies_to_msecs(timeout - jiffies));
 	mod_timer(&musb_idle_timer, timeout);
 }
 static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
 {
 	struct usb_otg	*otg = musb->xceiv->otg;
 	u8		devctl;
 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 	int ret = 1;
 	/* HDRC controls CPEN, but beware current surges during device
 	 * connect.  They can trigger transient overcurrent conditions
 	 * that must be ignored.
 	 */
 	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 	if (is_on) {
 		if (musb->xceiv->state == OTG_STATE_A_IDLE) {
 			/* start the session */
 			devctl |= MUSB_DEVCTL_SESSION;
 			musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 			/*
 			 * Wait for the musb to set as A device to enable the
 			 * VBUS
 			 */
 			while (musb_readb(musb->mregs, MUSB_DEVCTL) & 0x80) {
 				cpu_relax();
 				if (time_after(jiffies, timeout)) {
 					dev_err(musb->controller,
 					"configured as A device timeout");
 					ret = -EINVAL;
 					break;
 				}
 			}
 			if (ret && otg->set_vbus)
 				otg_set_vbus(otg, 1);
 		} else {
 			musb->is_active = 1;
 			otg->default_a = 1;
 			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 			devctl |= MUSB_DEVCTL_SESSION;
 			MUSB_HST_MODE(musb);
 		}
 	} else {
 		musb->is_active = 0;
 		/* NOTE:  we're skipping A_WAIT_VFALL -> A_IDLE and
 		 * jumping right to B_IDLE...
 		 */
 		otg->default_a = 0;
 		musb->xceiv->state = OTG_STATE_B_IDLE;
 		devctl &= ~MUSB_DEVCTL_SESSION;
 		MUSB_DEV_MODE(musb);
 	}
 	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
 		/* otg %3x conf %08x prcm %08x */ "\n",
 		otg_state_string(musb->xceiv->state),
 		musb_readb(musb->mregs, MUSB_DEVCTL));
 }
 static int omap2430_musb_set_mode(struct musb *musb, u8 musb_mode)
 {
 	u8	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 	devctl |= MUSB_DEVCTL_SESSION;
 	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 	return 0;
 }
 static inline void omap2430_low_level_exit(struct musb *musb)
 {
 	u32 l;
 	/* in any role */
 	l = musb_readl(musb->mregs, OTG_FORCESTDBY);
 	l |= ENABLEFORCE;	/* enable MSTANDBY */
 	musb_writel(musb->mregs, OTG_FORCESTDBY, l);
 }
 static inline void omap2430_low_level_init(struct musb *musb)
 {
 	u32 l;
 	l = musb_readl(musb->mregs, OTG_FORCESTDBY);
 	l &= ~ENABLEFORCE;	/* disable MSTANDBY */
 	musb_writel(musb->mregs, OTG_FORCESTDBY, l);
 }
 void omap_musb_mailbox(enum omap_musb_vbus_id_status status)
 {
 	struct omap2430_glue	*glue = _glue;
 	struct musb		*musb = glue_to_musb(glue);
 	glue->status = status;
 	if (!musb) {
 		dev_err(glue->dev, "musb core is not yet ready\n");
 		return;
 	}
 	schedule_work(&glue->omap_musb_mailbox_work);
 }
 EXPORT_SYMBOL_GPL(omap_musb_mailbox);
 static void omap_musb_set_mailbox(struct omap2430_glue *glue)
 {
 	struct musb *musb = glue_to_musb(glue);
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *pdata = dev->platform_data;
 	struct omap_musb_board_data *data = pdata->board_data;
 	struct usb_otg *otg = musb->xceiv->otg;
 	switch (glue->status) {
 	case OMAP_MUSB_ID_GROUND:
 		dev_dbg(dev, "ID GND\n");
 		otg->default_a = true;
 		musb->xceiv->state = OTG_STATE_A_IDLE;
 		musb->xceiv->last_event = USB_EVENT_ID;
-		if (!is_otg_enabled(musb) || musb->gadget_driver) {
+		if (musb->gadget_driver) {
 			pm_runtime_get_sync(dev);
 			usb_phy_init(musb->xceiv);
 			omap2430_musb_set_vbus(musb, 1);
 		}
 		break;
 	case OMAP_MUSB_VBUS_VALID:
 		dev_dbg(dev, "VBUS Connect\n");
 		otg->default_a = false;
 		musb->xceiv->state = OTG_STATE_B_IDLE;
 		musb->xceiv->last_event = USB_EVENT_VBUS;
 		if (musb->gadget_driver)
 			pm_runtime_get_sync(dev);
 		usb_phy_init(musb->xceiv);
 		break;
 	case OMAP_MUSB_ID_FLOAT:
 	case OMAP_MUSB_VBUS_OFF:
 		dev_dbg(dev, "VBUS Disconnect\n");
 		musb->xceiv->last_event = USB_EVENT_NONE;
-		if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
+		if (musb->gadget_driver) {
-			if (musb->gadget_driver) {
+			pm_runtime_mark_last_busy(dev);
-				pm_runtime_mark_last_busy(dev);
+			pm_runtime_put_autosuspend(dev);
-				pm_runtime_put_autosuspend(dev);
+		}
-			}
 		if (data->interface_type == MUSB_INTERFACE_UTMI) {
 			if (musb->xceiv->otg->set_vbus)
 				otg_set_vbus(musb->xceiv->otg, 0);
 		}
 		usb_phy_shutdown(musb->xceiv);
 		break;
 	default:
 		dev_dbg(dev, "ID float\n");
 	}
 }
 static void omap_musb_mailbox_work(struct work_struct *mailbox_work)
 {
 	struct omap2430_glue *glue = container_of(mailbox_work,
 				struct omap2430_glue, omap_musb_mailbox_work);
 	omap_musb_set_mailbox(glue);
 }
 static int omap2430_musb_init(struct musb *musb)
 {
 	u32 l;
 	int status = 0;
 	struct device *dev = musb->controller;
 	struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
 	struct musb_hdrc_platform_data *plat = dev->platform_data;
 	struct omap_musb_board_data *data = plat->board_data;
 	/* We require some kind of external transceiver, hooked
 	 * up through ULPI.  TWL4030-family PMICs include one,
 	 * which needs a driver, drivers aren't always needed.
 	 */
 	musb->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 	if (IS_ERR_OR_NULL(musb->xceiv)) {
 		pr_err("HS USB OTG: no transceiver configured\n");
 		return -ENODEV;
 	}
 	status = pm_runtime_get_sync(dev);
 	if (status < 0) {
 		dev_err(dev, "pm_runtime_get_sync FAILED %d\n", status);
 		goto err1;
 	}
 	l = musb_readl(musb->mregs, OTG_INTERFSEL);
 	if (data->interface_type == MUSB_INTERFACE_UTMI) {
 		/* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
 		l &= ~ULPI_12PIN;       /* Disable ULPI */
 		l |= UTMI_8BIT;         /* Enable UTMI  */
 	} else {
 		l |= ULPI_12PIN;
 	}
 	musb_writel(musb->mregs, OTG_INTERFSEL, l);
 	pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
 			"sysstatus 0x%x, intrfsel 0x%x, simenable  0x%x\n",
 			musb_readl(musb->mregs, OTG_REVISION),
 			musb_readl(musb->mregs, OTG_SYSCONFIG),
 			musb_readl(musb->mregs, OTG_SYSSTATUS),
 			musb_readl(musb->mregs, OTG_INTERFSEL),
 			musb_readl(musb->mregs, OTG_SIMENABLE));
 	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
 	if (glue->status != OMAP_MUSB_UNKNOWN)
 		omap_musb_set_mailbox(glue);
 	pm_runtime_put_noidle(musb->controller);
 	return 0;
 err1:
 	return status;
 }
 static void omap2430_musb_enable(struct musb *musb)
 {
 	u8		devctl;
 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 	struct device *dev = musb->controller;
 	struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
 	struct musb_hdrc_platform_data *pdata = dev->platform_data;
 	struct omap_musb_board_data *data = pdata->board_data;
 	switch (glue->status) {
 	case OMAP_MUSB_ID_GROUND:
 		usb_phy_init(musb->xceiv);
 		if (data->interface_type != MUSB_INTERFACE_UTMI)
 			break;
 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 		/* start the session */
 		devctl |= MUSB_DEVCTL_SESSION;
 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 		while (musb_readb(musb->mregs, MUSB_DEVCTL) &
 				MUSB_DEVCTL_BDEVICE) {
 			cpu_relax();
 			if (time_after(jiffies, timeout)) {
 				dev_err(dev, "configured as A device timeout");
 				break;
 			}
 		}
 		break;
 	case OMAP_MUSB_VBUS_VALID:
 		usb_phy_init(musb->xceiv);
 		break;
 	default:
 		break;
 	}
 }
 static void omap2430_musb_disable(struct musb *musb)
 {
 	struct device *dev = musb->controller;
 	struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
 	if (glue->status != OMAP_MUSB_UNKNOWN)
 		usb_phy_shutdown(musb->xceiv);
 }
 static int omap2430_musb_exit(struct musb *musb)
 {
 	del_timer_sync(&musb_idle_timer);
 	omap2430_low_level_exit(musb);
 	return 0;
 }
 static const struct musb_platform_ops omap2430_ops = {
 	.init		= omap2430_musb_init,
 	.exit		= omap2430_musb_exit,
 	.set_mode	= omap2430_musb_set_mode,
 	.try_idle	= omap2430_musb_try_idle,
 	.set_vbus	= omap2430_musb_set_vbus,
 	.enable		= omap2430_musb_enable,
 	.disable	= omap2430_musb_disable,
 };
 static u64 omap2430_dmamask = DMA_BIT_MASK(32);
 static int __devinit omap2430_probe(struct platform_device *pdev)
 {
 	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
 	struct platform_device		*musb;
 	struct omap2430_glue		*glue;
 	int				ret = -ENOMEM;
 	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
 	if (!glue) {
 		dev_err(&pdev->dev, "failed to allocate glue context\n");
 		goto err0;
 	}
 	musb = platform_device_alloc("musb-hdrc", -1);
 	if (!musb) {
 		dev_err(&pdev->dev, "failed to allocate musb device\n");
 		goto err0;
 	}
 	musb->dev.parent		= &pdev->dev;
 	musb->dev.dma_mask		= &omap2430_dmamask;
 	musb->dev.coherent_dma_mask	= omap2430_dmamask;
 	glue->dev			= &pdev->dev;
 	glue->musb			= musb;
 	glue->status			= OMAP_MUSB_UNKNOWN;
 	pdata->platform_ops		= &omap2430_ops;
 	platform_set_drvdata(pdev, glue);
 	/*
 	 * REVISIT if we ever have two instances of the wrapper, we will be
 	 * in big trouble
 	 */
 	_glue	= glue;
 	INIT_WORK(&glue->omap_musb_mailbox_work, omap_musb_mailbox_work);
 	ret = platform_device_add_resources(musb, pdev->resource,
 			pdev->num_resources);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add resources\n");
 		goto err1;
 	}
 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add platform_data\n");
 		goto err1;
 	}
 	pm_runtime_enable(&pdev->dev);
 	ret = platform_device_add(musb);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register musb device\n");
 		goto err1;
 	}
 	return 0;
 err1:
 	platform_device_put(musb);
 err0:
 	return ret;
 }
 static int __devexit omap2430_remove(struct platform_device *pdev)
 {
 	struct omap2430_glue		*glue = platform_get_drvdata(pdev);
 	cancel_work_sync(&glue->omap_musb_mailbox_work);
 	platform_device_unregister(glue->musb);
 	return 0;
 }
 #ifdef CONFIG_PM
 static int omap2430_runtime_suspend(struct device *dev)
 {
 	struct omap2430_glue		*glue = dev_get_drvdata(dev);
 	struct musb			*musb = glue_to_musb(glue);
 	if (musb) {
 		musb->context.otg_interfsel = musb_readl(musb->mregs,
 				OTG_INTERFSEL);
 		omap2430_low_level_exit(musb);
 		usb_phy_set_suspend(musb->xceiv, 1);
 	}
 	return 0;
 }
 static int omap2430_runtime_resume(struct device *dev)
 {
 	struct omap2430_glue		*glue = dev_get_drvdata(dev);
 	struct musb			*musb = glue_to_musb(glue);
 	if (musb) {
 		omap2430_low_level_init(musb);
 		musb_writel(musb->mregs, OTG_INTERFSEL,
 				musb->context.otg_interfsel);
 		usb_phy_set_suspend(musb->xceiv, 0);
 	}
 	return 0;
 }
 static struct dev_pm_ops omap2430_pm_ops = {
 	.runtime_suspend = omap2430_runtime_suspend,
 	.runtime_resume = omap2430_runtime_resume,
 };
 #define DEV_PM_OPS	(&omap2430_pm_ops)
 #else
 #define DEV_PM_OPS	NULL
 #endif
 static struct platform_driver omap2430_driver = {
 	.probe		= omap2430_probe,
 	.remove		= __devexit_p(omap2430_remove),
 	.driver		= {
 		.name	= "musb-omap2430",
 		.pm	= DEV_PM_OPS,
 	},
 };
 MODULE_DESCRIPTION("OMAP2PLUS MUSB Glue Layer");
 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 MODULE_LICENSE("GPL v2");
 static int __init omap2430_init(void)
 {
 	return platform_driver_register(&omap2430_driver);
 }
 subsys_initcall(omap2430_init);
 static void __exit omap2430_exit(void)
 {
 	platform_driver_unregister(&omap2430_driver);
 }
 module_exit(omap2430_exit);

drivers/usb/musb/tusb6010.c

Diff comments View file @ 032ec49

 /*
  * TUSB6010 USB 2.0 OTG Dual Role controller
  *
  * Copyright (C) 2006 Nokia Corporation
  * Tony Lindgren <tony@atomide.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
  * Notes:
  * - Driver assumes that interface to external host (main CPU) is
  *   configured for NOR FLASH interface instead of VLYNQ serial
  *   interface.
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/prefetch.h>
 #include <linux/usb.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include "musb_core.h"
 struct tusb6010_glue {
 	struct device		*dev;
 	struct platform_device	*musb;
 };
 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
 #define TUSB_REV_MAJOR(reg_val)		((reg_val >> 4) & 0xf)
 #define TUSB_REV_MINOR(reg_val)		(reg_val & 0xf)
 /*
  * Checks the revision. We need to use the DMA register as 3.0 does not
  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
  */
 u8 tusb_get_revision(struct musb *musb)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	u32		die_id;
 	u8		rev;
 	rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
 	if (TUSB_REV_MAJOR(rev) == 3) {
 		die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
 				TUSB_DIDR1_HI));
 		if (die_id >= TUSB_DIDR1_HI_REV_31)
 			rev |= 1;
 	}
 	return rev;
 }
 EXPORT_SYMBOL_GPL(tusb_get_revision);
 static int tusb_print_revision(struct musb *musb)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	u8		rev;
 	rev = tusb_get_revision(musb);
 	pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
 		"prcm",
 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
 		"int",
 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
 		"gpio",
 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
 		"dma",
 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
 		"dieid",
 		TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
 		"rev",
 		TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
 	return tusb_get_revision(musb);
 }
 #define WBUS_QUIRK_MASK	(TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
 				| TUSB_PHY_OTG_CTRL_TESTM0)
 /*
  * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
  * Disables power detection in PHY for the duration of idle.
  */
 static void tusb_wbus_quirk(struct musb *musb, int enabled)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	static u32	phy_otg_ctrl, phy_otg_ena;
 	u32		tmp;
 	if (enabled) {
 		phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
 		phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
 		tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
 				| phy_otg_ena | WBUS_QUIRK_MASK;
 		musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
 		tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
 		tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
 		musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
 		dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
 			musb_readl(tbase, TUSB_PHY_OTG_CTRL),
 			musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
 	} else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
 					& TUSB_PHY_OTG_CTRL_TESTM2) {
 		tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
 		musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
 		tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
 		musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
 		dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
 			musb_readl(tbase, TUSB_PHY_OTG_CTRL),
 			musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
 		phy_otg_ctrl = 0;
 		phy_otg_ena = 0;
 	}
 }
 /*
  * TUSB 6010 may use a parallel bus that doesn't support byte ops;
  * so both loading and unloading FIFOs need explicit byte counts.
  */
 static inline void
 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
 {
 	u32		val;
 	int		i;
 	if (len > 4) {
 		for (i = 0; i < (len >> 2); i++) {
 			memcpy(&val, buf, 4);
 			musb_writel(fifo, 0, val);
 			buf += 4;
 		}
 		len %= 4;
 	}
 	if (len > 0) {
 		/* Write the rest 1 - 3 bytes to FIFO */
 		memcpy(&val, buf, len);
 		musb_writel(fifo, 0, val);
 	}
 }
 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
 						void *buf, u16 len)
 {
 	u32		val;
 	int		i;
 	if (len > 4) {
 		for (i = 0; i < (len >> 2); i++) {
 			val = musb_readl(fifo, 0);
 			memcpy(buf, &val, 4);
 			buf += 4;
 		}
 		len %= 4;
 	}
 	if (len > 0) {
 		/* Read the rest 1 - 3 bytes from FIFO */
 		val = musb_readl(fifo, 0);
 		memcpy(buf, &val, len);
 	}
 }
 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
 {
 	struct musb *musb = hw_ep->musb;
 	void __iomem	*ep_conf = hw_ep->conf;
 	void __iomem	*fifo = hw_ep->fifo;
 	u8		epnum = hw_ep->epnum;
 	prefetch(buf);
 	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 			'T', epnum, fifo, len, buf);
 	if (epnum)
 		musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
 			TUSB_EP_CONFIG_XFR_SIZE(len));
 	else
 		musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
 			TUSB_EP0_CONFIG_XFR_SIZE(len));
 	if (likely((0x01 & (unsigned long) buf) == 0)) {
 		/* Best case is 32bit-aligned destination address */
 		if ((0x02 & (unsigned long) buf) == 0) {
 			if (len >= 4) {
 				writesl(fifo, buf, len >> 2);
 				buf += (len & ~0x03);
 				len &= 0x03;
 			}
 		} else {
 			if (len >= 2) {
 				u32 val;
 				int i;
 				/* Cannot use writesw, fifo is 32-bit */
 				for (i = 0; i < (len >> 2); i++) {
 					val = (u32)(*(u16 *)buf);
 					buf += 2;
 					val |= (*(u16 *)buf) << 16;
 					buf += 2;
 					musb_writel(fifo, 0, val);
 				}
 				len &= 0x03;
 			}
 		}
 	}
 	if (len > 0)
 		tusb_fifo_write_unaligned(fifo, buf, len);
 }
 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
 {
 	struct musb *musb = hw_ep->musb;
 	void __iomem	*ep_conf = hw_ep->conf;
 	void __iomem	*fifo = hw_ep->fifo;
 	u8		epnum = hw_ep->epnum;
 	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 			'R', epnum, fifo, len, buf);
 	if (epnum)
 		musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
 			TUSB_EP_CONFIG_XFR_SIZE(len));
 	else
 		musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
 	if (likely((0x01 & (unsigned long) buf) == 0)) {
 		/* Best case is 32bit-aligned destination address */
 		if ((0x02 & (unsigned long) buf) == 0) {
 			if (len >= 4) {
 				readsl(fifo, buf, len >> 2);
 				buf += (len & ~0x03);
 				len &= 0x03;
 			}
 		} else {
 			if (len >= 2) {
 				u32 val;
 				int i;
 				/* Cannot use readsw, fifo is 32-bit */
 				for (i = 0; i < (len >> 2); i++) {
 					val = musb_readl(fifo, 0);
 					*(u16 *)buf = (u16)(val & 0xffff);
 					buf += 2;
 					*(u16 *)buf = (u16)(val >> 16);
 					buf += 2;
 				}
 				len &= 0x03;
 			}
 		}
 	}
 	if (len > 0)
 		tusb_fifo_read_unaligned(fifo, buf, len);
 }
 static struct musb *the_musb;
 /* This is used by gadget drivers, and OTG transceiver logic, allowing
  * at most mA current to be drawn from VBUS during a Default-B session
  * (that is, while VBUS exceeds 4.4V).  In Default-A (including pure host
  * mode), or low power Default-B sessions, something else supplies power.
  * Caller must take care of locking.
  */
 static int tusb_draw_power(struct usb_phy *x, unsigned mA)
 {
 	struct musb	*musb = the_musb;
 	void __iomem	*tbase = musb->ctrl_base;
 	u32		reg;
 	/* tps65030 seems to consume max 100mA, with maybe 60mA available
 	 * (measured on one board) for things other than tps and tusb.
 	 *
 	 * Boards sharing the CPU clock with CLKIN will need to prevent
 	 * certain idle sleep states while the USB link is active.
 	 *
 	 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
 	 * The actual current usage would be very board-specific.  For now,
 	 * it's simpler to just use an aggregate (also board-specific).
 	 */
 	if (x->otg->default_a || mA < (musb->min_power << 1))
 		mA = 0;
 	reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
 	if (mA) {
 		musb->is_bus_powered = 1;
 		reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
 	} else {
 		musb->is_bus_powered = 0;
 		reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
 	}
 	musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
 	dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
 	return 0;
 }
 /* workaround for issue 13:  change clock during chip idle
  * (to be fixed in rev3 silicon) ... symptoms include disconnect
  * or looping suspend/resume cycles
  */
 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	u32		reg;
 	reg = musb_readl(tbase, TUSB_PRCM_CONF);
 	reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
 	/* 0 = refclk (clkin, XI)
 	 * 1 = PHY 60 MHz (internal PLL)
 	 * 2 = not supported
 	 * 3 = what?
 	 */
 	if (mode > 0)
 		reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
 	musb_writel(tbase, TUSB_PRCM_CONF, reg);
 	/* FIXME tusb6010_platform_retime(mode == 0); */
 }
 /*
  * Idle TUSB6010 until next wake-up event; NOR access always wakes.
  * Other code ensures that we idle unless we're connected _and_ the
  * USB link is not suspended ... and tells us the relevant wakeup
  * events.  SW_EN for voltage is handled separately.
  */
 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	u32		reg;
 	if ((wakeup_enables & TUSB_PRCM_WBUS)
 			&& (tusb_get_revision(musb) == TUSB_REV_30))
 		tusb_wbus_quirk(musb, 1);
 	tusb_set_clock_source(musb, 0);
 	wakeup_enables |= TUSB_PRCM_WNORCS;
 	musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
 	/* REVISIT writeup of WID implies that if WID set and ID is grounded,
 	 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
 	 * Presumably that's mostly to save power, hence WID is immaterial ...
 	 */
 	reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
 	/* issue 4: when driving vbus, use hipower (vbus_det) comparator */
 	if (is_host_active(musb)) {
 		reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 		reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
 	} else {
 		reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
 		reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 	}
 	reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
 	musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
 	dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
 }
 /*
  * Updates cable VBUS status. Caller must take care of locking.
  */
 static int tusb_musb_vbus_status(struct musb *musb)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	u32		otg_stat, prcm_mngmt;
 	int		ret = 0;
 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 	prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
 	/* Temporarily enable VBUS detection if it was disabled for
 	 * suspend mode. Unless it's enabled otg_stat and devctl will
 	 * not show correct VBUS state.
 	 */
 	if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
 		u32 tmp = prcm_mngmt;
 		tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 		musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
 		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 		musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
 	}
 	if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
 		ret = 1;
 	return ret;
 }
 static struct timer_list musb_idle_timer;
 static void musb_do_idle(unsigned long _musb)
 {
 	struct musb	*musb = (void *)_musb;
 	unsigned long	flags;
 	spin_lock_irqsave(&musb->lock, flags);
 	switch (musb->xceiv->state) {
 	case OTG_STATE_A_WAIT_BCON:
 		if ((musb->a_wait_bcon != 0)
 			&& (musb->idle_timeout == 0
 				|| time_after(jiffies, musb->idle_timeout))) {
 			dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
 					otg_state_string(musb->xceiv->state));
 		}
 		/* FALLTHROUGH */
 	case OTG_STATE_A_IDLE:
 		tusb_musb_set_vbus(musb, 0);
 	default:
 		break;
 	}
 	if (!musb->is_active) {
 		u32	wakeups;
 		/* wait until khubd handles port change status */
 		if (is_host_active(musb) && (musb->port1_status >> 16))
 			goto done;
-		if (is_peripheral_enabled(musb) && !musb->gadget_driver) {
+		if (!musb->gadget_driver) {
 			wakeups = 0;
 		} else {
 			wakeups = TUSB_PRCM_WHOSTDISCON
 				| TUSB_PRCM_WBUS
 					| TUSB_PRCM_WVBUS;
-			if (is_otg_enabled(musb))
+			wakeups |= TUSB_PRCM_WID;
-				wakeups |= TUSB_PRCM_WID;
 		}
 		tusb_allow_idle(musb, wakeups);
 	}
 done:
 	spin_unlock_irqrestore(&musb->lock, flags);
 }
 /*
  * Maybe put TUSB6010 into idle mode mode depending on USB link status,
  * like "disconnected" or "suspended".  We'll be woken out of it by
  * connect, resume, or disconnect.
  *
  * Needs to be called as the last function everywhere where there is
  * register access to TUSB6010 because of NOR flash wake-up.
  * Caller should own controller spinlock.
  *
  * Delay because peripheral enables D+ pullup 3msec after SE0, and
  * we don't want to treat that full speed J as a wakeup event.
  * ... peripherals must draw only suspend current after 10 msec.
  */
 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
 {
 	unsigned long		default_timeout = jiffies + msecs_to_jiffies(3);
 	static unsigned long	last_timer;
 	if (timeout == 0)
 		timeout = default_timeout;
 	/* Never idle if active, or when VBUS timeout is not set as host */
 	if (musb->is_active || ((musb->a_wait_bcon == 0)
 			&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
 		dev_dbg(musb->controller, "%s active, deleting timer\n",
 			otg_state_string(musb->xceiv->state));
 		del_timer(&musb_idle_timer);
 		last_timer = jiffies;
 		return;
 	}
 	if (time_after(last_timer, timeout)) {
 		if (!timer_pending(&musb_idle_timer))
 			last_timer = timeout;
 		else {
 			dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
 			return;
 		}
 	}
 	last_timer = timeout;
 	dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
 		otg_state_string(musb->xceiv->state),
 		(unsigned long)jiffies_to_msecs(timeout - jiffies));
 	mod_timer(&musb_idle_timer, timeout);
 }
 /* ticks of 60 MHz clock */
 #define DEVCLOCK		60000000
 #define OTG_TIMER_MS(msecs)	((msecs) \
 		? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
 				| TUSB_DEV_OTG_TIMER_ENABLE) \
 		: 0)
 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	u32		conf, prcm, timer;
 	u8		devctl;
 	struct usb_otg	*otg = musb->xceiv->otg;
 	/* HDRC controls CPEN, but beware current surges during device
 	 * connect.  They can trigger transient overcurrent conditions
 	 * that must be ignored.
 	 */
 	prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
 	conf = musb_readl(tbase, TUSB_DEV_CONF);
 	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 	if (is_on) {
 		timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
 		otg->default_a = 1;
 		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 		devctl |= MUSB_DEVCTL_SESSION;
 		conf |= TUSB_DEV_CONF_USB_HOST_MODE;
 		MUSB_HST_MODE(musb);
 	} else {
 		u32	otg_stat;
 		timer = 0;
 		/* If ID pin is grounded, we want to be a_idle */
 		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 		if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
 			switch (musb->xceiv->state) {
 			case OTG_STATE_A_WAIT_VRISE:
 			case OTG_STATE_A_WAIT_BCON:
 				musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 				break;
 			case OTG_STATE_A_WAIT_VFALL:
 				musb->xceiv->state = OTG_STATE_A_IDLE;
 				break;
 			default:
 				musb->xceiv->state = OTG_STATE_A_IDLE;
 			}
 			musb->is_active = 0;
 			otg->default_a = 1;
 			MUSB_HST_MODE(musb);
 		} else {
 			musb->is_active = 0;
 			otg->default_a = 0;
 			musb->xceiv->state = OTG_STATE_B_IDLE;
 			MUSB_DEV_MODE(musb);
 		}
 		devctl &= ~MUSB_DEVCTL_SESSION;
 		conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
 	}
 	prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
 	musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
 	musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
 	musb_writel(tbase, TUSB_DEV_CONF, conf);
 	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 	dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
 		otg_state_string(musb->xceiv->state),
 		musb_readb(musb->mregs, MUSB_DEVCTL),
 		musb_readl(tbase, TUSB_DEV_OTG_STAT),
 		conf, prcm);
 }
 /*
  * Sets the mode to OTG, peripheral or host by changing the ID detection.
  * Caller must take care of locking.
  *
  * Note that if a mini-A cable is plugged in the ID line will stay down as
  * the weak ID pull-up is not able to pull the ID up.
- *
- * REVISIT: It would be possible to add support for changing between host
- * and peripheral modes in non-OTG configurations by reconfiguring hardware
- * and then setting musb->board_mode. For now, only support OTG mode.
  */
 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	u32		otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
-	if (musb->board_mode != MUSB_OTG) {
-		ERR("Changing mode currently only supported in OTG mode\n");
-		return -EINVAL;
-	}
 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 	phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
 	phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
 	dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
 	switch (musb_mode) {
 	case MUSB_HOST:		/* Disable PHY ID detect, ground ID */
 		phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 		phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 		dev_conf |= TUSB_DEV_CONF_ID_SEL;
 		dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
 		break;
 	case MUSB_PERIPHERAL:	/* Disable PHY ID detect, keep ID pull-up on */
 		phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 		phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 		dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
 		break;
 	case MUSB_OTG:		/* Use PHY ID detection */
 		phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 		phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 		dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
 		break;
 	default:
 		dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
 		return -EINVAL;
 	}
 	musb_writel(tbase, TUSB_PHY_OTG_CTRL,
 			TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
 	musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
 			TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
 	musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 	if ((musb_mode == MUSB_PERIPHERAL) &&
 		!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
 			INFO("Cannot be peripheral with mini-A cable "
 			"otg_stat: %08x\n", otg_stat);
 	return 0;
 }
 static inline unsigned long
 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
 {
 	u32		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 	unsigned long	idle_timeout = 0;
 	struct usb_otg	*otg = musb->xceiv->otg;
 	/* ID pin */
 	if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
 		int	default_a;
-		if (is_otg_enabled(musb))
+		default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
-			default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
-		else
-			default_a = is_host_enabled(musb);
 		dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
 		otg->default_a = default_a;
 		tusb_musb_set_vbus(musb, default_a);
 		/* Don't allow idling immediately */
 		if (default_a)
 			idle_timeout = jiffies + (HZ * 3);
 	}
 	/* VBUS state change */
 	if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
 		/* B-dev state machine:  no vbus ~= disconnect */
-		if ((is_otg_enabled(musb) && !otg->default_a)
+		if (!otg->default_a) {
-				|| !is_host_enabled(musb)) {
 			/* ? musb_root_disconnect(musb); */
 			musb->port1_status &=
 				~(USB_PORT_STAT_CONNECTION
 				| USB_PORT_STAT_ENABLE
 				| USB_PORT_STAT_LOW_SPEED
 				| USB_PORT_STAT_HIGH_SPEED
 				| USB_PORT_STAT_TEST
 				);
 			if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
 				dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
 				if (musb->xceiv->state != OTG_STATE_B_IDLE) {
 					/* INTR_DISCONNECT can hide... */
 					musb->xceiv->state = OTG_STATE_B_IDLE;
 					musb->int_usb |= MUSB_INTR_DISCONNECT;
 				}
 				musb->is_active = 0;
 			}
 			dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
 				otg_state_string(musb->xceiv->state), otg_stat);
 			idle_timeout = jiffies + (1 * HZ);
 			schedule_work(&musb->irq_work);
 		} else /* A-dev state machine */ {
 			dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
 				otg_state_string(musb->xceiv->state), otg_stat);
 			switch (musb->xceiv->state) {
 			case OTG_STATE_A_IDLE:
 				dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
 				musb_platform_set_vbus(musb, 1);
 				/* CONNECT can wake if a_wait_bcon is set */
 				if (musb->a_wait_bcon != 0)
 					musb->is_active = 0;
 				else
 					musb->is_active = 1;
 				/*
 				 * OPT FS A TD.4.6 needs few seconds for
 				 * A_WAIT_VRISE
 				 */
 				idle_timeout = jiffies + (2 * HZ);
 				break;
 			case OTG_STATE_A_WAIT_VRISE:
 				/* ignore; A-session-valid < VBUS_VALID/2,
 				 * we monitor this with the timer
 				 */
 				break;
 			case OTG_STATE_A_WAIT_VFALL:
 				/* REVISIT this irq triggers during short
 				 * spikes caused by enumeration ...
 				 */
 				if (musb->vbuserr_retry) {
 					musb->vbuserr_retry--;
 					tusb_musb_set_vbus(musb, 1);
 				} else {
 					musb->vbuserr_retry
 						= VBUSERR_RETRY_COUNT;
 					tusb_musb_set_vbus(musb, 0);
 				}
 				break;
 			default:
 				break;
 			}
 		}
 	}
 	/* OTG timer expiration */
 	if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
 		u8	devctl;
 		dev_dbg(musb->controller, "%s timer, %03x\n",
 			otg_state_string(musb->xceiv->state), otg_stat);
 		switch (musb->xceiv->state) {
 		case OTG_STATE_A_WAIT_VRISE:
 			/* VBUS has probably been valid for a while now,
 			 * but may well have bounced out of range a bit
 			 */
 			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 			if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
 				if ((devctl & MUSB_DEVCTL_VBUS)
 						!= MUSB_DEVCTL_VBUS) {
 					dev_dbg(musb->controller, "devctl %02x\n", devctl);
 					break;
 				}
 				musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 				musb->is_active = 0;
 				idle_timeout = jiffies
 					+ msecs_to_jiffies(musb->a_wait_bcon);
 			} else {
 				/* REVISIT report overcurrent to hub? */
 				ERR("vbus too slow, devctl %02x\n", devctl);
 				tusb_musb_set_vbus(musb, 0);
 			}
 			break;
 		case OTG_STATE_A_WAIT_BCON:
 			if (musb->a_wait_bcon != 0)
 				idle_timeout = jiffies
 					+ msecs_to_jiffies(musb->a_wait_bcon);
 			break;
 		case OTG_STATE_A_SUSPEND:
 			break;
 		case OTG_STATE_B_WAIT_ACON:
 			break;
 		default:
 			break;
 		}
 	}
 	schedule_work(&musb->irq_work);
 	return idle_timeout;
 }
 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
 {
 	struct musb	*musb = __hci;
 	void __iomem	*tbase = musb->ctrl_base;
 	unsigned long	flags, idle_timeout = 0;
 	u32		int_mask, int_src;
 	spin_lock_irqsave(&musb->lock, flags);
 	/* Mask all interrupts to allow using both edge and level GPIO irq */
 	int_mask = musb_readl(tbase, TUSB_INT_MASK);
 	musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
 	int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
 	dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
 	musb->int_usb = (u8) int_src;
 	/* Acknowledge wake-up source interrupts */
 	if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
 		u32	reg;
 		u32	i;
 		if (tusb_get_revision(musb) == TUSB_REV_30)
 			tusb_wbus_quirk(musb, 0);
 		/* there are issues re-locking the PLL on wakeup ... */
 		/* work around issue 8 */
 		for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
 			musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
 			musb_writel(tbase, TUSB_SCRATCH_PAD, i);
 			reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
 			if (reg == i)
 				break;
 			dev_dbg(musb->controller, "TUSB NOR not ready\n");
 		}
 		/* work around issue 13 (2nd half) */
 		tusb_set_clock_source(musb, 1);
 		reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
 		musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
 		if (reg & ~TUSB_PRCM_WNORCS) {
 			musb->is_active = 1;
 			schedule_work(&musb->irq_work);
 		}
 		dev_dbg(musb->controller, "wake %sactive %02x\n",
 				musb->is_active ? "" : "in", reg);
 		/* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
 	}
 	if (int_src & TUSB_INT_SRC_USB_IP_CONN)
 		del_timer(&musb_idle_timer);
 	/* OTG state change reports (annoyingly) not issued by Mentor core */
 	if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
 				| TUSB_INT_SRC_OTG_TIMEOUT
 				| TUSB_INT_SRC_ID_STATUS_CHNG))
 		idle_timeout = tusb_otg_ints(musb, int_src, tbase);
 	/* TX dma callback must be handled here, RX dma callback is
 	 * handled in tusb_omap_dma_cb.
 	 */
 	if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
 		u32	dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
 		u32	real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
 		dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
 		real_dma_src = ~real_dma_src & dma_src;
 		if (tusb_dma_omap() && real_dma_src) {
 			int	tx_source = (real_dma_src & 0xffff);
 			int	i;
 			for (i = 1; i <= 15; i++) {
 				if (tx_source & (1 << i)) {
 					dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
 					musb_dma_completion(musb, i, 1);
 				}
 			}
 		}
 		musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
 	}
 	/* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
 	if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
 		u32	musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
 		musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
 		musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
 		musb->int_tx = (musb_src & 0xffff);
 	} else {
 		musb->int_rx = 0;
 		musb->int_tx = 0;
 	}
 	if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
 		musb_interrupt(musb);
 	/* Acknowledge TUSB interrupts. Clear only non-reserved bits */
 	musb_writel(tbase, TUSB_INT_SRC_CLEAR,
 		int_src & ~TUSB_INT_MASK_RESERVED_BITS);
 	tusb_musb_try_idle(musb, idle_timeout);
 	musb_writel(tbase, TUSB_INT_MASK, int_mask);
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return IRQ_HANDLED;
 }
 static int dma_off;
 /*
  * Enables TUSB6010. Caller must take care of locking.
  * REVISIT:
  * - Check what is unnecessary in MGC_HdrcStart()
  */
 static void tusb_musb_enable(struct musb *musb)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	/* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
 	 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
 	musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
 	/* Setup TUSB interrupt, disable DMA and GPIO interrupts */
 	musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
 	musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
 	musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
 	/* Clear all subsystem interrups */
 	musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
 	musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
 	musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
 	/* Acknowledge pending interrupt(s) */
 	musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
 	/* Only 0 clock cycles for minimum interrupt de-assertion time and
 	 * interrupt polarity active low seems to work reliably here */
 	musb_writel(tbase, TUSB_INT_CTRL_CONF,
 			TUSB_INT_CTRL_CONF_INT_RELCYC(0));
 	irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
 	/* maybe force into the Default-A OTG state machine */
 	if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
 			& TUSB_DEV_OTG_STAT_ID_STATUS))
 		musb_writel(tbase, TUSB_INT_SRC_SET,
 				TUSB_INT_SRC_ID_STATUS_CHNG);
 	if (is_dma_capable() && dma_off)
 		printk(KERN_WARNING "%s %s: dma not reactivated\n",
 				__FILE__, __func__);
 	else
 		dma_off = 1;
 }
 /*
  * Disables TUSB6010. Caller must take care of locking.
  */
 static void tusb_musb_disable(struct musb *musb)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	/* FIXME stop DMA, IRQs, timers, ... */
 	/* disable all IRQs */
 	musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
 	musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
 	musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
 	musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
 	del_timer(&musb_idle_timer);
 	if (is_dma_capable() && !dma_off) {
 		printk(KERN_WARNING "%s %s: dma still active\n",
 				__FILE__, __func__);
 		dma_off = 1;
 	}
 }
 /*
  * Sets up TUSB6010 CPU interface specific signals and registers
  * Note: Settings optimized for OMAP24xx
  */
 static void tusb_setup_cpu_interface(struct musb *musb)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	/*
 	 * Disable GPIO[5:0] pullups (used as output DMA requests)
 	 * Don't disable GPIO[7:6] as they are needed for wake-up.
 	 */
 	musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
 	/* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
 	musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
 	/* Turn GPIO[5:0] to DMAREQ[5:0] signals */
 	musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
 	/* Burst size 16x16 bits, all six DMA requests enabled, DMA request
 	 * de-assertion time 2 system clocks p 62 */
 	musb_writel(tbase, TUSB_DMA_REQ_CONF,
 		TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
 		TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
 		TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
 	/* Set 0 wait count for synchronous burst access */
 	musb_writel(tbase, TUSB_WAIT_COUNT, 1);
 }
 static int tusb_musb_start(struct musb *musb)
 {
 	void __iomem	*tbase = musb->ctrl_base;
 	int		ret = 0;
 	unsigned long	flags;
 	u32		reg;
 	if (musb->board_set_power)
 		ret = musb->board_set_power(1);
 	if (ret != 0) {
 		printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
 		return ret;
 	}
 	spin_lock_irqsave(&musb->lock, flags);
 	if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
 		TUSB_PROD_TEST_RESET_VAL) {
 		printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
 		goto err;
 	}
 	ret = tusb_print_revision(musb);
 	if (ret < 2) {
 		printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
 				ret);
 		goto err;
 	}
 	/* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
 	 * NOR FLASH interface is used */
 	musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
 	/* Select PHY free running 60MHz as a system clock */
 	tusb_set_clock_source(musb, 1);
 	/* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
 	 * power saving, enable VBus detect and session end comparators,
 	 * enable IDpullup, enable VBus charging */
 	musb_writel(tbase, TUSB_PRCM_MNGMT,
 		TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
 		TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
 		TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
 		TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
 		TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
 	tusb_setup_cpu_interface(musb);
 	/* simplify:  always sense/pullup ID pins, as if in OTG mode */
 	reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
 	reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 	musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
 	reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
 	reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 	musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
 	spin_unlock_irqrestore(&musb->lock, flags);
 	return 0;
 err:
 	spin_unlock_irqrestore(&musb->lock, flags);
 	if (musb->board_set_power)
 		musb->board_set_power(0);
 	return -ENODEV;
 }
 static int tusb_musb_init(struct musb *musb)
 {
 	struct platform_device	*pdev;
 	struct resource		*mem;
 	void __iomem		*sync = NULL;
 	int			ret;
 	usb_nop_xceiv_register();
 	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
 	if (IS_ERR_OR_NULL(musb->xceiv))
 		return -ENODEV;
 	pdev = to_platform_device(musb->controller);
 	/* dma address for async dma */
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	musb->async = mem->start;
 	/* dma address for sync dma */
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	if (!mem) {
 		pr_debug("no sync dma resource?\n");
 		ret = -ENODEV;
 		goto done;
 	}
 	musb->sync = mem->start;
 	sync = ioremap(mem->start, resource_size(mem));
 	if (!sync) {
 		pr_debug("ioremap for sync failed\n");
 		ret = -ENOMEM;
 		goto done;
 	}
 	musb->sync_va = sync;
 	/* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
 	 * FIFOs at 0x600, TUSB at 0x800
 	 */
 	musb->mregs += TUSB_BASE_OFFSET;
 	ret = tusb_musb_start(musb);
 	if (ret) {
 		printk(KERN_ERR "Could not start tusb6010 (%d)\n",
 				ret);
 		goto done;
 	}
 	musb->isr = tusb_musb_interrupt;
-	if (is_peripheral_enabled(musb)) {
+	musb->xceiv->set_power = tusb_draw_power;
-		musb->xceiv->set_power = tusb_draw_power;
+	the_musb = musb;
-		the_musb = musb;
-	}
 	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
 done:
 	if (ret < 0) {
 		if (sync)
 			iounmap(sync);
 		usb_put_phy(musb->xceiv);
 		usb_nop_xceiv_unregister();
 	}
 	return ret;
 }
 static int tusb_musb_exit(struct musb *musb)
 {
 	del_timer_sync(&musb_idle_timer);
 	the_musb = NULL;
 	if (musb->board_set_power)
 		musb->board_set_power(0);
 	iounmap(musb->sync_va);
 	usb_put_phy(musb->xceiv);
 	usb_nop_xceiv_unregister();
 	return 0;
 }
 static const struct musb_platform_ops tusb_ops = {
 	.init		= tusb_musb_init,
 	.exit		= tusb_musb_exit,
 	.enable		= tusb_musb_enable,
 	.disable	= tusb_musb_disable,
 	.set_mode	= tusb_musb_set_mode,
 	.try_idle	= tusb_musb_try_idle,
 	.vbus_status	= tusb_musb_vbus_status,
 	.set_vbus	= tusb_musb_set_vbus,
 };
 static u64 tusb_dmamask = DMA_BIT_MASK(32);
 static int __devinit tusb_probe(struct platform_device *pdev)
 {
 	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
 	struct platform_device		*musb;
 	struct tusb6010_glue		*glue;
 	int				ret = -ENOMEM;
 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 	if (!glue) {
 		dev_err(&pdev->dev, "failed to allocate glue context\n");
 		goto err0;
 	}
 	musb = platform_device_alloc("musb-hdrc", -1);
 	if (!musb) {
 		dev_err(&pdev->dev, "failed to allocate musb device\n");
 		goto err1;
 	}
 	musb->dev.parent		= &pdev->dev;
 	musb->dev.dma_mask		= &tusb_dmamask;
 	musb->dev.coherent_dma_mask	= tusb_dmamask;
 	glue->dev			= &pdev->dev;
 	glue->musb			= musb;
 	pdata->platform_ops		= &tusb_ops;
 	platform_set_drvdata(pdev, glue);
 	ret = platform_device_add_resources(musb, pdev->resource,
 			pdev->num_resources);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add resources\n");
 		goto err2;
 	}
 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add platform_data\n");
 		goto err2;
 	}
 	ret = platform_device_add(musb);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register musb device\n");
 		goto err1;
 	}
 	return 0;
 err2:
 	platform_device_put(musb);
 err1:
 	kfree(glue);
 err0:
 	return ret;
 }
 static int __devexit tusb_remove(struct platform_device *pdev)
 {
 	struct tusb6010_glue		*glue = platform_get_drvdata(pdev);
 	platform_device_del(glue->musb);
 	platform_device_put(glue->musb);
 	kfree(glue);
 	return 0;
 }
 static struct platform_driver tusb_driver = {
 	.probe		= tusb_probe,
 	.remove		= __devexit_p(tusb_remove),
 	.driver		= {
 		.name	= "musb-tusb",
 	},
 };
 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 MODULE_LICENSE("GPL v2");
 static int __init tusb_init(void)
 {
 	return platform_driver_register(&tusb_driver);
 }
 module_init(tusb_init);
 static void __exit tusb_exit(void)
 {
 	platform_driver_unregister(&tusb_driver);
 }
 module_exit(tusb_exit);