hwmon: (w83627ehf) Move fan pins check to a separate function

Move the check of fan pin usage to a separate function. This improves readability, and will make it easier to integrate chip-specific conditions. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>

hwmon: (w83627ehf) Move fan pins check to a separate function
Move the check of fan pin usage to a separate function. This improves readability, and will make it easier to integrate chip-specific conditions. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
Jean Delvare · Guenter Roeck
1 parent 389ef65d2e
Showing 1 changed file with 67 additions and 53 deletions Side-by-side Diff
drivers/hwmon/w83627ehf.c
@@ -1844,13 +1844,78 @@
 	data->reg_temp_config[r2] = tmp;
 }
  
+static void __devinit
+w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
+			   struct w83627ehf_data *data)
+{
+	int fan3pin, fan4pin, fan4min, fan5pin, regval;
+
+	superio_enter(sio_data->sioreg);
+
+	/* fan4 and fan5 share some pins with the GPIO and serial flash */
+	if (sio_data->kind == nct6775) {
+		/* On NCT6775, fan4 shares pins with the fdc interface */
+		fan3pin = 1;
+		fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
+		fan4min = 0;
+		fan5pin = 0;
+	} else if (sio_data->kind == nct6776) {
+		fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
+		fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
+		fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
+		fan4min = fan4pin;
+	} else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
+		fan3pin = 1;
+		fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
+		fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
+		fan4min = fan4pin;
+	} else {
+		fan3pin = 1;
+		fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
+		fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
+		fan4min = fan4pin;
+	}
+
+	superio_exit(sio_data->sioreg);
+
+	data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
+	data->has_fan |= (fan3pin << 2);
+	data->has_fan_min |= (fan3pin << 2);
+
+	if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
+		/*
+		 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
+		 * register
+		 */
+		data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
+		data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
+	} else {
+		/*
+		 * It looks like fan4 and fan5 pins can be alternatively used
+		 * as fan on/off switches, but fan5 control is write only :/
+		 * We assume that if the serial interface is disabled, designers
+		 * connected fan5 as input unless they are emitting log 1, which
+		 * is not the default.
+		 */
+		regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
+		if ((regval & (1 << 2)) && fan4pin) {
+			data->has_fan |= (1 << 3);
+			data->has_fan_min |= (1 << 3);
+		}
+		if (!(regval & (1 << 1)) && fan5pin) {
+			data->has_fan |= (1 << 4);
+			data->has_fan_min |= (1 << 4);
+		}
+	}
+}
+
 static int __devinit w83627ehf_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct w83627ehf_sio_data *sio_data = dev->platform_data;
 	struct w83627ehf_data *data;
 	struct resource *res;
-	u8 fan3pin, fan4pin, fan4min, fan5pin, en_vrm10;
+	u8 en_vrm10;
 	int i, err = 0;
  
 	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
@@ -2135,30 +2200,6 @@
 		}
 	}
  
-	/* fan4 and fan5 share some pins with the GPIO and serial flash */
-	if (sio_data->kind == nct6775) {
-		/* On NCT6775, fan4 shares pins with the fdc interface */
-		fan3pin = 1;
-		fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
-		fan4min = 0;
-		fan5pin = 0;
-	} else if (sio_data->kind == nct6776) {
-		fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
-		fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
-		fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
-		fan4min = fan4pin;
-	} else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
-		fan3pin = 1;
-		fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
-		fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
-		fan4min = fan4pin;
-	} else {
-		fan3pin = 1;
-		fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
-		fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
-		fan4min = fan4pin;
-	}
-
 	if (fan_debounce &&
 	    (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
 		u8 tmp;
@@ -2176,34 +2217,7 @@
  
 	superio_exit(sio_data->sioreg);
  
-	/* It looks like fan4 and fan5 pins can be alternatively used
-	   as fan on/off switches, but fan5 control is write only :/
-	   We assume that if the serial interface is disabled, designers
-	   connected fan5 as input unless they are emitting log 1, which
-	   is not the default. */
-
-	data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
-
-	data->has_fan |= (fan3pin << 2);
-	data->has_fan_min |= (fan3pin << 2);
-
-	/*
-	 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1 register
-	 */
-	if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
-		data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
-		data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
-	} else {
-		i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
-		if ((i & (1 << 2)) && fan4pin) {
-			data->has_fan |= (1 << 3);
-			data->has_fan_min |= (1 << 3);
-		}
-		if (!(i & (1 << 1)) && fan5pin) {
-			data->has_fan |= (1 << 4);
-			data->has_fan_min |= (1 << 4);
-		}
-	}
+	w83627ehf_check_fan_inputs(sio_data, data);
  
 	/* Read fan clock dividers immediately */
 	w83627ehf_update_fan_div_common(dev, data);
...	...	@@ -1844,13 +1844,78 @@
1844	1844	data->reg_temp_config[r2] = tmp;
1845	1845	}
1846	1846
	1847	+static void __devinit
	1848	+w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
	1849	+ struct w83627ehf_data *data)
	1850	+{
	1851	+ int fan3pin, fan4pin, fan4min, fan5pin, regval;
	1852	+
	1853	+ superio_enter(sio_data->sioreg);
	1854	+
	1855	+ /* fan4 and fan5 share some pins with the GPIO and serial flash */
	1856	+ if (sio_data->kind == nct6775) {
	1857	+ /* On NCT6775, fan4 shares pins with the fdc interface */
	1858	+ fan3pin = 1;
	1859	+ fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
	1860	+ fan4min = 0;
	1861	+ fan5pin = 0;
	1862	+ } else if (sio_data->kind == nct6776) {
	1863	+ fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
	1864	+ fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
	1865	+ fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
	1866	+ fan4min = fan4pin;
	1867	+ } else if (sio_data->kind == w83667hg \|\| sio_data->kind == w83667hg_b) {
	1868	+ fan3pin = 1;
	1869	+ fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
	1870	+ fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
	1871	+ fan4min = fan4pin;
	1872	+ } else {
	1873	+ fan3pin = 1;
	1874	+ fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
	1875	+ fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
	1876	+ fan4min = fan4pin;
	1877	+ }
	1878	+
	1879	+ superio_exit(sio_data->sioreg);
	1880	+
	1881	+ data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
	1882	+ data->has_fan \|= (fan3pin << 2);
	1883	+ data->has_fan_min \|= (fan3pin << 2);
	1884	+
	1885	+ if (sio_data->kind == nct6775 \|\| sio_data->kind == nct6776) {
	1886	+ /*
	1887	+ * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
	1888	+ * register
	1889	+ */
	1890	+ data->has_fan \|= (fan4pin << 3) \| (fan5pin << 4);
	1891	+ data->has_fan_min \|= (fan4min << 3) \| (fan5pin << 4);
	1892	+ } else {
	1893	+ /*
	1894	+ * It looks like fan4 and fan5 pins can be alternatively used
	1895	+ * as fan on/off switches, but fan5 control is write only :/
	1896	+ * We assume that if the serial interface is disabled, designers
	1897	+ * connected fan5 as input unless they are emitting log 1, which
	1898	+ * is not the default.
	1899	+ */
	1900	+ regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
	1901	+ if ((regval & (1 << 2)) && fan4pin) {
	1902	+ data->has_fan \|= (1 << 3);
	1903	+ data->has_fan_min \|= (1 << 3);
	1904	+ }
	1905	+ if (!(regval & (1 << 1)) && fan5pin) {
	1906	+ data->has_fan \|= (1 << 4);
	1907	+ data->has_fan_min \|= (1 << 4);
	1908	+ }
	1909	+ }
	1910	+}
	1911	+
1847	1912	static int __devinit w83627ehf_probe(struct platform_device *pdev)
1848	1913	{
1849	1914	struct device *dev = &pdev->dev;
1850	1915	struct w83627ehf_sio_data *sio_data = dev->platform_data;
1851	1916	struct w83627ehf_data *data;
1852	1917	struct resource *res;
1853		- u8 fan3pin, fan4pin, fan4min, fan5pin, en_vrm10;
	1918	+ u8 en_vrm10;
1854	1919	int i, err = 0;
1855	1920
1856	1921	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
...	...	@@ -2135,30 +2200,6 @@
2135	2200	}
2136	2201	}
2137	2202
2138		- /* fan4 and fan5 share some pins with the GPIO and serial flash */
2139		- if (sio_data->kind == nct6775) {
2140		- /* On NCT6775, fan4 shares pins with the fdc interface */
2141		- fan3pin = 1;
2142		- fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
2143		- fan4min = 0;
2144		- fan5pin = 0;
2145		- } else if (sio_data->kind == nct6776) {
2146		- fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
2147		- fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
2148		- fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
2149		- fan4min = fan4pin;
2150		- } else if (sio_data->kind == w83667hg \|\| sio_data->kind == w83667hg_b) {
2151		- fan3pin = 1;
2152		- fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
2153		- fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
2154		- fan4min = fan4pin;
2155		- } else {
2156		- fan3pin = 1;
2157		- fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
2158		- fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2159		- fan4min = fan4pin;
2160		- }
2161		-
2162	2203	if (fan_debounce &&
2163	2204	(sio_data->kind == nct6775 \|\| sio_data->kind == nct6776)) {
2164	2205	u8 tmp;
...	...	@@ -2176,34 +2217,7 @@
2176	2217
2177	2218	superio_exit(sio_data->sioreg);
2178	2219
2179		- /* It looks like fan4 and fan5 pins can be alternatively used
2180		- as fan on/off switches, but fan5 control is write only :/
2181		- We assume that if the serial interface is disabled, designers
2182		- connected fan5 as input unless they are emitting log 1, which
2183		- is not the default. */
2184		-
2185		- data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2186		-
2187		- data->has_fan \|= (fan3pin << 2);
2188		- data->has_fan_min \|= (fan3pin << 2);
2189		-
2190		- /*
2191		- * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1 register
2192		- */
2193		- if (sio_data->kind == nct6775 \|\| sio_data->kind == nct6776) {
2194		- data->has_fan \|= (fan4pin << 3) \| (fan5pin << 4);
2195		- data->has_fan_min \|= (fan4min << 3) \| (fan5pin << 4);
2196		- } else {
2197		- i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2198		- if ((i & (1 << 2)) && fan4pin) {
2199		- data->has_fan \|= (1 << 3);
2200		- data->has_fan_min \|= (1 << 3);
2201		- }
2202		- if (!(i & (1 << 1)) && fan5pin) {
2203		- data->has_fan \|= (1 << 4);
2204		- data->has_fan_min \|= (1 << 4);
2205		- }
2206		- }
	2220	+ w83627ehf_check_fan_inputs(sio_data, data);
2207	2221
2208	2222	/* Read fan clock dividers immediately */
2209	2223	w83627ehf_update_fan_div_common(dev, data);