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Commit 06cfa556949ead5d3c00dc68108c443be8dd8d17

Authored by Ben Dooks
Committed by Russell King
1 parent dd1313a167
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] 4524/1: S3C: Move register out of include/asm-arm/arch-s3c2410 

Move register and other definitions out of the
include/asm-arm/arch-s3c2410 into the the arch
directories of include/asm-arm/plat-s3c24xx and
include/asm-arm/plat-s3c.

This move is in preperation of the merging of
s3c2400 and s3c6400.

The following git mv commands are needed before
this patch can be applied:

git mv include/asm-arm/arch-s3c2410/regs-ac97.h include/asm-arm/plat-s3c/regs-ac97.h
git mv include/asm-arm/arch-s3c2410/regs-adc.h include/asm-arm/plat-s3c/regs-adc.h
git mv include/asm-arm/arch-s3c2410/regs-iis.h include/asm-arm/plat-s3c24xx/regs-iis.h
git mv include/asm-arm/arch-s3c2410/regs-spi.h include/asm-arm/plat-s3c24xx/regs-spi.h
git mv include/asm-arm/arch-s3c2410/regs-udc.h include/asm-arm/plat-s3c24xx/regs-udc.h
git mv include/asm-arm/arch-s3c2410/udc.h include/asm-arm/plat-s3c24xx/udc.h

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 21 changed files with 465 additions and 465 deletions Side-by-side Diff

arch/arm/mach-s3c2410/dma.c
Diff comments   View file @ 06cfa55
... ... @@ -25,12 +25,12 @@
25 25  
26 26 #include <asm/plat-s3c/regs-serial.h>
27 27 #include <asm/arch/regs-gpio.h>
28   -#include <asm/arch/regs-ac97.h>
  28 +#include <asm/plat-s3c/regs-ac97.h>
29 29 #include <asm/arch/regs-mem.h>
30 30 #include <asm/arch/regs-lcd.h>
31 31 #include <asm/arch/regs-sdi.h>
32   -#include <asm/arch/regs-iis.h>
33   -#include <asm/arch/regs-spi.h>
  32 +#include <asm/plat-s3c24xx/regs-iis.h>
  33 +#include <asm/plat-s3c24xx/regs-spi.h>
34 34  
35 35 static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
36 36 [DMACH_XD0] = {
arch/arm/mach-s3c2410/mach-h1940.c
Diff comments   View file @ 06cfa55
... ... @@ -38,7 +38,7 @@
38 38 #include <asm/arch/h1940.h>
39 39 #include <asm/arch/h1940-latch.h>
40 40 #include <asm/arch/fb.h>
41   -#include <asm/arch/udc.h>
  41 +#include <asm/plat-s3c24xx/udc.h>
42 42  
43 43 #include <asm/plat-s3c24xx/clock.h>
44 44 #include <asm/plat-s3c24xx/devs.h>
arch/arm/mach-s3c2410/mach-qt2410.c
Diff comments   View file @ 06cfa55
... ... @@ -52,7 +52,7 @@
52 52 #include <asm/plat-s3c/regs-serial.h>
53 53 #include <asm/arch/fb.h>
54 54 #include <asm/plat-s3c/nand.h>
55   -#include <asm/arch/udc.h>
  55 +#include <asm/plat-s3c24xx/udc.h>
56 56 #include <asm/arch/spi.h>
57 57 #include <asm/arch/spi-gpio.h>
58 58  
arch/arm/mach-s3c2412/dma.c
Diff comments   View file @ 06cfa55
... ... @@ -26,12 +26,12 @@
26 26  
27 27 #include <asm/plat-s3c/regs-serial.h>
28 28 #include <asm/arch/regs-gpio.h>
29   -#include <asm/arch/regs-ac97.h>
  29 +#include <asm/plat-s3c/regs-ac97.h>
30 30 #include <asm/arch/regs-mem.h>
31 31 #include <asm/arch/regs-lcd.h>
32 32 #include <asm/arch/regs-sdi.h>
33   -#include <asm/arch/regs-iis.h>
34   -#include <asm/arch/regs-spi.h>
  33 +#include <asm/plat-s3c24xx/regs-iis.h>
  34 +#include <asm/plat-s3c24xx/regs-spi.h>
35 35  
36 36 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
37 37  
arch/arm/mach-s3c2412/mach-smdk2413.c
Diff comments   View file @ 06cfa55
... ... @@ -37,7 +37,7 @@
37 37 #include <asm/arch/regs-lcd.h>
38 38  
39 39 #include <asm/arch/idle.h>
40   -#include <asm/arch/udc.h>
  40 +#include <asm/plat-s3c24xx/udc.h>
41 41 #include <asm/arch/fb.h>
42 42  
43 43 #include <asm/plat-s3c24xx/s3c2410.h>
arch/arm/mach-s3c2412/s3c2412.c
Diff comments   View file @ 06cfa55
... ... @@ -39,7 +39,7 @@
39 39 #include <asm/arch/regs-gpio.h>
40 40 #include <asm/arch/regs-gpioj.h>
41 41 #include <asm/arch/regs-dsc.h>
42   -#include <asm/arch/regs-spi.h>
  42 +#include <asm/plat-s3c24xx/regs-spi.h>
43 43 #include <asm/arch/regs-s3c2412.h>
44 44  
45 45 #include <asm/plat-s3c24xx/s3c2412.h>
arch/arm/mach-s3c2440/dma.c
Diff comments   View file @ 06cfa55
... ... @@ -25,12 +25,12 @@
25 25  
26 26 #include <asm/plat-s3c/regs-serial.h>
27 27 #include <asm/arch/regs-gpio.h>
28   -#include <asm/arch/regs-ac97.h>
  28 +#include <asm/plat-s3c/regs-ac97.h>
29 29 #include <asm/arch/regs-mem.h>
30 30 #include <asm/arch/regs-lcd.h>
31 31 #include <asm/arch/regs-sdi.h>
32   -#include <asm/arch/regs-iis.h>
33   -#include <asm/arch/regs-spi.h>
  32 +#include <asm/plat-s3c24xx/regs-iis.h>
  33 +#include <asm/plat-s3c24xx/regs-spi.h>
34 34  
35 35 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
36 36 [DMACH_XD0] = {
arch/arm/mach-s3c2443/dma.c
Diff comments   View file @ 06cfa55
... ... @@ -26,12 +26,12 @@
26 26  
27 27 #include <asm/plat-s3c/regs-serial.h>
28 28 #include <asm/arch/regs-gpio.h>
29   -#include <asm/arch/regs-ac97.h>
  29 +#include <asm/plat-s3c/regs-ac97.h>
30 30 #include <asm/arch/regs-mem.h>
31 31 #include <asm/arch/regs-lcd.h>
32 32 #include <asm/arch/regs-sdi.h>
33   -#include <asm/arch/regs-iis.h>
34   -#include <asm/arch/regs-spi.h>
  33 +#include <asm/plat-s3c24xx/regs-iis.h>
  34 +#include <asm/plat-s3c24xx/regs-spi.h>
35 35  
36 36 #define MAP(x) { \
37 37 [0] = (x) | DMA_CH_VALID, \
arch/arm/plat-s3c24xx/devs.c
Diff comments   View file @ 06cfa55
... ... @@ -29,11 +29,11 @@
29 29 #include <asm/irq.h>
30 30  
31 31 #include <asm/plat-s3c/regs-serial.h>
32   -#include <asm/arch/udc.h>
  32 +#include <asm/plat-s3c24xx/udc.h>
33 33  
34 34 #include <asm/plat-s3c24xx/devs.h>
35 35 #include <asm/plat-s3c24xx/cpu.h>
36   -#include <asm/arch/regs-spi.h>
  36 +#include <asm/plat-s3c24xx/regs-spi.h>
37 37  
38 38 /* Serial port registrations */
39 39  
include/asm-arm/arch-s3c2410/regs-ac97.h
View file @ 06cfa55
1   -/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h
2   - *
3   - * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
4   - * http://www.simtec.co.uk/products/SWLINUX/
5   - *
6   - * This program is free software; you can redistribute it and/or modify
7   - * it under the terms of the GNU General Public License version 2 as
8   - * published by the Free Software Foundation.
9   - *
10   - * S3C2440 AC97 Controller
11   -*/
12   -
13   -#ifndef __ASM_ARCH_REGS_AC97_H
14   -#define __ASM_ARCH_REGS_AC97_H __FILE__
15   -
16   -#define S3C_AC97_GLBCTRL (0x00)
17   -
18   -#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
19   -#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
20   -#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
21   -#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
22   -#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
23   -#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
24   -#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
25   -#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
26   -#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
27   -#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
28   -#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
29   -#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
30   -#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
31   -#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
32   -#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
33   -#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
34   -#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
35   -#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
36   -#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
37   -#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
38   -#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
39   -#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
40   -#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
41   -
42   -#define S3C_AC97_GLBSTAT (0x04)
43   -
44   -#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
45   -#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
46   -#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
47   -#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
48   -#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
49   -#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
50   -#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
51   -#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
52   -#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
53   -#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
54   -#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
55   -#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
56   -#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
57   -
58   -#define S3C_AC97_CODEC_CMD (0x08)
59   -
60   -#define S3C_AC97_CODEC_CMD_READ (1<<23)
61   -
62   -#define S3C_AC97_STAT (0x0c)
63   -#define S3C_AC97_PCM_ADDR (0x10)
64   -#define S3C_AC97_PCM_DATA (0x18)
65   -#define S3C_AC97_MIC_DATA (0x1C)
66   -
67   -#endif /* __ASM_ARCH_REGS_AC97_H */
include/asm-arm/arch-s3c2410/regs-adc.h
View file @ 06cfa55
1   -/* linux/include/asm-arm/arch-s3c2410/regs-adc.h
2   - *
3   - * Copyright (c) 2004 Shannon Holland <holland@loser.net>
4   - *
5   - * This program is free software; yosu can redistribute it and/or modify
6   - * it under the terms of the GNU General Public License version 2 as
7   - * published by the Free Software Foundation.
8   - *
9   - * S3C2410 ADC registers
10   -*/
11   -
12   -#ifndef __ASM_ARCH_REGS_ADC_H
13   -#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
14   -
15   -#define S3C2410_ADCREG(x) (x)
16   -
17   -#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
18   -#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
19   -#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
20   -#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
21   -#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
22   -
23   -
24   -/* ADCCON Register Bits */
25   -#define S3C2410_ADCCON_ECFLG (1<<15)
26   -#define S3C2410_ADCCON_PRSCEN (1<<14)
27   -#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
28   -#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
29   -#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
30   -#define S3C2410_ADCCON_MUXMASK (0x7<<3)
31   -#define S3C2410_ADCCON_STDBM (1<<2)
32   -#define S3C2410_ADCCON_READ_START (1<<1)
33   -#define S3C2410_ADCCON_ENABLE_START (1<<0)
34   -#define S3C2410_ADCCON_STARTMASK (0x3<<0)
35   -
36   -
37   -/* ADCTSC Register Bits */
38   -#define S3C2410_ADCTSC_YM_SEN (1<<7)
39   -#define S3C2410_ADCTSC_YP_SEN (1<<6)
40   -#define S3C2410_ADCTSC_XM_SEN (1<<5)
41   -#define S3C2410_ADCTSC_XP_SEN (1<<4)
42   -#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
43   -#define S3C2410_ADCTSC_AUTO_PST (1<<2)
44   -#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
45   -
46   -/* ADCDAT0 Bits */
47   -#define S3C2410_ADCDAT0_UPDOWN (1<<15)
48   -#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
49   -#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
50   -#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
51   -
52   -/* ADCDAT1 Bits */
53   -#define S3C2410_ADCDAT1_UPDOWN (1<<15)
54   -#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
55   -#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
56   -#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
57   -
58   -#endif /* __ASM_ARCH_REGS_ADC_H */
include/asm-arm/arch-s3c2410/regs-iis.h
View file @ 06cfa55
1   -/* linux/include/asm-arm/arch-s3c2410/regs-iis.h
2   - *
3   - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4   - * http://www.simtec.co.uk/products/SWLINUX/
5   - *
6   - * This program is free software; you can redistribute it and/or modify
7   - * it under the terms of the GNU General Public License version 2 as
8   - * published by the Free Software Foundation.
9   - *
10   - * S3C2410 IIS register definition
11   -*/
12   -
13   -#ifndef __ASM_ARCH_REGS_IIS_H
14   -#define __ASM_ARCH_REGS_IIS_H
15   -
16   -#define S3C2410_IISCON (0x00)
17   -
18   -#define S3C2410_IISCON_LRINDEX (1<<8)
19   -#define S3C2410_IISCON_TXFIFORDY (1<<7)
20   -#define S3C2410_IISCON_RXFIFORDY (1<<6)
21   -#define S3C2410_IISCON_TXDMAEN (1<<5)
22   -#define S3C2410_IISCON_RXDMAEN (1<<4)
23   -#define S3C2410_IISCON_TXIDLE (1<<3)
24   -#define S3C2410_IISCON_RXIDLE (1<<2)
25   -#define S3C2410_IISCON_PSCEN (1<<1)
26   -#define S3C2410_IISCON_IISEN (1<<0)
27   -
28   -#define S3C2410_IISMOD (0x04)
29   -
30   -#define S3C2440_IISMOD_MPLL (1<<9)
31   -#define S3C2410_IISMOD_SLAVE (1<<8)
32   -#define S3C2410_IISMOD_NOXFER (0<<6)
33   -#define S3C2410_IISMOD_RXMODE (1<<6)
34   -#define S3C2410_IISMOD_TXMODE (2<<6)
35   -#define S3C2410_IISMOD_TXRXMODE (3<<6)
36   -#define S3C2410_IISMOD_LR_LLOW (0<<5)
37   -#define S3C2410_IISMOD_LR_RLOW (1<<5)
38   -#define S3C2410_IISMOD_IIS (0<<4)
39   -#define S3C2410_IISMOD_MSB (1<<4)
40   -#define S3C2410_IISMOD_8BIT (0<<3)
41   -#define S3C2410_IISMOD_16BIT (1<<3)
42   -#define S3C2410_IISMOD_BITMASK (1<<3)
43   -#define S3C2410_IISMOD_256FS (0<<2)
44   -#define S3C2410_IISMOD_384FS (1<<2)
45   -#define S3C2410_IISMOD_16FS (0<<0)
46   -#define S3C2410_IISMOD_32FS (1<<0)
47   -#define S3C2410_IISMOD_48FS (2<<0)
48   -#define S3C2410_IISMOD_FS_MASK (3<<0)
49   -
50   -#define S3C2410_IISPSR (0x08)
51   -#define S3C2410_IISPSR_INTMASK (31<<5)
52   -#define S3C2410_IISPSR_INTSHIFT (5)
53   -#define S3C2410_IISPSR_EXTMASK (31<<0)
54   -#define S3C2410_IISPSR_EXTSHFIT (0)
55   -
56   -#define S3C2410_IISFCON (0x0c)
57   -
58   -#define S3C2410_IISFCON_TXDMA (1<<15)
59   -#define S3C2410_IISFCON_RXDMA (1<<14)
60   -#define S3C2410_IISFCON_TXENABLE (1<<13)
61   -#define S3C2410_IISFCON_RXENABLE (1<<12)
62   -#define S3C2410_IISFCON_TXMASK (0x3f << 6)
63   -#define S3C2410_IISFCON_TXSHIFT (6)
64   -#define S3C2410_IISFCON_RXMASK (0x3f)
65   -#define S3C2410_IISFCON_RXSHIFT (0)
66   -
67   -#define S3C2400_IISFCON_TXDMA (1<<11)
68   -#define S3C2400_IISFCON_RXDMA (1<<10)
69   -#define S3C2400_IISFCON_TXENABLE (1<<9)
70   -#define S3C2400_IISFCON_RXENABLE (1<<8)
71   -#define S3C2400_IISFCON_TXMASK (0x07 << 4)
72   -#define S3C2400_IISFCON_TXSHIFT (4)
73   -#define S3C2400_IISFCON_RXMASK (0x07)
74   -#define S3C2400_IISFCON_RXSHIFT (0)
75   -
76   -#define S3C2410_IISFIFO (0x10)
77   -#endif /* __ASM_ARCH_REGS_IIS_H */
include/asm-arm/arch-s3c2410/regs-spi.h
View file @ 06cfa55
1   -/* linux/include/asm-arm/arch-s3c2410/regs-spi.h
2   - *
3   - * Copyright (c) 2004 Fetron GmbH
4   - *
5   - * This program is free software; you can redistribute it and/or modify
6   - * it under the terms of the GNU General Public License version 2 as
7   - * published by the Free Software Foundation.
8   - *
9   - * S3C2410 SPI register definition
10   -*/
11   -
12   -#ifndef __ASM_ARCH_REGS_SPI_H
13   -#define __ASM_ARCH_REGS_SPI_H
14   -
15   -#define S3C2410_SPI1 (0x20)
16   -#define S3C2412_SPI1 (0x100)
17   -
18   -#define S3C2410_SPCON (0x00)
19   -
20   -#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
21   -#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
22   -#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
23   -#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
24   -#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
25   - 0: slave, 1: master */
26   -#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
27   -#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
28   -
29   -#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
30   -#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
31   -
32   -#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
33   -
34   -
35   -#define S3C2410_SPSTA (0x04)
36   -
37   -#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
38   -#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
39   -#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
40   -
41   -
42   -#define S3C2410_SPPIN (0x08)
43   -
44   -#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
45   -#define S3C2410_SPPIN_RESERVED (1<<1)
46   -#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
47   -#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
48   -
49   -
50   -#define S3C2410_SPPRE (0x0C)
51   -#define S3C2410_SPTDAT (0x10)
52   -#define S3C2410_SPRDAT (0x14)
53   -
54   -#endif /* __ASM_ARCH_REGS_SPI_H */
include/asm-arm/arch-s3c2410/regs-udc.h
View file @ 06cfa55
1   -/* linux/include/asm-arm/arch-s3c2410/regs-udc.h
2   - *
3   - * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4   - *
5   - * This include file is free software; you can redistribute it and/or
6   - * modify it under the terms of the GNU General Public License as
7   - * published by the Free Software Foundation; either version 2 of
8   - * the License, or (at your option) any later version.
9   -*/
10   -
11   -#ifndef __ASM_ARCH_REGS_UDC_H
12   -#define __ASM_ARCH_REGS_UDC_H
13   -
14   -#define S3C2410_USBDREG(x) (x)
15   -
16   -#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
17   -#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
18   -#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
19   -
20   -#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
21   -#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
22   -
23   -#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
24   -
25   -#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
26   -#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
27   -
28   -#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
29   -#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
30   -#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
31   -#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
32   -#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
33   -
34   -#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
35   -#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
36   -#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
37   -#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
38   -#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
39   -#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
40   -
41   -#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
42   -#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
43   -#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
44   -#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
45   -#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
46   -#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
47   -
48   -#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
49   -#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
50   -#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
51   -#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
52   -#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
53   -#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
54   -
55   -#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
56   -#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
57   -#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
58   -#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
59   -#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
60   -#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
61   -
62   -#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
63   -
64   -/* indexed registers */
65   -
66   -#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
67   -
68   -#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
69   -
70   -#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
71   -#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
72   -
73   -#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
74   -#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
75   -#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
76   -#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
77   -
78   -#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7)
79   -
80   -#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
81   -#define S3C2410_UDC_PWR_RESET (1<<3) // R
82   -#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
83   -#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
84   -#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
85   -
86   -#define S3C2410_UDC_PWR_DEFAULT 0x00
87   -
88   -#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
89   -#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
90   -#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
91   -#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
92   -#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
93   -
94   -#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
95   -#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
96   -#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
97   -
98   -#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
99   -#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
100   -#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
101   -#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
102   -#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
103   -
104   -#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
105   -#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
106   -
107   -
108   -#define S3C2410_UDC_INDEX_EP0 (0x00)
109   -#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
110   -#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
111   -#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
112   -#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
113   -
114   -#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
115   -#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
116   -#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
117   -#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
118   -#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
119   -#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
120   -
121   -#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
122   -#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
123   -#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
124   -#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
125   -
126   -#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
127   -#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
128   -#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
129   -#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
130   -#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
131   -#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
132   -#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
133   -
134   -#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
135   -#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
136   -#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
137   -
138   -#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
139   -#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
140   -#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
141   -#define S3C2410_UDC_EP0_CSR_DE (1<<3)
142   -#define S3C2410_UDC_EP0_CSR_SE (1<<4)
143   -#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
144   -#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
145   -#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
146   -
147   -#define S3C2410_UDC_MAXP_8 (1<<0)
148   -#define S3C2410_UDC_MAXP_16 (1<<1)
149   -#define S3C2410_UDC_MAXP_32 (1<<2)
150   -#define S3C2410_UDC_MAXP_64 (1<<3)
151   -
152   -
153   -#endif
include/asm-arm/arch-s3c2410/udc.h
View file @ 06cfa55
1   -/* linux/include/asm-arm/arch-s3c2410/udc.h
2   - *
3   - * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
4   - *
5   - *
6   - * This program is free software; you can redistribute it and/or modify
7   - * it under the terms of the GNU General Public License version 2 as
8   - * published by the Free Software Foundation.
9   - *
10   - *
11   - * Changelog:
12   - * 14-Mar-2005 RTP Created file
13   - * 02-Aug-2005 RTP File rename
14   - * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
15   - * 18-Jan-2007 HMW Add per-platform vbus_draw function
16   -*/
17   -
18   -#ifndef __ASM_ARM_ARCH_UDC_H
19   -#define __ASM_ARM_ARCH_UDC_H
20   -
21   -enum s3c2410_udc_cmd_e {
22   - S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
23   - S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
24   - S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
25   -};
26   -
27   -struct s3c2410_udc_mach_info {
28   - void (*udc_command)(enum s3c2410_udc_cmd_e);
29   - void (*vbus_draw)(unsigned int ma);
30   - unsigned int vbus_pin;
31   - unsigned char vbus_pin_inverted;
32   -};
33   -
34   -extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
35   -
36   -#endif /* __ASM_ARM_ARCH_UDC_H */
include/asm-arm/plat-s3c/regs-ac97.h
Diff comments   View file @ 06cfa55
  1 +/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h
  2 + *
  3 + * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
  4 + * http://www.simtec.co.uk/products/SWLINUX/
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License version 2 as
  8 + * published by the Free Software Foundation.
  9 + *
  10 + * S3C2440 AC97 Controller
  11 +*/
  12 +
  13 +#ifndef __ASM_ARCH_REGS_AC97_H
  14 +#define __ASM_ARCH_REGS_AC97_H __FILE__
  15 +
  16 +#define S3C_AC97_GLBCTRL (0x00)
  17 +
  18 +#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
  19 +#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
  20 +#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
  21 +#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
  22 +#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
  23 +#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
  24 +#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
  25 +#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
  26 +#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
  27 +#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
  28 +#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
  29 +#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
  30 +#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
  31 +#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
  32 +#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
  33 +#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
  34 +#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
  35 +#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
  36 +#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
  37 +#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
  38 +#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
  39 +#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
  40 +#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
  41 +
  42 +#define S3C_AC97_GLBSTAT (0x04)
  43 +
  44 +#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
  45 +#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
  46 +#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
  47 +#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
  48 +#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
  49 +#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
  50 +#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
  51 +#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
  52 +#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
  53 +#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
  54 +#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
  55 +#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
  56 +#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
  57 +
  58 +#define S3C_AC97_CODEC_CMD (0x08)
  59 +
  60 +#define S3C_AC97_CODEC_CMD_READ (1<<23)
  61 +
  62 +#define S3C_AC97_STAT (0x0c)
  63 +#define S3C_AC97_PCM_ADDR (0x10)
  64 +#define S3C_AC97_PCM_DATA (0x18)
  65 +#define S3C_AC97_MIC_DATA (0x1C)
  66 +
  67 +#endif /* __ASM_ARCH_REGS_AC97_H */
include/asm-arm/plat-s3c/regs-adc.h
Diff comments   View file @ 06cfa55
  1 +/* linux/include/asm-arm/arch-s3c2410/regs-adc.h
  2 + *
  3 + * Copyright (c) 2004 Shannon Holland <holland@loser.net>
  4 + *
  5 + * This program is free software; yosu can redistribute it and/or modify
  6 + * it under the terms of the GNU General Public License version 2 as
  7 + * published by the Free Software Foundation.
  8 + *
  9 + * S3C2410 ADC registers
  10 +*/
  11 +
  12 +#ifndef __ASM_ARCH_REGS_ADC_H
  13 +#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
  14 +
  15 +#define S3C2410_ADCREG(x) (x)
  16 +
  17 +#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
  18 +#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
  19 +#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
  20 +#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
  21 +#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
  22 +
  23 +
  24 +/* ADCCON Register Bits */
  25 +#define S3C2410_ADCCON_ECFLG (1<<15)
  26 +#define S3C2410_ADCCON_PRSCEN (1<<14)
  27 +#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
  28 +#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
  29 +#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
  30 +#define S3C2410_ADCCON_MUXMASK (0x7<<3)
  31 +#define S3C2410_ADCCON_STDBM (1<<2)
  32 +#define S3C2410_ADCCON_READ_START (1<<1)
  33 +#define S3C2410_ADCCON_ENABLE_START (1<<0)
  34 +#define S3C2410_ADCCON_STARTMASK (0x3<<0)
  35 +
  36 +
  37 +/* ADCTSC Register Bits */
  38 +#define S3C2410_ADCTSC_YM_SEN (1<<7)
  39 +#define S3C2410_ADCTSC_YP_SEN (1<<6)
  40 +#define S3C2410_ADCTSC_XM_SEN (1<<5)
  41 +#define S3C2410_ADCTSC_XP_SEN (1<<4)
  42 +#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
  43 +#define S3C2410_ADCTSC_AUTO_PST (1<<2)
  44 +#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
  45 +
  46 +/* ADCDAT0 Bits */
  47 +#define S3C2410_ADCDAT0_UPDOWN (1<<15)
  48 +#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
  49 +#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
  50 +#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
  51 +
  52 +/* ADCDAT1 Bits */
  53 +#define S3C2410_ADCDAT1_UPDOWN (1<<15)
  54 +#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
  55 +#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
  56 +#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
  57 +
  58 +#endif /* __ASM_ARCH_REGS_ADC_H */
include/asm-arm/plat-s3c24xx/regs-iis.h
Diff comments   View file @ 06cfa55
  1 +/* linux/include/asm-arm/arch-s3c2410/regs-iis.h
  2 + *
  3 + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
  4 + * http://www.simtec.co.uk/products/SWLINUX/
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License version 2 as
  8 + * published by the Free Software Foundation.
  9 + *
  10 + * S3C2410 IIS register definition
  11 +*/
  12 +
  13 +#ifndef __ASM_ARCH_REGS_IIS_H
  14 +#define __ASM_ARCH_REGS_IIS_H
  15 +
  16 +#define S3C2410_IISCON (0x00)
  17 +
  18 +#define S3C2410_IISCON_LRINDEX (1<<8)
  19 +#define S3C2410_IISCON_TXFIFORDY (1<<7)
  20 +#define S3C2410_IISCON_RXFIFORDY (1<<6)
  21 +#define S3C2410_IISCON_TXDMAEN (1<<5)
  22 +#define S3C2410_IISCON_RXDMAEN (1<<4)
  23 +#define S3C2410_IISCON_TXIDLE (1<<3)
  24 +#define S3C2410_IISCON_RXIDLE (1<<2)
  25 +#define S3C2410_IISCON_PSCEN (1<<1)
  26 +#define S3C2410_IISCON_IISEN (1<<0)
  27 +
  28 +#define S3C2410_IISMOD (0x04)
  29 +
  30 +#define S3C2440_IISMOD_MPLL (1<<9)
  31 +#define S3C2410_IISMOD_SLAVE (1<<8)
  32 +#define S3C2410_IISMOD_NOXFER (0<<6)
  33 +#define S3C2410_IISMOD_RXMODE (1<<6)
  34 +#define S3C2410_IISMOD_TXMODE (2<<6)
  35 +#define S3C2410_IISMOD_TXRXMODE (3<<6)
  36 +#define S3C2410_IISMOD_LR_LLOW (0<<5)
  37 +#define S3C2410_IISMOD_LR_RLOW (1<<5)
  38 +#define S3C2410_IISMOD_IIS (0<<4)
  39 +#define S3C2410_IISMOD_MSB (1<<4)
  40 +#define S3C2410_IISMOD_8BIT (0<<3)
  41 +#define S3C2410_IISMOD_16BIT (1<<3)
  42 +#define S3C2410_IISMOD_BITMASK (1<<3)
  43 +#define S3C2410_IISMOD_256FS (0<<2)
  44 +#define S3C2410_IISMOD_384FS (1<<2)
  45 +#define S3C2410_IISMOD_16FS (0<<0)
  46 +#define S3C2410_IISMOD_32FS (1<<0)
  47 +#define S3C2410_IISMOD_48FS (2<<0)
  48 +#define S3C2410_IISMOD_FS_MASK (3<<0)
  49 +
  50 +#define S3C2410_IISPSR (0x08)
  51 +#define S3C2410_IISPSR_INTMASK (31<<5)
  52 +#define S3C2410_IISPSR_INTSHIFT (5)
  53 +#define S3C2410_IISPSR_EXTMASK (31<<0)
  54 +#define S3C2410_IISPSR_EXTSHFIT (0)
  55 +
  56 +#define S3C2410_IISFCON (0x0c)
  57 +
  58 +#define S3C2410_IISFCON_TXDMA (1<<15)
  59 +#define S3C2410_IISFCON_RXDMA (1<<14)
  60 +#define S3C2410_IISFCON_TXENABLE (1<<13)
  61 +#define S3C2410_IISFCON_RXENABLE (1<<12)
  62 +#define S3C2410_IISFCON_TXMASK (0x3f << 6)
  63 +#define S3C2410_IISFCON_TXSHIFT (6)
  64 +#define S3C2410_IISFCON_RXMASK (0x3f)
  65 +#define S3C2410_IISFCON_RXSHIFT (0)
  66 +
  67 +#define S3C2400_IISFCON_TXDMA (1<<11)
  68 +#define S3C2400_IISFCON_RXDMA (1<<10)
  69 +#define S3C2400_IISFCON_TXENABLE (1<<9)
  70 +#define S3C2400_IISFCON_RXENABLE (1<<8)
  71 +#define S3C2400_IISFCON_TXMASK (0x07 << 4)
  72 +#define S3C2400_IISFCON_TXSHIFT (4)
  73 +#define S3C2400_IISFCON_RXMASK (0x07)
  74 +#define S3C2400_IISFCON_RXSHIFT (0)
  75 +
  76 +#define S3C2410_IISFIFO (0x10)
  77 +#endif /* __ASM_ARCH_REGS_IIS_H */
include/asm-arm/plat-s3c24xx/regs-spi.h
Diff comments   View file @ 06cfa55
  1 +/* linux/include/asm-arm/arch-s3c2410/regs-spi.h
  2 + *
  3 + * Copyright (c) 2004 Fetron GmbH
  4 + *
  5 + * This program is free software; you can redistribute it and/or modify
  6 + * it under the terms of the GNU General Public License version 2 as
  7 + * published by the Free Software Foundation.
  8 + *
  9 + * S3C2410 SPI register definition
  10 +*/
  11 +
  12 +#ifndef __ASM_ARCH_REGS_SPI_H
  13 +#define __ASM_ARCH_REGS_SPI_H
  14 +
  15 +#define S3C2410_SPI1 (0x20)
  16 +#define S3C2412_SPI1 (0x100)
  17 +
  18 +#define S3C2410_SPCON (0x00)
  19 +
  20 +#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
  21 +#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
  22 +#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
  23 +#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
  24 +#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
  25 + 0: slave, 1: master */
  26 +#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
  27 +#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
  28 +
  29 +#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
  30 +#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
  31 +
  32 +#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
  33 +
  34 +
  35 +#define S3C2410_SPSTA (0x04)
  36 +
  37 +#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
  38 +#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
  39 +#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
  40 +
  41 +
  42 +#define S3C2410_SPPIN (0x08)
  43 +
  44 +#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
  45 +#define S3C2410_SPPIN_RESERVED (1<<1)
  46 +#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
  47 +#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
  48 +
  49 +
  50 +#define S3C2410_SPPRE (0x0C)
  51 +#define S3C2410_SPTDAT (0x10)
  52 +#define S3C2410_SPRDAT (0x14)
  53 +
  54 +#endif /* __ASM_ARCH_REGS_SPI_H */
include/asm-arm/plat-s3c24xx/regs-udc.h
Diff comments   View file @ 06cfa55
  1 +/* linux/include/asm-arm/arch-s3c2410/regs-udc.h
  2 + *
  3 + * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
  4 + *
  5 + * This include file is free software; you can redistribute it and/or
  6 + * modify it under the terms of the GNU General Public License as
  7 + * published by the Free Software Foundation; either version 2 of
  8 + * the License, or (at your option) any later version.
  9 +*/
  10 +
  11 +#ifndef __ASM_ARCH_REGS_UDC_H
  12 +#define __ASM_ARCH_REGS_UDC_H
  13 +
  14 +#define S3C2410_USBDREG(x) (x)
  15 +
  16 +#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
  17 +#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
  18 +#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
  19 +
  20 +#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
  21 +#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
  22 +
  23 +#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
  24 +
  25 +#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
  26 +#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
  27 +
  28 +#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
  29 +#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
  30 +#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
  31 +#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
  32 +#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
  33 +
  34 +#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
  35 +#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
  36 +#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
  37 +#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
  38 +#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
  39 +#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
  40 +
  41 +#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
  42 +#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
  43 +#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
  44 +#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
  45 +#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
  46 +#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
  47 +
  48 +#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
  49 +#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
  50 +#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
  51 +#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
  52 +#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
  53 +#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
  54 +
  55 +#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
  56 +#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
  57 +#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
  58 +#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
  59 +#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
  60 +#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
  61 +
  62 +#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
  63 +
  64 +/* indexed registers */
  65 +
  66 +#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
  67 +
  68 +#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
  69 +
  70 +#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
  71 +#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
  72 +
  73 +#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
  74 +#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
  75 +#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
  76 +#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
  77 +
  78 +#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7)
  79 +
  80 +#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
  81 +#define S3C2410_UDC_PWR_RESET (1<<3) // R
  82 +#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
  83 +#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
  84 +#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
  85 +
  86 +#define S3C2410_UDC_PWR_DEFAULT 0x00
  87 +
  88 +#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
  89 +#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
  90 +#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
  91 +#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
  92 +#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
  93 +
  94 +#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
  95 +#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
  96 +#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
  97 +
  98 +#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
  99 +#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
  100 +#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
  101 +#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
  102 +#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
  103 +
  104 +#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
  105 +#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
  106 +
  107 +
  108 +#define S3C2410_UDC_INDEX_EP0 (0x00)
  109 +#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
  110 +#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
  111 +#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
  112 +#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
  113 +
  114 +#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
  115 +#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
  116 +#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
  117 +#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
  118 +#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
  119 +#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
  120 +
  121 +#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
  122 +#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
  123 +#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
  124 +#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
  125 +
  126 +#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
  127 +#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
  128 +#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
  129 +#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
  130 +#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
  131 +#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
  132 +#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
  133 +
  134 +#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
  135 +#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
  136 +#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
  137 +
  138 +#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
  139 +#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
  140 +#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
  141 +#define S3C2410_UDC_EP0_CSR_DE (1<<3)
  142 +#define S3C2410_UDC_EP0_CSR_SE (1<<4)
  143 +#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
  144 +#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
  145 +#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
  146 +
  147 +#define S3C2410_UDC_MAXP_8 (1<<0)
  148 +#define S3C2410_UDC_MAXP_16 (1<<1)
  149 +#define S3C2410_UDC_MAXP_32 (1<<2)
  150 +#define S3C2410_UDC_MAXP_64 (1<<3)
  151 +
  152 +
  153 +#endif
include/asm-arm/plat-s3c24xx/udc.h
Diff comments   View file @ 06cfa55
  1 +/* linux/include/asm-arm/arch-s3c2410/udc.h
  2 + *
  3 + * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
  4 + *
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License version 2 as
  8 + * published by the Free Software Foundation.
  9 + *
  10 + *
  11 + * Changelog:
  12 + * 14-Mar-2005 RTP Created file
  13 + * 02-Aug-2005 RTP File rename
  14 + * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
  15 + * 18-Jan-2007 HMW Add per-platform vbus_draw function
  16 +*/
  17 +
  18 +#ifndef __ASM_ARM_ARCH_UDC_H
  19 +#define __ASM_ARM_ARCH_UDC_H
  20 +
  21 +enum s3c2410_udc_cmd_e {
  22 + S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
  23 + S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
  24 + S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
  25 +};
  26 +
  27 +struct s3c2410_udc_mach_info {
  28 + void (*udc_command)(enum s3c2410_udc_cmd_e);
  29 + void (*vbus_draw)(unsigned int ma);
  30 + unsigned int vbus_pin;
  31 + unsigned char vbus_pin_inverted;
  32 +};
  33 +
  34 +extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
  35 +
  36 +#endif /* __ASM_ARM_ARCH_UDC_H */