Commit 0b3f0d12eff1ed23496fcf4cf468e1d317516e53
Committed by
David Woodhouse
David Woodhouse
1 parent
dd5ab24832
Exists in
smarc-l5.0.0_1.0.0-ga
and in
5 other branches
mtd: sh_flctl: Use cached register value for FLCMNCR
Instead of reading out the register, use a cached value. This will make way for a proper runtime power management implementation. Signed-off-by: Bastian Hecht <hechtb@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Showing 2 changed files with 8 additions and 15 deletions Side-by-side Diff
drivers/mtd/nand/sh_flctl.c
| ... | ... | @@ -283,7 +283,7 @@ |
| 283 | 283 | static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val) |
| 284 | 284 | { |
| 285 | 285 | struct sh_flctl *flctl = mtd_to_flctl(mtd); |
| 286 | - uint32_t flcmncr_val = readl(FLCMNCR(flctl)) & ~SEL_16BIT; | |
| 286 | + uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT; | |
| 287 | 287 | uint32_t flcmdcr_val, addr_len_bytes = 0; |
| 288 | 288 | |
| 289 | 289 | /* Set SNAND bit if page size is 2048byte */ |
| 290 | 290 | |
| 291 | 291 | |
| ... | ... | @@ -684,16 +684,15 @@ |
| 684 | 684 | static void flctl_select_chip(struct mtd_info *mtd, int chipnr) |
| 685 | 685 | { |
| 686 | 686 | struct sh_flctl *flctl = mtd_to_flctl(mtd); |
| 687 | - uint32_t flcmncr_val = readl(FLCMNCR(flctl)); | |
| 688 | 687 | |
| 689 | 688 | switch (chipnr) { |
| 690 | 689 | case -1: |
| 691 | - flcmncr_val &= ~CE0_ENABLE; | |
| 692 | - writel(flcmncr_val, FLCMNCR(flctl)); | |
| 690 | + flctl->flcmncr_base &= ~CE0_ENABLE; | |
| 691 | + writel(flctl->flcmncr_base, FLCMNCR(flctl)); | |
| 693 | 692 | break; |
| 694 | 693 | case 0: |
| 695 | - flcmncr_val |= CE0_ENABLE; | |
| 696 | - writel(flcmncr_val, FLCMNCR(flctl)); | |
| 694 | + flctl->flcmncr_base |= CE0_ENABLE; | |
| 695 | + writel(flctl->flcmncr_base, FLCMNCR(flctl)); | |
| 697 | 696 | break; |
| 698 | 697 | default: |
| 699 | 698 | BUG(); |
| ... | ... | @@ -751,11 +750,6 @@ |
| 751 | 750 | return 0; |
| 752 | 751 | } |
| 753 | 752 | |
| 754 | -static void flctl_register_init(struct sh_flctl *flctl, unsigned long val) | |
| 755 | -{ | |
| 756 | - writel(val, FLCMNCR(flctl)); | |
| 757 | -} | |
| 758 | - | |
| 759 | 753 | static int flctl_chip_init_tail(struct mtd_info *mtd) |
| 760 | 754 | { |
| 761 | 755 | struct sh_flctl *flctl = mtd_to_flctl(mtd); |
| ... | ... | @@ -807,8 +801,7 @@ |
| 807 | 801 | chip->ecc.mode = NAND_ECC_HW; |
| 808 | 802 | |
| 809 | 803 | /* 4 symbols ECC enabled */ |
| 810 | - writel(readl(FLCMNCR(flctl)) | _4ECCEN | ECCPOS2 | ECCPOS_02, | |
| 811 | - FLCMNCR(flctl)); | |
| 804 | + flctl->flcmncr_base |= _4ECCEN | ECCPOS2 | ECCPOS_02; | |
| 812 | 805 | } else { |
| 813 | 806 | chip->ecc.mode = NAND_ECC_SOFT; |
| 814 | 807 | } |
| 815 | 808 | |
| ... | ... | @@ -854,9 +847,8 @@ |
| 854 | 847 | nand = &flctl->chip; |
| 855 | 848 | flctl_mtd->priv = nand; |
| 856 | 849 | flctl->pdev = pdev; |
| 850 | + flctl->flcmncr_base = pdata->flcmncr_val; | |
| 857 | 851 | flctl->hwecc = pdata->has_hwecc; |
| 858 | - | |
| 859 | - flctl_register_init(flctl, pdata->flcmncr_val); | |
| 860 | 852 | |
| 861 | 853 | nand->options = NAND_NO_AUTOINCR; |
| 862 | 854 |
include/linux/mtd/sh_flctl.h
| ... | ... | @@ -132,6 +132,7 @@ |
| 132 | 132 | int erase1_page_addr; /* page_addr in ERASE1 cmd */ |
| 133 | 133 | uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ |
| 134 | 134 | uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ |
| 135 | + uint32_t flcmncr_base; /* base value of FLCMNCR */ | |
| 135 | 136 | |
| 136 | 137 | int hwecc_cant_correct[4]; |
| 137 | 138 |