Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm exynos/intel updates from Dave Airlie: "Two minor updates from Jesse for Intel SNB fixes, and a few fixes from Samsung for exynos. The pull req has Alan's commit in it since Intel based their tree on my tree at that time, but it all seems fine wrt merging." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm exynos: use drm_fb_helper_set_par directly drm/exynos: Fix fb_videomode <-> drm_mode_modeinfo conversion drm/exynos: fix runtime_pm fimd device state on probe drm/exynos: use correct 'exynos-drm' name for platform device drm/i915: support 32 bit BGR formats in sprite planes drm/i915: fix color order for BGR formats on SNB drm/gma500: Fix Cedarview boot failures in 3.3-rc

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm exynos/intel updates from Dave Airlie: "Two minor updates from Jesse for Intel SNB fixes, and a few fixes from Samsung for exynos. The pull req has Alan's commit in it since Intel based their tree on my tree at that time, but it all seems fine wrt merging." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm exynos: use drm_fb_helper_set_par directly drm/exynos: Fix fb_videomode <-> drm_mode_modeinfo conversion drm/exynos: fix runtime_pm fimd device state on probe drm/exynos: use correct 'exynos-drm' name for platform device drm/i915: support 32 bit BGR formats in sprite planes drm/i915: fix color order for BGR formats on SNB drm/gma500: Fix Cedarview boot failures in 3.3-rc
Linus Torvalds
2 parents 72c79bdbda bb2551da10
Showing 7 changed files Side-by-side Diff
drivers/gpu/drm/exynos/exynos_drm_connector.c
drivers/gpu/drm/exynos/exynos_drm_drv.c
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
drivers/gpu/drm/exynos/exynos_drm_fimd.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_sprite.c
@@ -54,14 +54,14 @@
 	mode->vrefresh = timing->refresh;
  
 	mode->hdisplay = timing->xres;
-	mode->hsync_start = mode->hdisplay + timing->left_margin;
+	mode->hsync_start = mode->hdisplay + timing->right_margin;
 	mode->hsync_end = mode->hsync_start + timing->hsync_len;
-	mode->htotal = mode->hsync_end + timing->right_margin;
+	mode->htotal = mode->hsync_end + timing->left_margin;
  
 	mode->vdisplay = timing->yres;
-	mode->vsync_start = mode->vdisplay + timing->upper_margin;
+	mode->vsync_start = mode->vdisplay + timing->lower_margin;
 	mode->vsync_end = mode->vsync_start + timing->vsync_len;
-	mode->vtotal = mode->vsync_end + timing->lower_margin;
+	mode->vtotal = mode->vsync_end + timing->upper_margin;
 	mode->width_mm = panel->width_mm;
 	mode->height_mm = panel->height_mm;
  
  
  
  
@@ -85,14 +85,14 @@
 	timing->refresh = drm_mode_vrefresh(mode);
  
 	timing->xres = mode->hdisplay;
-	timing->left_margin = mode->hsync_start - mode->hdisplay;
+	timing->right_margin = mode->hsync_start - mode->hdisplay;
 	timing->hsync_len = mode->hsync_end - mode->hsync_start;
-	timing->right_margin = mode->htotal - mode->hsync_end;
+	timing->left_margin = mode->htotal - mode->hsync_end;
  
 	timing->yres = mode->vdisplay;
-	timing->upper_margin = mode->vsync_start - mode->vdisplay;
+	timing->lower_margin = mode->vsync_start - mode->vdisplay;
 	timing->vsync_len = mode->vsync_end - mode->vsync_start;
-	timing->lower_margin = mode->vtotal - mode->vsync_end;
+	timing->upper_margin = mode->vtotal - mode->vsync_end;
  
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 		timing->vmode = FB_VMODE_INTERLACED;
@@ -246,7 +246,7 @@
 	.remove		= __devexit_p(exynos_drm_platform_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
-		.name	= DRIVER_NAME,
+		.name	= "exynos-drm",
 	},
 };
  
@@ -46,39 +46,13 @@
 	struct exynos_drm_gem_obj	*exynos_gem_obj;
 };
  
-static int exynos_drm_fbdev_set_par(struct fb_info *info)
-{
-	struct fb_var_screeninfo *var = &info->var;
-
-	switch (var->bits_per_pixel) {
-	case 32:
-	case 24:
-	case 18:
-	case 16:
-	case 12:
-		info->fix.visual = FB_VISUAL_TRUECOLOR;
-		break;
-	case 1:
-		info->fix.visual = FB_VISUAL_MONO01;
-		break;
-	default:
-		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
-		break;
-	}
-
-	info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
-
-	return drm_fb_helper_set_par(info);
-}
-
-
 static struct fb_ops exynos_drm_fb_ops = {
 	.owner		= THIS_MODULE,
 	.fb_fillrect	= cfb_fillrect,
 	.fb_copyarea	= cfb_copyarea,
 	.fb_imageblit	= cfb_imageblit,
 	.fb_check_var	= drm_fb_helper_check_var,
-	.fb_set_par	= exynos_drm_fbdev_set_par,
+	.fb_set_par	= drm_fb_helper_set_par,
 	.fb_blank	= drm_fb_helper_blank,
 	.fb_pan_display	= drm_fb_helper_pan_display,
 	.fb_setcmap	= drm_fb_helper_setcmap,
@@ -817,8 +817,6 @@
 		goto err_clk_get;
 	}
  
-	clk_enable(ctx->bus_clk);
-
 	ctx->lcd_clk = clk_get(dev, "sclk_fimd");
 	if (IS_ERR(ctx->lcd_clk)) {
 		dev_err(dev, "failed to get lcd clock\n");
@@ -826,8 +824,6 @@
 		goto err_bus_clk;
 	}
  
-	clk_enable(ctx->lcd_clk);
-
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(dev, "failed to find registers\n");
  
@@ -864,17 +860,11 @@
 		goto err_req_irq;
 	}
  
-	ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
 	ctx->vidcon0 = pdata->vidcon0;
 	ctx->vidcon1 = pdata->vidcon1;
 	ctx->default_win = pdata->default_win;
 	ctx->panel = panel;
  
-	panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
-
-	DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
-			panel->timing.pixclock, ctx->clkdiv);
-
 	subdrv = &ctx->subdrv;
  
 	subdrv->probe = fimd_subdrv_probe;
  
@@ -889,9 +879,14 @@
  
 	platform_set_drvdata(pdev, ctx);
  
-	pm_runtime_set_active(dev);
 	pm_runtime_enable(dev);
 	pm_runtime_get_sync(dev);
+
+	ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
+	panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
+
+	DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
+			panel->timing.pixclock, ctx->clkdiv);
  
 	for (win = 0; win < WINDOWS_NR; win++)
 		fimd_clear_win(ctx, win);
@@ -2689,7 +2689,7 @@
 #define   DVS_FORMAT_RGBX888	(2<<25)
 #define   DVS_FORMAT_RGBX161616	(3<<25)
 #define   DVS_SOURCE_KEY	(1<<22)
-#define   DVS_RGB_ORDER_RGBX	(1<<20)
+#define   DVS_RGB_ORDER_XBGR	(1<<20)
 #define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
 #define   DVS_YUV_ORDER_YUYV	(0<<16)
 #define   DVS_YUV_ORDER_UYVY	(1<<16)
@@ -7828,6 +7828,7 @@
 	case DRM_FORMAT_RGB332:
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB8888:
+	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_ARGB2101010:
@@ -225,16 +225,16 @@
  
 	/* Mask out pixel format bits in case we change it */
 	dvscntr &= ~DVS_PIXFORMAT_MASK;
-	dvscntr &= ~DVS_RGB_ORDER_RGBX;
+	dvscntr &= ~DVS_RGB_ORDER_XBGR;
 	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
  
 	switch (fb->pixel_format) {
 	case DRM_FORMAT_XBGR8888:
-		dvscntr |= DVS_FORMAT_RGBX888;
+		dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 		pixel_size = 4;
 		break;
 	case DRM_FORMAT_XRGB8888:
-		dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_RGBX;
+		dvscntr |= DVS_FORMAT_RGBX888;
 		pixel_size = 4;
 		break;
 	case DRM_FORMAT_YUYV:
...	...	@@ -54,14 +54,14 @@
54	54	mode->vrefresh = timing->refresh;
55	55
56	56	mode->hdisplay = timing->xres;
57		- mode->hsync_start = mode->hdisplay + timing->left_margin;
	57	+ mode->hsync_start = mode->hdisplay + timing->right_margin;
58	58	mode->hsync_end = mode->hsync_start + timing->hsync_len;
59		- mode->htotal = mode->hsync_end + timing->right_margin;
	59	+ mode->htotal = mode->hsync_end + timing->left_margin;
60	60
61	61	mode->vdisplay = timing->yres;
62		- mode->vsync_start = mode->vdisplay + timing->upper_margin;
	62	+ mode->vsync_start = mode->vdisplay + timing->lower_margin;
63	63	mode->vsync_end = mode->vsync_start + timing->vsync_len;
64		- mode->vtotal = mode->vsync_end + timing->lower_margin;
	64	+ mode->vtotal = mode->vsync_end + timing->upper_margin;
65	65	mode->width_mm = panel->width_mm;
66	66	mode->height_mm = panel->height_mm;
67	67
68	68
69	69
70	70
...	...	@@ -85,14 +85,14 @@
85	85	timing->refresh = drm_mode_vrefresh(mode);
86	86
87	87	timing->xres = mode->hdisplay;
88		- timing->left_margin = mode->hsync_start - mode->hdisplay;
	88	+ timing->right_margin = mode->hsync_start - mode->hdisplay;
89	89	timing->hsync_len = mode->hsync_end - mode->hsync_start;
90		- timing->right_margin = mode->htotal - mode->hsync_end;
	90	+ timing->left_margin = mode->htotal - mode->hsync_end;
91	91
92	92	timing->yres = mode->vdisplay;
93		- timing->upper_margin = mode->vsync_start - mode->vdisplay;
	93	+ timing->lower_margin = mode->vsync_start - mode->vdisplay;
94	94	timing->vsync_len = mode->vsync_end - mode->vsync_start;
95		- timing->lower_margin = mode->vtotal - mode->vsync_end;
	95	+ timing->upper_margin = mode->vtotal - mode->vsync_end;
96	96
97	97	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
98	98	timing->vmode = FB_VMODE_INTERLACED;
...	...	@@ -246,7 +246,7 @@
246	246	.remove = __devexit_p(exynos_drm_platform_remove),
247	247	.driver = {
248	248	.owner = THIS_MODULE,
249		- .name = DRIVER_NAME,
	249	+ .name = "exynos-drm",
250	250	},
251	251	};
252	252
...	...	@@ -46,39 +46,13 @@
46	46	struct exynos_drm_gem_obj *exynos_gem_obj;
47	47	};
48	48
49		-static int exynos_drm_fbdev_set_par(struct fb_info *info)
50		-{
51		- struct fb_var_screeninfo *var = &info->var;
52		-
53		- switch (var->bits_per_pixel) {
54		- case 32:
55		- case 24:
56		- case 18:
57		- case 16:
58		- case 12:
59		- info->fix.visual = FB_VISUAL_TRUECOLOR;
60		- break;
61		- case 1:
62		- info->fix.visual = FB_VISUAL_MONO01;
63		- break;
64		- default:
65		- info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
66		- break;
67		- }
68		-
69		- info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
70		-
71		- return drm_fb_helper_set_par(info);
72		-}
73		-
74		-
75	49	static struct fb_ops exynos_drm_fb_ops = {
76	50	.owner = THIS_MODULE,
77	51	.fb_fillrect = cfb_fillrect,
78	52	.fb_copyarea = cfb_copyarea,
79	53	.fb_imageblit = cfb_imageblit,
80	54	.fb_check_var = drm_fb_helper_check_var,
81		- .fb_set_par = exynos_drm_fbdev_set_par,
	55	+ .fb_set_par = drm_fb_helper_set_par,
82	56	.fb_blank = drm_fb_helper_blank,
83	57	.fb_pan_display = drm_fb_helper_pan_display,
84	58	.fb_setcmap = drm_fb_helper_setcmap,
...	...	@@ -817,8 +817,6 @@
817	817	goto err_clk_get;
818	818	}
819	819
820		- clk_enable(ctx->bus_clk);
821		-
822	820	ctx->lcd_clk = clk_get(dev, "sclk_fimd");
823	821	if (IS_ERR(ctx->lcd_clk)) {
824	822	dev_err(dev, "failed to get lcd clock\n");
...	...	@@ -826,8 +824,6 @@
826	824	goto err_bus_clk;
827	825	}
828	826
829		- clk_enable(ctx->lcd_clk);
830		-
831	827	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
832	828	if (!res) {
833	829	dev_err(dev, "failed to find registers\n");
834	830
...	...	@@ -864,17 +860,11 @@
864	860	goto err_req_irq;
865	861	}
866	862
867		- ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
868	863	ctx->vidcon0 = pdata->vidcon0;
869	864	ctx->vidcon1 = pdata->vidcon1;
870	865	ctx->default_win = pdata->default_win;
871	866	ctx->panel = panel;
872	867
873		- panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
874		-
875		- DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
876		- panel->timing.pixclock, ctx->clkdiv);
877		-
878	868	subdrv = &ctx->subdrv;
879	869
880	870	subdrv->probe = fimd_subdrv_probe;
881	871
...	...	@@ -889,9 +879,14 @@
889	879
890	880	platform_set_drvdata(pdev, ctx);
891	881
892		- pm_runtime_set_active(dev);
893	882	pm_runtime_enable(dev);
894	883	pm_runtime_get_sync(dev);
	884	+
	885	+ ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
	886	+ panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
	887	+
	888	+ DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
	889	+ panel->timing.pixclock, ctx->clkdiv);
895	890
896	891	for (win = 0; win < WINDOWS_NR; win++)
897	892	fimd_clear_win(ctx, win);
...	...	@@ -2689,7 +2689,7 @@
2689	2689	#define DVS_FORMAT_RGBX888 (2<<25)
2690	2690	#define DVS_FORMAT_RGBX161616 (3<<25)
2691	2691	#define DVS_SOURCE_KEY (1<<22)
2692		-#define DVS_RGB_ORDER_RGBX (1<<20)
	2692	+#define DVS_RGB_ORDER_XBGR (1<<20)
2693	2693	#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
2694	2694	#define DVS_YUV_ORDER_YUYV (0<<16)
2695	2695	#define DVS_YUV_ORDER_UYVY (1<<16)
...	...	@@ -7828,6 +7828,7 @@
7828	7828	case DRM_FORMAT_RGB332:
7829	7829	case DRM_FORMAT_RGB565:
7830	7830	case DRM_FORMAT_XRGB8888:
	7831	+ case DRM_FORMAT_XBGR8888:
7831	7832	case DRM_FORMAT_ARGB8888:
7832	7833	case DRM_FORMAT_XRGB2101010:
7833	7834	case DRM_FORMAT_ARGB2101010:
...	...	@@ -225,16 +225,16 @@
225	225
226	226	/* Mask out pixel format bits in case we change it */
227	227	dvscntr &= ~DVS_PIXFORMAT_MASK;
228		- dvscntr &= ~DVS_RGB_ORDER_RGBX;
	228	+ dvscntr &= ~DVS_RGB_ORDER_XBGR;
229	229	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
230	230
231	231	switch (fb->pixel_format) {
232	232	case DRM_FORMAT_XBGR8888:
233		- dvscntr \|= DVS_FORMAT_RGBX888;
	233	+ dvscntr \|= DVS_FORMAT_RGBX888 \| DVS_RGB_ORDER_XBGR;
234	234	pixel_size = 4;
235	235	break;
236	236	case DRM_FORMAT_XRGB8888:
237		- dvscntr \|= DVS_FORMAT_RGBX888 \| DVS_RGB_ORDER_RGBX;
	237	+ dvscntr \|= DVS_FORMAT_RGBX888;
238	238	pixel_size = 4;
239	239	break;
240	240	case DRM_FORMAT_YUYV: