Commit 0c58d0f15879856dd750223abeeb0410a0891ca2
1 parent
67779bf67e
Exists in
imx_3.0.35_4.1.0
ENGR00318393 [iMX6x] Ensure certain CP15 registers are maintained across suspend/resume
Many A9 errata require bits in the diagnostic control register to be set. During a suspend/resume cycle, the A9 core may get power gated, implying that the register needs to be maintained across a suspend/resume cycle. Also ensure that power control register is saved/restored. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Showing 1 changed file with 16 additions and 0 deletions Side-by-side Diff
arch/arm/mach-mx6/mx6_suspend.S
... | ... | @@ -1123,6 +1123,14 @@ |
1123 | 1123 | mrs r7, cpsr @ Store CPSR |
1124 | 1124 | stmfd r0!, {r4-r7} |
1125 | 1125 | |
1126 | + /* Save diagnostic control register */ | |
1127 | + mrc p15, 0, r4, c15, c0, 1 @ Diagnostic control reg | |
1128 | + stmfd r0!, {r4} | |
1129 | + | |
1130 | + /* Save Power control register */ | |
1131 | + mrc p15, 0, r4, c15, c0, 0 @ Diagnostic control reg | |
1132 | + stmfd r0!, {r4} | |
1133 | + | |
1126 | 1134 | /* c1 control register */ |
1127 | 1135 | mrc p15, 0, r4, c1, c0, 0 @ SCTLR |
1128 | 1136 | stmfd r0!, {r4} |
... | ... | @@ -1709,6 +1717,14 @@ |
1709 | 1717 | mcr p15, 0, r5, c13, c0, 2 @ User r/w thread ID |
1710 | 1718 | mrc p15, 0, r6, c12, c0, 0 @ Secure or NS VBAR |
1711 | 1719 | msr cpsr, r7 @ store cpsr |
1720 | + | |
1721 | + /* Restore diagnostic control register */ | |
1722 | + ldmea r0!,{r4} | |
1723 | + mcr p15, 0, r4, c15, c0, 1 @ Diagnostic control reg | |
1724 | + | |
1725 | + /* Restore Power control register */ | |
1726 | + ldmea r0!,{r4} | |
1727 | + mcr p15, 0, r4, c15, c0, 0 @ Diagnostic control reg | |
1712 | 1728 | |
1713 | 1729 | /* |
1714 | 1730 | * Enabling MMU here. Page entry needs to be altered |