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Commit 0c69fb037a6bb1faf06ea776872da54a6705c154

Authored by Kim Phillips
Committed by Artem Bityutskiy
1 parent 44fe63fc0f
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

mtd: fsl_ifc_nand: use more portable i/o accessors 

in/out_be32 accessors are Power arch centric whereas
ioread/writebe32 are available in other arches.

Since the IFC device registers are annotated big endian in
fsl_ifc.h, the accessor annotations now match, resulting in the
pleasant side-effect of this patch silencing sparse endian
warnings such as the following:

drivers/mtd/nand/fsl_ifc_nand.c:179:19: warning: incorrect type in argument 1 (different base types)
drivers/mtd/nand/fsl_ifc_nand.c:179:19:    expected unsigned int volatile [noderef] [usertype] <asn:2>*addr
drivers/mtd/nand/fsl_ifc_nand.c:179:19:    got restricted __be32 [noderef] <asn:2>*<noident>

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>

Showing 1 changed file with 119 additions and 114 deletions Side-by-side Diff

drivers/mtd/nand/fsl_ifc_nand.c
Diff comments   View file @ 0c69fb0
... ... @@ -176,8 +176,8 @@
176 176  
177 177 ifc_nand_ctrl->page = page_addr;
178 178 /* Program ROW0/COL0 */
179   - out_be32(&ifc->ifc_nand.row0, page_addr);
180   - out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
  179 + iowrite32be(page_addr, &ifc->ifc_nand.row0);
  180 + iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
181 181  
182 182 buf_num = page_addr & priv->bufnum_mask;
183 183  
184 184  
185 185  
... ... @@ -239,18 +239,19 @@
239 239 int i;
240 240  
241 241 /* set the chip select for NAND Transaction */
242   - out_be32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
  242 + iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,
  243 + &ifc->ifc_nand.nand_csel);
243 244  
244 245 dev_vdbg(priv->dev,
245 246 "%s: fir0=%08x fcr0=%08x\n",
246 247 __func__,
247   - in_be32(&ifc->ifc_nand.nand_fir0),
248   - in_be32(&ifc->ifc_nand.nand_fcr0));
  248 + ioread32be(&ifc->ifc_nand.nand_fir0),
  249 + ioread32be(&ifc->ifc_nand.nand_fcr0));
249 250  
250 251 ctrl->nand_stat = 0;
251 252  
252 253 /* start read/write seq */
253   - out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
  254 + iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
254 255  
255 256 /* wait for command complete flag or timeout */
256 257 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
... ... @@ -273,7 +274,7 @@
273 274 int sector_end = sector + chip->ecc.steps - 1;
274 275  
275 276 for (i = sector / 4; i <= sector_end / 4; i++)
276   - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
  277 + eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);
277 278  
278 279 for (i = sector; i <= sector_end; i++) {
279 280 errors = check_read_ecc(mtd, ctrl, eccstat, i);
280 281  
281 282  
282 283  
283 284  
... ... @@ -313,31 +314,33 @@
313 314  
314 315 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
315 316 if (mtd->writesize > 512) {
316   - out_be32(&ifc->ifc_nand.nand_fir0,
317   - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
318   - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
319   - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
320   - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
321   - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
322   - out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
  317 + iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  318 + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  319 + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  320 + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  321 + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
  322 + &ifc->ifc_nand.nand_fir0);
  323 + iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
323 324  
324   - out_be32(&ifc->ifc_nand.nand_fcr0,
325   - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
326   - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
  325 + iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  326 + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
  327 + &ifc->ifc_nand.nand_fcr0);
327 328 } else {
328   - out_be32(&ifc->ifc_nand.nand_fir0,
329   - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
330   - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
331   - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
332   - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
333   - out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
  329 + iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  330 + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  331 + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  332 + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
  333 + &ifc->ifc_nand.nand_fir0);
  334 + iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
334 335  
335 336 if (oob)
336   - out_be32(&ifc->ifc_nand.nand_fcr0,
337   - NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
  337 + iowrite32be(NAND_CMD_READOOB <<
  338 + IFC_NAND_FCR0_CMD0_SHIFT,
  339 + &ifc->ifc_nand.nand_fcr0);
338 340 else
339   - out_be32(&ifc->ifc_nand.nand_fcr0,
340   - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
  341 + iowrite32be(NAND_CMD_READ0 <<
  342 + IFC_NAND_FCR0_CMD0_SHIFT,
  343 + &ifc->ifc_nand.nand_fcr0);
341 344 }
342 345 }
343 346  
... ... @@ -357,7 +360,7 @@
357 360 switch (command) {
358 361 /* READ0 read the entire buffer to use hardware ECC. */
359 362 case NAND_CMD_READ0:
360   - out_be32(&ifc->ifc_nand.nand_fbcr, 0);
  363 + iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
361 364 set_addr(mtd, 0, page_addr, 0);
362 365  
363 366 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
... ... @@ -372,7 +375,7 @@
372 375  
373 376 /* READOOB reads only the OOB because no ECC is performed. */
374 377 case NAND_CMD_READOOB:
375   - out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
  378 + iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
376 379 set_addr(mtd, column, page_addr, 1);
377 380  
378 381 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
379 382  
... ... @@ -388,19 +391,19 @@
388 391 if (command == NAND_CMD_PARAM)
389 392 timing = IFC_FIR_OP_RBCD;
390 393  
391   - out_be32(&ifc->ifc_nand.nand_fir0,
392   - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
393   - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
394   - (timing << IFC_NAND_FIR0_OP2_SHIFT));
395   - out_be32(&ifc->ifc_nand.nand_fcr0,
396   - command << IFC_NAND_FCR0_CMD0_SHIFT);
397   - out_be32(&ifc->ifc_nand.row3, column);
  394 + iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  395 + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  396 + (timing << IFC_NAND_FIR0_OP2_SHIFT),
  397 + &ifc->ifc_nand.nand_fir0);
  398 + iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,
  399 + &ifc->ifc_nand.nand_fcr0);
  400 + iowrite32be(column, &ifc->ifc_nand.row3);
398 401  
399 402 /*
400 403 * although currently it's 8 bytes for READID, we always read
401 404 * the maximum 256 bytes(for PARAM)
402 405 */
403   - out_be32(&ifc->ifc_nand.nand_fbcr, 256);
  406 + iowrite32be(256, &ifc->ifc_nand.nand_fbcr);
404 407 ifc_nand_ctrl->read_bytes = 256;
405 408  
406 409 set_addr(mtd, 0, 0, 0);
407 410  
408 411  
... ... @@ -415,16 +418,16 @@
415 418  
416 419 /* ERASE2 uses the block and page address from ERASE1 */
417 420 case NAND_CMD_ERASE2:
418   - out_be32(&ifc->ifc_nand.nand_fir0,
419   - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
420   - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
421   - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
  421 + iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  422 + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  423 + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
  424 + &ifc->ifc_nand.nand_fir0);
422 425  
423   - out_be32(&ifc->ifc_nand.nand_fcr0,
424   - (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
425   - (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
  426 + iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
  427 + (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
  428 + &ifc->ifc_nand.nand_fcr0);
426 429  
427   - out_be32(&ifc->ifc_nand.nand_fbcr, 0);
  430 + iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
428 431 ifc_nand_ctrl->read_bytes = 0;
429 432 fsl_ifc_run_command(mtd);
430 433 return;
431 434  
... ... @@ -440,26 +443,28 @@
440 443 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
441 444 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
442 445  
443   - out_be32(&ifc->ifc_nand.nand_fir0,
444   - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
445   - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
446   - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
447   - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
448   - (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
  446 + iowrite32be(
  447 + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  448 + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  449 + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  450 + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
  451 + (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT),
  452 + &ifc->ifc_nand.nand_fir0);
449 453 } else {
450 454 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
451 455 IFC_NAND_FCR0_CMD1_SHIFT) |
452 456 (NAND_CMD_SEQIN <<
453 457 IFC_NAND_FCR0_CMD2_SHIFT));
454 458  
455   - out_be32(&ifc->ifc_nand.nand_fir0,
456   - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
457   - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
458   - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
459   - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
460   - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
461   - out_be32(&ifc->ifc_nand.nand_fir1,
462   - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
  459 + iowrite32be(
  460 + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  461 + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
  462 + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  463 + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
  464 + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
  465 + &ifc->ifc_nand.nand_fir0);
  466 + iowrite32be(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT,
  467 + &ifc->ifc_nand.nand_fir1);
463 468  
464 469 if (column >= mtd->writesize)
465 470 nand_fcr0 |=
... ... @@ -474,7 +479,7 @@
474 479 column -= mtd->writesize;
475 480 ifc_nand_ctrl->oob = 1;
476 481 }
477   - out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
  482 + iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
478 483 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
479 484 return;
480 485 }
481 486  
... ... @@ -482,10 +487,11 @@
482 487 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
483 488 case NAND_CMD_PAGEPROG: {
484 489 if (ifc_nand_ctrl->oob) {
485   - out_be32(&ifc->ifc_nand.nand_fbcr,
486   - ifc_nand_ctrl->index - ifc_nand_ctrl->column);
  490 + iowrite32be(ifc_nand_ctrl->index -
  491 + ifc_nand_ctrl->column,
  492 + &ifc->ifc_nand.nand_fbcr);
487 493 } else {
488   - out_be32(&ifc->ifc_nand.nand_fbcr, 0);
  494 + iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
489 495 }
490 496  
491 497 fsl_ifc_run_command(mtd);
... ... @@ -493,12 +499,12 @@
493 499 }
494 500  
495 501 case NAND_CMD_STATUS:
496   - out_be32(&ifc->ifc_nand.nand_fir0,
497   - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
498   - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
499   - out_be32(&ifc->ifc_nand.nand_fcr0,
500   - NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
501   - out_be32(&ifc->ifc_nand.nand_fbcr, 1);
  502 + iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  503 + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
  504 + &ifc->ifc_nand.nand_fir0);
  505 + iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
  506 + &ifc->ifc_nand.nand_fcr0);
  507 + iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
502 508 set_addr(mtd, 0, 0, 0);
503 509 ifc_nand_ctrl->read_bytes = 1;
504 510  
... ... @@ -512,10 +518,10 @@
512 518 return;
513 519  
514 520 case NAND_CMD_RESET:
515   - out_be32(&ifc->ifc_nand.nand_fir0,
516   - IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
517   - out_be32(&ifc->ifc_nand.nand_fcr0,
518   - NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
  521 + iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
  522 + &ifc->ifc_nand.nand_fir0);
  523 + iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
  524 + &ifc->ifc_nand.nand_fcr0);
519 525 fsl_ifc_run_command(mtd);
520 526 return;
521 527  
522 528  
... ... @@ -639,18 +645,18 @@
639 645 u32 nand_fsr;
640 646  
641 647 /* Use READ_STATUS command, but wait for the device to be ready */
642   - out_be32(&ifc->ifc_nand.nand_fir0,
643   - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
644   - (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
645   - out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
646   - IFC_NAND_FCR0_CMD0_SHIFT);
647   - out_be32(&ifc->ifc_nand.nand_fbcr, 1);
  648 + iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  649 + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
  650 + &ifc->ifc_nand.nand_fir0);
  651 + iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
  652 + &ifc->ifc_nand.nand_fcr0);
  653 + iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
648 654 set_addr(mtd, 0, 0, 0);
649 655 ifc_nand_ctrl->read_bytes = 1;
650 656  
651 657 fsl_ifc_run_command(mtd);
652 658  
653   - nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
  659 + nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);
654 660  
655 661 /*
656 662 * The chip always seems to report that it is
657 663  
658 664  
659 665  
660 666  
661 667  
662 668  
... ... @@ -744,34 +750,34 @@
744 750 uint32_t cs = priv->bank;
745 751  
746 752 /* Save CSOR and CSOR_ext */
747   - csor = in_be32(&ifc->csor_cs[cs].csor);
748   - csor_ext = in_be32(&ifc->csor_cs[cs].csor_ext);
  753 + csor = ioread32be(&ifc->csor_cs[cs].csor);
  754 + csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);
749 755  
750 756 /* chage PageSize 8K and SpareSize 1K*/
751 757 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
752   - out_be32(&ifc->csor_cs[cs].csor, csor_8k);
753   - out_be32(&ifc->csor_cs[cs].csor_ext, 0x0000400);
  758 + iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);
  759 + iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);
754 760  
755 761 /* READID */
756   - out_be32(&ifc->ifc_nand.nand_fir0,
757   - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
758   - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
759   - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
760   - out_be32(&ifc->ifc_nand.nand_fcr0,
761   - NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
762   - out_be32(&ifc->ifc_nand.row3, 0x0);
  762 + iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  763 + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  764 + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
  765 + &ifc->ifc_nand.nand_fir0);
  766 + iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
  767 + &ifc->ifc_nand.nand_fcr0);
  768 + iowrite32be(0x0, &ifc->ifc_nand.row3);
763 769  
764   - out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
  770 + iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);
765 771  
766 772 /* Program ROW0/COL0 */
767   - out_be32(&ifc->ifc_nand.row0, 0x0);
768   - out_be32(&ifc->ifc_nand.col0, 0x0);
  773 + iowrite32be(0x0, &ifc->ifc_nand.row0);
  774 + iowrite32be(0x0, &ifc->ifc_nand.col0);
769 775  
770 776 /* set the chip select for NAND Transaction */
771   - out_be32(&ifc->ifc_nand.nand_csel, cs << IFC_NAND_CSEL_SHIFT);
  777 + iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
772 778  
773 779 /* start read seq */
774   - out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
  780 + iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
775 781  
776 782 /* wait for command complete flag or timeout */
777 783 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
... ... @@ -781,8 +787,8 @@
781 787 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
782 788  
783 789 /* Restore CSOR and CSOR_ext */
784   - out_be32(&ifc->csor_cs[cs].csor, csor);
785   - out_be32(&ifc->csor_cs[cs].csor_ext, csor_ext);
  790 + iowrite32be(csor, &ifc->csor_cs[cs].csor);
  791 + iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);
786 792 }
787 793  
788 794 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
... ... @@ -799,7 +805,7 @@
799 805  
800 806 /* fill in nand_chip structure */
801 807 /* set up function call table */
802   - if ((in_be32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
  808 + if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
803 809 chip->read_byte = fsl_ifc_read_byte16;
804 810 else
805 811 chip->read_byte = fsl_ifc_read_byte;
806 812  
... ... @@ -813,13 +819,13 @@
813 819 chip->bbt_td = &bbt_main_descr;
814 820 chip->bbt_md = &bbt_mirror_descr;
815 821  
816   - out_be32(&ifc->ifc_nand.ncfgr, 0x0);
  822 + iowrite32be(0x0, &ifc->ifc_nand.ncfgr);
817 823  
818 824 /* set up nand options */
819 825 chip->bbt_options = NAND_BBT_USE_FLASH;
820 826  
821 827  
822   - if (in_be32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
  828 + if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
823 829 chip->read_byte = fsl_ifc_read_byte16;
824 830 chip->options |= NAND_BUSWIDTH_16;
825 831 } else {
... ... @@ -832,7 +838,7 @@
832 838 chip->ecc.read_page = fsl_ifc_read_page;
833 839 chip->ecc.write_page = fsl_ifc_write_page;
834 840  
835   - csor = in_be32(&ifc->csor_cs[priv->bank].csor);
  841 + csor = ioread32be(&ifc->csor_cs[priv->bank].csor);
836 842  
837 843 /* Hardware generates ECC per 512 Bytes */
838 844 chip->ecc.size = 512;
... ... @@ -884,7 +890,7 @@
884 890 chip->ecc.mode = NAND_ECC_SOFT;
885 891 }
886 892  
887   - ver = in_be32(&ifc->ifc_rev);
  893 + ver = ioread32be(&ifc->ifc_rev);
888 894 if (ver == FSL_IFC_V1_1_0)
889 895 fsl_ifc_sram_init(priv);
890 896  
... ... @@ -910,7 +916,7 @@
910 916 static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
911 917 phys_addr_t addr)
912 918 {
913   - u32 cspr = in_be32(&ifc->cspr_cs[bank].cspr);
  919 + u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);
914 920  
915 921 if (!(cspr & CSPR_V))
916 922 return 0;
917 923  
... ... @@ -997,17 +1003,16 @@
997 1003  
998 1004 dev_set_drvdata(priv->dev, priv);
999 1005  
1000   - out_be32(&ifc->ifc_nand.nand_evter_en,
1001   - IFC_NAND_EVTER_EN_OPC_EN |
1002   - IFC_NAND_EVTER_EN_FTOER_EN |
1003   - IFC_NAND_EVTER_EN_WPER_EN);
  1006 + iowrite32be(IFC_NAND_EVTER_EN_OPC_EN |
  1007 + IFC_NAND_EVTER_EN_FTOER_EN |
  1008 + IFC_NAND_EVTER_EN_WPER_EN,
  1009 + &ifc->ifc_nand.nand_evter_en);
1004 1010  
1005 1011 /* enable NAND Machine Interrupts */
1006   - out_be32(&ifc->ifc_nand.nand_evter_intr_en,
1007   - IFC_NAND_EVTER_INTR_OPCIR_EN |
1008   - IFC_NAND_EVTER_INTR_FTOERIR_EN |
1009   - IFC_NAND_EVTER_INTR_WPERIR_EN);
1010   -
  1012 + iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN |
  1013 + IFC_NAND_EVTER_INTR_FTOERIR_EN |
  1014 + IFC_NAND_EVTER_INTR_WPERIR_EN,
  1015 + &ifc->ifc_nand.nand_evter_intr_en);
1011 1016 priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
1012 1017 if (!priv->mtd.name) {
1013 1018 ret = -ENOMEM;