PCI: pciehp: change wait time for valid configuration access

Naoki Yanagimoto reported that configuration read on some hot-added PCIe device returns invalid value. This patch fixes this problem. According to the PCIe spec, software must wait for at least 1 second to judge if the hot-added device is broken after Data Link Layer State Changed Event. This patch changes pciehp driver to wait for 1 second after the Data Link Layer State Changed Event is detected before initiating a configuration access instead of 100 ms. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Tested-by: Naoki Yanagimoto <yanagimoto@np.css.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

PCI: pciehp: change wait time for valid configuration access
Naoki Yanagimoto reported that configuration read on some hot-added PCIe device returns invalid value. This patch fixes this problem. According to the PCIe spec, software must wait for at least 1 second to judge if the hot-added device is broken after Data Link Layer State Changed Event. This patch changes pciehp driver to wait for 1 second after the Data Link Layer State Changed Event is detected before initiating a configuration access instead of 100 ms. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Tested-by: Naoki Yanagimoto <yanagimoto@np.css.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Kenji Kaneshige · Jesse Barnes
1 parent 9b373ed18f
Showing 2 changed files with 5 additions and 9 deletions Side-by-side Diff
drivers/pci/hotplug/pciehp_ctrl.c
drivers/pci/hotplug/pciehp_hpc.c
@@ -213,6 +213,9 @@
 		goto err_exit;
 	}
  
+	/* Wait for 1 second after checking link training status */
+	msleep(1000);
+
 	/* Check for a power fault */
 	if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) {
 		ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot));
@@ -275,16 +275,9 @@
          * hot-plug capable downstream port. But old controller might
          * not implement it. In this case, we wait for 1000 ms.
          */
-        if (ctrl->link_active_reporting){
-                /* Wait for Data Link Layer Link Active bit to be set */
+        if (ctrl->link_active_reporting)
                 pcie_wait_link_active(ctrl);
-                /*
-                 * We must wait for 100 ms after the Data Link Layer
-                 * Link Active bit reads 1b before initiating a
-                 * configuration access to the hot added device.
-                 */
-                msleep(100);
-        } else
+        else
                 msleep(1000);
  
 	retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
...	...	@@ -213,6 +213,9 @@
213	213	goto err_exit;
214	214	}
215	215
	216	+ /* Wait for 1 second after checking link training status */
	217	+ msleep(1000);
	218	+
216	219	/* Check for a power fault */
217	220	if (ctrl->power_fault_detected \|\| pciehp_query_power_fault(p_slot)) {
218	221	ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot));
...	...	@@ -275,16 +275,9 @@
275	275	* hot-plug capable downstream port. But old controller might
276	276	* not implement it. In this case, we wait for 1000 ms.
277	277	*/
278		- if (ctrl->link_active_reporting){
279		- /* Wait for Data Link Layer Link Active bit to be set */
	278	+ if (ctrl->link_active_reporting)
280	279	pcie_wait_link_active(ctrl);
281		- /*
282		- * We must wait for 100 ms after the Data Link Layer
283		- * Link Active bit reads 1b before initiating a
284		- * configuration access to the hot added device.
285		- */
286		- msleep(100);
287		- } else
	280	+ else
288	281	msleep(1000);
289	282
290	283	retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);