Commit 0cc8674f2be3078fb586add1900c7835c977f384
Committed by
Jeff Garzik
1 parent
683349a3fa
Exists in
master
and in
7 other branches
AT91: MACB support
The Atmel MACB Ethernet peripheral is also integrated in the AT91SAM9260 and AT91SAM9263 processors. The differences from the AVR32 version are: * Single peripheral clock. * MII/RMII selection bit is inverted. * Clock enable bit. Original patch from Patrice Vilchez. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Showing 3 changed files with 31 additions and 4 deletions Side-by-side Diff
drivers/net/Kconfig
... | ... | @@ -190,7 +190,7 @@ |
190 | 190 | |
191 | 191 | config MACB |
192 | 192 | tristate "Atmel MACB support" |
193 | - depends on NET_ETHERNET && AVR32 | |
193 | + depends on NET_ETHERNET && (AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263) | |
194 | 194 | select MII |
195 | 195 | help |
196 | 196 | The Atmel MACB ethernet interface is found on many AT32 and AT91 |
drivers/net/macb.c
... | ... | @@ -1046,6 +1046,14 @@ |
1046 | 1046 | |
1047 | 1047 | spin_lock_init(&bp->lock); |
1048 | 1048 | |
1049 | +#if defined(CONFIG_ARCH_AT91) | |
1050 | + bp->pclk = clk_get(&pdev->dev, "macb_clk"); | |
1051 | + if (IS_ERR(bp->pclk)) { | |
1052 | + dev_err(&pdev->dev, "failed to get macb_clk\n"); | |
1053 | + goto err_out_free_dev; | |
1054 | + } | |
1055 | + clk_enable(bp->pclk); | |
1056 | +#else | |
1049 | 1057 | bp->pclk = clk_get(&pdev->dev, "pclk"); |
1050 | 1058 | if (IS_ERR(bp->pclk)) { |
1051 | 1059 | dev_err(&pdev->dev, "failed to get pclk\n"); |
... | ... | @@ -1059,6 +1067,7 @@ |
1059 | 1067 | |
1060 | 1068 | clk_enable(bp->pclk); |
1061 | 1069 | clk_enable(bp->hclk); |
1070 | +#endif | |
1062 | 1071 | |
1063 | 1072 | bp->regs = ioremap(regs->start, regs->end - regs->start + 1); |
1064 | 1073 | if (!bp->regs) { |
1065 | 1074 | |
1066 | 1075 | |
1067 | 1076 | |
... | ... | @@ -1119,9 +1128,17 @@ |
1119 | 1128 | |
1120 | 1129 | pdata = pdev->dev.platform_data; |
1121 | 1130 | if (pdata && pdata->is_rmii) |
1131 | +#if defined(CONFIG_ARCH_AT91) | |
1132 | + macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) ); | |
1133 | +#else | |
1122 | 1134 | macb_writel(bp, USRIO, 0); |
1135 | +#endif | |
1123 | 1136 | else |
1137 | +#if defined(CONFIG_ARCH_AT91) | |
1138 | + macb_writel(bp, USRIO, MACB_BIT(CLKEN)); | |
1139 | +#else | |
1124 | 1140 | macb_writel(bp, USRIO, MACB_BIT(MII)); |
1141 | +#endif | |
1125 | 1142 | |
1126 | 1143 | bp->tx_pending = DEF_TX_RING_PENDING; |
1127 | 1144 | |
1128 | 1145 | |
1129 | 1146 | |
... | ... | @@ -1148,9 +1165,11 @@ |
1148 | 1165 | err_out_iounmap: |
1149 | 1166 | iounmap(bp->regs); |
1150 | 1167 | err_out_disable_clocks: |
1168 | +#ifndef CONFIG_ARCH_AT91 | |
1151 | 1169 | clk_disable(bp->hclk); |
1152 | - clk_disable(bp->pclk); | |
1153 | 1170 | clk_put(bp->hclk); |
1171 | +#endif | |
1172 | + clk_disable(bp->pclk); | |
1154 | 1173 | err_out_put_pclk: |
1155 | 1174 | clk_put(bp->pclk); |
1156 | 1175 | err_out_free_dev: |
1157 | 1176 | |
1158 | 1177 | |
... | ... | @@ -1173,9 +1192,11 @@ |
1173 | 1192 | unregister_netdev(dev); |
1174 | 1193 | free_irq(dev->irq, dev); |
1175 | 1194 | iounmap(bp->regs); |
1195 | +#ifndef CONFIG_ARCH_AT91 | |
1176 | 1196 | clk_disable(bp->hclk); |
1177 | - clk_disable(bp->pclk); | |
1178 | 1197 | clk_put(bp->hclk); |
1198 | +#endif | |
1199 | + clk_disable(bp->pclk); | |
1179 | 1200 | clk_put(bp->pclk); |
1180 | 1201 | free_netdev(dev); |
1181 | 1202 | platform_set_drvdata(pdev, NULL); |
drivers/net/macb.h
... | ... | @@ -200,7 +200,7 @@ |
200 | 200 | #define MACB_SOF_OFFSET 30 |
201 | 201 | #define MACB_SOF_SIZE 2 |
202 | 202 | |
203 | -/* Bitfields in USRIO */ | |
203 | +/* Bitfields in USRIO (AVR32) */ | |
204 | 204 | #define MACB_MII_OFFSET 0 |
205 | 205 | #define MACB_MII_SIZE 1 |
206 | 206 | #define MACB_EAM_OFFSET 1 |
... | ... | @@ -209,6 +209,12 @@ |
209 | 209 | #define MACB_TX_PAUSE_SIZE 1 |
210 | 210 | #define MACB_TX_PAUSE_ZERO_OFFSET 3 |
211 | 211 | #define MACB_TX_PAUSE_ZERO_SIZE 1 |
212 | + | |
213 | +/* Bitfields in USRIO (AT91) */ | |
214 | +#define MACB_RMII_OFFSET 0 | |
215 | +#define MACB_RMII_SIZE 1 | |
216 | +#define MACB_CLKEN_OFFSET 1 | |
217 | +#define MACB_CLKEN_SIZE 1 | |
212 | 218 | |
213 | 219 | /* Bitfields in WOL */ |
214 | 220 | #define MACB_IP_OFFSET 0 |