pinctrl: SPEAr1310: add register entries for enabling pad direction

Pad direction must also be updated for SPEAr1310, while setting pads values. This patch adds support for that. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl: SPEAr1310: add register entries for enabling pad direction
Pad direction must also be updated for SPEAr1310, while setting pads values. This patch adds support for that. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Shiraz Hashim · Linus Walleij
1 parent f7c5b3d574
Showing 1 changed file with 266 additions and 0 deletions Side-by-side Diff
drivers/pinctrl/spear/pinctrl-spear1310.c
@@ -164,6 +164,10 @@
 	#define PMX_SSP0_CS0_MASK			(1 << 29)
 	#define PMX_SSP0_CS1_2_MASK			(1 << 30)
  
+#define PAD_DIRECTION_SEL_0				0x65C
+#define PAD_DIRECTION_SEL_1				0x660
+#define PAD_DIRECTION_SEL_2				0x664
+
 /* combined macros */
 #define PMX_GMII_MASK		(PMX_GMIICLK_MASK |			\
 				PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK |	\
@@ -237,6 +241,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_I2C0_MASK,
 		.val = PMX_I2C0_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_I2C0_MASK,
+		.val = PMX_I2C0_MASK,
 	},
 };
  
@@ -269,6 +277,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_SSP0_MASK,
 		.val = PMX_SSP0_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_SSP0_MASK,
+		.val = PMX_SSP0_MASK,
 	},
 };
  
@@ -294,6 +306,10 @@
 		.reg = PAD_FUNCTION_EN_2,
 		.mask = PMX_SSP0_CS0_MASK,
 		.val = PMX_SSP0_CS0_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_SSP0_CS0_MASK,
+		.val = PMX_SSP0_CS0_MASK,
 	},
 };
  
@@ -319,6 +335,10 @@
 		.reg = PAD_FUNCTION_EN_2,
 		.mask = PMX_SSP0_CS1_2_MASK,
 		.val = PMX_SSP0_CS1_2_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_SSP0_CS1_2_MASK,
+		.val = PMX_SSP0_CS1_2_MASK,
 	},
 };
  
@@ -352,6 +372,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_I2S0_MASK,
 		.val = PMX_I2S0_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_I2S0_MASK,
+		.val = PMX_I2S0_MASK,
 	},
 };
  
@@ -384,6 +408,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_I2S1_MASK,
 		.val = PMX_I2S1_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_I2S1_MASK,
+		.val = PMX_I2S1_MASK,
 	},
 };
  
@@ -418,6 +446,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_CLCD1_MASK,
 		.val = PMX_CLCD1_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_CLCD1_MASK,
+		.val = PMX_CLCD1_MASK,
 	},
 };
  
@@ -443,6 +475,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_CLCD2_MASK,
 		.val = PMX_CLCD2_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_CLCD2_MASK,
+		.val = PMX_CLCD2_MASK,
 	},
 };
  
@@ -479,6 +515,14 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_EGPIO_1_GRP_MASK,
 		.val = PMX_EGPIO_1_GRP_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_EGPIO_0_GRP_MASK,
+		.val = PMX_EGPIO_0_GRP_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_EGPIO_1_GRP_MASK,
+		.val = PMX_EGPIO_1_GRP_MASK,
 	},
 };
  
@@ -511,6 +555,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_SMI_MASK,
 		.val = PMX_SMI_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_SMI_MASK,
+		.val = PMX_SMI_MASK,
 	},
 };
  
@@ -539,6 +587,14 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
 		.val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_SMI_MASK,
+		.val = PMX_SMI_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+		.val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
 	},
 };
  
@@ -573,6 +629,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_GMII_MASK,
 		.val = PMX_GMII_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_GMII_MASK,
+		.val = PMX_GMII_MASK,
 	},
 };
  
@@ -615,6 +675,18 @@
 		.reg = PAD_FUNCTION_EN_2,
 		.mask = PMX_RGMII_REG2_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_RGMII_REG0_MASK,
+		.val = PMX_RGMII_REG0_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_RGMII_REG1_MASK,
+		.val = PMX_RGMII_REG1_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_RGMII_REG2_MASK,
+		.val = PMX_RGMII_REG2_MASK,
 	},
 };
  
@@ -649,6 +721,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_SMII_0_1_2_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_SMII_0_1_2_MASK,
+		.val = PMX_SMII_0_1_2_MASK,
 	},
 };
  
@@ -681,6 +757,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_NFCE2_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_NFCE2_MASK,
+		.val = PMX_NFCE2_MASK,
 	},
 };
  
@@ -721,6 +801,14 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_NAND8BIT_1_MASK,
 		.val = PMX_NAND8BIT_1_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_NAND8BIT_0_MASK,
+		.val = PMX_NAND8BIT_0_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_NAND8BIT_1_MASK,
+		.val = PMX_NAND8BIT_1_MASK,
 	},
 };
  
@@ -747,6 +835,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_NAND16BIT_1_MASK,
 		.val = PMX_NAND16BIT_1_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_NAND16BIT_1_MASK,
+		.val = PMX_NAND16BIT_1_MASK,
 	},
 };
  
@@ -772,6 +864,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_NAND_4CHIPS_MASK,
 		.val = PMX_NAND_4CHIPS_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_NAND_4CHIPS_MASK,
+		.val = PMX_NAND_4CHIPS_MASK,
 	},
 };
  
@@ -833,6 +929,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_KBD_ROWCOL68_MASK,
 		.val = PMX_KBD_ROWCOL68_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_KBD_ROWCOL68_MASK,
+		.val = PMX_KBD_ROWCOL68_MASK,
 	},
 };
  
@@ -866,6 +966,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_UART0_MASK,
 		.val = PMX_UART0_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_UART0_MASK,
+		.val = PMX_UART0_MASK,
 	},
 };
  
@@ -891,6 +995,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_UART0_MODEM_MASK,
 		.val = PMX_UART0_MODEM_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_UART0_MODEM_MASK,
+		.val = PMX_UART0_MODEM_MASK,
 	},
 };
  
@@ -923,6 +1031,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_GPT0_TMR0_MASK,
 		.val = PMX_GPT0_TMR0_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_GPT0_TMR0_MASK,
+		.val = PMX_GPT0_TMR0_MASK,
 	},
 };
  
@@ -948,6 +1060,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_GPT0_TMR1_MASK,
 		.val = PMX_GPT0_TMR1_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_GPT0_TMR1_MASK,
+		.val = PMX_GPT0_TMR1_MASK,
 	},
 };
  
@@ -980,6 +1096,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_GPT1_TMR0_MASK,
 		.val = PMX_GPT1_TMR0_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_GPT1_TMR0_MASK,
+		.val = PMX_GPT1_TMR0_MASK,
 	},
 };
  
@@ -1005,6 +1125,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_GPT1_TMR1_MASK,
 		.val = PMX_GPT1_TMR1_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_GPT1_TMR1_MASK,
+		.val = PMX_GPT1_TMR1_MASK,
 	},
 };
  
@@ -1049,6 +1173,20 @@
 		.reg = PAD_FUNCTION_EN_2,			\
 		.mask = PMX_MCIFALL_2_MASK,			\
 		.val = PMX_MCIFALL_2_MASK,			\
+	}, {							\
+		.reg = PAD_DIRECTION_SEL_0,			\
+		.mask = PMX_MCI_DATA8_15_MASK,			\
+		.val = PMX_MCI_DATA8_15_MASK,			\
+	}, {							\
+		.reg = PAD_DIRECTION_SEL_1,			\
+		.mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK |	\
+			PMX_NFWPRT2_MASK,			\
+		.val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK |  \
+			PMX_NFWPRT2_MASK,			\
+	}, {							\
+		.reg = PAD_DIRECTION_SEL_2,			\
+		.mask = PMX_MCIFALL_2_MASK,			\
+		.val = PMX_MCIFALL_2_MASK,			\
 	}
  
 /* sdhci device */
@@ -1154,6 +1292,10 @@
 		.reg = PAD_FUNCTION_EN_2,
 		.mask = PMX_TOUCH_XY_MASK,
 		.val = PMX_TOUCH_XY_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_TOUCH_XY_MASK,
+		.val = PMX_TOUCH_XY_MASK,
 	},
 };
  
@@ -1187,6 +1329,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_I2C0_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_I2C0_MASK,
+		.val = PMX_I2C0_MASK,
 	},
 };
  
@@ -1213,6 +1359,12 @@
 		.mask = PMX_MCIDATA1_MASK |
 			PMX_MCIDATA2_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_MCIDATA1_MASK |
+			PMX_MCIDATA2_MASK,
+		.val = PMX_MCIDATA1_MASK |
+			PMX_MCIDATA2_MASK,
 	},
 };
  
@@ -1246,6 +1398,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_I2S0_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_I2S0_MASK,
+		.val = PMX_I2S0_MASK,
 	},
 };
  
@@ -1278,6 +1434,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
+		.val = PMX_I2S0_MASK | PMX_CLCD1_MASK,
 	},
 };
  
@@ -1310,6 +1470,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_CLCD1_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_CLCD1_MASK,
+		.val = PMX_CLCD1_MASK,
 	},
 };
  
@@ -1344,6 +1508,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_CLCD1_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_CLCD1_MASK,
+		.val = PMX_CLCD1_MASK,
 	},
 };
  
@@ -1376,6 +1544,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_CLCD1_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_CLCD1_MASK,
+		.val = PMX_CLCD1_MASK,
 	},
 };
  
@@ -1409,6 +1581,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
+		.val = PMX_CLCD1_MASK | PMX_SMI_MASK,
 	},
 };
  
@@ -1435,6 +1611,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
+		.val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
 	},
 };
  
@@ -1469,6 +1649,10 @@
 		.reg = PAD_FUNCTION_EN_0,
 		.mask = PMX_SMI_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_SMI_MASK,
+		.val = PMX_SMI_MASK,
 	},
 };
  
@@ -1499,6 +1683,14 @@
 		.reg = PAD_FUNCTION_EN_2,
 		.mask = PMX_MCIDATA5_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_MCIDATA4_MASK,
+		.val = PMX_MCIDATA4_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_MCIDATA5_MASK,
+		.val = PMX_MCIDATA5_MASK,
 	},
 };
  
@@ -1526,6 +1718,12 @@
 		.mask = PMX_MCIDATA6_MASK |
 			PMX_MCIDATA7_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_MCIDATA6_MASK |
+			PMX_MCIDATA7_MASK,
+		.val = PMX_MCIDATA6_MASK |
+			PMX_MCIDATA7_MASK,
 	},
 };
  
@@ -1560,6 +1758,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_KBD_ROWCOL25_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_KBD_ROWCOL25_MASK,
+		.val = PMX_KBD_ROWCOL25_MASK,
 	},
 };
  
@@ -1587,6 +1789,12 @@
 		.mask = PMX_MCIIORDRE_MASK |
 			PMX_MCIIOWRWE_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_MCIIORDRE_MASK |
+			PMX_MCIIOWRWE_MASK,
+		.val = PMX_MCIIORDRE_MASK |
+			PMX_MCIIOWRWE_MASK,
 	},
 };
  
@@ -1613,6 +1821,12 @@
 		.mask = PMX_MCIRESETCF_MASK |
 			PMX_MCICS0CE_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_MCIRESETCF_MASK |
+			PMX_MCICS0CE_MASK,
+		.val = PMX_MCIRESETCF_MASK |
+			PMX_MCICS0CE_MASK,
 	},
 };
  
@@ -1651,6 +1865,14 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_NFRSTPWDWN3_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_NFRSTPWDWN2_MASK,
+		.val = PMX_NFRSTPWDWN2_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_NFRSTPWDWN3_MASK,
+		.val = PMX_NFRSTPWDWN3_MASK,
 	},
 };
  
@@ -1677,6 +1899,10 @@
 		.reg = PAD_FUNCTION_EN_2,
 		.mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
+		.val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
 	},
 };
  
@@ -1711,6 +1937,10 @@
 		.reg = PAD_FUNCTION_EN_2,
 		.mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
+		.val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
 	},
 };
  
@@ -1737,6 +1967,10 @@
 		.reg = PAD_FUNCTION_EN_1,
 		.mask = PMX_KBD_ROWCOL25_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_KBD_ROWCOL25_MASK,
+		.val = PMX_KBD_ROWCOL25_MASK,
 	},
 };
  
@@ -1782,6 +2016,18 @@
 		.reg = PAD_FUNCTION_EN_2,
 		.mask = PMX_PCI_REG2_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_0,
+		.mask = PMX_MCI_DATA8_15_MASK,
+		.val = PMX_MCI_DATA8_15_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_PCI_REG1_MASK,
+		.val = PMX_PCI_REG1_MASK,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_PCI_REG2_MASK,
+		.val = PMX_PCI_REG2_MASK,
 	},
 };
  
@@ -1964,6 +2210,14 @@
 			PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
 			PMX_NFCE2_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_1,
+		.mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
+			PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
+			PMX_NFCE2_MASK,
+		.val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
+			PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
+			PMX_NFCE2_MASK,
 	},
 };
  
@@ -1990,6 +2244,12 @@
 		.mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
 			PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
+			PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
+		.val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
+			PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
 	},
 };
  
@@ -2024,6 +2284,12 @@
 		.mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
 			| PMX_MCILEDS_MASK,
 		.val = 0,
+	}, {
+		.reg = PAD_DIRECTION_SEL_2,
+		.mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
+			| PMX_MCILEDS_MASK,
+		.val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
+			| PMX_MCILEDS_MASK,
 	},
 };
...	...	@@ -164,6 +164,10 @@
164	164	#define PMX_SSP0_CS0_MASK (1 << 29)
165	165	#define PMX_SSP0_CS1_2_MASK (1 << 30)
166	166
	167	+#define PAD_DIRECTION_SEL_0 0x65C
	168	+#define PAD_DIRECTION_SEL_1 0x660
	169	+#define PAD_DIRECTION_SEL_2 0x664
	170	+
167	171	/* combined macros */
168	172	#define PMX_GMII_MASK (PMX_GMIICLK_MASK \| \
169	173	PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK \| \
...	...	@@ -237,6 +241,10 @@
237	241	.reg = PAD_FUNCTION_EN_0,
238	242	.mask = PMX_I2C0_MASK,
239	243	.val = PMX_I2C0_MASK,
	244	+ }, {
	245	+ .reg = PAD_DIRECTION_SEL_0,
	246	+ .mask = PMX_I2C0_MASK,
	247	+ .val = PMX_I2C0_MASK,
240	248	},
241	249	};
242	250
...	...	@@ -269,6 +277,10 @@
269	277	.reg = PAD_FUNCTION_EN_0,
270	278	.mask = PMX_SSP0_MASK,
271	279	.val = PMX_SSP0_MASK,
	280	+ }, {
	281	+ .reg = PAD_DIRECTION_SEL_0,
	282	+ .mask = PMX_SSP0_MASK,
	283	+ .val = PMX_SSP0_MASK,
272	284	},
273	285	};
274	286
...	...	@@ -294,6 +306,10 @@
294	306	.reg = PAD_FUNCTION_EN_2,
295	307	.mask = PMX_SSP0_CS0_MASK,
296	308	.val = PMX_SSP0_CS0_MASK,
	309	+ }, {
	310	+ .reg = PAD_DIRECTION_SEL_2,
	311	+ .mask = PMX_SSP0_CS0_MASK,
	312	+ .val = PMX_SSP0_CS0_MASK,
297	313	},
298	314	};
299	315
...	...	@@ -319,6 +335,10 @@
319	335	.reg = PAD_FUNCTION_EN_2,
320	336	.mask = PMX_SSP0_CS1_2_MASK,
321	337	.val = PMX_SSP0_CS1_2_MASK,
	338	+ }, {
	339	+ .reg = PAD_DIRECTION_SEL_2,
	340	+ .mask = PMX_SSP0_CS1_2_MASK,
	341	+ .val = PMX_SSP0_CS1_2_MASK,
322	342	},
323	343	};
324	344
...	...	@@ -352,6 +372,10 @@
352	372	.reg = PAD_FUNCTION_EN_0,
353	373	.mask = PMX_I2S0_MASK,
354	374	.val = PMX_I2S0_MASK,
	375	+ }, {
	376	+ .reg = PAD_DIRECTION_SEL_0,
	377	+ .mask = PMX_I2S0_MASK,
	378	+ .val = PMX_I2S0_MASK,
355	379	},
356	380	};
357	381
...	...	@@ -384,6 +408,10 @@
384	408	.reg = PAD_FUNCTION_EN_1,
385	409	.mask = PMX_I2S1_MASK,
386	410	.val = PMX_I2S1_MASK,
	411	+ }, {
	412	+ .reg = PAD_DIRECTION_SEL_1,
	413	+ .mask = PMX_I2S1_MASK,
	414	+ .val = PMX_I2S1_MASK,
387	415	},
388	416	};
389	417
...	...	@@ -418,6 +446,10 @@
418	446	.reg = PAD_FUNCTION_EN_0,
419	447	.mask = PMX_CLCD1_MASK,
420	448	.val = PMX_CLCD1_MASK,
	449	+ }, {
	450	+ .reg = PAD_DIRECTION_SEL_0,
	451	+ .mask = PMX_CLCD1_MASK,
	452	+ .val = PMX_CLCD1_MASK,
421	453	},
422	454	};
423	455
...	...	@@ -443,6 +475,10 @@
443	475	.reg = PAD_FUNCTION_EN_1,
444	476	.mask = PMX_CLCD2_MASK,
445	477	.val = PMX_CLCD2_MASK,
	478	+ }, {
	479	+ .reg = PAD_DIRECTION_SEL_1,
	480	+ .mask = PMX_CLCD2_MASK,
	481	+ .val = PMX_CLCD2_MASK,
446	482	},
447	483	};
448	484
...	...	@@ -479,6 +515,14 @@
479	515	.reg = PAD_FUNCTION_EN_1,
480	516	.mask = PMX_EGPIO_1_GRP_MASK,
481	517	.val = PMX_EGPIO_1_GRP_MASK,
	518	+ }, {
	519	+ .reg = PAD_DIRECTION_SEL_0,
	520	+ .mask = PMX_EGPIO_0_GRP_MASK,
	521	+ .val = PMX_EGPIO_0_GRP_MASK,
	522	+ }, {
	523	+ .reg = PAD_DIRECTION_SEL_1,
	524	+ .mask = PMX_EGPIO_1_GRP_MASK,
	525	+ .val = PMX_EGPIO_1_GRP_MASK,
482	526	},
483	527	};
484	528
...	...	@@ -511,6 +555,10 @@
511	555	.reg = PAD_FUNCTION_EN_0,
512	556	.mask = PMX_SMI_MASK,
513	557	.val = PMX_SMI_MASK,
	558	+ }, {
	559	+ .reg = PAD_DIRECTION_SEL_0,
	560	+ .mask = PMX_SMI_MASK,
	561	+ .val = PMX_SMI_MASK,
514	562	},
515	563	};
516	564
...	...	@@ -539,6 +587,14 @@
539	587	.reg = PAD_FUNCTION_EN_1,
540	588	.mask = PMX_SMINCS2_MASK \| PMX_SMINCS3_MASK,
541	589	.val = PMX_SMINCS2_MASK \| PMX_SMINCS3_MASK,
	590	+ }, {
	591	+ .reg = PAD_DIRECTION_SEL_0,
	592	+ .mask = PMX_SMI_MASK,
	593	+ .val = PMX_SMI_MASK,
	594	+ }, {
	595	+ .reg = PAD_DIRECTION_SEL_1,
	596	+ .mask = PMX_SMINCS2_MASK \| PMX_SMINCS3_MASK,
	597	+ .val = PMX_SMINCS2_MASK \| PMX_SMINCS3_MASK,
542	598	},
543	599	};
544	600
...	...	@@ -573,6 +629,10 @@
573	629	.reg = PAD_FUNCTION_EN_0,
574	630	.mask = PMX_GMII_MASK,
575	631	.val = PMX_GMII_MASK,
	632	+ }, {
	633	+ .reg = PAD_DIRECTION_SEL_0,
	634	+ .mask = PMX_GMII_MASK,
	635	+ .val = PMX_GMII_MASK,
576	636	},
577	637	};
578	638
...	...	@@ -615,6 +675,18 @@
615	675	.reg = PAD_FUNCTION_EN_2,
616	676	.mask = PMX_RGMII_REG2_MASK,
617	677	.val = 0,
	678	+ }, {
	679	+ .reg = PAD_DIRECTION_SEL_0,
	680	+ .mask = PMX_RGMII_REG0_MASK,
	681	+ .val = PMX_RGMII_REG0_MASK,
	682	+ }, {
	683	+ .reg = PAD_DIRECTION_SEL_1,
	684	+ .mask = PMX_RGMII_REG1_MASK,
	685	+ .val = PMX_RGMII_REG1_MASK,
	686	+ }, {
	687	+ .reg = PAD_DIRECTION_SEL_2,
	688	+ .mask = PMX_RGMII_REG2_MASK,
	689	+ .val = PMX_RGMII_REG2_MASK,
618	690	},
619	691	};
620	692
...	...	@@ -649,6 +721,10 @@
649	721	.reg = PAD_FUNCTION_EN_1,
650	722	.mask = PMX_SMII_0_1_2_MASK,
651	723	.val = 0,
	724	+ }, {
	725	+ .reg = PAD_DIRECTION_SEL_1,
	726	+ .mask = PMX_SMII_0_1_2_MASK,
	727	+ .val = PMX_SMII_0_1_2_MASK,
652	728	},
653	729	};
654	730
...	...	@@ -681,6 +757,10 @@
681	757	.reg = PAD_FUNCTION_EN_1,
682	758	.mask = PMX_NFCE2_MASK,
683	759	.val = 0,
	760	+ }, {
	761	+ .reg = PAD_DIRECTION_SEL_1,
	762	+ .mask = PMX_NFCE2_MASK,
	763	+ .val = PMX_NFCE2_MASK,
684	764	},
685	765	};
686	766
...	...	@@ -721,6 +801,14 @@
721	801	.reg = PAD_FUNCTION_EN_1,
722	802	.mask = PMX_NAND8BIT_1_MASK,
723	803	.val = PMX_NAND8BIT_1_MASK,
	804	+ }, {
	805	+ .reg = PAD_DIRECTION_SEL_0,
	806	+ .mask = PMX_NAND8BIT_0_MASK,
	807	+ .val = PMX_NAND8BIT_0_MASK,
	808	+ }, {
	809	+ .reg = PAD_DIRECTION_SEL_1,
	810	+ .mask = PMX_NAND8BIT_1_MASK,
	811	+ .val = PMX_NAND8BIT_1_MASK,
724	812	},
725	813	};
726	814
...	...	@@ -747,6 +835,10 @@
747	835	.reg = PAD_FUNCTION_EN_1,
748	836	.mask = PMX_NAND16BIT_1_MASK,
749	837	.val = PMX_NAND16BIT_1_MASK,
	838	+ }, {
	839	+ .reg = PAD_DIRECTION_SEL_1,
	840	+ .mask = PMX_NAND16BIT_1_MASK,
	841	+ .val = PMX_NAND16BIT_1_MASK,
750	842	},
751	843	};
752	844
...	...	@@ -772,6 +864,10 @@
772	864	.reg = PAD_FUNCTION_EN_1,
773	865	.mask = PMX_NAND_4CHIPS_MASK,
774	866	.val = PMX_NAND_4CHIPS_MASK,
	867	+ }, {
	868	+ .reg = PAD_DIRECTION_SEL_1,
	869	+ .mask = PMX_NAND_4CHIPS_MASK,
	870	+ .val = PMX_NAND_4CHIPS_MASK,
775	871	},
776	872	};
777	873
...	...	@@ -833,6 +929,10 @@
833	929	.reg = PAD_FUNCTION_EN_1,
834	930	.mask = PMX_KBD_ROWCOL68_MASK,
835	931	.val = PMX_KBD_ROWCOL68_MASK,
	932	+ }, {
	933	+ .reg = PAD_DIRECTION_SEL_1,
	934	+ .mask = PMX_KBD_ROWCOL68_MASK,
	935	+ .val = PMX_KBD_ROWCOL68_MASK,
836	936	},
837	937	};
838	938
...	...	@@ -866,6 +966,10 @@
866	966	.reg = PAD_FUNCTION_EN_0,
867	967	.mask = PMX_UART0_MASK,
868	968	.val = PMX_UART0_MASK,
	969	+ }, {
	970	+ .reg = PAD_DIRECTION_SEL_0,
	971	+ .mask = PMX_UART0_MASK,
	972	+ .val = PMX_UART0_MASK,
869	973	},
870	974	};
871	975
...	...	@@ -891,6 +995,10 @@
891	995	.reg = PAD_FUNCTION_EN_1,
892	996	.mask = PMX_UART0_MODEM_MASK,
893	997	.val = PMX_UART0_MODEM_MASK,
	998	+ }, {
	999	+ .reg = PAD_DIRECTION_SEL_1,
	1000	+ .mask = PMX_UART0_MODEM_MASK,
	1001	+ .val = PMX_UART0_MODEM_MASK,
894	1002	},
895	1003	};
896	1004
...	...	@@ -923,6 +1031,10 @@
923	1031	.reg = PAD_FUNCTION_EN_1,
924	1032	.mask = PMX_GPT0_TMR0_MASK,
925	1033	.val = PMX_GPT0_TMR0_MASK,
	1034	+ }, {
	1035	+ .reg = PAD_DIRECTION_SEL_1,
	1036	+ .mask = PMX_GPT0_TMR0_MASK,
	1037	+ .val = PMX_GPT0_TMR0_MASK,
926	1038	},
927	1039	};
928	1040
...	...	@@ -948,6 +1060,10 @@
948	1060	.reg = PAD_FUNCTION_EN_1,
949	1061	.mask = PMX_GPT0_TMR1_MASK,
950	1062	.val = PMX_GPT0_TMR1_MASK,
	1063	+ }, {
	1064	+ .reg = PAD_DIRECTION_SEL_1,
	1065	+ .mask = PMX_GPT0_TMR1_MASK,
	1066	+ .val = PMX_GPT0_TMR1_MASK,
951	1067	},
952	1068	};
953	1069
...	...	@@ -980,6 +1096,10 @@
980	1096	.reg = PAD_FUNCTION_EN_1,
981	1097	.mask = PMX_GPT1_TMR0_MASK,
982	1098	.val = PMX_GPT1_TMR0_MASK,
	1099	+ }, {
	1100	+ .reg = PAD_DIRECTION_SEL_1,
	1101	+ .mask = PMX_GPT1_TMR0_MASK,
	1102	+ .val = PMX_GPT1_TMR0_MASK,
983	1103	},
984	1104	};
985	1105
...	...	@@ -1005,6 +1125,10 @@
1005	1125	.reg = PAD_FUNCTION_EN_1,
1006	1126	.mask = PMX_GPT1_TMR1_MASK,
1007	1127	.val = PMX_GPT1_TMR1_MASK,
	1128	+ }, {
	1129	+ .reg = PAD_DIRECTION_SEL_1,
	1130	+ .mask = PMX_GPT1_TMR1_MASK,
	1131	+ .val = PMX_GPT1_TMR1_MASK,
1008	1132	},
1009	1133	};
1010	1134
...	...	@@ -1049,6 +1173,20 @@
1049	1173	.reg = PAD_FUNCTION_EN_2, \
1050	1174	.mask = PMX_MCIFALL_2_MASK, \
1051	1175	.val = PMX_MCIFALL_2_MASK, \
	1176	+ }, { \
	1177	+ .reg = PAD_DIRECTION_SEL_0, \
	1178	+ .mask = PMX_MCI_DATA8_15_MASK, \
	1179	+ .val = PMX_MCI_DATA8_15_MASK, \
	1180	+ }, { \
	1181	+ .reg = PAD_DIRECTION_SEL_1, \
	1182	+ .mask = PMX_MCIFALL_1_MASK \| PMX_NFWPRT1_MASK \| \
	1183	+ PMX_NFWPRT2_MASK, \
	1184	+ .val = PMX_MCIFALL_1_MASK \| PMX_NFWPRT1_MASK \| \
	1185	+ PMX_NFWPRT2_MASK, \
	1186	+ }, { \
	1187	+ .reg = PAD_DIRECTION_SEL_2, \
	1188	+ .mask = PMX_MCIFALL_2_MASK, \
	1189	+ .val = PMX_MCIFALL_2_MASK, \
1052	1190	}
1053	1191
1054	1192	/* sdhci device */
...	...	@@ -1154,6 +1292,10 @@
1154	1292	.reg = PAD_FUNCTION_EN_2,
1155	1293	.mask = PMX_TOUCH_XY_MASK,
1156	1294	.val = PMX_TOUCH_XY_MASK,
	1295	+ }, {
	1296	+ .reg = PAD_DIRECTION_SEL_2,
	1297	+ .mask = PMX_TOUCH_XY_MASK,
	1298	+ .val = PMX_TOUCH_XY_MASK,
1157	1299	},
1158	1300	};
1159	1301
...	...	@@ -1187,6 +1329,10 @@
1187	1329	.reg = PAD_FUNCTION_EN_0,
1188	1330	.mask = PMX_I2C0_MASK,
1189	1331	.val = 0,
	1332	+ }, {
	1333	+ .reg = PAD_DIRECTION_SEL_0,
	1334	+ .mask = PMX_I2C0_MASK,
	1335	+ .val = PMX_I2C0_MASK,
1190	1336	},
1191	1337	};
1192	1338
...	...	@@ -1213,6 +1359,12 @@
1213	1359	.mask = PMX_MCIDATA1_MASK \|
1214	1360	PMX_MCIDATA2_MASK,
1215	1361	.val = 0,
	1362	+ }, {
	1363	+ .reg = PAD_DIRECTION_SEL_1,
	1364	+ .mask = PMX_MCIDATA1_MASK \|
	1365	+ PMX_MCIDATA2_MASK,
	1366	+ .val = PMX_MCIDATA1_MASK \|
	1367	+ PMX_MCIDATA2_MASK,
1216	1368	},
1217	1369	};
1218	1370
...	...	@@ -1246,6 +1398,10 @@
1246	1398	.reg = PAD_FUNCTION_EN_0,
1247	1399	.mask = PMX_I2S0_MASK,
1248	1400	.val = 0,
	1401	+ }, {
	1402	+ .reg = PAD_DIRECTION_SEL_0,
	1403	+ .mask = PMX_I2S0_MASK,
	1404	+ .val = PMX_I2S0_MASK,
1249	1405	},
1250	1406	};
1251	1407
...	...	@@ -1278,6 +1434,10 @@
1278	1434	.reg = PAD_FUNCTION_EN_0,
1279	1435	.mask = PMX_I2S0_MASK \| PMX_CLCD1_MASK,
1280	1436	.val = 0,
	1437	+ }, {
	1438	+ .reg = PAD_DIRECTION_SEL_0,
	1439	+ .mask = PMX_I2S0_MASK \| PMX_CLCD1_MASK,
	1440	+ .val = PMX_I2S0_MASK \| PMX_CLCD1_MASK,
1281	1441	},
1282	1442	};
1283	1443
...	...	@@ -1310,6 +1470,10 @@
1310	1470	.reg = PAD_FUNCTION_EN_0,
1311	1471	.mask = PMX_CLCD1_MASK,
1312	1472	.val = 0,
	1473	+ }, {
	1474	+ .reg = PAD_DIRECTION_SEL_0,
	1475	+ .mask = PMX_CLCD1_MASK,
	1476	+ .val = PMX_CLCD1_MASK,
1313	1477	},
1314	1478	};
1315	1479
...	...	@@ -1344,6 +1508,10 @@
1344	1508	.reg = PAD_FUNCTION_EN_0,
1345	1509	.mask = PMX_CLCD1_MASK,
1346	1510	.val = 0,
	1511	+ }, {
	1512	+ .reg = PAD_DIRECTION_SEL_0,
	1513	+ .mask = PMX_CLCD1_MASK,
	1514	+ .val = PMX_CLCD1_MASK,
1347	1515	},
1348	1516	};
1349	1517
...	...	@@ -1376,6 +1544,10 @@
1376	1544	.reg = PAD_FUNCTION_EN_0,
1377	1545	.mask = PMX_CLCD1_MASK,
1378	1546	.val = 0,
	1547	+ }, {
	1548	+ .reg = PAD_DIRECTION_SEL_0,
	1549	+ .mask = PMX_CLCD1_MASK,
	1550	+ .val = PMX_CLCD1_MASK,
1379	1551	},
1380	1552	};
1381	1553
...	...	@@ -1409,6 +1581,10 @@
1409	1581	.reg = PAD_FUNCTION_EN_0,
1410	1582	.mask = PMX_CLCD1_MASK \| PMX_SMI_MASK,
1411	1583	.val = 0,
	1584	+ }, {
	1585	+ .reg = PAD_DIRECTION_SEL_0,
	1586	+ .mask = PMX_CLCD1_MASK \| PMX_SMI_MASK,
	1587	+ .val = PMX_CLCD1_MASK \| PMX_SMI_MASK,
1412	1588	},
1413	1589	};
1414	1590
...	...	@@ -1435,6 +1611,10 @@
1435	1611	.reg = PAD_FUNCTION_EN_1,
1436	1612	.mask = PMX_I2S1_MASK \| PMX_MCIDATA3_MASK,
1437	1613	.val = 0,
	1614	+ }, {
	1615	+ .reg = PAD_DIRECTION_SEL_1,
	1616	+ .mask = PMX_I2S1_MASK \| PMX_MCIDATA3_MASK,
	1617	+ .val = PMX_I2S1_MASK \| PMX_MCIDATA3_MASK,
1438	1618	},
1439	1619	};
1440	1620
...	...	@@ -1469,6 +1649,10 @@
1469	1649	.reg = PAD_FUNCTION_EN_0,
1470	1650	.mask = PMX_SMI_MASK,
1471	1651	.val = 0,
	1652	+ }, {
	1653	+ .reg = PAD_DIRECTION_SEL_0,
	1654	+ .mask = PMX_SMI_MASK,
	1655	+ .val = PMX_SMI_MASK,
1472	1656	},
1473	1657	};
1474	1658
...	...	@@ -1499,6 +1683,14 @@
1499	1683	.reg = PAD_FUNCTION_EN_2,
1500	1684	.mask = PMX_MCIDATA5_MASK,
1501	1685	.val = 0,
	1686	+ }, {
	1687	+ .reg = PAD_DIRECTION_SEL_1,
	1688	+ .mask = PMX_MCIDATA4_MASK,
	1689	+ .val = PMX_MCIDATA4_MASK,
	1690	+ }, {
	1691	+ .reg = PAD_DIRECTION_SEL_2,
	1692	+ .mask = PMX_MCIDATA5_MASK,
	1693	+ .val = PMX_MCIDATA5_MASK,
1502	1694	},
1503	1695	};
1504	1696
...	...	@@ -1526,6 +1718,12 @@
1526	1718	.mask = PMX_MCIDATA6_MASK \|
1527	1719	PMX_MCIDATA7_MASK,
1528	1720	.val = 0,
	1721	+ }, {
	1722	+ .reg = PAD_DIRECTION_SEL_2,
	1723	+ .mask = PMX_MCIDATA6_MASK \|
	1724	+ PMX_MCIDATA7_MASK,
	1725	+ .val = PMX_MCIDATA6_MASK \|
	1726	+ PMX_MCIDATA7_MASK,
1529	1727	},
1530	1728	};
1531	1729
...	...	@@ -1560,6 +1758,10 @@
1560	1758	.reg = PAD_FUNCTION_EN_1,
1561	1759	.mask = PMX_KBD_ROWCOL25_MASK,
1562	1760	.val = 0,
	1761	+ }, {
	1762	+ .reg = PAD_DIRECTION_SEL_1,
	1763	+ .mask = PMX_KBD_ROWCOL25_MASK,
	1764	+ .val = PMX_KBD_ROWCOL25_MASK,
1563	1765	},
1564	1766	};
1565	1767
...	...	@@ -1587,6 +1789,12 @@
1587	1789	.mask = PMX_MCIIORDRE_MASK \|
1588	1790	PMX_MCIIOWRWE_MASK,
1589	1791	.val = 0,
	1792	+ }, {
	1793	+ .reg = PAD_DIRECTION_SEL_2,
	1794	+ .mask = PMX_MCIIORDRE_MASK \|
	1795	+ PMX_MCIIOWRWE_MASK,
	1796	+ .val = PMX_MCIIORDRE_MASK \|
	1797	+ PMX_MCIIOWRWE_MASK,
1590	1798	},
1591	1799	};
1592	1800
...	...	@@ -1613,6 +1821,12 @@
1613	1821	.mask = PMX_MCIRESETCF_MASK \|
1614	1822	PMX_MCICS0CE_MASK,
1615	1823	.val = 0,
	1824	+ }, {
	1825	+ .reg = PAD_DIRECTION_SEL_2,
	1826	+ .mask = PMX_MCIRESETCF_MASK \|
	1827	+ PMX_MCICS0CE_MASK,
	1828	+ .val = PMX_MCIRESETCF_MASK \|
	1829	+ PMX_MCICS0CE_MASK,
1616	1830	},
1617	1831	};
1618	1832
...	...	@@ -1651,6 +1865,14 @@
1651	1865	.reg = PAD_FUNCTION_EN_1,
1652	1866	.mask = PMX_NFRSTPWDWN3_MASK,
1653	1867	.val = 0,
	1868	+ }, {
	1869	+ .reg = PAD_DIRECTION_SEL_0,
	1870	+ .mask = PMX_NFRSTPWDWN2_MASK,
	1871	+ .val = PMX_NFRSTPWDWN2_MASK,
	1872	+ }, {
	1873	+ .reg = PAD_DIRECTION_SEL_1,
	1874	+ .mask = PMX_NFRSTPWDWN3_MASK,
	1875	+ .val = PMX_NFRSTPWDWN3_MASK,
1654	1876	},
1655	1877	};
1656	1878
...	...	@@ -1677,6 +1899,10 @@
1677	1899	.reg = PAD_FUNCTION_EN_2,
1678	1900	.mask = PMX_MCICFINTR_MASK \| PMX_MCIIORDY_MASK,
1679	1901	.val = 0,
	1902	+ }, {
	1903	+ .reg = PAD_DIRECTION_SEL_2,
	1904	+ .mask = PMX_MCICFINTR_MASK \| PMX_MCIIORDY_MASK,
	1905	+ .val = PMX_MCICFINTR_MASK \| PMX_MCIIORDY_MASK,
1680	1906	},
1681	1907	};
1682	1908
...	...	@@ -1711,6 +1937,10 @@
1711	1937	.reg = PAD_FUNCTION_EN_2,
1712	1938	.mask = PMX_MCICS1_MASK \| PMX_MCIDMAACK_MASK,
1713	1939	.val = 0,
	1940	+ }, {
	1941	+ .reg = PAD_DIRECTION_SEL_2,
	1942	+ .mask = PMX_MCICS1_MASK \| PMX_MCIDMAACK_MASK,
	1943	+ .val = PMX_MCICS1_MASK \| PMX_MCIDMAACK_MASK,
1714	1944	},
1715	1945	};
1716	1946
...	...	@@ -1737,6 +1967,10 @@
1737	1967	.reg = PAD_FUNCTION_EN_1,
1738	1968	.mask = PMX_KBD_ROWCOL25_MASK,
1739	1969	.val = 0,
	1970	+ }, {
	1971	+ .reg = PAD_DIRECTION_SEL_1,
	1972	+ .mask = PMX_KBD_ROWCOL25_MASK,
	1973	+ .val = PMX_KBD_ROWCOL25_MASK,
1740	1974	},
1741	1975	};
1742	1976
...	...	@@ -1782,6 +2016,18 @@
1782	2016	.reg = PAD_FUNCTION_EN_2,
1783	2017	.mask = PMX_PCI_REG2_MASK,
1784	2018	.val = 0,
	2019	+ }, {
	2020	+ .reg = PAD_DIRECTION_SEL_0,
	2021	+ .mask = PMX_MCI_DATA8_15_MASK,
	2022	+ .val = PMX_MCI_DATA8_15_MASK,
	2023	+ }, {
	2024	+ .reg = PAD_DIRECTION_SEL_1,
	2025	+ .mask = PMX_PCI_REG1_MASK,
	2026	+ .val = PMX_PCI_REG1_MASK,
	2027	+ }, {
	2028	+ .reg = PAD_DIRECTION_SEL_2,
	2029	+ .mask = PMX_PCI_REG2_MASK,
	2030	+ .val = PMX_PCI_REG2_MASK,
1785	2031	},
1786	2032	};
1787	2033
...	...	@@ -1964,6 +2210,14 @@
1964	2210	PMX_KBD_COL0_MASK \| PMX_NFIO8_15_MASK \| PMX_NFCE1_MASK \|
1965	2211	PMX_NFCE2_MASK,
1966	2212	.val = 0,
	2213	+ }, {
	2214	+ .reg = PAD_DIRECTION_SEL_1,
	2215	+ .mask = PMX_KBD_ROWCOL25_MASK \| PMX_KBD_COL1_MASK \|
	2216	+ PMX_KBD_COL0_MASK \| PMX_NFIO8_15_MASK \| PMX_NFCE1_MASK \|
	2217	+ PMX_NFCE2_MASK,
	2218	+ .val = PMX_KBD_ROWCOL25_MASK \| PMX_KBD_COL1_MASK \|
	2219	+ PMX_KBD_COL0_MASK \| PMX_NFIO8_15_MASK \| PMX_NFCE1_MASK \|
	2220	+ PMX_NFCE2_MASK,
1967	2221	},
1968	2222	};
1969	2223
...	...	@@ -1990,6 +2244,12 @@
1990	2244	.mask = PMX_MCIADDR0ALE_MASK \| PMX_MCIADDR2_MASK \|
1991	2245	PMX_MCICECF_MASK \| PMX_MCICEXD_MASK,
1992	2246	.val = 0,
	2247	+ }, {
	2248	+ .reg = PAD_DIRECTION_SEL_2,
	2249	+ .mask = PMX_MCIADDR0ALE_MASK \| PMX_MCIADDR2_MASK \|
	2250	+ PMX_MCICECF_MASK \| PMX_MCICEXD_MASK,
	2251	+ .val = PMX_MCIADDR0ALE_MASK \| PMX_MCIADDR2_MASK \|
	2252	+ PMX_MCICECF_MASK \| PMX_MCICEXD_MASK,
1993	2253	},
1994	2254	};
1995	2255
...	...	@@ -2024,6 +2284,12 @@
2024	2284	.mask = PMX_MCICDCF1_MASK \| PMX_MCICDCF2_MASK \| PMX_MCICDXD_MASK
2025	2285	\| PMX_MCILEDS_MASK,
2026	2286	.val = 0,
	2287	+ }, {
	2288	+ .reg = PAD_DIRECTION_SEL_2,
	2289	+ .mask = PMX_MCICDCF1_MASK \| PMX_MCICDCF2_MASK \| PMX_MCICDXD_MASK
	2290	+ \| PMX_MCILEDS_MASK,
	2291	+ .val = PMX_MCICDCF1_MASK \| PMX_MCICDCF2_MASK \| PMX_MCICDXD_MASK
	2292	+ \| PMX_MCILEDS_MASK,
2027	2293	},
2028	2294	};
2029	2295