Commit 0f531431d3de88efb4234d6c0ce22089ec035a38

Authored by Mathias Nyman
Committed by Ingo Molnar
1 parent 9d8e3f9693

x86/intel/lpss: Add pin control support to Intel low power subsystem

x86 chips with LPSS (low power subsystem) such as Lynxpoint and
Baytrail have SoC like peripheral support and controllable pins.

At the moment, Baytrail needs the pinctrl-baytrail driver to let
peripherals control their gpio resources, but more pincontrol
functions such as pin muxing and grouping are possible to add
later.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: http://lkml.kernel.org/r/1379080949-21734-1-git-send-email-mathias.nyman@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

Showing 1 changed file with 3 additions and 2 deletions Side-by-side Diff

... ... @@ -482,11 +482,12 @@
482 482 bool "Intel Low Power Subsystem Support"
483 483 depends on ACPI
484 484 select COMMON_CLK
  485 + select PINCTRL
485 486 ---help---
486 487 Select to build support for Intel Low Power Subsystem such as
487 488 found on Intel Lynxpoint PCH. Selecting this option enables
488   - things like clock tree (common clock framework) which are needed
489   - by the LPSS peripheral drivers.
  489 + things like clock tree (common clock framework) and pincontrol
  490 + which are needed by the LPSS peripheral drivers.
490 491  
491 492 config X86_RDC321X
492 493 bool "RDC R-321x SoC"