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Commit 10290030d7d31e387f602190ece2cdb3abfb3d71

Authored by Prashant Gaikwad
Committed by Mike Turquette
1 parent 5b6e0adb69
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

clk: zynq: Use common of_clk_init() function 

Use common of_clk_init() function for clock initialization.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Josh Cartwright <josh.cartwright@ni.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Showing 1 changed file with 4 additions and 10 deletions Side-by-side Diff

drivers/clk/clk-zynq.c
Diff comments   View file @ 1029003
... ... @@ -81,6 +81,7 @@
81 81 if (WARN_ON(ret))
82 82 return;
83 83 }
  84 +CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup);
84 85  
85 86 struct zynq_periph_clk {
86 87 struct clk_hw hw;
... ... @@ -187,6 +188,7 @@
187 188 if (WARN_ON(err))
188 189 return;
189 190 }
  191 +CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup);
190 192  
191 193 /* CPU Clock domain is modelled as a mux with 4 children subclks, whose
192 194 * derivative rates depend on CLK_621_TRUE
193 195  
194 196  
... ... @@ -366,19 +368,11 @@
366 368 if (WARN_ON(err))
367 369 return;
368 370 }
  371 +CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup);
369 372  
370   -static const __initconst struct of_device_id zynq_clk_match[] = {
371   - { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
372   - { .compatible = "xlnx,zynq-pll", .data = zynq_pll_clk_setup, },
373   - { .compatible = "xlnx,zynq-periph-clock",
374   - .data = zynq_periph_clk_setup, },
375   - { .compatible = "xlnx,zynq-cpu-clock", .data = zynq_cpu_clk_setup, },
376   - {}
377   -};
378   -
379 373 void __init xilinx_zynq_clocks_init(void __iomem *slcr)
380 374 {
381 375 slcr_base = slcr;
382   - of_clk_init(zynq_clk_match);
  376 + of_clk_init(NULL);
383 377 }