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Commit 1198168733c8d6fbc6898fd8d7fcfb42befabb41

Authored by Chris Metcalf
1 parent 1c43649a99
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

tile PCI RC: eliminate pci_controller.mem_resources field 

The .mem_resources[] field in the pci_controller struct
is now obsoleted by the .mem_space and .io_space fields.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

Showing 2 changed files with 12 additions and 62 deletions Side-by-side Diff

arch/tile/include/asm/pci.h
Diff comments   View file @ 1198168
... ... @@ -173,9 +173,6 @@
173 173  
174 174 /* Table that maps the INTx numbers to Linux irq numbers. */
175 175 int irq_intx_table[4];
176   -
177   - /* Address ranges that are routed to this controller/bridge. */
178   - struct resource mem_resources[3];
179 176 };
180 177  
181 178 extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
arch/tile/kernel/pci_gx.c
Diff comments   View file @ 1198168
... ... @@ -929,9 +929,6 @@
929 929 struct pci_controller *controller = &pci_controllers[i];
930 930 gxio_trio_context_t *trio_context = controller->trio;
931 931 struct pci_bus *root_bus = pci_controllers[i].root_bus;
932   - struct pci_bus *next_bus;
933   - uint32_t bus_address_hi;
934   - struct pci_dev *dev;
935 932 int ret;
936 933 int j;
937 934  
... ... @@ -945,35 +942,6 @@
945 942 /* Configure the max_payload_size values for this domain. */
946 943 fixup_read_and_payload_sizes(controller);
947 944  
948   - list_for_each_entry(dev, &root_bus->devices, bus_list) {
949   - /* Find the PCI host controller, ie. the 1st bridge. */
950   - if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
951   - (PCI_SLOT(dev->devfn) == 0)) {
952   - next_bus = dev->subordinate;
953   - pci_controllers[i].mem_resources[0] =
954   - *next_bus->resource[0];
955   - pci_controllers[i].mem_resources[1] =
956   - *next_bus->resource[1];
957   - pci_controllers[i].mem_resources[2] =
958   - *next_bus->resource[2];
959   -
960   - break;
961   - }
962   - }
963   -
964   - if (pci_controllers[i].mem_resources[1].flags & IORESOURCE_MEM)
965   - bus_address_hi =
966   - pci_controllers[i].mem_resources[1].start >> 32;
967   - else if (pci_controllers[i].mem_resources[2].flags & IORESOURCE_PREFETCH)
968   - bus_address_hi =
969   - pci_controllers[i].mem_resources[2].start >> 32;
970   - else {
971   - /* This is unlikely. */
972   - pr_err("PCI: no memory resources on TRIO %d mac %d\n",
973   - controller->trio_index, controller->mac);
974   - continue;
975   - }
976   -
977 945 /*
978 946 * Alloc a PIO region for PCI memory access for each RC port.
979 947 */
980 948  
... ... @@ -1153,16 +1121,13 @@
1153 1121 resource_size_t start;
1154 1122 resource_size_t end;
1155 1123 int trio_fd;
1156   - int i, j;
  1124 + int i;
1157 1125  
1158 1126 start = phys_addr;
1159 1127 end = phys_addr + size - 1;
1160 1128  
1161 1129 /*
1162   - * In the following, each PCI controller's mem_resources[1]
1163   - * represents its (non-prefetchable) PCI memory resource and
1164   - * mem_resources[2] refers to its prefetchable PCI memory resource.
1165   - * By searching phys_addr in each controller's mem_resources[], we can
  1130 + * By searching phys_addr in each controller's mem_space, we can
1166 1131 * determine the controller that should accept the PCI memory access.
1167 1132 */
1168 1133  
1169 1134  
1170 1135  
... ... @@ -1174,25 +1139,18 @@
1174 1139 if (pci_controllers[i].root_bus == NULL)
1175 1140 continue;
1176 1141  
1177   - for (j = 1; j < 3; j++) {
1178   - bar_start =
1179   - pci_controllers[i].mem_resources[j].start;
1180   - bar_end =
1181   - pci_controllers[i].mem_resources[j].end;
  1142 + bar_start = pci_controllers[i].mem_space.start;
  1143 + bar_end = pci_controllers[i].mem_space.end;
1182 1144  
1183   - if ((start >= bar_start) && (end <= bar_end)) {
1184   -
1185   - controller = &pci_controllers[i];
1186   -
1187   - goto got_it;
1188   - }
  1145 + if ((start >= bar_start) && (end <= bar_end)) {
  1146 + controller = &pci_controllers[i];
  1147 + break;
1189 1148 }
1190 1149 }
1191 1150  
1192 1151 if (controller == NULL)
1193 1152 return NULL;
1194 1153  
1195   -got_it:
1196 1154 trio_fd = controller->trio->fd;
1197 1155  
1198 1156 /* Convert the resource start to the bus address offset. */
... ... @@ -1225,10 +1183,8 @@
1225 1183 end = port + size - 1;
1226 1184  
1227 1185 /*
1228   - * In the following, each PCI controller's mem_resources[0]
1229   - * represents its PCI I/O resource. By searching port in each
1230   - * controller's mem_resources[0], we can determine the controller
1231   - * that should accept the PCI I/O access.
  1186 + * By searching the port in each controller's io_space, we can
  1187 + * determine the controller that should accept the PCI I/O access.
1232 1188 */
1233 1189  
1234 1190 for (i = 0; i < num_rc_controllers; i++) {
1235 1191  
1236 1192  
1237 1193  
... ... @@ -1239,21 +1195,18 @@
1239 1195 if (pci_controllers[i].root_bus == NULL)
1240 1196 continue;
1241 1197  
1242   - bar_start = pci_controllers[i].mem_resources[0].start;
1243   - bar_end = pci_controllers[i].mem_resources[0].end;
  1198 + bar_start = pci_controllers[i].io_space.start;
  1199 + bar_end = pci_controllers[i].io_space.end;
1244 1200  
1245 1201 if ((start >= bar_start) && (end <= bar_end)) {
1246   -
1247 1202 controller = &pci_controllers[i];
1248   -
1249   - goto got_it;
  1203 + break;
1250 1204 }
1251 1205 }
1252 1206  
1253 1207 if (controller == NULL)
1254 1208 return NULL;
1255 1209  
1256   -got_it:
1257 1210 trio_fd = controller->trio->fd;
1258 1211  
1259 1212 /* Convert the resource start to the bus address offset. */