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Commit 11ad14f86a7847b084d3e3f114180be39b1c7322

Authored by Jorge Eduardo Candelaria
Committed by Liam Girdwood
1 parent 83545d836c
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

TPS65911: Add support for added GPIO lines 

GPIO 1 to 8 are added for TPS65911 chip version. The gpio driver
now handles more than one gpio lines. Subsequent versions of the
chip family can add new GPIO lines with minimal driver changes.

Signed-off-by: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>

Showing 2 changed files with 33 additions and 86 deletions Inline Diff

drivers/gpio/tps65910-gpio.c
Diff comments   View file @ 11ad14f
1 /* 1 /*
2 * tps65910-gpio.c -- TI TPS6591x 2 * tps65910-gpio.c -- TI TPS6591x
3 * 3 *
4 * Copyright 2010 Texas Instruments Inc. 4 * Copyright 2010 Texas Instruments Inc.
5 * 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria jedu@slimlogic.co.uk> 7 * Author: Jorge Eduardo Candelaria jedu@slimlogic.co.uk>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 * 13 *
14 */ 14 */
15 15
16 #include <linux/kernel.h> 16 #include <linux/kernel.h>
17 #include <linux/module.h> 17 #include <linux/module.h>
18 #include <linux/errno.h> 18 #include <linux/errno.h>
19 #include <linux/gpio.h> 19 #include <linux/gpio.h>
20 #include <linux/i2c.h> 20 #include <linux/i2c.h>
21 #include <linux/mfd/tps65910.h> 21 #include <linux/mfd/tps65910.h>
22 22
23 static int tps65910_gpio_get(struct gpio_chip *gc, unsigned offset) 23 static int tps65910_gpio_get(struct gpio_chip *gc, unsigned offset)
24 { 24 {
25 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio); 25 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
26 uint8_t val; 26 uint8_t val;
27 27
28 tps65910->read(tps65910, TPS65910_GPIO0, 1, &val); 28 tps65910->read(tps65910, TPS65910_GPIO0 + offset, 1, &val);
29 29
30 if (val & GPIO0_GPIO_STS_MASK) 30 if (val & GPIO_STS_MASK)
31 return 1; 31 return 1;
32 32
33 return 0; 33 return 0;
34 } 34 }
35 35
36 static void tps65910_gpio_set(struct gpio_chip *gc, unsigned offset, 36 static void tps65910_gpio_set(struct gpio_chip *gc, unsigned offset,
37 int value) 37 int value)
38 { 38 {
39 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio); 39 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
40 40
41 if (value) 41 if (value)
42 tps65910_set_bits(tps65910, TPS65910_GPIO0, 42 tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset,
43 GPIO0_GPIO_SET_MASK); 43 GPIO_SET_MASK);
44 else 44 else
45 tps65910_clear_bits(tps65910, TPS65910_GPIO0, 45 tps65910_clear_bits(tps65910, TPS65910_GPIO0 + offset,
46 GPIO0_GPIO_SET_MASK); 46 GPIO_SET_MASK);
47 } 47 }
48 48
49 static int tps65910_gpio_output(struct gpio_chip *gc, unsigned offset, 49 static int tps65910_gpio_output(struct gpio_chip *gc, unsigned offset,
50 int value) 50 int value)
51 { 51 {
52 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio); 52 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
53 53
54 /* Set the initial value */ 54 /* Set the initial value */
55 tps65910_gpio_set(gc, 0, value); 55 tps65910_gpio_set(gc, 0, value);
56 56
57 return tps65910_set_bits(tps65910, TPS65910_GPIO0, GPIO0_GPIO_CFG_MASK); 57 return tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset,
58 GPIO_CFG_MASK);
58 } 59 }
59 60
60 static int tps65910_gpio_input(struct gpio_chip *gc, unsigned offset) 61 static int tps65910_gpio_input(struct gpio_chip *gc, unsigned offset)
61 { 62 {
62 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio); 63 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
63 64
64 return tps65910_clear_bits(tps65910, TPS65910_GPIO0, 65 return tps65910_clear_bits(tps65910, TPS65910_GPIO0 + offset,
65 GPIO0_GPIO_CFG_MASK); 66 GPIO_CFG_MASK);
66 } 67 }
67 68
68 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base) 69 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
69 { 70 {
70 int ret; 71 int ret;
71 72
72 if (!gpio_base) 73 if (!gpio_base)
73 return; 74 return;
74 75
75 tps65910->gpio.owner = THIS_MODULE; 76 tps65910->gpio.owner = THIS_MODULE;
76 tps65910->gpio.label = tps65910->i2c_client->name; 77 tps65910->gpio.label = tps65910->i2c_client->name;
77 tps65910->gpio.dev = tps65910->dev; 78 tps65910->gpio.dev = tps65910->dev;
78 tps65910->gpio.base = gpio_base; 79 tps65910->gpio.base = gpio_base;
79 tps65910->gpio.ngpio = 1; 80
81 switch(tps65910_chip_id(tps65910)) {
82 case TPS65910:
83 tps65910->gpio.ngpio = 6;
84 case TPS65911:
85 tps65910->gpio.ngpio = 9;
86 default:
87 return;
88 }
80 tps65910->gpio.can_sleep = 1; 89 tps65910->gpio.can_sleep = 1;
81 90
82 tps65910->gpio.direction_input = tps65910_gpio_input; 91 tps65910->gpio.direction_input = tps65910_gpio_input;
83 tps65910->gpio.direction_output = tps65910_gpio_output; 92 tps65910->gpio.direction_output = tps65910_gpio_output;
84 tps65910->gpio.set = tps65910_gpio_set; 93 tps65910->gpio.set = tps65910_gpio_set;
85 tps65910->gpio.get = tps65910_gpio_get; 94 tps65910->gpio.get = tps65910_gpio_get;
86 95
87 ret = gpiochip_add(&tps65910->gpio); 96 ret = gpiochip_add(&tps65910->gpio);
88 97
89 if (ret) 98 if (ret)
90 dev_warn(tps65910->dev, "GPIO registration failed: %d\n", ret); 99 dev_warn(tps65910->dev, "GPIO registration failed: %d\n", ret);
91 } 100 }
92 101
include/linux/mfd/tps65910.h
Diff comments   View file @ 11ad14f
1 /* 1 /*
2 * tps65910.h -- TI TPS6591x 2 * tps65910.h -- TI TPS6591x
3 * 3 *
4 * Copyright 2010-2011 Texas Instruments Inc. 4 * Copyright 2010-2011 Texas Instruments Inc.
5 * 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> 7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 * Author: Arnaud Deconinck <a-deconinck@ti.com> 8 * Author: Arnaud Deconinck <a-deconinck@ti.com>
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify it 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your 12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version. 13 * option) any later version.
14 * 14 *
15 */ 15 */
16 16
17 #ifndef __LINUX_MFD_TPS65910_H 17 #ifndef __LINUX_MFD_TPS65910_H
18 #define __LINUX_MFD_TPS65910_H 18 #define __LINUX_MFD_TPS65910_H
19 19
20 /* TPS chip id list */ 20 /* TPS chip id list */
21 #define TPS65910 0 21 #define TPS65910 0
22 #define TPS65911 1 22 #define TPS65911 1
23 23
24 /* TPS regulator type list */ 24 /* TPS regulator type list */
25 #define REGULATOR_LDO 0 25 #define REGULATOR_LDO 0
26 #define REGULATOR_DCDC 1 26 #define REGULATOR_DCDC 1
27 27
28 /* 28 /*
29 * List of registers for component TPS65910 29 * List of registers for component TPS65910
30 * 30 *
31 */ 31 */
32 32
33 #define TPS65910_SECONDS 0x0 33 #define TPS65910_SECONDS 0x0
34 #define TPS65910_MINUTES 0x1 34 #define TPS65910_MINUTES 0x1
35 #define TPS65910_HOURS 0x2 35 #define TPS65910_HOURS 0x2
36 #define TPS65910_DAYS 0x3 36 #define TPS65910_DAYS 0x3
37 #define TPS65910_MONTHS 0x4 37 #define TPS65910_MONTHS 0x4
38 #define TPS65910_YEARS 0x5 38 #define TPS65910_YEARS 0x5
39 #define TPS65910_WEEKS 0x6 39 #define TPS65910_WEEKS 0x6
40 #define TPS65910_ALARM_SECONDS 0x8 40 #define TPS65910_ALARM_SECONDS 0x8
41 #define TPS65910_ALARM_MINUTES 0x9 41 #define TPS65910_ALARM_MINUTES 0x9
42 #define TPS65910_ALARM_HOURS 0xA 42 #define TPS65910_ALARM_HOURS 0xA
43 #define TPS65910_ALARM_DAYS 0xB 43 #define TPS65910_ALARM_DAYS 0xB
44 #define TPS65910_ALARM_MONTHS 0xC 44 #define TPS65910_ALARM_MONTHS 0xC
45 #define TPS65910_ALARM_YEARS 0xD 45 #define TPS65910_ALARM_YEARS 0xD
46 #define TPS65910_RTC_CTRL 0x10 46 #define TPS65910_RTC_CTRL 0x10
47 #define TPS65910_RTC_STATUS 0x11 47 #define TPS65910_RTC_STATUS 0x11
48 #define TPS65910_RTC_INTERRUPTS 0x12 48 #define TPS65910_RTC_INTERRUPTS 0x12
49 #define TPS65910_RTC_COMP_LSB 0x13 49 #define TPS65910_RTC_COMP_LSB 0x13
50 #define TPS65910_RTC_COMP_MSB 0x14 50 #define TPS65910_RTC_COMP_MSB 0x14
51 #define TPS65910_RTC_RES_PROG 0x15 51 #define TPS65910_RTC_RES_PROG 0x15
52 #define TPS65910_RTC_RESET_STATUS 0x16 52 #define TPS65910_RTC_RESET_STATUS 0x16
53 #define TPS65910_BCK1 0x17 53 #define TPS65910_BCK1 0x17
54 #define TPS65910_BCK2 0x18 54 #define TPS65910_BCK2 0x18
55 #define TPS65910_BCK3 0x19 55 #define TPS65910_BCK3 0x19
56 #define TPS65910_BCK4 0x1A 56 #define TPS65910_BCK4 0x1A
57 #define TPS65910_BCK5 0x1B 57 #define TPS65910_BCK5 0x1B
58 #define TPS65910_PUADEN 0x1C 58 #define TPS65910_PUADEN 0x1C
59 #define TPS65910_REF 0x1D 59 #define TPS65910_REF 0x1D
60 #define TPS65910_VRTC 0x1E 60 #define TPS65910_VRTC 0x1E
61 #define TPS65910_VIO 0x20 61 #define TPS65910_VIO 0x20
62 #define TPS65910_VDD1 0x21 62 #define TPS65910_VDD1 0x21
63 #define TPS65910_VDD1_OP 0x22 63 #define TPS65910_VDD1_OP 0x22
64 #define TPS65910_VDD1_SR 0x23 64 #define TPS65910_VDD1_SR 0x23
65 #define TPS65910_VDD2 0x24 65 #define TPS65910_VDD2 0x24
66 #define TPS65910_VDD2_OP 0x25 66 #define TPS65910_VDD2_OP 0x25
67 #define TPS65910_VDD2_SR 0x26 67 #define TPS65910_VDD2_SR 0x26
68 #define TPS65910_VDD3 0x27 68 #define TPS65910_VDD3 0x27
69 #define TPS65910_VDIG1 0x30 69 #define TPS65910_VDIG1 0x30
70 #define TPS65910_VDIG2 0x31 70 #define TPS65910_VDIG2 0x31
71 #define TPS65910_VAUX1 0x32 71 #define TPS65910_VAUX1 0x32
72 #define TPS65910_VAUX2 0x33 72 #define TPS65910_VAUX2 0x33
73 #define TPS65910_VAUX33 0x34 73 #define TPS65910_VAUX33 0x34
74 #define TPS65910_VMMC 0x35 74 #define TPS65910_VMMC 0x35
75 #define TPS65910_VPLL 0x36 75 #define TPS65910_VPLL 0x36
76 #define TPS65910_VDAC 0x37 76 #define TPS65910_VDAC 0x37
77 #define TPS65910_THERM 0x38 77 #define TPS65910_THERM 0x38
78 #define TPS65910_BBCH 0x39 78 #define TPS65910_BBCH 0x39
79 #define TPS65910_DCDCCTRL 0x3E 79 #define TPS65910_DCDCCTRL 0x3E
80 #define TPS65910_DEVCTRL 0x3F 80 #define TPS65910_DEVCTRL 0x3F
81 #define TPS65910_DEVCTRL2 0x40 81 #define TPS65910_DEVCTRL2 0x40
82 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41 82 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41
83 #define TPS65910_SLEEP_KEEP_RES_ON 0x42 83 #define TPS65910_SLEEP_KEEP_RES_ON 0x42
84 #define TPS65910_SLEEP_SET_LDO_OFF 0x43 84 #define TPS65910_SLEEP_SET_LDO_OFF 0x43
85 #define TPS65910_SLEEP_SET_RES_OFF 0x44 85 #define TPS65910_SLEEP_SET_RES_OFF 0x44
86 #define TPS65910_EN1_LDO_ASS 0x45 86 #define TPS65910_EN1_LDO_ASS 0x45
87 #define TPS65910_EN1_SMPS_ASS 0x46 87 #define TPS65910_EN1_SMPS_ASS 0x46
88 #define TPS65910_EN2_LDO_ASS 0x47 88 #define TPS65910_EN2_LDO_ASS 0x47
89 #define TPS65910_EN2_SMPS_ASS 0x48 89 #define TPS65910_EN2_SMPS_ASS 0x48
90 #define TPS65910_EN3_LDO_ASS 0x49 90 #define TPS65910_EN3_LDO_ASS 0x49
91 #define TPS65910_SPARE 0x4A 91 #define TPS65910_SPARE 0x4A
92 #define TPS65910_INT_STS 0x50 92 #define TPS65910_INT_STS 0x50
93 #define TPS65910_INT_MSK 0x51 93 #define TPS65910_INT_MSK 0x51
94 #define TPS65910_INT_STS2 0x52 94 #define TPS65910_INT_STS2 0x52
95 #define TPS65910_INT_MSK2 0x53 95 #define TPS65910_INT_MSK2 0x53
96 #define TPS65910_INT_STS3 0x54 96 #define TPS65910_INT_STS3 0x54
97 #define TPS65910_INT_MSK3 0x55 97 #define TPS65910_INT_MSK3 0x55
98 #define TPS65910_GPIO0 0x60 98 #define TPS65910_GPIO0 0x60
99 #define TPS65910_GPIO1 0x61 99 #define TPS65910_GPIO1 0x61
100 #define TPS65910_GPIO2 0x62 100 #define TPS65910_GPIO2 0x62
101 #define TPS65910_GPIO3 0x63 101 #define TPS65910_GPIO3 0x63
102 #define TPS65910_GPIO4 0x64 102 #define TPS65910_GPIO4 0x64
103 #define TPS65910_GPIO5 0x65 103 #define TPS65910_GPIO5 0x65
104 #define TPS65910_GPIO6 0x66
105 #define TPS65910_GPIO7 0x67
106 #define TPS65910_GPIO8 0x68
104 #define TPS65910_JTAGVERNUM 0x80 107 #define TPS65910_JTAGVERNUM 0x80
105 #define TPS65910_MAX_REGISTER 0x80 108 #define TPS65910_MAX_REGISTER 0x80
106 109
107 /* 110 /*
108 * List of registers specific to TPS65911 111 * List of registers specific to TPS65911
109 */ 112 */
110 #define TPS65911_VDDCTRL 0x27 113 #define TPS65911_VDDCTRL 0x27
111 #define TPS65911_VDDCTRL_OP 0x28 114 #define TPS65911_VDDCTRL_OP 0x28
112 #define TPS65911_VDDCTRL_SR 0x29 115 #define TPS65911_VDDCTRL_SR 0x29
113 #define TPS65911_LDO1 0x30 116 #define TPS65911_LDO1 0x30
114 #define TPS65911_LDO2 0x31 117 #define TPS65911_LDO2 0x31
115 #define TPS65911_LDO5 0x32 118 #define TPS65911_LDO5 0x32
116 #define TPS65911_LDO8 0x33 119 #define TPS65911_LDO8 0x33
117 #define TPS65911_LDO7 0x34 120 #define TPS65911_LDO7 0x34
118 #define TPS65911_LDO6 0x35 121 #define TPS65911_LDO6 0x35
119 #define TPS65911_LDO4 0x36 122 #define TPS65911_LDO4 0x36
120 #define TPS65911_LDO3 0x37 123 #define TPS65911_LDO3 0x37
121 124
122 /* 125 /*
123 * List of register bitfields for component TPS65910 126 * List of register bitfields for component TPS65910
124 * 127 *
125 */ 128 */
126 129
127 130
128 /*Register BCK1 (0x80) register.RegisterDescription */ 131 /*Register BCK1 (0x80) register.RegisterDescription */
129 #define BCK1_BCKUP_MASK 0xFF 132 #define BCK1_BCKUP_MASK 0xFF
130 #define BCK1_BCKUP_SHIFT 0 133 #define BCK1_BCKUP_SHIFT 0
131 134
132 135
133 /*Register BCK2 (0x80) register.RegisterDescription */ 136 /*Register BCK2 (0x80) register.RegisterDescription */
134 #define BCK2_BCKUP_MASK 0xFF 137 #define BCK2_BCKUP_MASK 0xFF
135 #define BCK2_BCKUP_SHIFT 0 138 #define BCK2_BCKUP_SHIFT 0
136 139
137 140
138 /*Register BCK3 (0x80) register.RegisterDescription */ 141 /*Register BCK3 (0x80) register.RegisterDescription */
139 #define BCK3_BCKUP_MASK 0xFF 142 #define BCK3_BCKUP_MASK 0xFF
140 #define BCK3_BCKUP_SHIFT 0 143 #define BCK3_BCKUP_SHIFT 0
141 144
142 145
143 /*Register BCK4 (0x80) register.RegisterDescription */ 146 /*Register BCK4 (0x80) register.RegisterDescription */
144 #define BCK4_BCKUP_MASK 0xFF 147 #define BCK4_BCKUP_MASK 0xFF
145 #define BCK4_BCKUP_SHIFT 0 148 #define BCK4_BCKUP_SHIFT 0
146 149
147 150
148 /*Register BCK5 (0x80) register.RegisterDescription */ 151 /*Register BCK5 (0x80) register.RegisterDescription */
149 #define BCK5_BCKUP_MASK 0xFF 152 #define BCK5_BCKUP_MASK 0xFF
150 #define BCK5_BCKUP_SHIFT 0 153 #define BCK5_BCKUP_SHIFT 0
151 154
152 155
153 /*Register PUADEN (0x80) register.RegisterDescription */ 156 /*Register PUADEN (0x80) register.RegisterDescription */
154 #define PUADEN_EN3P_MASK 0x80 157 #define PUADEN_EN3P_MASK 0x80
155 #define PUADEN_EN3P_SHIFT 7 158 #define PUADEN_EN3P_SHIFT 7
156 #define PUADEN_I2CCTLP_MASK 0x40 159 #define PUADEN_I2CCTLP_MASK 0x40
157 #define PUADEN_I2CCTLP_SHIFT 6 160 #define PUADEN_I2CCTLP_SHIFT 6
158 #define PUADEN_I2CSRP_MASK 0x20 161 #define PUADEN_I2CSRP_MASK 0x20
159 #define PUADEN_I2CSRP_SHIFT 5 162 #define PUADEN_I2CSRP_SHIFT 5
160 #define PUADEN_PWRONP_MASK 0x10 163 #define PUADEN_PWRONP_MASK 0x10
161 #define PUADEN_PWRONP_SHIFT 4 164 #define PUADEN_PWRONP_SHIFT 4
162 #define PUADEN_SLEEPP_MASK 0x08 165 #define PUADEN_SLEEPP_MASK 0x08
163 #define PUADEN_SLEEPP_SHIFT 3 166 #define PUADEN_SLEEPP_SHIFT 3
164 #define PUADEN_PWRHOLDP_MASK 0x04 167 #define PUADEN_PWRHOLDP_MASK 0x04
165 #define PUADEN_PWRHOLDP_SHIFT 2 168 #define PUADEN_PWRHOLDP_SHIFT 2
166 #define PUADEN_BOOT1P_MASK 0x02 169 #define PUADEN_BOOT1P_MASK 0x02
167 #define PUADEN_BOOT1P_SHIFT 1 170 #define PUADEN_BOOT1P_SHIFT 1
168 #define PUADEN_BOOT0P_MASK 0x01 171 #define PUADEN_BOOT0P_MASK 0x01
169 #define PUADEN_BOOT0P_SHIFT 0 172 #define PUADEN_BOOT0P_SHIFT 0
170 173
171 174
172 /*Register REF (0x80) register.RegisterDescription */ 175 /*Register REF (0x80) register.RegisterDescription */
173 #define REF_VMBCH_SEL_MASK 0x0C 176 #define REF_VMBCH_SEL_MASK 0x0C
174 #define REF_VMBCH_SEL_SHIFT 2 177 #define REF_VMBCH_SEL_SHIFT 2
175 #define REF_ST_MASK 0x03 178 #define REF_ST_MASK 0x03
176 #define REF_ST_SHIFT 0 179 #define REF_ST_SHIFT 0
177 180
178 181
179 /*Register VRTC (0x80) register.RegisterDescription */ 182 /*Register VRTC (0x80) register.RegisterDescription */
180 #define VRTC_VRTC_OFFMASK_MASK 0x08 183 #define VRTC_VRTC_OFFMASK_MASK 0x08
181 #define VRTC_VRTC_OFFMASK_SHIFT 3 184 #define VRTC_VRTC_OFFMASK_SHIFT 3
182 #define VRTC_ST_MASK 0x03 185 #define VRTC_ST_MASK 0x03
183 #define VRTC_ST_SHIFT 0 186 #define VRTC_ST_SHIFT 0
184 187
185 188
186 /*Register VIO (0x80) register.RegisterDescription */ 189 /*Register VIO (0x80) register.RegisterDescription */
187 #define VIO_ILMAX_MASK 0xC0 190 #define VIO_ILMAX_MASK 0xC0
188 #define VIO_ILMAX_SHIFT 6 191 #define VIO_ILMAX_SHIFT 6
189 #define VIO_SEL_MASK 0x0C 192 #define VIO_SEL_MASK 0x0C
190 #define VIO_SEL_SHIFT 2 193 #define VIO_SEL_SHIFT 2
191 #define VIO_ST_MASK 0x03 194 #define VIO_ST_MASK 0x03
192 #define VIO_ST_SHIFT 0 195 #define VIO_ST_SHIFT 0
193 196
194 197
195 /*Register VDD1 (0x80) register.RegisterDescription */ 198 /*Register VDD1 (0x80) register.RegisterDescription */
196 #define VDD1_VGAIN_SEL_MASK 0xC0 199 #define VDD1_VGAIN_SEL_MASK 0xC0
197 #define VDD1_VGAIN_SEL_SHIFT 6 200 #define VDD1_VGAIN_SEL_SHIFT 6
198 #define VDD1_ILMAX_MASK 0x20 201 #define VDD1_ILMAX_MASK 0x20
199 #define VDD1_ILMAX_SHIFT 5 202 #define VDD1_ILMAX_SHIFT 5
200 #define VDD1_TSTEP_MASK 0x1C 203 #define VDD1_TSTEP_MASK 0x1C
201 #define VDD1_TSTEP_SHIFT 2 204 #define VDD1_TSTEP_SHIFT 2
202 #define VDD1_ST_MASK 0x03 205 #define VDD1_ST_MASK 0x03
203 #define VDD1_ST_SHIFT 0 206 #define VDD1_ST_SHIFT 0
204 207
205 208
206 /*Register VDD1_OP (0x80) register.RegisterDescription */ 209 /*Register VDD1_OP (0x80) register.RegisterDescription */
207 #define VDD1_OP_CMD_MASK 0x80 210 #define VDD1_OP_CMD_MASK 0x80
208 #define VDD1_OP_CMD_SHIFT 7 211 #define VDD1_OP_CMD_SHIFT 7
209 #define VDD1_OP_SEL_MASK 0x7F 212 #define VDD1_OP_SEL_MASK 0x7F
210 #define VDD1_OP_SEL_SHIFT 0 213 #define VDD1_OP_SEL_SHIFT 0
211 214
212 215
213 /*Register VDD1_SR (0x80) register.RegisterDescription */ 216 /*Register VDD1_SR (0x80) register.RegisterDescription */
214 #define VDD1_SR_SEL_MASK 0x7F 217 #define VDD1_SR_SEL_MASK 0x7F
215 #define VDD1_SR_SEL_SHIFT 0 218 #define VDD1_SR_SEL_SHIFT 0
216 219
217 220
218 /*Register VDD2 (0x80) register.RegisterDescription */ 221 /*Register VDD2 (0x80) register.RegisterDescription */
219 #define VDD2_VGAIN_SEL_MASK 0xC0 222 #define VDD2_VGAIN_SEL_MASK 0xC0
220 #define VDD2_VGAIN_SEL_SHIFT 6 223 #define VDD2_VGAIN_SEL_SHIFT 6
221 #define VDD2_ILMAX_MASK 0x20 224 #define VDD2_ILMAX_MASK 0x20
222 #define VDD2_ILMAX_SHIFT 5 225 #define VDD2_ILMAX_SHIFT 5
223 #define VDD2_TSTEP_MASK 0x1C 226 #define VDD2_TSTEP_MASK 0x1C
224 #define VDD2_TSTEP_SHIFT 2 227 #define VDD2_TSTEP_SHIFT 2
225 #define VDD2_ST_MASK 0x03 228 #define VDD2_ST_MASK 0x03
226 #define VDD2_ST_SHIFT 0 229 #define VDD2_ST_SHIFT 0
227 230
228 231
229 /*Register VDD2_OP (0x80) register.RegisterDescription */ 232 /*Register VDD2_OP (0x80) register.RegisterDescription */
230 #define VDD2_OP_CMD_MASK 0x80 233 #define VDD2_OP_CMD_MASK 0x80
231 #define VDD2_OP_CMD_SHIFT 7 234 #define VDD2_OP_CMD_SHIFT 7
232 #define VDD2_OP_SEL_MASK 0x7F 235 #define VDD2_OP_SEL_MASK 0x7F
233 #define VDD2_OP_SEL_SHIFT 0 236 #define VDD2_OP_SEL_SHIFT 0
234 237
235 /*Register VDD2_SR (0x80) register.RegisterDescription */ 238 /*Register VDD2_SR (0x80) register.RegisterDescription */
236 #define VDD2_SR_SEL_MASK 0x7F 239 #define VDD2_SR_SEL_MASK 0x7F
237 #define VDD2_SR_SEL_SHIFT 0 240 #define VDD2_SR_SEL_SHIFT 0
238 241
239 242
240 /*Registers VDD1, VDD2 voltage values definitions */ 243 /*Registers VDD1, VDD2 voltage values definitions */
241 #define VDD1_2_NUM_VOLTS 73 244 #define VDD1_2_NUM_VOLTS 73
242 #define VDD1_2_MIN_VOLT 6000 245 #define VDD1_2_MIN_VOLT 6000
243 #define VDD1_2_OFFSET 125 246 #define VDD1_2_OFFSET 125
244 247
245 248
246 /*Register VDD3 (0x80) register.RegisterDescription */ 249 /*Register VDD3 (0x80) register.RegisterDescription */
247 #define VDD3_CKINEN_MASK 0x04 250 #define VDD3_CKINEN_MASK 0x04
248 #define VDD3_CKINEN_SHIFT 2 251 #define VDD3_CKINEN_SHIFT 2
249 #define VDD3_ST_MASK 0x03 252 #define VDD3_ST_MASK 0x03
250 #define VDD3_ST_SHIFT 0 253 #define VDD3_ST_SHIFT 0
251 #define VDDCTRL_MIN_VOLT 6000 254 #define VDDCTRL_MIN_VOLT 6000
252 #define VDDCTRL_OFFSET 125 255 #define VDDCTRL_OFFSET 125
253 256
254 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 257 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */
255 #define LDO_SEL_MASK 0x0C 258 #define LDO_SEL_MASK 0x0C
256 #define LDO_SEL_SHIFT 2 259 #define LDO_SEL_SHIFT 2
257 #define LDO_ST_MASK 0x03 260 #define LDO_ST_MASK 0x03
258 #define LDO_ST_SHIFT 0 261 #define LDO_ST_SHIFT 0
259 #define LDO_ST_ON_BIT 0x01 262 #define LDO_ST_ON_BIT 0x01
260 #define LDO_ST_MODE_BIT 0x02 263 #define LDO_ST_MODE_BIT 0x02
261 264
262 265
263 /* Registers LDO1 to LDO8 in tps65910 */ 266 /* Registers LDO1 to LDO8 in tps65910 */
264 #define LDO1_SEL_MASK 0xFC 267 #define LDO1_SEL_MASK 0xFC
265 #define LDO3_SEL_MASK 0x7C 268 #define LDO3_SEL_MASK 0x7C
266 #define LDO_MIN_VOLT 1000 269 #define LDO_MIN_VOLT 1000
267 #define LDO_MAX_VOLT 3300; 270 #define LDO_MAX_VOLT 3300;
268 271
269 272
270 /*Register VDIG1 (0x80) register.RegisterDescription */ 273 /*Register VDIG1 (0x80) register.RegisterDescription */
271 #define VDIG1_SEL_MASK 0x0C 274 #define VDIG1_SEL_MASK 0x0C
272 #define VDIG1_SEL_SHIFT 2 275 #define VDIG1_SEL_SHIFT 2
273 #define VDIG1_ST_MASK 0x03 276 #define VDIG1_ST_MASK 0x03
274 #define VDIG1_ST_SHIFT 0 277 #define VDIG1_ST_SHIFT 0
275 278
276 279
277 /*Register VDIG2 (0x80) register.RegisterDescription */ 280 /*Register VDIG2 (0x80) register.RegisterDescription */
278 #define VDIG2_SEL_MASK 0x0C 281 #define VDIG2_SEL_MASK 0x0C
279 #define VDIG2_SEL_SHIFT 2 282 #define VDIG2_SEL_SHIFT 2
280 #define VDIG2_ST_MASK 0x03 283 #define VDIG2_ST_MASK 0x03
281 #define VDIG2_ST_SHIFT 0 284 #define VDIG2_ST_SHIFT 0
282 285
283 286
284 /*Register VAUX1 (0x80) register.RegisterDescription */ 287 /*Register VAUX1 (0x80) register.RegisterDescription */
285 #define VAUX1_SEL_MASK 0x0C 288 #define VAUX1_SEL_MASK 0x0C
286 #define VAUX1_SEL_SHIFT 2 289 #define VAUX1_SEL_SHIFT 2
287 #define VAUX1_ST_MASK 0x03 290 #define VAUX1_ST_MASK 0x03
288 #define VAUX1_ST_SHIFT 0 291 #define VAUX1_ST_SHIFT 0
289 292
290 293
291 /*Register VAUX2 (0x80) register.RegisterDescription */ 294 /*Register VAUX2 (0x80) register.RegisterDescription */
292 #define VAUX2_SEL_MASK 0x0C 295 #define VAUX2_SEL_MASK 0x0C
293 #define VAUX2_SEL_SHIFT 2 296 #define VAUX2_SEL_SHIFT 2
294 #define VAUX2_ST_MASK 0x03 297 #define VAUX2_ST_MASK 0x03
295 #define VAUX2_ST_SHIFT 0 298 #define VAUX2_ST_SHIFT 0
296 299
297 300
298 /*Register VAUX33 (0x80) register.RegisterDescription */ 301 /*Register VAUX33 (0x80) register.RegisterDescription */
299 #define VAUX33_SEL_MASK 0x0C 302 #define VAUX33_SEL_MASK 0x0C
300 #define VAUX33_SEL_SHIFT 2 303 #define VAUX33_SEL_SHIFT 2
301 #define VAUX33_ST_MASK 0x03 304 #define VAUX33_ST_MASK 0x03
302 #define VAUX33_ST_SHIFT 0 305 #define VAUX33_ST_SHIFT 0
303 306
304 307
305 /*Register VMMC (0x80) register.RegisterDescription */ 308 /*Register VMMC (0x80) register.RegisterDescription */
306 #define VMMC_SEL_MASK 0x0C 309 #define VMMC_SEL_MASK 0x0C
307 #define VMMC_SEL_SHIFT 2 310 #define VMMC_SEL_SHIFT 2
308 #define VMMC_ST_MASK 0x03 311 #define VMMC_ST_MASK 0x03
309 #define VMMC_ST_SHIFT 0 312 #define VMMC_ST_SHIFT 0
310 313
311 314
312 /*Register VPLL (0x80) register.RegisterDescription */ 315 /*Register VPLL (0x80) register.RegisterDescription */
313 #define VPLL_SEL_MASK 0x0C 316 #define VPLL_SEL_MASK 0x0C
314 #define VPLL_SEL_SHIFT 2 317 #define VPLL_SEL_SHIFT 2
315 #define VPLL_ST_MASK 0x03 318 #define VPLL_ST_MASK 0x03
316 #define VPLL_ST_SHIFT 0 319 #define VPLL_ST_SHIFT 0
317 320
318 321
319 /*Register VDAC (0x80) register.RegisterDescription */ 322 /*Register VDAC (0x80) register.RegisterDescription */
320 #define VDAC_SEL_MASK 0x0C 323 #define VDAC_SEL_MASK 0x0C
321 #define VDAC_SEL_SHIFT 2 324 #define VDAC_SEL_SHIFT 2
322 #define VDAC_ST_MASK 0x03 325 #define VDAC_ST_MASK 0x03
323 #define VDAC_ST_SHIFT 0 326 #define VDAC_ST_SHIFT 0
324 327
325 328
326 /*Register THERM (0x80) register.RegisterDescription */ 329 /*Register THERM (0x80) register.RegisterDescription */
327 #define THERM_THERM_HD_MASK 0x20 330 #define THERM_THERM_HD_MASK 0x20
328 #define THERM_THERM_HD_SHIFT 5 331 #define THERM_THERM_HD_SHIFT 5
329 #define THERM_THERM_TS_MASK 0x10 332 #define THERM_THERM_TS_MASK 0x10
330 #define THERM_THERM_TS_SHIFT 4 333 #define THERM_THERM_TS_SHIFT 4
331 #define THERM_THERM_HDSEL_MASK 0x0C 334 #define THERM_THERM_HDSEL_MASK 0x0C
332 #define THERM_THERM_HDSEL_SHIFT 2 335 #define THERM_THERM_HDSEL_SHIFT 2
333 #define THERM_RSVD1_MASK 0x02 336 #define THERM_RSVD1_MASK 0x02
334 #define THERM_RSVD1_SHIFT 1 337 #define THERM_RSVD1_SHIFT 1
335 #define THERM_THERM_STATE_MASK 0x01 338 #define THERM_THERM_STATE_MASK 0x01
336 #define THERM_THERM_STATE_SHIFT 0 339 #define THERM_THERM_STATE_SHIFT 0
337 340
338 341
339 /*Register BBCH (0x80) register.RegisterDescription */ 342 /*Register BBCH (0x80) register.RegisterDescription */
340 #define BBCH_BBSEL_MASK 0x06 343 #define BBCH_BBSEL_MASK 0x06
341 #define BBCH_BBSEL_SHIFT 1 344 #define BBCH_BBSEL_SHIFT 1
342 #define BBCH_BBCHEN_MASK 0x01 345 #define BBCH_BBCHEN_MASK 0x01
343 #define BBCH_BBCHEN_SHIFT 0 346 #define BBCH_BBCHEN_SHIFT 0
344 347
345 348
346 /*Register DCDCCTRL (0x80) register.RegisterDescription */ 349 /*Register DCDCCTRL (0x80) register.RegisterDescription */
347 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20 350 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20
348 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5 351 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5
349 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10 352 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10
350 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4 353 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4
351 #define DCDCCTRL_VIO_PSKIP_MASK 0x08 354 #define DCDCCTRL_VIO_PSKIP_MASK 0x08
352 #define DCDCCTRL_VIO_PSKIP_SHIFT 3 355 #define DCDCCTRL_VIO_PSKIP_SHIFT 3
353 #define DCDCCTRL_DCDCCKEXT_MASK 0x04 356 #define DCDCCTRL_DCDCCKEXT_MASK 0x04
354 #define DCDCCTRL_DCDCCKEXT_SHIFT 2 357 #define DCDCCTRL_DCDCCKEXT_SHIFT 2
355 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03 358 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03
356 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 359 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0
357 360
358 361
359 /*Register DEVCTRL (0x80) register.RegisterDescription */ 362 /*Register DEVCTRL (0x80) register.RegisterDescription */
360 #define DEVCTRL_RTC_PWDN_MASK 0x40 363 #define DEVCTRL_RTC_PWDN_MASK 0x40
361 #define DEVCTRL_RTC_PWDN_SHIFT 6 364 #define DEVCTRL_RTC_PWDN_SHIFT 6
362 #define DEVCTRL_CK32K_CTRL_MASK 0x20 365 #define DEVCTRL_CK32K_CTRL_MASK 0x20
363 #define DEVCTRL_CK32K_CTRL_SHIFT 5 366 #define DEVCTRL_CK32K_CTRL_SHIFT 5
364 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 367 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
365 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 368 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4
366 #define DEVCTRL_DEV_OFF_RST_MASK 0x08 369 #define DEVCTRL_DEV_OFF_RST_MASK 0x08
367 #define DEVCTRL_DEV_OFF_RST_SHIFT 3 370 #define DEVCTRL_DEV_OFF_RST_SHIFT 3
368 #define DEVCTRL_DEV_ON_MASK 0x04 371 #define DEVCTRL_DEV_ON_MASK 0x04
369 #define DEVCTRL_DEV_ON_SHIFT 2 372 #define DEVCTRL_DEV_ON_SHIFT 2
370 #define DEVCTRL_DEV_SLP_MASK 0x02 373 #define DEVCTRL_DEV_SLP_MASK 0x02
371 #define DEVCTRL_DEV_SLP_SHIFT 1 374 #define DEVCTRL_DEV_SLP_SHIFT 1
372 #define DEVCTRL_DEV_OFF_MASK 0x01 375 #define DEVCTRL_DEV_OFF_MASK 0x01
373 #define DEVCTRL_DEV_OFF_SHIFT 0 376 #define DEVCTRL_DEV_OFF_SHIFT 0
374 377
375 378
376 /*Register DEVCTRL2 (0x80) register.RegisterDescription */ 379 /*Register DEVCTRL2 (0x80) register.RegisterDescription */
377 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 380 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
378 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 381 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
379 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 382 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
380 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 383 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3
381 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04 384 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04
382 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2 385 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2
383 #define DEVCTRL2_PWON_LP_RST_MASK 0x02 386 #define DEVCTRL2_PWON_LP_RST_MASK 0x02
384 #define DEVCTRL2_PWON_LP_RST_SHIFT 1 387 #define DEVCTRL2_PWON_LP_RST_SHIFT 1
385 #define DEVCTRL2_IT_POL_MASK 0x01 388 #define DEVCTRL2_IT_POL_MASK 0x01
386 #define DEVCTRL2_IT_POL_SHIFT 0 389 #define DEVCTRL2_IT_POL_SHIFT 0
387 390
388 391
389 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 392 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
390 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 393 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
391 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 394 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
392 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 395 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
393 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 396 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6
394 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 397 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
395 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 398 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5
396 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 399 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
397 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 400 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4
398 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 401 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
399 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 402 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3
400 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 403 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
401 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 404 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2
402 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 405 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
403 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 406 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1
404 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 407 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
405 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 408 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
406 409
407 410
408 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 411 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
409 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 412 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
410 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 413 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
411 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 414 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
412 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 415 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6
413 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 416 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
414 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 417 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5
415 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 418 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
416 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 419 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4
417 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 420 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
418 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 421 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3
419 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 422 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
420 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 423 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2
421 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 424 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
422 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 425 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1
423 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 426 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
424 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 427 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
425 428
426 429
427 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 430 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
428 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 431 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
429 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 432 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
430 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 433 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
431 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 434 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6
432 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 435 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
433 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 436 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5
434 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 437 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
435 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 438 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4
436 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 439 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
437 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 440 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3
438 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 441 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
439 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 442 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2
440 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 443 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
441 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 444 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1
442 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 445 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
443 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 446 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
444 447
445 448
446 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 449 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
447 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 450 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
448 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 451 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
449 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 452 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
450 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 453 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5
451 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 454 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
452 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 455 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4
453 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 456 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
454 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 457 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3
455 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 458 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
456 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 459 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2
457 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 460 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
458 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 461 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1
459 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 462 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
460 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 463 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
461 464
462 465
463 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 466 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
464 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 467 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
465 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 468 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
466 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 469 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
467 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 470 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6
468 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 471 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
469 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 472 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5
470 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 473 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
471 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 474 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4
472 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 475 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
473 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 476 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3
474 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 477 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
475 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 478 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2
476 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 479 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
477 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 480 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1
478 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 481 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
479 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 482 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
480 483
481 484
482 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 485 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
483 #define EN1_SMPS_ASS_RSVD_MASK 0xE0 486 #define EN1_SMPS_ASS_RSVD_MASK 0xE0
484 #define EN1_SMPS_ASS_RSVD_SHIFT 5 487 #define EN1_SMPS_ASS_RSVD_SHIFT 5
485 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 488 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
486 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 489 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4
487 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 490 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
488 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 491 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3
489 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 492 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
490 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 493 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2
491 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 494 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
492 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 495 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1
493 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 496 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
494 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 497 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
495 498
496 499
497 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 500 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
498 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 501 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
499 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 502 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
500 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 503 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
501 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 504 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6
502 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 505 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
503 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 506 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5
504 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 507 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
505 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 508 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4
506 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 509 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
507 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 510 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3
508 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 511 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
509 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 512 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2
510 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 513 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
511 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 514 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1
512 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 515 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
513 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 516 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
514 517
515 518
516 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 519 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
517 #define EN2_SMPS_ASS_RSVD_MASK 0xE0 520 #define EN2_SMPS_ASS_RSVD_MASK 0xE0
518 #define EN2_SMPS_ASS_RSVD_SHIFT 5 521 #define EN2_SMPS_ASS_RSVD_SHIFT 5
519 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 522 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
520 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 523 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4
521 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 524 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
522 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 525 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3
523 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 526 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
524 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 527 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2
525 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 528 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
526 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 529 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1
527 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 530 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
528 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 531 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
529 532
530 533
531 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 534 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
532 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 535 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
533 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 536 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7
534 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 537 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
535 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 538 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6
536 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 539 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
537 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 540 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5
538 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 541 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
539 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 542 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4
540 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 543 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
541 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 544 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3
542 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 545 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
543 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 546 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2
544 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 547 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
545 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 548 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1
546 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 549 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
547 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 550 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
548 551
549 552
550 /*Register SPARE (0x80) register.RegisterDescription */ 553 /*Register SPARE (0x80) register.RegisterDescription */
551 #define SPARE_SPARE_MASK 0xFF 554 #define SPARE_SPARE_MASK 0xFF
552 #define SPARE_SPARE_SHIFT 0 555 #define SPARE_SPARE_SHIFT 0
553 556
554 557
555 /*Register INT_STS (0x80) register.RegisterDescription */ 558 /*Register INT_STS (0x80) register.RegisterDescription */
556 #define INT_STS_RTC_PERIOD_IT_MASK 0x80 559 #define INT_STS_RTC_PERIOD_IT_MASK 0x80
557 #define INT_STS_RTC_PERIOD_IT_SHIFT 7 560 #define INT_STS_RTC_PERIOD_IT_SHIFT 7
558 #define INT_STS_RTC_ALARM_IT_MASK 0x40 561 #define INT_STS_RTC_ALARM_IT_MASK 0x40
559 #define INT_STS_RTC_ALARM_IT_SHIFT 6 562 #define INT_STS_RTC_ALARM_IT_SHIFT 6
560 #define INT_STS_HOTDIE_IT_MASK 0x20 563 #define INT_STS_HOTDIE_IT_MASK 0x20
561 #define INT_STS_HOTDIE_IT_SHIFT 5 564 #define INT_STS_HOTDIE_IT_SHIFT 5
562 #define INT_STS_PWRHOLD_IT_MASK 0x10 565 #define INT_STS_PWRHOLD_IT_MASK 0x10
563 #define INT_STS_PWRHOLD_IT_SHIFT 4 566 #define INT_STS_PWRHOLD_IT_SHIFT 4
564 #define INT_STS_PWRON_LP_IT_MASK 0x08 567 #define INT_STS_PWRON_LP_IT_MASK 0x08
565 #define INT_STS_PWRON_LP_IT_SHIFT 3 568 #define INT_STS_PWRON_LP_IT_SHIFT 3
566 #define INT_STS_PWRON_IT_MASK 0x04 569 #define INT_STS_PWRON_IT_MASK 0x04
567 #define INT_STS_PWRON_IT_SHIFT 2 570 #define INT_STS_PWRON_IT_SHIFT 2
568 #define INT_STS_VMBHI_IT_MASK 0x02 571 #define INT_STS_VMBHI_IT_MASK 0x02
569 #define INT_STS_VMBHI_IT_SHIFT 1 572 #define INT_STS_VMBHI_IT_SHIFT 1
570 #define INT_STS_VMBDCH_IT_MASK 0x01 573 #define INT_STS_VMBDCH_IT_MASK 0x01
571 #define INT_STS_VMBDCH_IT_SHIFT 0 574 #define INT_STS_VMBDCH_IT_SHIFT 0
572 575
573 576
574 /*Register INT_MSK (0x80) register.RegisterDescription */ 577 /*Register INT_MSK (0x80) register.RegisterDescription */
575 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 578 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
576 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 579 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
577 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 580 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
578 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 581 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
579 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 582 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
580 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 583 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
581 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 584 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
582 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 585 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
583 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 586 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
584 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 587 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
585 #define INT_MSK_PWRON_IT_MSK_MASK 0x04 588 #define INT_MSK_PWRON_IT_MSK_MASK 0x04
586 #define INT_MSK_PWRON_IT_MSK_SHIFT 2 589 #define INT_MSK_PWRON_IT_MSK_SHIFT 2
587 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02 590 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02
588 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1 591 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1
589 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 592 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01
590 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 593 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0
591 594
592 595
593 /*Register INT_STS2 (0x80) register.RegisterDescription */ 596 /*Register INT_STS2 (0x80) register.RegisterDescription */
594 #define INT_STS2_GPIO3_F_IT_MASK 0x80 597 #define INT_STS2_GPIO3_F_IT_MASK 0x80
595 #define INT_STS2_GPIO3_F_IT_SHIFT 7 598 #define INT_STS2_GPIO3_F_IT_SHIFT 7
596 #define INT_STS2_GPIO3_R_IT_MASK 0x40 599 #define INT_STS2_GPIO3_R_IT_MASK 0x40
597 #define INT_STS2_GPIO3_R_IT_SHIFT 6 600 #define INT_STS2_GPIO3_R_IT_SHIFT 6
598 #define INT_STS2_GPIO2_F_IT_MASK 0x20 601 #define INT_STS2_GPIO2_F_IT_MASK 0x20
599 #define INT_STS2_GPIO2_F_IT_SHIFT 5 602 #define INT_STS2_GPIO2_F_IT_SHIFT 5
600 #define INT_STS2_GPIO2_R_IT_MASK 0x10 603 #define INT_STS2_GPIO2_R_IT_MASK 0x10
601 #define INT_STS2_GPIO2_R_IT_SHIFT 4 604 #define INT_STS2_GPIO2_R_IT_SHIFT 4
602 #define INT_STS2_GPIO1_F_IT_MASK 0x08 605 #define INT_STS2_GPIO1_F_IT_MASK 0x08
603 #define INT_STS2_GPIO1_F_IT_SHIFT 3 606 #define INT_STS2_GPIO1_F_IT_SHIFT 3
604 #define INT_STS2_GPIO1_R_IT_MASK 0x04 607 #define INT_STS2_GPIO1_R_IT_MASK 0x04
605 #define INT_STS2_GPIO1_R_IT_SHIFT 2 608 #define INT_STS2_GPIO1_R_IT_SHIFT 2
606 #define INT_STS2_GPIO0_F_IT_MASK 0x02 609 #define INT_STS2_GPIO0_F_IT_MASK 0x02
607 #define INT_STS2_GPIO0_F_IT_SHIFT 1 610 #define INT_STS2_GPIO0_F_IT_SHIFT 1
608 #define INT_STS2_GPIO0_R_IT_MASK 0x01 611 #define INT_STS2_GPIO0_R_IT_MASK 0x01
609 #define INT_STS2_GPIO0_R_IT_SHIFT 0 612 #define INT_STS2_GPIO0_R_IT_SHIFT 0
610 613
611 614
612 /*Register INT_MSK2 (0x80) register.RegisterDescription */ 615 /*Register INT_MSK2 (0x80) register.RegisterDescription */
613 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 616 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
614 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 617 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7
615 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 618 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
616 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 619 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6
617 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 620 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
618 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 621 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5
619 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 622 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
620 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 623 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4
621 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 624 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
622 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 625 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3
623 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 626 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
624 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 627 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2
625 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 628 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
626 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 629 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1
627 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 630 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
628 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 631 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
629 632
630 633
631 /*Register INT_STS3 (0x80) register.RegisterDescription */ 634 /*Register INT_STS3 (0x80) register.RegisterDescription */
632 #define INT_STS3_GPIO5_F_IT_MASK 0x08 635 #define INT_STS3_GPIO5_F_IT_MASK 0x08
633 #define INT_STS3_GPIO5_F_IT_SHIFT 3 636 #define INT_STS3_GPIO5_F_IT_SHIFT 3
634 #define INT_STS3_GPIO5_R_IT_MASK 0x04 637 #define INT_STS3_GPIO5_R_IT_MASK 0x04
635 #define INT_STS3_GPIO5_R_IT_SHIFT 2 638 #define INT_STS3_GPIO5_R_IT_SHIFT 2
636 #define INT_STS3_GPIO4_F_IT_MASK 0x02 639 #define INT_STS3_GPIO4_F_IT_MASK 0x02
637 #define INT_STS3_GPIO4_F_IT_SHIFT 1 640 #define INT_STS3_GPIO4_F_IT_SHIFT 1
638 #define INT_STS3_GPIO4_R_IT_MASK 0x01 641 #define INT_STS3_GPIO4_R_IT_MASK 0x01
639 #define INT_STS3_GPIO4_R_IT_SHIFT 0 642 #define INT_STS3_GPIO4_R_IT_SHIFT 0
640 643
641 644
642 /*Register INT_MSK3 (0x80) register.RegisterDescription */ 645 /*Register INT_MSK3 (0x80) register.RegisterDescription */
643 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 646 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
644 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 647 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
645 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 648 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
646 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 649 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2
647 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 650 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
648 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 651 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1
649 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 652 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
650 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 653 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
651 654
652 655
653 /*Register GPIO0 (0x80) register.RegisterDescription */ 656 /*Register GPIO (0x80) register.RegisterDescription */
654 #define GPIO0_GPIO_DEB_MASK 0x10 657 #define GPIO_DEB_MASK 0x10
655 #define GPIO0_GPIO_DEB_SHIFT 4 658 #define GPIO_DEB_SHIFT 4
656 #define GPIO0_GPIO_PUEN_MASK 0x08 659 #define GPIO_PUEN_MASK 0x08
657 #define GPIO0_GPIO_PUEN_SHIFT 3 660 #define GPIO_PUEN_SHIFT 3
658 #define GPIO0_GPIO_CFG_MASK 0x04 661 #define GPIO_CFG_MASK 0x04
659 #define GPIO0_GPIO_CFG_SHIFT 2 662 #define GPIO_CFG_SHIFT 2
660 #define GPIO0_GPIO_STS_MASK 0x02 663 #define GPIO_STS_MASK 0x02
661 #define GPIO0_GPIO_STS_SHIFT 1 664 #define GPIO_STS_SHIFT 1
662 #define GPIO0_GPIO_SET_MASK 0x01 665 #define GPIO_SET_MASK 0x01
663 #define GPIO0_GPIO_SET_SHIFT 0 666 #define GPIO_SET_SHIFT 0
664
665
666 /*Register GPIO1 (0x80) register.RegisterDescription */
667 #define GPIO1_GPIO_DEB_MASK 0x10
668 #define GPIO1_GPIO_DEB_SHIFT 4
669 #define GPIO1_GPIO_PUEN_MASK 0x08
670 #define GPIO1_GPIO_PUEN_SHIFT 3
671 #define GPIO1_GPIO_CFG_MASK 0x04
672 #define GPIO1_GPIO_CFG_SHIFT 2
673 #define GPIO1_GPIO_STS_MASK 0x02
674 #define GPIO1_GPIO_STS_SHIFT 1
675 #define GPIO1_GPIO_SET_MASK 0x01
676 #define GPIO1_GPIO_SET_SHIFT 0
677
678
679 /*Register GPIO2 (0x80) register.RegisterDescription */
680 #define GPIO2_GPIO_DEB_MASK 0x10
681 #define GPIO2_GPIO_DEB_SHIFT 4
682 #define GPIO2_GPIO_PUEN_MASK 0x08
683 #define GPIO2_GPIO_PUEN_SHIFT 3
684 #define GPIO2_GPIO_CFG_MASK 0x04
685 #define GPIO2_GPIO_CFG_SHIFT 2
686 #define GPIO2_GPIO_STS_MASK 0x02
687 #define GPIO2_GPIO_STS_SHIFT 1
688 #define GPIO2_GPIO_SET_MASK 0x01
689 #define GPIO2_GPIO_SET_SHIFT 0
690
691
692 /*Register GPIO3 (0x80) register.RegisterDescription */
693 #define GPIO3_GPIO_DEB_MASK 0x10
694 #define GPIO3_GPIO_DEB_SHIFT 4
695 #define GPIO3_GPIO_PUEN_MASK 0x08
696 #define GPIO3_GPIO_PUEN_SHIFT 3
697 #define GPIO3_GPIO_CFG_MASK 0x04
698 #define GPIO3_GPIO_CFG_SHIFT 2
699 #define GPIO3_GPIO_STS_MASK 0x02
700 #define GPIO3_GPIO_STS_SHIFT 1
701 #define GPIO3_GPIO_SET_MASK 0x01
702 #define GPIO3_GPIO_SET_SHIFT 0
703
704
705 /*Register GPIO4 (0x80) register.RegisterDescription */
706 #define GPIO4_GPIO_DEB_MASK 0x10
707 #define GPIO4_GPIO_DEB_SHIFT 4
708 #define GPIO4_GPIO_PUEN_MASK 0x08
709 #define GPIO4_GPIO_PUEN_SHIFT 3
710 #define GPIO4_GPIO_CFG_MASK 0x04
711 #define GPIO4_GPIO_CFG_SHIFT 2
712 #define GPIO4_GPIO_STS_MASK 0x02
713 #define GPIO4_GPIO_STS_SHIFT 1
714 #define GPIO4_GPIO_SET_MASK 0x01
715 #define GPIO4_GPIO_SET_SHIFT 0
716
717
718 /*Register GPIO5 (0x80) register.RegisterDescription */
719 #define GPIO5_GPIO_DEB_MASK 0x10
720 #define GPIO5_GPIO_DEB_SHIFT 4
721 #define GPIO5_GPIO_PUEN_MASK 0x08
722 #define GPIO5_GPIO_PUEN_SHIFT 3
723 #define GPIO5_GPIO_CFG_MASK 0x04
724 #define GPIO5_GPIO_CFG_SHIFT 2
725 #define GPIO5_GPIO_STS_MASK 0x02
726 #define GPIO5_GPIO_STS_SHIFT 1
727 #define GPIO5_GPIO_SET_MASK 0x01
728 #define GPIO5_GPIO_SET_SHIFT 0
729 667
730 668
731 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ 669 /*Register JTAGVERNUM (0x80) register.RegisterDescription */
732 #define JTAGVERNUM_VERNUM_MASK 0x0F 670 #define JTAGVERNUM_VERNUM_MASK 0x0F
733 #define JTAGVERNUM_VERNUM_SHIFT 0 671 #define JTAGVERNUM_VERNUM_SHIFT 0
734 672
735 673
736 /* Register VDDCTRL (0x27) bit definitions */ 674 /* Register VDDCTRL (0x27) bit definitions */
737 #define VDDCTRL_ST_MASK 0x03 675 #define VDDCTRL_ST_MASK 0x03
738 #define VDDCTRL_ST_SHIFT 0 676 #define VDDCTRL_ST_SHIFT 0
739 677
740 678
741 /*Register VDDCTRL_OP (0x28) bit definitios */ 679 /*Register VDDCTRL_OP (0x28) bit definitios */
742 #define VDDCTRL_OP_CMD_MASK 0x80 680 #define VDDCTRL_OP_CMD_MASK 0x80
743 #define VDDCTRL_OP_CMD_SHIFT 7 681 #define VDDCTRL_OP_CMD_SHIFT 7
744 #define VDDCTRL_OP_SEL_MASK 0x7F 682 #define VDDCTRL_OP_SEL_MASK 0x7F
745 #define VDDCTRL_OP_SEL_SHIFT 0 683 #define VDDCTRL_OP_SEL_SHIFT 0
746 684
747 685
748 /*Register VDDCTRL_SR (0x29) bit definitions */ 686 /*Register VDDCTRL_SR (0x29) bit definitions */
749 #define VDDCTRL_SR_SEL_MASK 0x7F 687 #define VDDCTRL_SR_SEL_MASK 0x7F
750 #define VDDCTRL_SR_SEL_SHIFT 0 688 #define VDDCTRL_SR_SEL_SHIFT 0
751 689
752 690
753 /* IRQ Definitions */ 691 /* IRQ Definitions */
754 #define TPS65910_IRQ_VBAT_VMBDCH 0 692 #define TPS65910_IRQ_VBAT_VMBDCH 0
755 #define TPS65910_IRQ_VBAT_VMHI 1 693 #define TPS65910_IRQ_VBAT_VMHI 1
756 #define TPS65910_IRQ_PWRON 2 694 #define TPS65910_IRQ_PWRON 2
757 #define TPS65910_IRQ_PWRON_LP 3 695 #define TPS65910_IRQ_PWRON_LP 3
758 #define TPS65910_IRQ_PWRHOLD 4 696 #define TPS65910_IRQ_PWRHOLD 4
759 #define TPS65910_IRQ_HOTDIE 5 697 #define TPS65910_IRQ_HOTDIE 5
760 #define TPS65910_IRQ_RTC_ALARM 6 698 #define TPS65910_IRQ_RTC_ALARM 6
761 #define TPS65910_IRQ_RTC_PERIOD 7 699 #define TPS65910_IRQ_RTC_PERIOD 7
762 #define TPS65910_IRQ_GPIO_R 8 700 #define TPS65910_IRQ_GPIO_R 8
763 #define TPS65910_IRQ_GPIO_F 9 701 #define TPS65910_IRQ_GPIO_F 9
764 #define TPS65910_NUM_IRQ 10 702 #define TPS65910_NUM_IRQ 10
765 703
766 #define TPS65911_IRQ_VBAT_VMBDCH 0 704 #define TPS65911_IRQ_VBAT_VMBDCH 0
767 #define TPS65911_IRQ_VBAT_VMBDCH2L 1 705 #define TPS65911_IRQ_VBAT_VMBDCH2L 1
768 #define TPS65911_IRQ_VBAT_VMBDCH2H 2 706 #define TPS65911_IRQ_VBAT_VMBDCH2H 2
769 #define TPS65911_IRQ_VBAT_VMHI 3 707 #define TPS65911_IRQ_VBAT_VMHI 3
770 #define TPS65911_IRQ_PWRON 4 708 #define TPS65911_IRQ_PWRON 4
771 #define TPS65911_IRQ_PWRON_LP 5 709 #define TPS65911_IRQ_PWRON_LP 5
772 #define TPS65911_IRQ_PWRHOLD_F 6 710 #define TPS65911_IRQ_PWRHOLD_F 6
773 #define TPS65911_IRQ_PWRHOLD_R 7 711 #define TPS65911_IRQ_PWRHOLD_R 7
774 #define TPS65911_IRQ_HOTDIE 8 712 #define TPS65911_IRQ_HOTDIE 8
775 #define TPS65911_IRQ_RTC_ALARM 9 713 #define TPS65911_IRQ_RTC_ALARM 9
776 #define TPS65911_IRQ_RTC_PERIOD 10 714 #define TPS65911_IRQ_RTC_PERIOD 10
777 #define TPS65911_IRQ_GPIO0_R 11 715 #define TPS65911_IRQ_GPIO0_R 11
778 #define TPS65911_IRQ_GPIO0_F 12 716 #define TPS65911_IRQ_GPIO0_F 12
779 #define TPS65911_IRQ_GPIO1_R 13 717 #define TPS65911_IRQ_GPIO1_R 13
780 #define TPS65911_IRQ_GPIO1_F 14 718 #define TPS65911_IRQ_GPIO1_F 14
781 #define TPS65911_IRQ_GPIO2_R 15 719 #define TPS65911_IRQ_GPIO2_R 15
782 #define TPS65911_IRQ_GPIO2_F 16 720 #define TPS65911_IRQ_GPIO2_F 16
783 #define TPS65911_IRQ_GPIO3_R 17 721 #define TPS65911_IRQ_GPIO3_R 17
784 #define TPS65911_IRQ_GPIO3_F 18 722 #define TPS65911_IRQ_GPIO3_F 18
785 #define TPS65911_IRQ_GPIO4_R 19 723 #define TPS65911_IRQ_GPIO4_R 19
786 #define TPS65911_IRQ_GPIO4_F 20 724 #define TPS65911_IRQ_GPIO4_F 20
787 #define TPS65911_IRQ_GPIO5_R 21 725 #define TPS65911_IRQ_GPIO5_R 21
788 #define TPS65911_IRQ_GPIO5_F 22 726 #define TPS65911_IRQ_GPIO5_F 22
789 #define TPS65911_IRQ_WTCHDG 23 727 #define TPS65911_IRQ_WTCHDG 23
790 #define TPS65911_IRQ_PWRDN 24 728 #define TPS65911_IRQ_PWRDN 24
791 729
792 #define TPS65911_NUM_IRQ 25 730 #define TPS65911_NUM_IRQ 25
793 731
794 732
795 /* GPIO Register Definitions */ 733 /* GPIO Register Definitions */
796 #define TPS65910_GPIO_DEB BIT(2) 734 #define TPS65910_GPIO_DEB BIT(2)
797 #define TPS65910_GPIO_PUEN BIT(3) 735 #define TPS65910_GPIO_PUEN BIT(3)
798 #define TPS65910_GPIO_CFG BIT(2) 736 #define TPS65910_GPIO_CFG BIT(2)
799 #define TPS65910_GPIO_STS BIT(1) 737 #define TPS65910_GPIO_STS BIT(1)
800 #define TPS65910_GPIO_SET BIT(0) 738 #define TPS65910_GPIO_SET BIT(0)
801 739
802 /** 740 /**
803 * struct tps65910_board 741 * struct tps65910_board
804 * Board platform data may be used to initialize regulators. 742 * Board platform data may be used to initialize regulators.
805 */ 743 */
806 744
807 struct tps65910_board { 745 struct tps65910_board {
808 int gpio_base; 746 int gpio_base;
809 int irq; 747 int irq;
810 int irq_base; 748 int irq_base;
811 struct regulator_init_data *tps65910_pmic_init_data; 749 struct regulator_init_data *tps65910_pmic_init_data;
812 }; 750 };
813 751
814 /** 752 /**
815 * struct tps65910 - tps65910 sub-driver chip access routines 753 * struct tps65910 - tps65910 sub-driver chip access routines
816 */ 754 */
817 755
818 struct tps65910 { 756 struct tps65910 {
819 struct device *dev; 757 struct device *dev;
820 struct i2c_client *i2c_client; 758 struct i2c_client *i2c_client;
821 struct mutex io_mutex; 759 struct mutex io_mutex;
822 unsigned int id; 760 unsigned int id;
823 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); 761 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
824 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src); 762 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
825 763
826 /* Client devices */ 764 /* Client devices */
827 struct tps65910_pmic *pmic; 765 struct tps65910_pmic *pmic;
828 struct tps65910_rtc *rtc; 766 struct tps65910_rtc *rtc;
829 struct tps65910_power *power; 767 struct tps65910_power *power;
830 768
831 /* GPIO Handling */ 769 /* GPIO Handling */
832 struct gpio_chip gpio; 770 struct gpio_chip gpio;
833 771
834 /* IRQ Handling */ 772 /* IRQ Handling */
835 struct mutex irq_lock; 773 struct mutex irq_lock;
836 int chip_irq; 774 int chip_irq;
837 int irq_base; 775 int irq_base;
838 int irq_num; 776 int irq_num;
839 u32 irq_mask; 777 u32 irq_mask;
840 }; 778 };
841 779
842 struct tps65910_platform_data { 780 struct tps65910_platform_data {
843 int irq; 781 int irq;
844 int irq_base; 782 int irq_base;
845 }; 783 };
846 784
847 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 785 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
848 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 786 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
849 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); 787 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
850 int tps65910_irq_init(struct tps65910 *tps65910, int irq, 788 int tps65910_irq_init(struct tps65910 *tps65910, int irq,
851 struct tps65910_platform_data *pdata); 789 struct tps65910_platform_data *pdata);
852 790
853 static inline int tps65910_chip_id(struct tps65910 *tps65910) 791 static inline int tps65910_chip_id(struct tps65910 *tps65910)
854 { 792 {
855 return tps65910->id; 793 return tps65910->id;
856 } 794 }