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Commit 11c1965687b0a472add948d4240dfe65a2fcb298

Authored by Paul Mundt
1 parent aec5e0e1c1
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

sh: Fixup cpu_data references for the non-boot CPUs. 

There are a lot of bogus cpu_data-> references that only end up working
for the boot CPU, convert these to current_cpu_data to fixup SMP.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 20 changed files with 251 additions and 238 deletions Side-by-side Diff

arch/sh/kernel/cpu/init.c
Diff comments   View file @ 11c1965
... ... @@ -48,7 +48,7 @@
48 48 {
49 49 unsigned long ccr, flags;
50 50  
51   - if (cpu_data->type == CPU_SH_NONE)
  51 + if (current_cpu_data.type == CPU_SH_NONE)
52 52 panic("Unknown CPU");
53 53  
54 54 jump_to_P2();
... ... @@ -68,7 +68,7 @@
68 68 if (ccr & CCR_CACHE_ENABLE) {
69 69 unsigned long ways, waysize, addrstart;
70 70  
71   - waysize = cpu_data->dcache.sets;
  71 + waysize = current_cpu_data.dcache.sets;
72 72  
73 73 #ifdef CCR_CACHE_ORA
74 74 /*
... ... @@ -79,7 +79,7 @@
79 79 waysize >>= 1;
80 80 #endif
81 81  
82   - waysize <<= cpu_data->dcache.entry_shift;
  82 + waysize <<= current_cpu_data.dcache.entry_shift;
83 83  
84 84 #ifdef CCR_CACHE_EMODE
85 85 /* If EMODE is not set, we only have 1 way to flush. */
... ... @@ -87,7 +87,7 @@
87 87 ways = 1;
88 88 else
89 89 #endif
90   - ways = cpu_data->dcache.ways;
  90 + ways = current_cpu_data.dcache.ways;
91 91  
92 92 addrstart = CACHE_OC_ADDRESS_ARRAY;
93 93 do {
94 94  
... ... @@ -95,10 +95,10 @@
95 95  
96 96 for (addr = addrstart;
97 97 addr < addrstart + waysize;
98   - addr += cpu_data->dcache.linesz)
  98 + addr += current_cpu_data.dcache.linesz)
99 99 ctrl_outl(0, addr);
100 100  
101   - addrstart += cpu_data->dcache.way_incr;
  101 + addrstart += current_cpu_data.dcache.way_incr;
102 102 } while (--ways);
103 103 }
104 104  
... ... @@ -110,7 +110,7 @@
110 110  
111 111 #ifdef CCR_CACHE_EMODE
112 112 /* Force EMODE if possible */
113   - if (cpu_data->dcache.ways > 1)
  113 + if (current_cpu_data.dcache.ways > 1)
114 114 flags |= CCR_CACHE_EMODE;
115 115 else
116 116 flags &= ~CCR_CACHE_EMODE;
117 117  
... ... @@ -127,10 +127,10 @@
127 127 #ifdef CONFIG_SH_OCRAM
128 128 /* Turn on OCRAM -- halve the OC */
129 129 flags |= CCR_CACHE_ORA;
130   - cpu_data->dcache.sets >>= 1;
  130 + current_cpu_data.dcache.sets >>= 1;
131 131  
132   - cpu_data->dcache.way_size = cpu_data->dcache.sets *
133   - cpu_data->dcache.linesz;
  132 + current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
  133 + current_cpu_data.dcache.linesz;
134 134 #endif
135 135  
136 136 ctrl_outl(flags, CCR);
... ... @@ -172,7 +172,7 @@
172 172  
173 173 /* If the DSP bit is still set, this CPU has a DSP */
174 174 if (sr & SR_DSP)
175   - cpu_data->flags |= CPU_HAS_DSP;
  175 + current_cpu_data.flags |= CPU_HAS_DSP;
176 176  
177 177 /* Now that we've determined the DSP status, clear the DSP bit. */
178 178 release_dsp();
179 179  
180 180  
... ... @@ -204,18 +204,18 @@
204 204 cache_init();
205 205  
206 206 shm_align_mask = max_t(unsigned long,
207   - cpu_data->dcache.way_size - 1,
  207 + current_cpu_data.dcache.way_size - 1,
208 208 PAGE_SIZE - 1);
209 209  
210 210 /* Disable the FPU */
211 211 if (fpu_disabled) {
212 212 printk("FPU Disabled\n");
213   - cpu_data->flags &= ~CPU_HAS_FPU;
  213 + current_cpu_data.flags &= ~CPU_HAS_FPU;
214 214 disable_fpu();
215 215 }
216 216  
217 217 /* FPU initialization */
218   - if ((cpu_data->flags & CPU_HAS_FPU)) {
  218 + if ((current_cpu_data.flags & CPU_HAS_FPU)) {
219 219 clear_thread_flag(TIF_USEDFPU);
220 220 clear_used_math();
221 221 }
... ... @@ -233,7 +233,7 @@
233 233 /* Disable the DSP */
234 234 if (dsp_disabled) {
235 235 printk("DSP Disabled\n");
236   - cpu_data->flags &= ~CPU_HAS_DSP;
  236 + current_cpu_data.flags &= ~CPU_HAS_DSP;
237 237 release_dsp();
238 238 }
239 239 #endif
arch/sh/kernel/cpu/sh2/probe.c
Diff comments   View file @ 11c1965
... ... @@ -18,27 +18,27 @@
18 18 int __init detect_cpu_and_cache_system(void)
19 19 {
20 20 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
21   - cpu_data->type = CPU_SH7604;
22   - cpu_data->dcache.ways = 4;
23   - cpu_data->dcache.way_incr = (1<<10);
24   - cpu_data->dcache.sets = 64;
25   - cpu_data->dcache.entry_shift = 4;
26   - cpu_data->dcache.linesz = L1_CACHE_BYTES;
27   - cpu_data->dcache.flags = 0;
  21 + current_cpu_data.type = CPU_SH7604;
  22 + current_cpu_data.dcache.ways = 4;
  23 + current_cpu_data.dcache.way_incr = (1<<10);
  24 + current_cpu_data.dcache.sets = 64;
  25 + current_cpu_data.dcache.entry_shift = 4;
  26 + current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
  27 + current_cpu_data.dcache.flags = 0;
28 28 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
29   - cpu_data->type = CPU_SH7619;
30   - cpu_data->dcache.ways = 4;
31   - cpu_data->dcache.way_incr = (1<<12);
32   - cpu_data->dcache.sets = 256;
33   - cpu_data->dcache.entry_shift = 4;
34   - cpu_data->dcache.linesz = L1_CACHE_BYTES;
35   - cpu_data->dcache.flags = 0;
  29 + current_cpu_data.type = CPU_SH7619;
  30 + current_cpu_data.dcache.ways = 4;
  31 + current_cpu_data.dcache.way_incr = (1<<12);
  32 + current_cpu_data.dcache.sets = 256;
  33 + current_cpu_data.dcache.entry_shift = 4;
  34 + current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
  35 + current_cpu_data.dcache.flags = 0;
36 36 #endif
37 37 /*
38 38 * SH-2 doesn't have separate caches
39 39 */
40   - cpu_data->dcache.flags |= SH_CACHE_COMBINED;
41   - cpu_data->icache = cpu_data->dcache;
  40 + current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
  41 + current_cpu_data.icache = current_cpu_data.dcache;
42 42  
43 43 return 0;
44 44 }
arch/sh/kernel/cpu/sh2a/probe.c
Diff comments   View file @ 11c1965
... ... @@ -17,14 +17,14 @@
17 17 int __init detect_cpu_and_cache_system(void)
18 18 {
19 19 /* Just SH7206 for now .. */
20   - cpu_data->type = CPU_SH7206;
  20 + current_cpu_data.type = CPU_SH7206;
21 21  
22   - cpu_data->dcache.ways = 4;
23   - cpu_data->dcache.way_incr = (1 << 11);
24   - cpu_data->dcache.sets = 128;
25   - cpu_data->dcache.entry_shift = 4;
26   - cpu_data->dcache.linesz = L1_CACHE_BYTES;
27   - cpu_data->dcache.flags = 0;
  22 + current_cpu_data.dcache.ways = 4;
  23 + current_cpu_data.dcache.way_incr = (1 << 11);
  24 + current_cpu_data.dcache.sets = 128;
  25 + current_cpu_data.dcache.entry_shift = 4;
  26 + current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
  27 + current_cpu_data.dcache.flags = 0;
28 28  
29 29 /*
30 30 * The icache is the same as the dcache as far as this setup is
... ... @@ -32,7 +32,7 @@
32 32 * lacks the U bit that the dcache has, none of this has any bearing
33 33 * on the cache info.
34 34 */
35   - cpu_data->icache = cpu_data->dcache;
  35 + current_cpu_data.icache = current_cpu_data.dcache;
36 36  
37 37 return 0;
38 38 }
arch/sh/kernel/cpu/sh3/probe.c
Diff comments   View file @ 11c1965
... ... @@ -50,41 +50,41 @@
50 50  
51 51 back_to_P1();
52 52  
53   - cpu_data->dcache.ways = 4;
54   - cpu_data->dcache.entry_shift = 4;
55   - cpu_data->dcache.linesz = L1_CACHE_BYTES;
56   - cpu_data->dcache.flags = 0;
  53 + current_cpu_data.dcache.ways = 4;
  54 + current_cpu_data.dcache.entry_shift = 4;
  55 + current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
  56 + current_cpu_data.dcache.flags = 0;
57 57  
58 58 /*
59 59 * 7709A/7729 has 16K cache (256-entry), while 7702 has only
60 60 * 2K(direct) 7702 is not supported (yet)
61 61 */
62 62 if (data0 == data1 && data2 == data3) { /* Shadow */
63   - cpu_data->dcache.way_incr = (1 << 11);
64   - cpu_data->dcache.entry_mask = 0x7f0;
65   - cpu_data->dcache.sets = 128;
66   - cpu_data->type = CPU_SH7708;
  63 + current_cpu_data.dcache.way_incr = (1 << 11);
  64 + current_cpu_data.dcache.entry_mask = 0x7f0;
  65 + current_cpu_data.dcache.sets = 128;
  66 + current_cpu_data.type = CPU_SH7708;
67 67  
68   - cpu_data->flags |= CPU_HAS_MMU_PAGE_ASSOC;
  68 + current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
69 69 } else { /* 7709A or 7729 */
70   - cpu_data->dcache.way_incr = (1 << 12);
71   - cpu_data->dcache.entry_mask = 0xff0;
72   - cpu_data->dcache.sets = 256;
73   - cpu_data->type = CPU_SH7729;
  70 + current_cpu_data.dcache.way_incr = (1 << 12);
  71 + current_cpu_data.dcache.entry_mask = 0xff0;
  72 + current_cpu_data.dcache.sets = 256;
  73 + current_cpu_data.type = CPU_SH7729;
74 74  
75 75 #if defined(CONFIG_CPU_SUBTYPE_SH7706)
76   - cpu_data->type = CPU_SH7706;
  76 + current_cpu_data.type = CPU_SH7706;
77 77 #endif
78 78 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
79   - cpu_data->type = CPU_SH7710;
  79 + current_cpu_data.type = CPU_SH7710;
80 80 #endif
81 81 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
82   - cpu_data->type = CPU_SH7705;
  82 + current_cpu_data.type = CPU_SH7705;
83 83  
84 84 #if defined(CONFIG_SH7705_CACHE_32KB)
85   - cpu_data->dcache.way_incr = (1 << 13);
86   - cpu_data->dcache.entry_mask = 0x1ff0;
87   - cpu_data->dcache.sets = 512;
  85 + current_cpu_data.dcache.way_incr = (1 << 13);
  86 + current_cpu_data.dcache.entry_mask = 0x1ff0;
  87 + current_cpu_data.dcache.sets = 512;
88 88 ctrl_outl(CCR_CACHE_32KB, CCR3);
89 89 #else
90 90 ctrl_outl(CCR_CACHE_16KB, CCR3);
... ... @@ -95,8 +95,8 @@
95 95 /*
96 96 * SH-3 doesn't have separate caches
97 97 */
98   - cpu_data->dcache.flags |= SH_CACHE_COMBINED;
99   - cpu_data->icache = cpu_data->dcache;
  98 + current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
  99 + current_cpu_data.icache = current_cpu_data.dcache;
100 100  
101 101 return 0;
102 102 }
arch/sh/kernel/cpu/sh4/probe.c
Diff comments   View file @ 11c1965
... ... @@ -10,11 +10,10 @@
10 10 * License. See the file "COPYING" in the main directory of this archive
11 11 * for more details.
12 12 */
13   -
14 13 #include <linux/init.h>
  14 +#include <linux/io.h>
15 15 #include <asm/processor.h>
16 16 #include <asm/cache.h>
17   -#include <asm/io.h>
18 17  
19 18 int __init detect_cpu_and_cache_system(void)
20 19 {
21 20  
... ... @@ -36,20 +35,20 @@
36 35 /*
37 36 * Setup some sane SH-4 defaults for the icache
38 37 */
39   - cpu_data->icache.way_incr = (1 << 13);
40   - cpu_data->icache.entry_shift = 5;
41   - cpu_data->icache.sets = 256;
42   - cpu_data->icache.ways = 1;
43   - cpu_data->icache.linesz = L1_CACHE_BYTES;
  38 + current_cpu_data.icache.way_incr = (1 << 13);
  39 + current_cpu_data.icache.entry_shift = 5;
  40 + current_cpu_data.icache.sets = 256;
  41 + current_cpu_data.icache.ways = 1;
  42 + current_cpu_data.icache.linesz = L1_CACHE_BYTES;
44 43  
45 44 /*
46 45 * And again for the dcache ..
47 46 */
48   - cpu_data->dcache.way_incr = (1 << 14);
49   - cpu_data->dcache.entry_shift = 5;
50   - cpu_data->dcache.sets = 512;
51   - cpu_data->dcache.ways = 1;
52   - cpu_data->dcache.linesz = L1_CACHE_BYTES;
  47 + current_cpu_data.dcache.way_incr = (1 << 14);
  48 + current_cpu_data.dcache.entry_shift = 5;
  49 + current_cpu_data.dcache.sets = 512;
  50 + current_cpu_data.dcache.ways = 1;
  51 + current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
53 52  
54 53 /*
55 54 * Setup some generic flags we can probe
56 55  
57 56  
58 57  
... ... @@ -57,16 +56,16 @@
57 56 */
58 57 if (((pvr >> 16) & 0xff) == 0x10) {
59 58 if ((cvr & 0x02000000) == 0)
60   - cpu_data->flags |= CPU_HAS_L2_CACHE;
  59 + current_cpu_data.flags |= CPU_HAS_L2_CACHE;
61 60 if ((cvr & 0x10000000) == 0)
62   - cpu_data->flags |= CPU_HAS_DSP;
  61 + current_cpu_data.flags |= CPU_HAS_DSP;
63 62  
64   - cpu_data->flags |= CPU_HAS_LLSC;
  63 + current_cpu_data.flags |= CPU_HAS_LLSC;
65 64 }
66 65  
67 66 /* FPU detection works for everyone */
68 67 if ((cvr & 0x20000000) == 1)
69   - cpu_data->flags |= CPU_HAS_FPU;
  68 + current_cpu_data.flags |= CPU_HAS_FPU;
70 69  
71 70 /* Mask off the upper chip ID */
72 71 pvr &= 0xffff;
73 72  
74 73  
75 74  
76 75  
77 76  
78 77  
79 78  
80 79  
81 80  
82 81  
83 82  
84 83  
85 84  
86 85  
87 86  
88 87  
89 88  
90 89  
91 90  
92 91  
93 92  
94 93  
95 94  
96 95  
97 96  
98 97  
99 98  
100 99  
101 100  
102 101  
103 102  
104 103  
... ... @@ -77,147 +76,151 @@
77 76 */
78 77 switch (pvr) {
79 78 case 0x205:
80   - cpu_data->type = CPU_SH7750;
81   - cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  79 + current_cpu_data.type = CPU_SH7750;
  80 + current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
82 81 CPU_HAS_PERF_COUNTER;
83 82 break;
84 83 case 0x206:
85   - cpu_data->type = CPU_SH7750S;
86   - cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  84 + current_cpu_data.type = CPU_SH7750S;
  85 + current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
87 86 CPU_HAS_PERF_COUNTER;
88 87 break;
89 88 case 0x1100:
90   - cpu_data->type = CPU_SH7751;
91   - cpu_data->flags |= CPU_HAS_FPU;
  89 + current_cpu_data.type = CPU_SH7751;
  90 + current_cpu_data.flags |= CPU_HAS_FPU;
92 91 break;
93 92 case 0x2000:
94   - cpu_data->type = CPU_SH73180;
95   - cpu_data->icache.ways = 4;
96   - cpu_data->dcache.ways = 4;
97   - cpu_data->flags |= CPU_HAS_LLSC;
  93 + current_cpu_data.type = CPU_SH73180;
  94 + current_cpu_data.icache.ways = 4;
  95 + current_cpu_data.dcache.ways = 4;
  96 + current_cpu_data.flags |= CPU_HAS_LLSC;
98 97 break;
99 98 case 0x2001:
100 99 case 0x2004:
101   - cpu_data->type = CPU_SH7770;
102   - cpu_data->icache.ways = 4;
103   - cpu_data->dcache.ways = 4;
  100 + current_cpu_data.type = CPU_SH7770;
  101 + current_cpu_data.icache.ways = 4;
  102 + current_cpu_data.dcache.ways = 4;
104 103  
105   - cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
  104 + current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
106 105 break;
107 106 case 0x2006:
108 107 case 0x200A:
109 108 if (prr == 0x61)
110   - cpu_data->type = CPU_SH7781;
  109 + current_cpu_data.type = CPU_SH7781;
111 110 else
112   - cpu_data->type = CPU_SH7780;
  111 + current_cpu_data.type = CPU_SH7780;
113 112  
114   - cpu_data->icache.ways = 4;
115   - cpu_data->dcache.ways = 4;
  113 + current_cpu_data.icache.ways = 4;
  114 + current_cpu_data.dcache.ways = 4;
116 115  
117   - cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
  116 + current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
118 117 CPU_HAS_LLSC;
119 118 break;
120 119 case 0x3000:
121 120 case 0x3003:
122 121 case 0x3009:
123   - cpu_data->type = CPU_SH7343;
124   - cpu_data->icache.ways = 4;
125   - cpu_data->dcache.ways = 4;
126   - cpu_data->flags |= CPU_HAS_LLSC;
  122 + current_cpu_data.type = CPU_SH7343;
  123 + current_cpu_data.icache.ways = 4;
  124 + current_cpu_data.dcache.ways = 4;
  125 + current_cpu_data.flags |= CPU_HAS_LLSC;
127 126 break;
128 127 case 0x3008:
129 128 if (prr == 0xa0) {
130   - cpu_data->type = CPU_SH7722;
131   - cpu_data->icache.ways = 4;
132   - cpu_data->dcache.ways = 4;
133   - cpu_data->flags |= CPU_HAS_LLSC;
  129 + current_cpu_data.type = CPU_SH7722;
  130 + current_cpu_data.icache.ways = 4;
  131 + current_cpu_data.dcache.ways = 4;
  132 + current_cpu_data.flags |= CPU_HAS_LLSC;
134 133 }
135 134 break;
136 135 case 0x8000:
137   - cpu_data->type = CPU_ST40RA;
138   - cpu_data->flags |= CPU_HAS_FPU;
  136 + current_cpu_data.type = CPU_ST40RA;
  137 + current_cpu_data.flags |= CPU_HAS_FPU;
139 138 break;
140 139 case 0x8100:
141   - cpu_data->type = CPU_ST40GX1;
142   - cpu_data->flags |= CPU_HAS_FPU;
  140 + current_cpu_data.type = CPU_ST40GX1;
  141 + current_cpu_data.flags |= CPU_HAS_FPU;
143 142 break;
144 143 case 0x700:
145   - cpu_data->type = CPU_SH4_501;
146   - cpu_data->icache.ways = 2;
147   - cpu_data->dcache.ways = 2;
  144 + current_cpu_data.type = CPU_SH4_501;
  145 + current_cpu_data.icache.ways = 2;
  146 + current_cpu_data.dcache.ways = 2;
148 147 break;
149 148 case 0x600:
150   - cpu_data->type = CPU_SH4_202;
151   - cpu_data->icache.ways = 2;
152   - cpu_data->dcache.ways = 2;
153   - cpu_data->flags |= CPU_HAS_FPU;
  149 + current_cpu_data.type = CPU_SH4_202;
  150 + current_cpu_data.icache.ways = 2;
  151 + current_cpu_data.dcache.ways = 2;
  152 + current_cpu_data.flags |= CPU_HAS_FPU;
154 153 break;
155 154 case 0x500 ... 0x501:
156 155 switch (prr) {
157 156 case 0x10:
158   - cpu_data->type = CPU_SH7750R;
  157 + current_cpu_data.type = CPU_SH7750R;
159 158 break;
160 159 case 0x11:
161   - cpu_data->type = CPU_SH7751R;
  160 + current_cpu_data.type = CPU_SH7751R;
162 161 break;
163 162 case 0x50 ... 0x5f:
164   - cpu_data->type = CPU_SH7760;
  163 + current_cpu_data.type = CPU_SH7760;
165 164 break;
166 165 }
167 166  
168   - cpu_data->icache.ways = 2;
169   - cpu_data->dcache.ways = 2;
  167 + current_cpu_data.icache.ways = 2;
  168 + current_cpu_data.dcache.ways = 2;
170 169  
171   - cpu_data->flags |= CPU_HAS_FPU;
  170 + current_cpu_data.flags |= CPU_HAS_FPU;
172 171  
173 172 break;
174 173 default:
175   - cpu_data->type = CPU_SH_NONE;
  174 + current_cpu_data.type = CPU_SH_NONE;
176 175 break;
177 176 }
178 177  
179 178 #ifdef CONFIG_SH_DIRECT_MAPPED
180   - cpu_data->icache.ways = 1;
181   - cpu_data->dcache.ways = 1;
  179 + current_cpu_data.icache.ways = 1;
  180 + current_cpu_data.dcache.ways = 1;
182 181 #endif
183 182  
  183 +#ifdef CONFIG_CPU_HAS_PTEA
  184 + current_cpu_data.flags |= CPU_HAS_PTEA;
  185 +#endif
  186 +
184 187 /*
185 188 * On anything that's not a direct-mapped cache, look to the CVR
186 189 * for I/D-cache specifics.
187 190 */
188   - if (cpu_data->icache.ways > 1) {
  191 + if (current_cpu_data.icache.ways > 1) {
189 192 size = sizes[(cvr >> 20) & 0xf];
190   - cpu_data->icache.way_incr = (size >> 1);
191   - cpu_data->icache.sets = (size >> 6);
  193 + current_cpu_data.icache.way_incr = (size >> 1);
  194 + current_cpu_data.icache.sets = (size >> 6);
192 195  
193 196 }
194 197  
195 198 /* Setup the rest of the I-cache info */
196   - cpu_data->icache.entry_mask = cpu_data->icache.way_incr -
197   - cpu_data->icache.linesz;
  199 + current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
  200 + current_cpu_data.icache.linesz;
198 201  
199   - cpu_data->icache.way_size = cpu_data->icache.sets *
200   - cpu_data->icache.linesz;
  202 + current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
  203 + current_cpu_data.icache.linesz;
201 204  
202 205 /* And the rest of the D-cache */
203   - if (cpu_data->dcache.ways > 1) {
  206 + if (current_cpu_data.dcache.ways > 1) {
204 207 size = sizes[(cvr >> 16) & 0xf];
205   - cpu_data->dcache.way_incr = (size >> 1);
206   - cpu_data->dcache.sets = (size >> 6);
  208 + current_cpu_data.dcache.way_incr = (size >> 1);
  209 + current_cpu_data.dcache.sets = (size >> 6);
207 210 }
208 211  
209   - cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr -
210   - cpu_data->dcache.linesz;
  212 + current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
  213 + current_cpu_data.dcache.linesz;
211 214  
212   - cpu_data->dcache.way_size = cpu_data->dcache.sets *
213   - cpu_data->dcache.linesz;
  215 + current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
  216 + current_cpu_data.dcache.linesz;
214 217  
215 218 /*
216 219 * Setup the L2 cache desc
217 220 *
218 221 * SH-4A's have an optional PIPT L2.
219 222 */
220   - if (cpu_data->flags & CPU_HAS_L2_CACHE) {
  223 + if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
221 224 /*
222 225 * Size calculation is much more sensible
223 226 * than it is for the L1.
... ... @@ -228,16 +231,22 @@
228 231  
229 232 BUG_ON(!size);
230 233  
231   - cpu_data->scache.way_incr = (1 << 16);
232   - cpu_data->scache.entry_shift = 5;
233   - cpu_data->scache.ways = 4;
234   - cpu_data->scache.linesz = L1_CACHE_BYTES;
235   - cpu_data->scache.entry_mask =
236   - (cpu_data->scache.way_incr - cpu_data->scache.linesz);
237   - cpu_data->scache.sets = size /
238   - (cpu_data->scache.linesz * cpu_data->scache.ways);
239   - cpu_data->scache.way_size =
240   - (cpu_data->scache.sets * cpu_data->scache.linesz);
  234 + current_cpu_data.scache.way_incr = (1 << 16);
  235 + current_cpu_data.scache.entry_shift = 5;
  236 + current_cpu_data.scache.ways = 4;
  237 + current_cpu_data.scache.linesz = L1_CACHE_BYTES;
  238 +
  239 + current_cpu_data.scache.entry_mask =
  240 + (current_cpu_data.scache.way_incr -
  241 + current_cpu_data.scache.linesz);
  242 +
  243 + current_cpu_data.scache.sets = size /
  244 + (current_cpu_data.scache.linesz *
  245 + current_cpu_data.scache.ways);
  246 +
  247 + current_cpu_data.scache.way_size =
  248 + (current_cpu_data.scache.sets *
  249 + current_cpu_data.scache.linesz);
241 250 }
242 251  
243 252 return 0;
arch/sh/kernel/process.c
Diff comments   View file @ 11c1965
... ... @@ -293,13 +293,14 @@
293 293  
294 294 #ifdef CONFIG_MMU
295 295 /* We don't have any ASID settings for the SH-2! */
296   - if (cpu_data->type != CPU_SH7604)
  296 + if (current_cpu_data.type != CPU_SH7604)
297 297 ctrl_outb(asid, UBC_BASRA);
298 298 #endif
299 299  
300 300 ctrl_outl(0, UBC_BAMRA);
301 301  
302   - if (cpu_data->type == CPU_SH7729 || cpu_data->type == CPU_SH7710) {
  302 + if (current_cpu_data.type == CPU_SH7729 ||
  303 + current_cpu_data.type == CPU_SH7710) {
303 304 ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
304 305 ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
305 306 } else {
arch/sh/kernel/setup.c
Diff comments   View file @ 11c1965
1 1 /*
2   - * linux/arch/sh/kernel/setup.c
  2 + * arch/sh/kernel/setup.c
3 3 *
  4 + * This file handles the architecture-dependent parts of initialization
  5 + *
4 6 * Copyright (C) 1999 Niibe Yutaka
5   - * Copyright (C) 2002, 2003 Paul Mundt
  7 + * Copyright (C) 2002 - 2006 Paul Mundt
6 8 */
7   -
8   -/*
9   - * This file handles the architecture-dependent parts of initialization
10   - */
11   -
12 9 #include <linux/screen_info.h>
13 10 #include <linux/ioport.h>
14 11 #include <linux/init.h>
15 12  
... ... @@ -395,9 +392,9 @@
395 392 [CPU_SH_NONE] = "Unknown"
396 393 };
397 394  
398   -const char *get_cpu_subtype(void)
  395 +const char *get_cpu_subtype(struct sh_cpuinfo *c)
399 396 {
400   - return cpu_name[boot_cpu_data.type];
  397 + return cpu_name[c->type];
401 398 }
402 399  
403 400 #ifdef CONFIG_PROC_FS
404 401  
405 402  
... ... @@ -407,19 +404,19 @@
407 404 "ptea", "llsc", "l2", NULL
408 405 };
409 406  
410   -static void show_cpuflags(struct seq_file *m)
  407 +static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
411 408 {
412 409 unsigned long i;
413 410  
414 411 seq_printf(m, "cpu flags\t:");
415 412  
416   - if (!cpu_data->flags) {
  413 + if (!c->flags) {
417 414 seq_printf(m, " %s\n", cpu_flags[0]);
418 415 return;
419 416 }
420 417  
421 418 for (i = 0; cpu_flags[i]; i++)
422   - if ((cpu_data->flags & (1 << i)))
  419 + if ((c->flags & (1 << i)))
423 420 seq_printf(m, " %s", cpu_flags[i+1]);
424 421  
425 422 seq_printf(m, "\n");
426 423  
427 424  
428 425  
... ... @@ -441,16 +438,20 @@
441 438 */
442 439 static int show_cpuinfo(struct seq_file *m, void *v)
443 440 {
444   - unsigned int cpu = smp_processor_id();
  441 + struct sh_cpuinfo *c = v;
  442 + unsigned int cpu = c - cpu_data;
445 443  
446   - if (!cpu && cpu_online(cpu))
  444 + if (!cpu_online(cpu))
  445 + return 0;
  446 +
  447 + if (cpu == 0)
447 448 seq_printf(m, "machine\t\t: %s\n", get_system_type());
448 449  
449 450 seq_printf(m, "processor\t: %d\n", cpu);
450 451 seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
451   - seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype());
  452 + seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
452 453  
453   - show_cpuflags(m);
  454 + show_cpuflags(m, c);
454 455  
455 456 seq_printf(m, "cache type\t: ");
456 457  
457 458  
458 459  
459 460  
460 461  
... ... @@ -459,22 +460,22 @@
459 460 * unified cache on the SH-2 and SH-3, as well as the harvard
460 461 * style cache on the SH-4.
461 462 */
462   - if (boot_cpu_data.icache.flags & SH_CACHE_COMBINED) {
  463 + if (c->icache.flags & SH_CACHE_COMBINED) {
463 464 seq_printf(m, "unified\n");
464   - show_cacheinfo(m, "cache", boot_cpu_data.icache);
  465 + show_cacheinfo(m, "cache", c->icache);
465 466 } else {
466 467 seq_printf(m, "split (harvard)\n");
467   - show_cacheinfo(m, "icache", boot_cpu_data.icache);
468   - show_cacheinfo(m, "dcache", boot_cpu_data.dcache);
  468 + show_cacheinfo(m, "icache", c->icache);
  469 + show_cacheinfo(m, "dcache", c->dcache);
469 470 }
470 471  
471 472 /* Optional secondary cache */
472   - if (boot_cpu_data.flags & CPU_HAS_L2_CACHE)
473   - show_cacheinfo(m, "scache", boot_cpu_data.scache);
  473 + if (c->flags & CPU_HAS_L2_CACHE)
  474 + show_cacheinfo(m, "scache", c->scache);
474 475  
475 476 seq_printf(m, "bogomips\t: %lu.%02lu\n",
476   - boot_cpu_data.loops_per_jiffy/(500000/HZ),
477   - (boot_cpu_data.loops_per_jiffy/(5000/HZ)) % 100);
  477 + c->loops_per_jiffy/(500000/HZ),
  478 + (c->loops_per_jiffy/(5000/HZ)) % 100);
478 479  
479 480 return show_clocks(m);
480 481 }
arch/sh/kernel/signal.c
Diff comments   View file @ 11c1965
... ... @@ -127,7 +127,7 @@
127 127 {
128 128 struct task_struct *tsk = current;
129 129  
130   - if (!(cpu_data->flags & CPU_HAS_FPU))
  130 + if (!(current_cpu_data.flags & CPU_HAS_FPU))
131 131 return 0;
132 132  
133 133 set_used_math();
... ... @@ -140,7 +140,7 @@
140 140 {
141 141 struct task_struct *tsk = current;
142 142  
143   - if (!(cpu_data->flags & CPU_HAS_FPU))
  143 + if (!(current_cpu_data.flags & CPU_HAS_FPU))
144 144 return 0;
145 145  
146 146 if (!used_math()) {
... ... @@ -181,7 +181,7 @@
181 181 #undef COPY
182 182  
183 183 #ifdef CONFIG_SH_FPU
184   - if (cpu_data->flags & CPU_HAS_FPU) {
  184 + if (current_cpu_data.flags & CPU_HAS_FPU) {
185 185 int owned_fp;
186 186 struct task_struct *tsk = current;
187 187  
arch/sh/kernel/traps.c
Diff comments   View file @ 11c1965
... ... @@ -641,7 +641,7 @@
641 641 * Safe guard if DSP mode is already enabled or we're lacking
642 642 * the DSP altogether.
643 643 */
644   - if (!(cpu_data->flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
  644 + if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
645 645 return 0;
646 646  
647 647 get_user(inst, ((unsigned short *) regs->pc));
arch/sh/mm/cache-debugfs.c
Diff comments   View file @ 11c1965
... ... @@ -46,10 +46,10 @@
46 46  
47 47 if (cache_type == CACHE_TYPE_DCACHE) {
48 48 base = CACHE_OC_ADDRESS_ARRAY;
49   - cache = &cpu_data->dcache;
  49 + cache = &current_cpu_data.dcache;
50 50 } else {
51 51 base = CACHE_IC_ADDRESS_ARRAY;
52   - cache = &cpu_data->icache;
  52 + cache = &current_cpu_data.icache;
53 53 }
54 54  
55 55 /*
arch/sh/mm/cache-sh3.c
Diff comments   View file @ 11c1965
... ... @@ -44,11 +44,11 @@
44 44  
45 45 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
46 46 unsigned long addrstart = CACHE_OC_ADDRESS_ARRAY;
47   - for (j = 0; j < cpu_data->dcache.ways; j++) {
  47 + for (j = 0; j < current_cpu_data.dcache.ways; j++) {
48 48 unsigned long data, addr, p;
49 49  
50 50 p = __pa(v);
51   - addr = addrstart | (v & cpu_data->dcache.entry_mask);
  51 + addr = addrstart | (v & current_cpu_data.dcache.entry_mask);
52 52 local_irq_save(flags);
53 53 data = ctrl_inl(addr);
54 54  
... ... @@ -60,7 +60,7 @@
60 60 break;
61 61 }
62 62 local_irq_restore(flags);
63   - addrstart += cpu_data->dcache.way_incr;
  63 + addrstart += current_cpu_data.dcache.way_incr;
64 64 }
65 65 }
66 66 }
... ... @@ -85,7 +85,7 @@
85 85  
86 86 data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */
87 87 addr = CACHE_OC_ADDRESS_ARRAY |
88   - (v & cpu_data->dcache.entry_mask) | SH_CACHE_ASSOC;
  88 + (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC;
89 89 ctrl_outl(data, addr);
90 90 }
91 91 }
arch/sh/mm/cache-sh4.c
Diff comments   View file @ 11c1965
... ... @@ -54,21 +54,21 @@
54 54 ctrl_inl(CCN_CVR),
55 55 ctrl_inl(CCN_PRR));
56 56 printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
57   - cpu_data->icache.ways,
58   - cpu_data->icache.sets,
59   - cpu_data->icache.way_incr);
  57 + current_cpu_data.icache.ways,
  58 + current_cpu_data.icache.sets,
  59 + current_cpu_data.icache.way_incr);
60 60 printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
61   - cpu_data->icache.entry_mask,
62   - cpu_data->icache.alias_mask,
63   - cpu_data->icache.n_aliases);
  61 + current_cpu_data.icache.entry_mask,
  62 + current_cpu_data.icache.alias_mask,
  63 + current_cpu_data.icache.n_aliases);
64 64 printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
65   - cpu_data->dcache.ways,
66   - cpu_data->dcache.sets,
67   - cpu_data->dcache.way_incr);
  65 + current_cpu_data.dcache.ways,
  66 + current_cpu_data.dcache.sets,
  67 + current_cpu_data.dcache.way_incr);
68 68 printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
69   - cpu_data->dcache.entry_mask,
70   - cpu_data->dcache.alias_mask,
71   - cpu_data->dcache.n_aliases);
  69 + current_cpu_data.dcache.entry_mask,
  70 + current_cpu_data.dcache.alias_mask,
  71 + current_cpu_data.dcache.n_aliases);
72 72  
73 73 if (!__flush_dcache_segment_fn)
74 74 panic("unknown number of cache ways\n");
75 75  
... ... @@ -87,10 +87,10 @@
87 87 {
88 88 int i;
89 89  
90   - compute_alias(&cpu_data->icache);
91   - compute_alias(&cpu_data->dcache);
  90 + compute_alias(&current_cpu_data.icache);
  91 + compute_alias(&current_cpu_data.dcache);
92 92  
93   - switch (cpu_data->dcache.ways) {
  93 + switch (current_cpu_data.dcache.ways) {
94 94 case 1:
95 95 __flush_dcache_segment_fn = __flush_dcache_segment_1way;
96 96 break;
... ... @@ -110,7 +110,7 @@
110 110 if (ioremap_page_range(P3SEG, P3SEG + (PAGE_SIZE * 4), 0, PAGE_KERNEL))
111 111 panic("%s failed.", __FUNCTION__);
112 112  
113   - for (i = 0; i < cpu_data->dcache.n_aliases; i++)
  113 + for (i = 0; i < current_cpu_data.dcache.n_aliases; i++)
114 114 mutex_init(&p3map_mutex[i]);
115 115 }
116 116  
117 117  
... ... @@ -200,13 +200,14 @@
200 200 : /* no output */
201 201 : "m" (__m(v)));
202 202  
203   - index = CACHE_IC_ADDRESS_ARRAY | (v & cpu_data->icache.entry_mask);
  203 + index = CACHE_IC_ADDRESS_ARRAY |
  204 + (v & current_cpu_data.icache.entry_mask);
204 205  
205 206 local_irq_save(flags);
206 207 jump_to_P2();
207 208  
208   - for (i = 0; i < cpu_data->icache.ways;
209   - i++, index += cpu_data->icache.way_incr)
  209 + for (i = 0; i < current_cpu_data.icache.ways;
  210 + i++, index += current_cpu_data.icache.way_incr)
210 211 ctrl_outl(0, index); /* Clear out Valid-bit */
211 212  
212 213 back_to_P1();
... ... @@ -223,7 +224,7 @@
223 224 * All types of SH-4 require PC to be in P2 to operate on the I-cache.
224 225 * Some types of SH-4 require PC to be in P2 to operate on the D-cache.
225 226 */
226   - if ((cpu_data->flags & CPU_HAS_P2_FLUSH_BUG) ||
  227 + if ((current_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
227 228 (start < CACHE_OC_ADDRESS_ARRAY))
228 229 exec_offset = 0x20000000;
229 230  
... ... @@ -255,7 +256,7 @@
255 256 int i, n;
256 257  
257 258 /* Loop all the D-cache */
258   - n = cpu_data->dcache.n_aliases;
  259 + n = current_cpu_data.dcache.n_aliases;
259 260 for (i = 0; i < n; i++, addr += 4096)
260 261 flush_cache_4096(addr, phys);
261 262 }
... ... @@ -287,7 +288,7 @@
287 288  
288 289 void flush_dcache_all(void)
289 290 {
290   - (*__flush_dcache_segment_fn)(0UL, cpu_data->dcache.way_size);
  291 + (*__flush_dcache_segment_fn)(0UL, current_cpu_data.dcache.way_size);
291 292 wmb();
292 293 }
293 294  
... ... @@ -301,8 +302,8 @@
301 302 unsigned long end)
302 303 {
303 304 unsigned long d = 0, p = start & PAGE_MASK;
304   - unsigned long alias_mask = cpu_data->dcache.alias_mask;
305   - unsigned long n_aliases = cpu_data->dcache.n_aliases;
  305 + unsigned long alias_mask = current_cpu_data.dcache.alias_mask;
  306 + unsigned long n_aliases = current_cpu_data.dcache.n_aliases;
306 307 unsigned long select_bit;
307 308 unsigned long all_aliases_mask;
308 309 unsigned long addr_offset;
... ... @@ -389,7 +390,7 @@
389 390 * If cache is only 4k-per-way, there are never any 'aliases'. Since
390 391 * the cache is physically tagged, the data can just be left in there.
391 392 */
392   - if (cpu_data->dcache.n_aliases == 0)
  393 + if (current_cpu_data.dcache.n_aliases == 0)
393 394 return;
394 395  
395 396 /*
... ... @@ -426,7 +427,7 @@
426 427 unsigned long phys = pfn << PAGE_SHIFT;
427 428 unsigned int alias_mask;
428 429  
429   - alias_mask = cpu_data->dcache.alias_mask;
  430 + alias_mask = current_cpu_data.dcache.alias_mask;
430 431  
431 432 /* We only need to flush D-cache when we have alias */
432 433 if ((address^phys) & alias_mask) {
... ... @@ -440,7 +441,7 @@
440 441 phys);
441 442 }
442 443  
443   - alias_mask = cpu_data->icache.alias_mask;
  444 + alias_mask = current_cpu_data.icache.alias_mask;
444 445 if (vma->vm_flags & VM_EXEC) {
445 446 /*
446 447 * Evict entries from the portion of the cache from which code
... ... @@ -472,7 +473,7 @@
472 473 * If cache is only 4k-per-way, there are never any 'aliases'. Since
473 474 * the cache is physically tagged, the data can just be left in there.
474 475 */
475   - if (cpu_data->dcache.n_aliases == 0)
  476 + if (current_cpu_data.dcache.n_aliases == 0)
476 477 return;
477 478  
478 479 /*
... ... @@ -533,7 +534,7 @@
533 534 unsigned long a, ea, p;
534 535 unsigned long temp_pc;
535 536  
536   - dcache = &cpu_data->dcache;
  537 + dcache = &current_cpu_data.dcache;
537 538 /* Write this way for better assembly. */
538 539 way_count = dcache->ways;
539 540 way_incr = dcache->way_incr;
... ... @@ -608,7 +609,7 @@
608 609 base_addr = ((base_addr >> 16) << 16);
609 610 base_addr |= start;
610 611  
611   - dcache = &cpu_data->dcache;
  612 + dcache = &current_cpu_data.dcache;
612 613 linesz = dcache->linesz;
613 614 way_incr = dcache->way_incr;
614 615 way_size = dcache->way_size;
... ... @@ -650,7 +651,7 @@
650 651 base_addr = ((base_addr >> 16) << 16);
651 652 base_addr |= start;
652 653  
653   - dcache = &cpu_data->dcache;
  654 + dcache = &current_cpu_data.dcache;
654 655 linesz = dcache->linesz;
655 656 way_incr = dcache->way_incr;
656 657 way_size = dcache->way_size;
... ... @@ -709,7 +710,7 @@
709 710 base_addr = ((base_addr >> 16) << 16);
710 711 base_addr |= start;
711 712  
712   - dcache = &cpu_data->dcache;
  713 + dcache = &current_cpu_data.dcache;
713 714 linesz = dcache->linesz;
714 715 way_incr = dcache->way_incr;
715 716 way_size = dcache->way_size;
arch/sh/mm/cache-sh7705.c
Diff comments   View file @ 11c1965
... ... @@ -32,9 +32,9 @@
32 32 {
33 33 unsigned long ways, waysize, addrstart;
34 34  
35   - ways = cpu_data->dcache.ways;
36   - waysize = cpu_data->dcache.sets;
37   - waysize <<= cpu_data->dcache.entry_shift;
  35 + ways = current_cpu_data.dcache.ways;
  36 + waysize = current_cpu_data.dcache.sets;
  37 + waysize <<= current_cpu_data.dcache.entry_shift;
38 38  
39 39 addrstart = CACHE_OC_ADDRESS_ARRAY;
40 40  
... ... @@ -43,7 +43,7 @@
43 43  
44 44 for (addr = addrstart;
45 45 addr < addrstart + waysize;
46   - addr += cpu_data->dcache.linesz) {
  46 + addr += current_cpu_data.dcache.linesz) {
47 47 unsigned long data;
48 48 int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
49 49  
... ... @@ -53,7 +53,7 @@
53 53 ctrl_outl(data & ~v, addr);
54 54 }
55 55  
56   - addrstart += cpu_data->dcache.way_incr;
  56 + addrstart += current_cpu_data.dcache.way_incr;
57 57 } while (--ways);
58 58 }
59 59  
... ... @@ -93,9 +93,9 @@
93 93 local_irq_save(flags);
94 94 jump_to_P2();
95 95  
96   - ways = cpu_data->dcache.ways;
97   - waysize = cpu_data->dcache.sets;
98   - waysize <<= cpu_data->dcache.entry_shift;
  96 + ways = current_cpu_data.dcache.ways;
  97 + waysize = current_cpu_data.dcache.sets;
  98 + waysize <<= current_cpu_data.dcache.entry_shift;
99 99  
100 100 addrstart = CACHE_OC_ADDRESS_ARRAY;
101 101  
... ... @@ -104,7 +104,7 @@
104 104  
105 105 for (addr = addrstart;
106 106 addr < addrstart + waysize;
107   - addr += cpu_data->dcache.linesz) {
  107 + addr += current_cpu_data.dcache.linesz) {
108 108 unsigned long data;
109 109  
110 110 data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
... ... @@ -114,7 +114,7 @@
114 114 }
115 115 }
116 116  
117   - addrstart += cpu_data->dcache.way_incr;
  117 + addrstart += current_cpu_data.dcache.way_incr;
118 118 } while (--ways);
119 119  
120 120 back_to_P1();
... ... @@ -13,7 +13,7 @@
13 13  
14 14 extern struct mutex p3map_mutex[];
15 15  
16   -#define CACHE_ALIAS (cpu_data->dcache.alias_mask)
  16 +#define CACHE_ALIAS (current_cpu_data.dcache.alias_mask)
17 17  
18 18 /*
19 19 * clear_user_page
arch/sh/mm/pg-sh7705.c
Diff comments   View file @ 11c1965
... ... @@ -43,13 +43,13 @@
43 43  
44 44 p = __pa(p1_begin);
45 45  
46   - ways = cpu_data->dcache.ways;
  46 + ways = current_cpu_data.dcache.ways;
47 47 addr = CACHE_OC_ADDRESS_ARRAY;
48 48  
49 49 do {
50 50 unsigned long data;
51 51  
52   - addr |= (v & cpu_data->dcache.entry_mask);
  52 + addr |= (v & current_cpu_data.dcache.entry_mask);
53 53  
54 54 data = ctrl_inl(addr);
55 55 if ((data & CACHE_PHYSADDR_MASK) ==
... ... @@ -58,7 +58,7 @@
58 58 ctrl_outl(data, addr);
59 59 }
60 60  
61   - addr += cpu_data->dcache.way_incr;
  61 + addr += current_cpu_data.dcache.way_incr;
62 62 } while (--ways);
63 63  
64 64 p1_begin += L1_CACHE_BYTES;
arch/sh/mm/tlb-sh3.c
Diff comments   View file @ 11c1965
... ... @@ -26,7 +26,7 @@
26 26 addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
27 27 data = (page & 0xfffe0000) | asid; /* VALID bit is off */
28 28  
29   - if ((cpu_data->flags & CPU_HAS_MMU_PAGE_ASSOC)) {
  29 + if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
30 30 addr |= MMU_PAGE_ASSOC_BIT;
31 31 ways = 1; /* we already know the way .. */
32 32 }
arch/sh/oprofile/op_model_sh7750.c
Diff comments   View file @ 11c1965
... ... @@ -259,7 +259,7 @@
259 259  
260 260 int __init oprofile_arch_init(struct oprofile_operations **ops)
261 261 {
262   - if (!(cpu_data->flags & CPU_HAS_PERF_COUNTER))
  262 + if (!(current_cpu_data.flags & CPU_HAS_PERF_COUNTER))
263 263 return -ENODEV;
264 264  
265 265 sh7750_perf_counter_ops.cpu_type = (char *)get_cpu_subtype();
include/asm-sh/bugs.h
Diff comments   View file @ 11c1965
... ... @@ -19,9 +19,9 @@
19 19 extern unsigned long loops_per_jiffy;
20 20 char *p = &init_utsname()->machine[2]; /* "sh" */
21 21  
22   - cpu_data->loops_per_jiffy = loops_per_jiffy;
  22 + current_cpu_data.loops_per_jiffy = loops_per_jiffy;
23 23  
24   - switch (cpu_data->type) {
  24 + switch (current_cpu_data.type) {
25 25 case CPU_SH7604 ... CPU_SH7619:
26 26 *p++ = '2';
27 27 break;
... ... @@ -54,7 +54,7 @@
54 54 break;
55 55 }
56 56  
57   - printk("CPU: %s\n", get_cpu_subtype());
  57 + printk("CPU: %s\n", get_cpu_subtype(&current_cpu_data));
58 58  
59 59 #ifndef __LITTLE_ENDIAN__
60 60 /* 'eb' means 'Endian Big' */
include/asm-sh/processor.h
Diff comments   View file @ 11c1965
... ... @@ -27,8 +27,6 @@
27 27 #define CCN_CVR 0xff000040
28 28 #define CCN_PRR 0xff000044
29 29  
30   -const char *get_cpu_subtype(void);
31   -
32 30 /*
33 31 * CPU type and hardware bug flags. Kept separately for each CPU.
34 32 *
... ... @@ -288,6 +286,9 @@
288 286 #else
289 287 #define vsyscall_init() do { } while (0)
290 288 #endif
  289 +
  290 +/* arch/sh/kernel/setup.c */
  291 +const char *get_cpu_subtype(struct sh_cpuinfo *c);
291 292  
292 293 #endif /* __KERNEL__ */
293 294 #endif /* __ASM_SH_PROCESSOR_H */
include/asm-sh/ubc.h
Diff comments   View file @ 11c1965
... ... @@ -17,7 +17,7 @@
17 17 /* User Break Controller */
18 18 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
19 19 defined(CONFIG_CPU_SUBTYPE_SH7300)
20   -#define UBC_TYPE_SH7729 (cpu_data->type == CPU_SH7729)
  20 +#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
21 21 #else
22 22 #define UBC_TYPE_SH7729 0
23 23 #endif