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Commit 11ed6d5bb01c5f347fd5c47e0005f06687c66f1f

Authored by Ralf Baechle
1 parent fcdb27ad1d
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[MIPS] Rename include/asm-mips/cobalt to include/asm-mips/mach-cobalt. 

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 11 changed files with 124 additions and 124 deletions Side-by-side Diff

... ... @@ -369,7 +369,7 @@
369 369 # Cobalt Server
370 370 #
371 371 core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
372   -cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt
  372 +cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/mach-cobalt
373 373 load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
374 374  
375 375 #
arch/mips/cobalt/int-handler.S
Diff comments   View file @ 11ed6d5
... ... @@ -8,7 +8,7 @@
8 8 */
9 9 #include <asm/asm.h>
10 10 #include <asm/mipsregs.h>
11   -#include <asm/cobalt/cobalt.h>
  11 +#include <asm/mach-cobalt/cobalt.h>
12 12 #include <asm/regdef.h>
13 13 #include <asm/stackframe.h>
14 14  
arch/mips/cobalt/irq.c
Diff comments   View file @ 11ed6d5
... ... @@ -18,7 +18,7 @@
18 18 #include <asm/gt64120.h>
19 19 #include <asm/ptrace.h>
20 20  
21   -#include <asm/cobalt/cobalt.h>
  21 +#include <asm/mach-cobalt/cobalt.h>
22 22  
23 23 extern void cobalt_handle_int(void);
24 24  
arch/mips/cobalt/reset.c
Diff comments   View file @ 11ed6d5
... ... @@ -16,7 +16,7 @@
16 16 #include <asm/reboot.h>
17 17 #include <asm/system.h>
18 18 #include <asm/mipsregs.h>
19   -#include <asm/cobalt/cobalt.h>
  19 +#include <asm/mach-cobalt/cobalt.h>
20 20  
21 21 void cobalt_machine_halt(void)
22 22 {
arch/mips/cobalt/setup.c
Diff comments   View file @ 11ed6d5
... ... @@ -26,7 +26,7 @@
26 26 #include <asm/gt64120.h>
27 27 #include <asm/serial.h>
28 28  
29   -#include <asm/cobalt/cobalt.h>
  29 +#include <asm/mach-cobalt/cobalt.h>
30 30  
31 31 extern void cobalt_machine_restart(char *command);
32 32 extern void cobalt_machine_halt(void);
arch/mips/pci/fixup-cobalt.c
Diff comments   View file @ 11ed6d5
... ... @@ -17,7 +17,7 @@
17 17 #include <asm/io.h>
18 18 #include <asm/gt64120.h>
19 19  
20   -#include <asm/cobalt/cobalt.h>
  20 +#include <asm/mach-cobalt/cobalt.h>
21 21  
22 22 extern int cobalt_board_id;
23 23  
arch/mips/pci/ops-gt64111.c
Diff comments   View file @ 11ed6d5
... ... @@ -15,7 +15,7 @@
15 15 #include <asm/io.h>
16 16 #include <asm/gt64120.h>
17 17  
18   -#include <asm/cobalt/cobalt.h>
  18 +#include <asm/mach-cobalt/cobalt.h>
19 19  
20 20 /*
21 21 * Device 31 on the GT64111 is used to generate PCI special
include/asm-mips/cobalt/cobalt.h
View file @ 11ed6d5
1   -/*
2   - * Lowlevel hardware stuff for the MIPS based Cobalt microservers.
3   - *
4   - * This file is subject to the terms and conditions of the GNU General Public
5   - * License. See the file "COPYING" in the main directory of this archive
6   - * for more details.
7   - *
8   - * Copyright (C) 1997 Cobalt Microserver
9   - * Copyright (C) 1997, 2003 Ralf Baechle
10   - * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
11   - */
12   -#ifndef __ASM_COBALT_H
13   -#define __ASM_COBALT_H
14   -
15   -/*
16   - * i8259 legacy interrupts used on Cobalt:
17   - *
18   - * 8 - RTC
19   - * 9 - PCI
20   - * 14 - IDE0
21   - * 15 - IDE1
22   - */
23   -#define COBALT_QUBE_SLOT_IRQ 9
24   -
25   -/*
26   - * CPU IRQs are 16 ... 23
27   - */
28   -#define COBALT_CPU_IRQ 16
29   -
30   -#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
31   -#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */
32   -#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
33   -#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
34   -#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
35   -#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
36   -#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
37   -#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
38   -#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
39   -
40   -/*
41   - * PCI configuration space manifest constants. These are wired into
42   - * the board layout according to the PCI spec to enable the software
43   - * to probe the hardware configuration space in a well defined manner.
44   - *
45   - * The PCI_DEVSHFT() macro transforms these values into numbers
46   - * suitable for passing as the dev parameter to the various
47   - * pcibios_read/write_config routines.
48   - */
49   -#define COBALT_PCICONF_CPU 0x06
50   -#define COBALT_PCICONF_ETH0 0x07
51   -#define COBALT_PCICONF_RAQSCSI 0x08
52   -#define COBALT_PCICONF_VIA 0x09
53   -#define COBALT_PCICONF_PCISLOT 0x0A
54   -#define COBALT_PCICONF_ETH1 0x0C
55   -
56   -
57   -/*
58   - * The Cobalt board id information. The boards have an ID number wired
59   - * into the VIA that is available in the high nibble of register 94.
60   - * This register is available in the VIA configuration space through the
61   - * interface routines qube_pcibios_read/write_config. See cobalt/pci.c
62   - */
63   -#define VIA_COBALT_BRD_ID_REG 0x94
64   -#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4)
65   -#define COBALT_BRD_ID_QUBE1 0x3
66   -#define COBALT_BRD_ID_RAQ1 0x4
67   -#define COBALT_BRD_ID_QUBE2 0x5
68   -#define COBALT_BRD_ID_RAQ2 0x6
69   -
70   -/*
71   - * Galileo chipset access macros for the Cobalt. The base address for
72   - * the GT64111 chip is 0x14000000
73   - *
74   - * Most of this really should go into a separate GT64111 header file.
75   - */
76   -#define GT64111_IO_BASE 0x10000000UL
77   -#define GT64111_IO_END 0x11ffffffUL
78   -#define GT64111_MEM_BASE 0x12000000UL
79   -#define GT64111_MEM_END 0x13ffffffUL
80   -#define GT64111_BASE 0x14000000UL
81   -#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
82   -
83   -#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port))
84   -#define GALILEO_OUTL(val, port) \
85   -do { \
86   - *(volatile unsigned int *) GALILEO_REG(port) = (val); \
87   -} while (0)
88   -
89   -#define GALILEO_INTR_T0EXP (1 << 8)
90   -#define GALILEO_INTR_RETRY_CTR (1 << 20)
91   -
92   -#define GALILEO_ENTC0 0x01
93   -#define GALILEO_SELTC0 0x02
94   -
95   -#define PCI_CFG_SET(devfn,where) \
96   - GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \
97   - (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
98   -
99   -#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
100   -# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
101   -# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */
102   -# define COBALT_LED_WEB (1 << 2) /* RaQ */
103   -# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */
104   -# define COBALT_LED_RESET 0x0f
105   -
106   -#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
107   -# define COBALT_KEY_CLEAR (1 << 1)
108   -# define COBALT_KEY_LEFT (1 << 2)
109   -# define COBALT_KEY_UP (1 << 3)
110   -# define COBALT_KEY_DOWN (1 << 4)
111   -# define COBALT_KEY_RIGHT (1 << 5)
112   -# define COBALT_KEY_ENTER (1 << 6)
113   -# define COBALT_KEY_SELECT (1 << 7)
114   -# define COBALT_KEY_MASK 0xfe
115   -
116   -#endif /* __ASM_COBALT_H */
include/asm-mips/cobalt/mach-gt64120.h
View file @ 11ed6d5
1   -/* there's something here ... in the dark */
include/asm-mips/mach-cobalt/cobalt.h
Diff comments   View file @ 11ed6d5
  1 +/*
  2 + * Lowlevel hardware stuff for the MIPS based Cobalt microservers.
  3 + *
  4 + * This file is subject to the terms and conditions of the GNU General Public
  5 + * License. See the file "COPYING" in the main directory of this archive
  6 + * for more details.
  7 + *
  8 + * Copyright (C) 1997 Cobalt Microserver
  9 + * Copyright (C) 1997, 2003 Ralf Baechle
  10 + * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
  11 + */
  12 +#ifndef __ASM_COBALT_H
  13 +#define __ASM_COBALT_H
  14 +
  15 +/*
  16 + * i8259 legacy interrupts used on Cobalt:
  17 + *
  18 + * 8 - RTC
  19 + * 9 - PCI
  20 + * 14 - IDE0
  21 + * 15 - IDE1
  22 + */
  23 +#define COBALT_QUBE_SLOT_IRQ 9
  24 +
  25 +/*
  26 + * CPU IRQs are 16 ... 23
  27 + */
  28 +#define COBALT_CPU_IRQ 16
  29 +
  30 +#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
  31 +#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */
  32 +#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
  33 +#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
  34 +#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
  35 +#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
  36 +#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
  37 +#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
  38 +#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
  39 +
  40 +/*
  41 + * PCI configuration space manifest constants. These are wired into
  42 + * the board layout according to the PCI spec to enable the software
  43 + * to probe the hardware configuration space in a well defined manner.
  44 + *
  45 + * The PCI_DEVSHFT() macro transforms these values into numbers
  46 + * suitable for passing as the dev parameter to the various
  47 + * pcibios_read/write_config routines.
  48 + */
  49 +#define COBALT_PCICONF_CPU 0x06
  50 +#define COBALT_PCICONF_ETH0 0x07
  51 +#define COBALT_PCICONF_RAQSCSI 0x08
  52 +#define COBALT_PCICONF_VIA 0x09
  53 +#define COBALT_PCICONF_PCISLOT 0x0A
  54 +#define COBALT_PCICONF_ETH1 0x0C
  55 +
  56 +
  57 +/*
  58 + * The Cobalt board id information. The boards have an ID number wired
  59 + * into the VIA that is available in the high nibble of register 94.
  60 + * This register is available in the VIA configuration space through the
  61 + * interface routines qube_pcibios_read/write_config. See cobalt/pci.c
  62 + */
  63 +#define VIA_COBALT_BRD_ID_REG 0x94
  64 +#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4)
  65 +#define COBALT_BRD_ID_QUBE1 0x3
  66 +#define COBALT_BRD_ID_RAQ1 0x4
  67 +#define COBALT_BRD_ID_QUBE2 0x5
  68 +#define COBALT_BRD_ID_RAQ2 0x6
  69 +
  70 +/*
  71 + * Galileo chipset access macros for the Cobalt. The base address for
  72 + * the GT64111 chip is 0x14000000
  73 + *
  74 + * Most of this really should go into a separate GT64111 header file.
  75 + */
  76 +#define GT64111_IO_BASE 0x10000000UL
  77 +#define GT64111_IO_END 0x11ffffffUL
  78 +#define GT64111_MEM_BASE 0x12000000UL
  79 +#define GT64111_MEM_END 0x13ffffffUL
  80 +#define GT64111_BASE 0x14000000UL
  81 +#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
  82 +
  83 +#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port))
  84 +#define GALILEO_OUTL(val, port) \
  85 +do { \
  86 + *(volatile unsigned int *) GALILEO_REG(port) = (val); \
  87 +} while (0)
  88 +
  89 +#define GALILEO_INTR_T0EXP (1 << 8)
  90 +#define GALILEO_INTR_RETRY_CTR (1 << 20)
  91 +
  92 +#define GALILEO_ENTC0 0x01
  93 +#define GALILEO_SELTC0 0x02
  94 +
  95 +#define PCI_CFG_SET(devfn,where) \
  96 + GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \
  97 + (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
  98 +
  99 +#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
  100 +# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
  101 +# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */
  102 +# define COBALT_LED_WEB (1 << 2) /* RaQ */
  103 +# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */
  104 +# define COBALT_LED_RESET 0x0f
  105 +
  106 +#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
  107 +# define COBALT_KEY_CLEAR (1 << 1)
  108 +# define COBALT_KEY_LEFT (1 << 2)
  109 +# define COBALT_KEY_UP (1 << 3)
  110 +# define COBALT_KEY_DOWN (1 << 4)
  111 +# define COBALT_KEY_RIGHT (1 << 5)
  112 +# define COBALT_KEY_ENTER (1 << 6)
  113 +# define COBALT_KEY_SELECT (1 << 7)
  114 +# define COBALT_KEY_MASK 0xfe
  115 +
  116 +#endif /* __ASM_COBALT_H */
include/asm-mips/mach-cobalt/mach-gt64120.h
Diff comments   View file @ 11ed6d5
  1 +/* there's something here ... in the dark */