Commit 12eaa328f9fb2d3fcb5afb682c762690d05a3cd8
1 parent
1839794464
Exists in
master
and in
7 other branches
[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.
This is where the virtual address of the fault status area belongs. To set it up we don't make a hypervisor call, instead we call OBP's SUNW,set-trap-table with the real address of the fault status area as the second argument. And right before that call we write the virtual address into ASI_SCRATCHPAD vaddr 0x0. Signed-off-by: David S. Miller <davem@davemloft.net>
Showing 9 changed files with 144 additions and 192 deletions Side-by-side Diff
arch/sparc64/kernel/head.S
| ... | ... | @@ -521,11 +521,36 @@ |
| 521 | 521 | wrpr %g0, 15, %pil |
| 522 | 522 | |
| 523 | 523 | /* Make the firmware call to jump over to the Linux trap table. */ |
| 524 | - call prom_set_trap_table | |
| 524 | + sethi %hi(is_sun4v), %o0 | |
| 525 | + lduw [%o0 + %lo(is_sun4v)], %o0 | |
| 526 | + brz,pt %o0, 1f | |
| 527 | + nop | |
| 528 | + | |
| 529 | + TRAP_LOAD_TRAP_BLOCK(%g2, %g3) | |
| 530 | + add %g2, TRAP_PER_CPU_FAULT_INFO, %g2 | |
| 531 | + stxa %g2, [%g0] ASI_SCRATCHPAD | |
| 532 | + | |
| 533 | + /* Compute physical address: | |
| 534 | + * | |
| 535 | + * paddr = kern_base + (mmfsa_vaddr - KERNBASE) | |
| 536 | + */ | |
| 537 | + sethi %hi(KERNBASE), %g3 | |
| 538 | + sub %g2, %g3, %g2 | |
| 539 | + sethi %hi(kern_base), %g3 | |
| 540 | + ldx [%g3 + %lo(kern_base)], %g3 | |
| 541 | + add %g2, %g3, %o1 | |
| 542 | + | |
| 543 | + call prom_set_trap_table_sun4v | |
| 525 | 544 | sethi %hi(sparc64_ttable_tl0), %o0 |
| 526 | 545 | |
| 546 | + ba,pt %xcc, 2f | |
| 547 | + nop | |
| 548 | + | |
| 549 | +1: call prom_set_trap_table | |
| 550 | + sethi %hi(sparc64_ttable_tl0), %o0 | |
| 551 | + | |
| 527 | 552 | /* Start using proper page size encodings in ctx register. */ |
| 528 | - sethi %hi(sparc64_kern_pri_context), %g3 | |
| 553 | +2: sethi %hi(sparc64_kern_pri_context), %g3 | |
| 529 | 554 | ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2 |
| 530 | 555 | |
| 531 | 556 | mov PRIMARY_CONTEXT, %g1 |
arch/sparc64/kernel/sun4v_ivec.S
| ... | ... | @@ -22,11 +22,8 @@ |
| 22 | 22 | nop |
| 23 | 23 | |
| 24 | 24 | /* Get &trap_block[smp_processor_id()] into %g3. */ |
| 25 | - __GET_CPUID(%g1) | |
| 26 | - sethi %hi(trap_block), %g3 | |
| 27 | - sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g7 | |
| 28 | - or %g3, %lo(trap_block), %g3 | |
| 29 | - add %g3, %g7, %g3 | |
| 25 | + ldxa [%g0] ASI_SCRATCHPAD, %g3 | |
| 26 | + sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3 | |
| 30 | 27 | |
| 31 | 28 | /* Get CPU mondo queue base phys address into %g7. */ |
| 32 | 29 | ldx [%g3 + TRAP_PER_CPU_CPU_MONDO_PA], %g7 |
| ... | ... | @@ -74,11 +71,8 @@ |
| 74 | 71 | nop |
| 75 | 72 | |
| 76 | 73 | /* Get &trap_block[smp_processor_id()] into %g3. */ |
| 77 | - __GET_CPUID(%g1) | |
| 78 | - sethi %hi(trap_block), %g3 | |
| 79 | - sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g7 | |
| 80 | - or %g3, %lo(trap_block), %g3 | |
| 81 | - add %g3, %g7, %g3 | |
| 74 | + ldxa [%g0] ASI_SCRATCHPAD, %g3 | |
| 75 | + sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3 | |
| 82 | 76 | |
| 83 | 77 | /* Get DEV mondo queue base phys address into %g5. */ |
| 84 | 78 | ldx [%g3 + TRAP_PER_CPU_DEV_MONDO_PA], %g5 |
| ... | ... | @@ -143,11 +137,8 @@ |
| 143 | 137 | nop |
| 144 | 138 | |
| 145 | 139 | /* Get &trap_block[smp_processor_id()] into %g3. */ |
| 146 | - __GET_CPUID(%g1) | |
| 147 | - sethi %hi(trap_block), %g3 | |
| 148 | - sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g7 | |
| 149 | - or %g3, %lo(trap_block), %g3 | |
| 150 | - add %g3, %g7, %g3 | |
| 140 | + ldxa [%g0] ASI_SCRATCHPAD, %g3 | |
| 141 | + sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3 | |
| 151 | 142 | |
| 152 | 143 | /* Get RES mondo queue base phys address into %g5. */ |
| 153 | 144 | ldx [%g3 + TRAP_PER_CPU_RESUM_MONDO_PA], %g5 |
| ... | ... | @@ -251,11 +242,8 @@ |
| 251 | 242 | nop |
| 252 | 243 | |
| 253 | 244 | /* Get &trap_block[smp_processor_id()] into %g3. */ |
| 254 | - __GET_CPUID(%g1) | |
| 255 | - sethi %hi(trap_block), %g3 | |
| 256 | - sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g7 | |
| 257 | - or %g3, %lo(trap_block), %g3 | |
| 258 | - add %g3, %g7, %g3 | |
| 245 | + ldxa [%g0] ASI_SCRATCHPAD, %g3 | |
| 246 | + sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3 | |
| 259 | 247 | |
| 260 | 248 | /* Get RES mondo queue base phys address into %g5. */ |
| 261 | 249 | ldx [%g3 + TRAP_PER_CPU_NONRESUM_MONDO_PA], %g5 |
arch/sparc64/kernel/sun4v_tlb_miss.S
| ... | ... | @@ -7,26 +7,20 @@ |
| 7 | 7 | .align 32 |
| 8 | 8 | |
| 9 | 9 | sun4v_itlb_miss: |
| 10 | - /* Load CPU ID into %g3. */ | |
| 11 | - mov SCRATCHPAD_CPUID, %g1 | |
| 12 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 10 | + /* Load MMU Miss base into %g2. */ | |
| 11 | + ldxa [%g0] ASI_SCRATCHPAD, %g3 | |
| 13 | 12 | |
| 14 | 13 | /* Load UTSB reg into %g1. */ |
| 15 | - ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1 | |
| 14 | + mov SCRATCHPAD_UTSBREG1, %g1 | |
| 15 | + ldxa [%g1] ASI_SCRATCHPAD, %g1 | |
| 16 | 16 | |
| 17 | - /* Load &trap_block[smp_processor_id()] into %g2. */ | |
| 18 | - sethi %hi(trap_block), %g2 | |
| 19 | - or %g2, %lo(trap_block), %g2 | |
| 20 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 21 | - add %g2, %g3, %g2 | |
| 22 | - | |
| 23 | 17 | /* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6. |
| 24 | 18 | * Branch if kernel TLB miss. The kernel TSB and user TSB miss |
| 25 | 19 | * code wants the missing virtual address in %g4, so that value |
| 26 | 20 | * cannot be modified through the entirety of this handler. |
| 27 | 21 | */ |
| 28 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4 | |
| 29 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5 | |
| 22 | + ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4 | |
| 23 | + ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5 | |
| 30 | 24 | srlx %g4, 22, %g3 |
| 31 | 25 | sllx %g5, 48, %g6 |
| 32 | 26 | or %g6, %g3, %g6 |
| 33 | 27 | |
| 34 | 28 | |
| 35 | 29 | |
| ... | ... | @@ -90,26 +84,20 @@ |
| 90 | 84 | retry |
| 91 | 85 | |
| 92 | 86 | sun4v_dtlb_miss: |
| 93 | - /* Load CPU ID into %g3. */ | |
| 94 | - mov SCRATCHPAD_CPUID, %g1 | |
| 95 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 87 | + /* Load MMU Miss base into %g2. */ | |
| 88 | + ldxa [%g0] ASI_SCRATCHPAD, %g2 | |
| 96 | 89 | |
| 97 | 90 | /* Load UTSB reg into %g1. */ |
| 91 | + mov SCRATCHPAD_UTSBREG1, %g1 | |
| 98 | 92 | ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1 |
| 99 | 93 | |
| 100 | - /* Load &trap_block[smp_processor_id()] into %g2. */ | |
| 101 | - sethi %hi(trap_block), %g2 | |
| 102 | - or %g2, %lo(trap_block), %g2 | |
| 103 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 104 | - add %g2, %g3, %g2 | |
| 105 | - | |
| 106 | 94 | /* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6. |
| 107 | 95 | * Branch if kernel TLB miss. The kernel TSB and user TSB miss |
| 108 | 96 | * code wants the missing virtual address in %g4, so that value |
| 109 | 97 | * cannot be modified through the entirety of this handler. |
| 110 | 98 | */ |
| 111 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 112 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 99 | + ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 100 | + ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 113 | 101 | srlx %g4, 22, %g3 |
| 114 | 102 | sllx %g5, 48, %g6 |
| 115 | 103 | or %g6, %g3, %g6 |
| 116 | 104 | |
| ... | ... | @@ -169,17 +157,10 @@ |
| 169 | 157 | retry |
| 170 | 158 | |
| 171 | 159 | sun4v_dtlb_prot: |
| 172 | - /* Load CPU ID into %g3. */ | |
| 173 | - mov SCRATCHPAD_CPUID, %g1 | |
| 174 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 160 | + /* Load MMU Miss base into %g2. */ | |
| 161 | + ldxa [%g0] ASI_SCRATCHPAD, %g2 | |
| 175 | 162 | |
| 176 | - /* Load &trap_block[smp_processor_id()] into %g2. */ | |
| 177 | - sethi %hi(trap_block), %g2 | |
| 178 | - or %g2, %lo(trap_block), %g2 | |
| 179 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 180 | - add %g2, %g3, %g2 | |
| 181 | - | |
| 182 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g5 | |
| 163 | + ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g5 | |
| 183 | 164 | rdpr %tl, %g1 |
| 184 | 165 | cmp %g1, 1 |
| 185 | 166 | bgu,pn %xcc, winfix_trampoline |
| 186 | 167 | |
| 187 | 168 | |
| 188 | 169 | |
| ... | ... | @@ -187,35 +168,17 @@ |
| 187 | 168 | ba,pt %xcc, sparc64_realfault_common |
| 188 | 169 | mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4 |
| 189 | 170 | |
| 190 | - /* Called from trap table with &trap_block[smp_processor_id()] in | |
| 191 | - * %g5 and SCRATCHPAD_UTSBREG1 contents in %g1. | |
| 171 | + /* Called from trap table with TAG TARGET placed into | |
| 172 | + * %g6 and SCRATCHPAD_UTSBREG1 contents in %g1. | |
| 192 | 173 | */ |
| 193 | 174 | sun4v_itsb_miss: |
| 194 | - ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4 | |
| 195 | - ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5 | |
| 196 | - | |
| 197 | - srlx %g4, 22, %g7 | |
| 198 | - sllx %g5, 48, %g6 | |
| 199 | - or %g6, %g7, %g6 | |
| 200 | - brz,pn %g5, kvmap_itlb_4v | |
| 201 | - nop | |
| 202 | - | |
| 203 | 175 | ba,pt %xcc, sun4v_tsb_miss_common |
| 204 | 176 | mov FAULT_CODE_ITLB, %g3 |
| 205 | 177 | |
| 206 | - /* Called from trap table with &trap_block[smp_processor_id()] in | |
| 207 | - * %g5 and SCRATCHPAD_UTSBREG1 contents in %g1. | |
| 178 | + /* Called from trap table with TAG TARGET placed into | |
| 179 | + * %g6 and SCRATCHPAD_UTSBREG1 contents in %g1. | |
| 208 | 180 | */ |
| 209 | 181 | sun4v_dtsb_miss: |
| 210 | - ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 211 | - ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 212 | - | |
| 213 | - srlx %g4, 22, %g7 | |
| 214 | - sllx %g5, 48, %g6 | |
| 215 | - or %g6, %g7, %g6 | |
| 216 | - brz,pn %g5, kvmap_dtlb_4v | |
| 217 | - nop | |
| 218 | - | |
| 219 | 182 | mov FAULT_CODE_DTLB, %g3 |
| 220 | 183 | |
| 221 | 184 | /* Create TSB pointer into %g1. This is something like: |
| ... | ... | @@ -239,15 +202,10 @@ |
| 239 | 202 | |
| 240 | 203 | /* Instruction Access Exception, tl0. */ |
| 241 | 204 | sun4v_iacc: |
| 242 | - mov SCRATCHPAD_CPUID, %g1 | |
| 243 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 244 | - sethi %hi(trap_block), %g2 | |
| 245 | - or %g2, %lo(trap_block), %g2 | |
| 246 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 247 | - add %g2, %g3, %g2 | |
| 248 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3 | |
| 249 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4 | |
| 250 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5 | |
| 205 | + ldxa [%g0] ASI_SCRATCHPAD, %g2 | |
| 206 | + ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3 | |
| 207 | + ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4 | |
| 208 | + ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5 | |
| 251 | 209 | sllx %g3, 16, %g3 |
| 252 | 210 | or %g5, %g3, %g5 |
| 253 | 211 | ba,pt %xcc, etrap |
| ... | ... | @@ -260,15 +218,10 @@ |
| 260 | 218 | |
| 261 | 219 | /* Instruction Access Exception, tl1. */ |
| 262 | 220 | sun4v_iacc_tl1: |
| 263 | - mov SCRATCHPAD_CPUID, %g1 | |
| 264 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 265 | - sethi %hi(trap_block), %g2 | |
| 266 | - or %g2, %lo(trap_block), %g2 | |
| 267 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 268 | - add %g2, %g3, %g2 | |
| 269 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3 | |
| 270 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4 | |
| 271 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5 | |
| 221 | + ldxa [%g0] ASI_SCRATCHPAD, %g2 | |
| 222 | + ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3 | |
| 223 | + ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4 | |
| 224 | + ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5 | |
| 272 | 225 | sllx %g3, 16, %g3 |
| 273 | 226 | or %g5, %g3, %g5 |
| 274 | 227 | ba,pt %xcc, etraptl1 |
| ... | ... | @@ -281,15 +234,10 @@ |
| 281 | 234 | |
| 282 | 235 | /* Data Access Exception, tl0. */ |
| 283 | 236 | sun4v_dacc: |
| 284 | - mov SCRATCHPAD_CPUID, %g1 | |
| 285 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 286 | - sethi %hi(trap_block), %g2 | |
| 287 | - or %g2, %lo(trap_block), %g2 | |
| 288 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 289 | - add %g2, %g3, %g2 | |
| 290 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3 | |
| 291 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 292 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 237 | + ldxa [%g0] ASI_SCRATCHPAD, %g2 | |
| 238 | + ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3 | |
| 239 | + ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 240 | + ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 293 | 241 | sllx %g3, 16, %g3 |
| 294 | 242 | or %g5, %g3, %g5 |
| 295 | 243 | ba,pt %xcc, etrap |
| ... | ... | @@ -302,15 +250,10 @@ |
| 302 | 250 | |
| 303 | 251 | /* Data Access Exception, tl1. */ |
| 304 | 252 | sun4v_dacc_tl1: |
| 305 | - mov SCRATCHPAD_CPUID, %g1 | |
| 306 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 307 | - sethi %hi(trap_block), %g2 | |
| 308 | - or %g2, %lo(trap_block), %g2 | |
| 309 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 310 | - add %g2, %g3, %g2 | |
| 311 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3 | |
| 312 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 313 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 253 | + ldxa [%g0] ASI_SCRATCHPAD, %g2 | |
| 254 | + ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3 | |
| 255 | + ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 256 | + ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 314 | 257 | sllx %g3, 16, %g3 |
| 315 | 258 | or %g5, %g3, %g5 |
| 316 | 259 | ba,pt %xcc, etraptl1 |
| 317 | 260 | |
| ... | ... | @@ -323,15 +266,10 @@ |
| 323 | 266 | |
| 324 | 267 | /* Memory Address Unaligned. */ |
| 325 | 268 | sun4v_mna: |
| 326 | - mov SCRATCHPAD_CPUID, %g1 | |
| 327 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 328 | - sethi %hi(trap_block), %g2 | |
| 329 | - or %g2, %lo(trap_block), %g2 | |
| 330 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 331 | - add %g2, %g3, %g2 | |
| 269 | + ldxa [%g0] ASI_SCRATCHPAD, %g2 | |
| 332 | 270 | mov HV_FAULT_TYPE_UNALIGNED, %g3 |
| 333 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 334 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 271 | + ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 272 | + ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 335 | 273 | sllx %g3, 16, %g3 |
| 336 | 274 | or %g5, %g3, %g5 |
| 337 | 275 | |
| ... | ... | @@ -359,15 +297,10 @@ |
| 359 | 297 | |
| 360 | 298 | /* Unaligned ldd float, tl0. */ |
| 361 | 299 | sun4v_lddfmna: |
| 362 | - mov SCRATCHPAD_CPUID, %g1 | |
| 363 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 364 | - sethi %hi(trap_block), %g2 | |
| 365 | - or %g2, %lo(trap_block), %g2 | |
| 366 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 367 | - add %g2, %g3, %g2 | |
| 368 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3 | |
| 369 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 370 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 300 | + ldxa [%g0] ASI_SCRATCHPAD, %g2 | |
| 301 | + ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3 | |
| 302 | + ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 303 | + ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 371 | 304 | sllx %g3, 16, %g3 |
| 372 | 305 | or %g5, %g3, %g5 |
| 373 | 306 | ba,pt %xcc, etrap |
| ... | ... | @@ -380,15 +313,10 @@ |
| 380 | 313 | |
| 381 | 314 | /* Unaligned std float, tl0. */ |
| 382 | 315 | sun4v_stdfmna: |
| 383 | - mov SCRATCHPAD_CPUID, %g1 | |
| 384 | - ldxa [%g1] ASI_SCRATCHPAD, %g3 | |
| 385 | - sethi %hi(trap_block), %g2 | |
| 386 | - or %g2, %lo(trap_block), %g2 | |
| 387 | - sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3 | |
| 388 | - add %g2, %g3, %g2 | |
| 389 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3 | |
| 390 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 391 | - ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 316 | + ldxa [%g0] ASI_SCRATCHPAD, %g2 | |
| 317 | + ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3 | |
| 318 | + ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4 | |
| 319 | + ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5 | |
| 392 | 320 | sllx %g3, 16, %g3 |
| 393 | 321 | or %g5, %g3, %g5 |
| 394 | 322 | ba,pt %xcc, etrap |
arch/sparc64/kernel/trampoline.S
| ... | ... | @@ -389,10 +389,35 @@ |
| 389 | 389 | or %o1, PSTATE_IE, %o1 |
| 390 | 390 | wrpr %o1, 0, %pstate |
| 391 | 391 | |
| 392 | - call prom_set_trap_table | |
| 392 | + sethi %hi(is_sun4v), %o0 | |
| 393 | + lduw [%o0 + %lo(is_sun4v)], %o0 | |
| 394 | + brz,pt %o0, 1f | |
| 395 | + nop | |
| 396 | + | |
| 397 | + TRAP_LOAD_TRAP_BLOCK(%g2, %g3) | |
| 398 | + add %g2, TRAP_PER_CPU_FAULT_INFO, %g2 | |
| 399 | + stxa %g2, [%g0] ASI_SCRATCHPAD | |
| 400 | + | |
| 401 | + /* Compute physical address: | |
| 402 | + * | |
| 403 | + * paddr = kern_base + (mmfsa_vaddr - KERNBASE) | |
| 404 | + */ | |
| 405 | + sethi %hi(KERNBASE), %g3 | |
| 406 | + sub %g2, %g3, %g2 | |
| 407 | + sethi %hi(kern_base), %g3 | |
| 408 | + ldx [%g3 + %lo(kern_base)], %g3 | |
| 409 | + add %g2, %g3, %o1 | |
| 410 | + | |
| 411 | + call prom_set_trap_table_sun4v | |
| 393 | 412 | sethi %hi(sparc64_ttable_tl0), %o0 |
| 394 | 413 | |
| 395 | - call smp_callin | |
| 414 | + ba,pt %xcc, 2f | |
| 415 | + nop | |
| 416 | + | |
| 417 | +1: call prom_set_trap_table | |
| 418 | + sethi %hi(sparc64_ttable_tl0), %o0 | |
| 419 | + | |
| 420 | +2: call smp_callin | |
| 396 | 421 | nop |
| 397 | 422 | call cpu_idle |
| 398 | 423 | mov 0, %o0 |
arch/sparc64/mm/init.c
| ... | ... | @@ -1109,24 +1109,6 @@ |
| 1109 | 1109 | } |
| 1110 | 1110 | } |
| 1111 | 1111 | |
| 1112 | -/* Register this cpu's fault status area with the hypervisor. */ | |
| 1113 | -void __cpuinit sun4v_register_fault_status(void) | |
| 1114 | -{ | |
| 1115 | - register unsigned long func asm("%o5"); | |
| 1116 | - register unsigned long arg0 asm("%o0"); | |
| 1117 | - int cpu = hard_smp_processor_id(); | |
| 1118 | - struct trap_per_cpu *tb = &trap_block[cpu]; | |
| 1119 | - unsigned long pa; | |
| 1120 | - | |
| 1121 | - pa = kern_base + ((unsigned long) tb - KERNBASE); | |
| 1122 | - func = HV_FAST_MMU_FAULT_AREA_CONF; | |
| 1123 | - arg0 = pa; | |
| 1124 | - __asm__ __volatile__("ta %4" | |
| 1125 | - : "=&r" (func), "=&r" (arg0) | |
| 1126 | - : "0" (func), "1" (arg0), | |
| 1127 | - "i" (HV_FAST_TRAP)); | |
| 1128 | -} | |
| 1129 | - | |
| 1130 | 1112 | /* paging_init() sets up the page tables */ |
| 1131 | 1113 | |
| 1132 | 1114 | extern void cheetah_ecache_flush_init(void); |
| 1133 | 1115 | |
| ... | ... | @@ -1147,10 +1129,8 @@ |
| 1147 | 1129 | tlb_type == hypervisor) |
| 1148 | 1130 | tsb_phys_patch(); |
| 1149 | 1131 | |
| 1150 | - if (tlb_type == hypervisor) { | |
| 1132 | + if (tlb_type == hypervisor) | |
| 1151 | 1133 | sun4v_patch_tlb_handlers(); |
| 1152 | - sun4v_register_fault_status(); | |
| 1153 | - } | |
| 1154 | 1134 | |
| 1155 | 1135 | /* Find available physical memory... */ |
| 1156 | 1136 | read_obp_memory("available", &pavail[0], &pavail_ents); |
arch/sparc64/prom/misc.c
| ... | ... | @@ -136,6 +136,11 @@ |
| 136 | 136 | p1275_cmd("SUNW,set-trap-table", P1275_INOUT(1, 0), tba); |
| 137 | 137 | } |
| 138 | 138 | |
| 139 | +void prom_set_trap_table_sun4v(unsigned long tba, unsigned long mmfsa) | |
| 140 | +{ | |
| 141 | + p1275_cmd("SUNW,set-trap-table", P1275_INOUT(2, 0), tba, mmfsa); | |
| 142 | +} | |
| 143 | + | |
| 139 | 144 | int prom_get_mmu_ihandle(void) |
| 140 | 145 | { |
| 141 | 146 | int node, ret; |
include/asm-sparc64/cpudata.h
| ... | ... | @@ -156,13 +156,16 @@ |
| 156 | 156 | nop; \ |
| 157 | 157 | .previous; |
| 158 | 158 | |
| 159 | -/* Clobbers TMP, current address space PGD phys address into DEST. */ | |
| 160 | -#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ | |
| 159 | +#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
| 161 | 160 | __GET_CPUID(TMP) \ |
| 162 | 161 | sethi %hi(trap_block), DEST; \ |
| 163 | 162 | sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \ |
| 164 | 163 | or DEST, %lo(trap_block), DEST; \ |
| 165 | 164 | add DEST, TMP, DEST; \ |
| 165 | + | |
| 166 | +/* Clobbers TMP, current address space PGD phys address into DEST. */ | |
| 167 | +#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ | |
| 168 | + TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
| 166 | 169 | ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; |
| 167 | 170 | |
| 168 | 171 | /* Clobbers TMP, loads local processor's IRQ work area into DEST. */ |
| ... | ... | @@ -175,11 +178,8 @@ |
| 175 | 178 | |
| 176 | 179 | /* Clobbers TMP, loads DEST with current thread info pointer. */ |
| 177 | 180 | #define TRAP_LOAD_THREAD_REG(DEST, TMP) \ |
| 178 | - __GET_CPUID(TMP) \ | |
| 179 | - sethi %hi(trap_block), DEST; \ | |
| 180 | - sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \ | |
| 181 | - or DEST, %lo(trap_block), DEST; \ | |
| 182 | - ldx [DEST + TMP], DEST; | |
| 181 | + TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
| 182 | + ldx [DEST + TRAP_PER_CPU_THREAD], DEST; | |
| 183 | 183 | |
| 184 | 184 | /* Given the current thread info pointer in THR, load the per-cpu |
| 185 | 185 | * area base of the current processor into DEST. REG1, REG2, and REG3 are |
| 186 | 186 | |
| ... | ... | @@ -201,13 +201,13 @@ |
| 201 | 201 | |
| 202 | 202 | #else |
| 203 | 203 | |
| 204 | -#define __GET_CPUID(REG) \ | |
| 205 | - mov 0, REG; | |
| 204 | +#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
| 205 | + sethi %hi(trap_block), DEST; \ | |
| 206 | + or DEST, %lo(trap_block), DEST; \ | |
| 206 | 207 | |
| 207 | 208 | /* Uniprocessor versions, we know the cpuid is zero. */ |
| 208 | 209 | #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ |
| 209 | - sethi %hi(trap_block), DEST; \ | |
| 210 | - or DEST, %lo(trap_block), DEST; \ | |
| 210 | + TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
| 211 | 211 | ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; |
| 212 | 212 | |
| 213 | 213 | #define TRAP_LOAD_IRQ_WORK(DEST, TMP) \ |
| ... | ... | @@ -215,8 +215,8 @@ |
| 215 | 215 | or DEST, %lo(__irq_work), DEST; |
| 216 | 216 | |
| 217 | 217 | #define TRAP_LOAD_THREAD_REG(DEST, TMP) \ |
| 218 | - sethi %hi(trap_block), DEST; \ | |
| 219 | - ldx [DEST + %lo(trap_block)], DEST; | |
| 218 | + TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
| 219 | + ldx [DEST + TRAP_PER_CPU_THREAD], DEST; | |
| 220 | 220 | |
| 221 | 221 | /* No per-cpu areas on uniprocessor, so no need to load DEST. */ |
| 222 | 222 | #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) |
include/asm-sparc64/oplib.h
include/asm-sparc64/ttable.h
| ... | ... | @@ -180,25 +180,25 @@ |
| 180 | 180 | #define KPROBES_TRAP(lvl) TRAP_ARG(bad_trap, lvl) |
| 181 | 181 | #endif |
| 182 | 182 | |
| 183 | -#define SUN4V_ITSB_MISS \ | |
| 184 | - mov SCRATCHPAD_CPUID, %g1; \ | |
| 185 | - ldxa [%g1] ASI_SCRATCHPAD, %g2; \ | |
| 186 | - ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1;\ | |
| 187 | - sethi %hi(trap_block), %g5; \ | |
| 188 | - sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2; \ | |
| 189 | - or %g5, %lo(trap_block), %g5; \ | |
| 190 | - ba,pt %xcc, sun4v_itsb_miss; \ | |
| 191 | - add %g5, %g2, %g5; | |
| 183 | +#define SUN4V_ITSB_MISS \ | |
| 184 | + ldxa [%g0] ASI_SCRATCHPAD, %g2; \ | |
| 185 | + ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4; \ | |
| 186 | + ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \ | |
| 187 | + srlx %g4, 22, %g7; \ | |
| 188 | + sllx %g5, 48, %g6; \ | |
| 189 | + brz,pn %g5, kvmap_itlb_4v; \ | |
| 190 | + or %g6, %g7, %g6; \ | |
| 191 | + ba,a,pt %xcc, sun4v_itsb_miss; | |
| 192 | 192 | |
| 193 | 193 | #define SUN4V_DTSB_MISS \ |
| 194 | - mov SCRATCHPAD_CPUID, %g1; \ | |
| 195 | - ldxa [%g1] ASI_SCRATCHPAD, %g2; \ | |
| 196 | - ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1;\ | |
| 197 | - sethi %hi(trap_block), %g5; \ | |
| 198 | - sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2; \ | |
| 199 | - or %g5, %lo(trap_block), %g5; \ | |
| 200 | - ba,pt %xcc, sun4v_dtsb_miss; \ | |
| 201 | - add %g5, %g2, %g5; | |
| 194 | + ldxa [%g0] ASI_SCRATCHPAD, %g2; \ | |
| 195 | + ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \ | |
| 196 | + ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \ | |
| 197 | + srlx %g4, 22, %g7; \ | |
| 198 | + sllx %g5, 48, %g6; \ | |
| 199 | + brz,pn %g5, kvmap_dtlb_4v; \ | |
| 200 | + or %g6, %g7, %g6; \ | |
| 201 | + ba,a,pt %xcc, sun4v_dtsb_miss; | |
| 202 | 202 | |
| 203 | 203 | /* Before touching these macros, you owe it to yourself to go and |
| 204 | 204 | * see how arch/sparc64/kernel/winfixup.S works... -DaveM |