Commit 13051c5cc3dd2600afe980049eb566b9b6a4afda
Committed by
Ralf Baechle
1 parent
d57f341ba0
Exists in
master
and in
6 other branches
MIPS: ath79: register UART device for the AR933X SoCs
The AR933X SoCs does not have a 8250 compatible UART, they are using a different UART core. Register a different platform device for the different UART. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Kathy Giori <kgiori@qca.qualcomm.com> Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com> Patchwork: https://patchwork.linux-mips.org/patch/2528/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Showing 1 changed file with 36 additions and 2 deletions Side-by-side Diff
arch/mips/ath79/dev-common.c
... | ... | @@ -20,6 +20,7 @@ |
20 | 20 | |
21 | 21 | #include <asm/mach-ath79/ath79.h> |
22 | 22 | #include <asm/mach-ath79/ar71xx_regs.h> |
23 | +#include <asm/mach-ath79/ar933x_uart_platform.h> | |
23 | 24 | #include "common.h" |
24 | 25 | #include "dev-common.h" |
25 | 26 | |
... | ... | @@ -54,6 +55,30 @@ |
54 | 55 | }, |
55 | 56 | }; |
56 | 57 | |
58 | +static struct resource ar933x_uart_resources[] = { | |
59 | + { | |
60 | + .start = AR933X_UART_BASE, | |
61 | + .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1, | |
62 | + .flags = IORESOURCE_MEM, | |
63 | + }, | |
64 | + { | |
65 | + .start = ATH79_MISC_IRQ_UART, | |
66 | + .end = ATH79_MISC_IRQ_UART, | |
67 | + .flags = IORESOURCE_IRQ, | |
68 | + }, | |
69 | +}; | |
70 | + | |
71 | +static struct ar933x_uart_platform_data ar933x_uart_data; | |
72 | +static struct platform_device ar933x_uart_device = { | |
73 | + .name = "ar933x-uart", | |
74 | + .id = -1, | |
75 | + .resource = ar933x_uart_resources, | |
76 | + .num_resources = ARRAY_SIZE(ar933x_uart_resources), | |
77 | + .dev = { | |
78 | + .platform_data = &ar933x_uart_data, | |
79 | + }, | |
80 | +}; | |
81 | + | |
57 | 82 | void __init ath79_register_uart(void) |
58 | 83 | { |
59 | 84 | struct clk *clk; |
... | ... | @@ -62,8 +87,17 @@ |
62 | 87 | if (IS_ERR(clk)) |
63 | 88 | panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); |
64 | 89 | |
65 | - ath79_uart_data[0].uartclk = clk_get_rate(clk); | |
66 | - platform_device_register(&ath79_uart_device); | |
90 | + if (soc_is_ar71xx() || | |
91 | + soc_is_ar724x() || | |
92 | + soc_is_ar913x()) { | |
93 | + ath79_uart_data[0].uartclk = clk_get_rate(clk); | |
94 | + platform_device_register(&ath79_uart_device); | |
95 | + } else if (soc_is_ar933x()) { | |
96 | + ar933x_uart_data.uartclk = clk_get_rate(clk); | |
97 | + platform_device_register(&ar933x_uart_device); | |
98 | + } else { | |
99 | + BUG(); | |
100 | + } | |
67 | 101 | } |
68 | 102 | |
69 | 103 | static struct platform_device ath79_wdt_device = { |