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Commit 13ed7aed45e370f30a746e49e674144297a92e16

Authored by Brian Norris
Committed by David Woodhouse
1 parent 5c709ee9f3
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

mtd: nand: support new Toshiba SLC 

Toshiba does not use ONFI for their NAND flash. So we have to continue
to add new IDs used by Toshiba devices as well as heuristic detection
for scanning the 2nd page for a BBM. This is a relatively harmless
start at supporting many of them.

These chips mostly follow the same ID fields of previous generations,
but there is a need for a tweak.

These chips introduce a strange 576 byte OOB (that's 36 bytes per
512 bytes of page). In the preliminary data, Toshiba has not
defined exactly how their ID strings should decode. In the future,
a new tweak must be added.

Data is taken from, among others, Toshiba TC58TxG4S2FBAxx

Signed-off-by: Brian Norris <norris@broadcom.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

Showing 2 changed files with 34 additions and 2 deletions Side-by-side Diff

drivers/mtd/nand/nand_base.c
Diff comments   View file @ 13ed7ae
... ... @@ -2972,8 +2972,8 @@
2972 2972 * Bad block marker is stored in the last page of each block
2973 2973 * on Samsung and Hynix MLC devices; stored in first two pages
2974 2974 * of each block on Micron devices with 2KiB pages and on
2975   - * SLC Samsung, Hynix, and AMD/Spansion. All others scan only
2976   - * the first page.
  2975 + * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
  2976 + * only the first page.
2977 2977 */
2978 2978 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2979 2979 (*maf_id == NAND_MFR_SAMSUNG ||
... ... @@ -2982,6 +2982,7 @@
2982 2982 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2983 2983 (*maf_id == NAND_MFR_SAMSUNG ||
2984 2984 *maf_id == NAND_MFR_HYNIX ||
  2985 + *maf_id == NAND_MFR_TOSHIBA ||
2985 2986 *maf_id == NAND_MFR_AMD)) ||
2986 2987 (mtd->writesize == 2048 &&
2987 2988 *maf_id == NAND_MFR_MICRON))
drivers/mtd/nand/nand_ids.c
Diff comments   View file @ 13ed7ae
... ... @@ -75,9 +75,13 @@
75 75  
76 76 /*512 Megabit */
77 77 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
  78 + {"NAND 64MiB 1,8V 8-bit", 0xA0, 0, 64, 0, LP_OPTIONS},
78 79 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
  80 + {"NAND 64MiB 3,3V 8-bit", 0xD0, 0, 64, 0, LP_OPTIONS},
79 81 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
  82 + {"NAND 64MiB 1,8V 16-bit", 0xB0, 0, 64, 0, LP_OPTIONS16},
80 83 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
  84 + {"NAND 64MiB 3,3V 16-bit", 0xC0, 0, 64, 0, LP_OPTIONS16},
81 85  
82 86 /* 1 Gigabit */
83 87 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
84 88  
... ... @@ -112,7 +116,34 @@
112 116 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
113 117  
114 118 /* 32 Gigabit */
  119 + {"NAND 4GiB 1,8V 8-bit", 0xA7, 0, 4096, 0, LP_OPTIONS},
115 120 {"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 4096, 0, LP_OPTIONS},
  121 + {"NAND 4GiB 1,8V 16-bit", 0xB7, 0, 4096, 0, LP_OPTIONS16},
  122 + {"NAND 4GiB 3,3V 16-bit", 0xC7, 0, 4096, 0, LP_OPTIONS16},
  123 +
  124 + /* 64 Gigabit */
  125 + {"NAND 8GiB 1,8V 8-bit", 0xAE, 0, 8192, 0, LP_OPTIONS},
  126 + {"NAND 8GiB 3,3V 8-bit", 0xDE, 0, 8192, 0, LP_OPTIONS},
  127 + {"NAND 8GiB 1,8V 16-bit", 0xBE, 0, 8192, 0, LP_OPTIONS16},
  128 + {"NAND 8GiB 3,3V 16-bit", 0xCE, 0, 8192, 0, LP_OPTIONS16},
  129 +
  130 + /* 128 Gigabit */
  131 + {"NAND 16GiB 1,8V 8-bit", 0x1A, 0, 16384, 0, LP_OPTIONS},
  132 + {"NAND 16GiB 3,3V 8-bit", 0x3A, 0, 16384, 0, LP_OPTIONS},
  133 + {"NAND 16GiB 1,8V 16-bit", 0x2A, 0, 16384, 0, LP_OPTIONS16},
  134 + {"NAND 16GiB 3,3V 16-bit", 0x4A, 0, 16384, 0, LP_OPTIONS16},
  135 +
  136 + /* 256 Gigabit */
  137 + {"NAND 32GiB 1,8V 8-bit", 0x1C, 0, 32768, 0, LP_OPTIONS},
  138 + {"NAND 32GiB 3,3V 8-bit", 0x3C, 0, 32768, 0, LP_OPTIONS},
  139 + {"NAND 32GiB 1,8V 16-bit", 0x2C, 0, 32768, 0, LP_OPTIONS16},
  140 + {"NAND 32GiB 3,3V 16-bit", 0x4C, 0, 32768, 0, LP_OPTIONS16},
  141 +
  142 + /* 512 Gigabit */
  143 + {"NAND 64GiB 1,8V 8-bit", 0x1E, 0, 65536, 0, LP_OPTIONS},
  144 + {"NAND 64GiB 3,3V 8-bit", 0x3E, 0, 65536, 0, LP_OPTIONS},
  145 + {"NAND 64GiB 1,8V 16-bit", 0x2E, 0, 65536, 0, LP_OPTIONS16},
  146 + {"NAND 64GiB 3,3V 16-bit", 0x4E, 0, 65536, 0, LP_OPTIONS16},
116 147  
117 148 /*
118 149 * Renesas AND 1 Gigabit. Those chips do not support extended id and