Commit 15b9350a177b9fb23b69e00f78f52890ee338880

Authored by David Miller
Committed by Linus Torvalds
1 parent d760afd4d2

sparc64: Only support 4MB huge pages and 8KB base pages.

Narrowing the scope of the page size configurations will make the
transparent hugepage changes much simpler.

In the end what we really want to do is have the kernel support multiple
huge page sizes and use whatever is appropriate as the context dictactes.

Signed-off-by: David S. Miller <davem@davemloft.net>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Johannes Weiner <hannes@cmpxchg.org>
Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 6 changed files with 9 additions and 121 deletions Side-by-side Diff

... ... @@ -230,25 +230,6 @@
230 230 help
231 231 Say Y here to enable a faster early framebuffer boot console.
232 232  
233   -choice
234   - prompt "Kernel page size" if SPARC64
235   - default SPARC64_PAGE_SIZE_8KB
236   -
237   -config SPARC64_PAGE_SIZE_8KB
238   - bool "8KB"
239   - help
240   - This lets you select the page size of the kernel.
241   -
242   - 8KB and 64KB work quite well, since SPARC ELF sections
243   - provide for up to 64KB alignment.
244   -
245   - If you don't know what to do, choose 8KB.
246   -
247   -config SPARC64_PAGE_SIZE_64KB
248   - bool "64KB"
249   -
250   -endchoice
251   -
252 233 config SECCOMP
253 234 bool "Enable seccomp to safely compute untrusted bytecode"
254 235 depends on SPARC64 && PROC_FS
... ... @@ -319,23 +300,6 @@
319 300 bool
320 301 default y
321 302 depends on SPARC64 && SMP && PREEMPT
322   -
323   -choice
324   - prompt "SPARC64 Huge TLB Page Size"
325   - depends on SPARC64 && HUGETLB_PAGE
326   - default HUGETLB_PAGE_SIZE_4MB
327   -
328   -config HUGETLB_PAGE_SIZE_4MB
329   - bool "4MB"
330   -
331   -config HUGETLB_PAGE_SIZE_512K
332   - bool "512K"
333   -
334   -config HUGETLB_PAGE_SIZE_64K
335   - depends on !SPARC64_PAGE_SIZE_64KB
336   - bool "64K"
337   -
338   -endchoice
339 303  
340 304 config NUMA
341 305 bool "NUMA support"
arch/sparc/include/asm/mmu_64.h
... ... @@ -30,22 +30,8 @@
30 30 #define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
31 31 (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
32 32  
33   -#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
34 33 #define CTX_PGSZ_BASE CTX_PGSZ_8KB
35   -#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
36   -#define CTX_PGSZ_BASE CTX_PGSZ_64KB
37   -#else
38   -#error No page size specified in kernel configuration
39   -#endif
40   -
41   -#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
42   -#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
43   -#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
44   -#define CTX_PGSZ_HUGE CTX_PGSZ_512KB
45   -#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
46   -#define CTX_PGSZ_HUGE CTX_PGSZ_64KB
47   -#endif
48   -
  34 +#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
49 35 #define CTX_PGSZ_KERN CTX_PGSZ_4MB
50 36  
51 37 /* Thus, when running on UltraSPARC-III+ and later, we use the following
arch/sparc/include/asm/page_64.h
... ... @@ -3,13 +3,7 @@
3 3  
4 4 #include <linux/const.h>
5 5  
6   -#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
7 6 #define PAGE_SHIFT 13
8   -#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
9   -#define PAGE_SHIFT 16
10   -#else
11   -#error No page size specified in kernel configuration
12   -#endif
13 7  
14 8 #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
15 9 #define PAGE_MASK (~(PAGE_SIZE-1))
16 10  
... ... @@ -21,13 +15,7 @@
21 15 #define DCACHE_ALIASING_POSSIBLE
22 16 #endif
23 17  
24   -#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
25 18 #define HPAGE_SHIFT 22
26   -#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
27   -#define HPAGE_SHIFT 19
28   -#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
29   -#define HPAGE_SHIFT 16
30   -#endif
31 19  
32 20 #ifdef CONFIG_HUGETLB_PAGE
33 21 #define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
arch/sparc/include/asm/pgtable_64.h
... ... @@ -160,26 +160,11 @@
160 160 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
161 161 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
162 162  
163   -#if PAGE_SHIFT == 13
164 163 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
165 164 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
166   -#elif PAGE_SHIFT == 16
167   -#define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
168   -#define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
169   -#else
170   -#error Wrong PAGE_SHIFT specified
171   -#endif
172 165  
173   -#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
174 166 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
175 167 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
176   -#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
177   -#define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
178   -#define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
179   -#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
180   -#define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
181   -#define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
182   -#endif
183 168  
184 169 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
185 170 #define __P000 __pgprot(0)
... ... @@ -218,7 +203,6 @@
218 203  
219 204 extern unsigned long pg_iobits;
220 205 extern unsigned long _PAGE_ALL_SZ_BITS;
221   -extern unsigned long _PAGE_SZBITS;
222 206  
223 207 extern struct page *mem_map_zero;
224 208 #define ZERO_PAGE(vaddr) (mem_map_zero)
225 209  
... ... @@ -231,22 +215,9 @@
231 215 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
232 216 {
233 217 unsigned long paddr = pfn << PAGE_SHIFT;
234   - unsigned long sz_bits;
235 218  
236   - sz_bits = 0UL;
237   - if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
238   - __asm__ __volatile__(
239   - "\n661: sethi %%uhi(%1), %0\n"
240   - " sllx %0, 32, %0\n"
241   - " .section .sun4v_2insn_patch, \"ax\"\n"
242   - " .word 661b\n"
243   - " mov %2, %0\n"
244   - " nop\n"
245   - " .previous\n"
246   - : "=r" (sz_bits)
247   - : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
248   - }
249   - return __pte(paddr | sz_bits | pgprot_val(prot));
  219 + BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
  220 + return __pte(paddr | pgprot_val(prot));
250 221 }
251 222 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
252 223  
... ... @@ -286,6 +257,7 @@
286 257 * Note: We encode this into 3 sun4v 2-insn patch sequences.
287 258 */
288 259  
  260 + BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
289 261 __asm__ __volatile__(
290 262 "\n661: sethi %%uhi(%2), %1\n"
291 263 " sethi %%hi(%2), %0\n"
292 264  
... ... @@ -307,10 +279,10 @@
307 279 : "=r" (mask), "=r" (tmp)
308 280 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
309 281 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
310   - _PAGE_SZBITS_4U | _PAGE_SPECIAL),
  282 + _PAGE_SPECIAL),
311 283 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
312 284 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
313   - _PAGE_SZBITS_4V | _PAGE_SPECIAL));
  285 + _PAGE_SPECIAL));
314 286  
315 287 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
316 288 }
arch/sparc/mm/init_64.c
... ... @@ -276,7 +276,6 @@
276 276 }
277 277  
278 278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
279   -unsigned long _PAGE_SZBITS __read_mostly;
280 279  
281 280 static void flush_dcache(unsigned long pfn)
282 281 {
... ... @@ -2275,8 +2274,7 @@
2275 2274 __ACCESS_BITS_4U | _PAGE_E_4U);
2276 2275  
2277 2276 #ifdef CONFIG_DEBUG_PAGEALLOC
2278   - kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2279   - 0xfffff80000000000UL;
  2277 + kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2280 2278 #else
2281 2279 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2282 2280 0xfffff80000000000UL;
... ... @@ -2287,7 +2285,6 @@
2287 2285 for (i = 1; i < 4; i++)
2288 2286 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2289 2287  
2290   - _PAGE_SZBITS = _PAGE_SZBITS_4U;
2291 2288 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2292 2289 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2293 2290 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
... ... @@ -2324,8 +2321,7 @@
2324 2321 _PAGE_CACHE = _PAGE_CACHE_4V;
2325 2322  
2326 2323 #ifdef CONFIG_DEBUG_PAGEALLOC
2327   - kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2328   - 0xfffff80000000000UL;
  2324 + kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2329 2325 #else
2330 2326 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2331 2327 0xfffff80000000000UL;
... ... @@ -2339,7 +2335,6 @@
2339 2335 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2340 2336 __ACCESS_BITS_4V | _PAGE_E_4V);
2341 2337  
2342   - _PAGE_SZBITS = _PAGE_SZBITS_4V;
2343 2338 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2344 2339 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2345 2340 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
... ... @@ -90,29 +90,12 @@
90 90 spin_unlock_irqrestore(&mm->context.lock, flags);
91 91 }
92 92  
93   -#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
94 93 #define HV_PGSZ_IDX_BASE HV_PGSZ_IDX_8K
95 94 #define HV_PGSZ_MASK_BASE HV_PGSZ_MASK_8K
96   -#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
97   -#define HV_PGSZ_IDX_BASE HV_PGSZ_IDX_64K
98   -#define HV_PGSZ_MASK_BASE HV_PGSZ_MASK_64K
99   -#else
100   -#error Broken base page size setting...
101   -#endif
102 95  
103 96 #ifdef CONFIG_HUGETLB_PAGE
104   -#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
105   -#define HV_PGSZ_IDX_HUGE HV_PGSZ_IDX_64K
106   -#define HV_PGSZ_MASK_HUGE HV_PGSZ_MASK_64K
107   -#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
108   -#define HV_PGSZ_IDX_HUGE HV_PGSZ_IDX_512K
109   -#define HV_PGSZ_MASK_HUGE HV_PGSZ_MASK_512K
110   -#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
111 97 #define HV_PGSZ_IDX_HUGE HV_PGSZ_IDX_4MB
112 98 #define HV_PGSZ_MASK_HUGE HV_PGSZ_MASK_4MB
113   -#else
114   -#error Broken huge page size setting...
115   -#endif
116 99 #endif
117 100  
118 101 static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_idx, unsigned long tsb_bytes)