[PARISC] Create shared <asm/ropes.h> header

Pull out struct sba_device and struct lba_device into a common ropes.h header. Also fold the parisc portion of iosapic.h into this file. (Then delete the useless portion of iosapic.h) Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>

[PARISC] Create shared <asm/ropes.h> header
Pull out struct sba_device and struct lba_device into a common ropes.h header. Also fold the parisc portion of iosapic.h into this file. (Then delete the useless portion of iosapic.h) Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Kyle McMartin · Matthew Wilcox
1 parent b0eecc4da9
Showing 5 changed files with 153 additions and 201 deletions Side-by-side Diff
drivers/parisc/iosapic.c
drivers/parisc/lba_pci.c
drivers/parisc/sba_iommu.c
include/asm-parisc/iosapic.h
include/asm-parisc/ropes.h
@@ -146,7 +146,7 @@
 #include <asm/superio.h>
 #endif
  
-#include <asm/iosapic.h>
+#include <asm/ropes.h>
 #include "./iosapic_private.h"
  
 #define MODULE_NAME "iosapic"
@@ -46,9 +46,9 @@
 #include <asm/page.h>
 #include <asm/system.h>
  
+#include <asm/ropes.h>
 #include <asm/hardware.h>	/* for register_parisc_driver() stuff */
 #include <asm/parisc-device.h>
-#include <asm/iosapic.h>	/* for iosapic_register() */
 #include <asm/io.h>		/* read/write stuff */
  
 #undef DEBUG_LBA	/* general stuff */
@@ -168,44 +168,6 @@
 /* non-postable I/O port space, densely packed */
 #define LBA_PORT_BASE	(PCI_F_EXTEND | 0xfee00000UL)
 static void __iomem *astro_iop_base __read_mostly;
-
-#define ELROY_HVERS	0x782
-#define MERCURY_HVERS	0x783
-#define QUICKSILVER_HVERS	0x784
-
-static inline int IS_ELROY(struct parisc_device *d)
-{
-	return (d->id.hversion == ELROY_HVERS);
-}
-
-static inline int IS_MERCURY(struct parisc_device *d)
-{
-	return (d->id.hversion == MERCURY_HVERS);
-}
-
-static inline int IS_QUICKSILVER(struct parisc_device *d)
-{
-	return (d->id.hversion == QUICKSILVER_HVERS);
-}
-
-
-/*
-** lba_device: Per instance Elroy data structure
-*/
-struct lba_device {
-	struct pci_hba_data hba;
-
-	spinlock_t	lba_lock;
-	void		*iosapic_obj;
-
-#ifdef CONFIG_64BIT
-	void __iomem *	iop_base;    /* PA_VIEW - for IO port accessor funcs */
-#endif
-
-	int		flags;       /* state/functionality enabled */
-	int		hw_rev;      /* HW revision of chip */
-};
-
  
 static u32 lba_t32;
  
@@ -38,6 +38,7 @@
 #include <linux/proc_fs.h>
 #include <linux/seq_file.h>
  
+#include <asm/ropes.h>
 #include <asm/mckinley.h>	/* for proc_mckinley_root */
 #include <asm/runway.h>		/* for proc_runway_root */
 #include <asm/pdc.h>		/* for PDC_MODEL_* */
@@ -46,11 +47,6 @@
  
 #define MODULE_NAME "SBA"
  
-#ifdef CONFIG_PROC_FS
-/* depends on proc fs support. But costs CPU performance */
-#undef SBA_COLLECT_STATS
-#endif
-
 /*
 ** The number of debug flags is a clue - this code is fragile.
 ** Don't even think about messing with it unless you have
  
  
  
@@ -89,46 +85,13 @@
 #define DBG_RES(x...)
 #endif
  
-#if defined(CONFIG_64BIT)
-/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
-#define ZX1_SUPPORT
-#endif
-
 #define SBA_INLINE	__inline__
  
-
-/*
-** The number of pdir entries to "free" before issueing
-** a read to PCOM register to flush out PCOM writes.
-** Interacts with allocation granularity (ie 4 or 8 entries
-** allocated and free'd/purged at a time might make this
-** less interesting).
-*/
-#define DELAYED_RESOURCE_CNT	16
-
 #define DEFAULT_DMA_HINT_REG	0
  
-#define ASTRO_RUNWAY_PORT	0x582
-#define IKE_MERCED_PORT		0x803
-#define REO_MERCED_PORT		0x804
-#define REOG_MERCED_PORT	0x805
-#define PLUTO_MCKINLEY_PORT	0x880
-
 #define SBA_FUNC_ID	0x0000	/* function id */
 #define SBA_FCLASS	0x0008	/* function class, bist, header, rev... */
  
-static inline int IS_ASTRO(struct parisc_device *d) {
-	return d->id.hversion == ASTRO_RUNWAY_PORT;
-}
-
-static inline int IS_IKE(struct parisc_device *d) {
-	return d->id.hversion == IKE_MERCED_PORT;
-}
-
-static inline int IS_PLUTO(struct parisc_device *d) {
-	return d->id.hversion == PLUTO_MCKINLEY_PORT;
-}
-
 #define SBA_FUNC_SIZE 4096   /* SBA configuration function reg set */
  
 #define ASTRO_IOC_OFFSET	(32 * SBA_FUNC_SIZE)
  
@@ -145,11 +108,7 @@
 #define IOC_CTRL_D4       (1 << 11) /* Disable 4-byte coalescing */
 #define IOC_CTRL_DD       (1 << 13) /* Disable distr. LMMIO range coalescing */
  
-#define MAX_IOC		2	/* per Ike. Pluto/Astro only have 1. */
  
-#define ROPES_PER_IOC	8	/* per Ike half or Pluto/Astro */
-
-
 /*
 ** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
 ** Firmware programs this stuff. Don't touch it.
  
@@ -196,10 +155,7 @@
 #define IOC_TCNFG	0x318
 #define IOC_PDIR_BASE	0x320
  
-/* AGP GART driver looks for this */
-#define SBA_IOMMU_COOKIE    0x0000badbadc0ffeeUL
  
-
 /*
 ** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
 ** It's safer (avoid memory corruption) to keep DMA page mappings
@@ -227,69 +183,6 @@
 #define SBA_PERF_CNT1	0x200
 #define SBA_PERF_CNT2	0x208
 #define SBA_PERF_CNT3	0x210
-
-
-struct ioc {
-	void __iomem	*ioc_hpa;	/* I/O MMU base address */
-	char		*res_map;	/* resource map, bit == pdir entry */
-	u64		*pdir_base;	/* physical base address */
-	unsigned long	ibase;	/* pdir IOV Space base - shared w/lba_pci */
-	unsigned long	imask;	/* pdir IOV Space mask - shared w/lba_pci */
-#ifdef ZX1_SUPPORT
-	unsigned long	iovp_mask;	/* help convert IOVA to IOVP */
-#endif
-	unsigned long	*res_hint;	/* next avail IOVP - circular search */
-	spinlock_t	res_lock;
-	unsigned int	res_bitshift;	/* from the LEFT! */
-	unsigned int	res_size;	/* size of resource map in bytes */
-#ifdef SBA_HINT_SUPPORT
-/* FIXME : DMA HINTs not used */
-	unsigned long	hint_mask_pdir;	/* bits used for DMA hints */
-	unsigned int	hint_shift_pdir;
-#endif
-#if DELAYED_RESOURCE_CNT > 0
-	int saved_cnt;
-	struct sba_dma_pair {
-		dma_addr_t	iova;
-		size_t		size;
-	} saved[DELAYED_RESOURCE_CNT];
-#endif
-
-#ifdef SBA_COLLECT_STATS
-#define SBA_SEARCH_SAMPLE	0x100
-	unsigned long avg_search[SBA_SEARCH_SAMPLE];
-	unsigned long avg_idx;	/* current index into avg_search */
-	unsigned long used_pages;
-	unsigned long msingle_calls;
-	unsigned long msingle_pages;
-	unsigned long msg_calls;
-	unsigned long msg_pages;
-	unsigned long usingle_calls;
-	unsigned long usingle_pages;
-	unsigned long usg_calls;
-	unsigned long usg_pages;
-#endif
-
-	/* STUFF We don't need in performance path */
-	unsigned int	pdir_size;	/* in bytes, determined by IOV Space size */
-};
-
-struct sba_device {
-	struct sba_device	*next;	/* list of SBA's in system */
-	struct parisc_device	*dev;	/* dev found in bus walk */
-	const char 		*name;
-	void __iomem		*sba_hpa; /* base address */
-	spinlock_t		sba_lock;
-	unsigned int		flags;  /* state/functionality enabled */
-	unsigned int		hw_rev;  /* HW revision of chip */
-
-	struct resource		chip_resv; /* MMIO reserved for chip */
-	struct resource		iommu_resv; /* MMIO reserved for iommu */
-
-	unsigned int		num_ioc;  /* number of on-board IOC's */
-	struct ioc		ioc[MAX_IOC];
-};
-
  
 static struct sba_device *sba_list;
  
-/*
-** This file is private to iosapic driver.
-** If stuff needs to be used by another driver, move it to a common file.
-**
-** WARNING: fields most data structures here are ordered to make sure
-**          they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
-*/
-
-
-/*
-** I/O SAPIC init function
-** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
-** Call setup as part of per instance initialization.
-** (ie *not* init_module() function unless only one is present.)
-** fixup_irq is to initialize PCI IRQ line support and
-** virtualize pcidev->irq value. To be called by pci_fixup_bus().
-*/
-extern void *iosapic_register(unsigned long hpa);
-extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
-
-
-#ifdef __IA64__
-/*
-** PA: PIB (Processor Interrupt Block) is handled by Runway bus adapter.
-**     and is hardcoded to 0xfeeNNNN0 where NNNN is id_eid field.
-**
-** IA64: PIB is handled by "Local SAPIC" (integrated in the processor).
-*/
-struct local_sapic_info {
-	struct local_sapic_info *lsi_next;      /* point to next CPU info */
-	int                     *lsi_cpu_id;    /* point to logical CPU id */
-	unsigned long           *lsi_id_eid;    /* point to IA-64 CPU id */
-	int                     *lsi_status;    /* point to CPU status   */
-	void                    *lsi_private;   /* point to special info */
-};
-
-/*
-** "root" data structure which ties everything together.
-** Should always be able to start with sapic_root and locate
-** the desired information.
-*/
-struct sapic_info {
-	struct sapic_info	*si_next;	/* info is per cell */
-	int                     si_cellid;      /* cell id */
-	unsigned int            si_status;       /* status  */
-	char                    *si_pib_base;   /* intr blk base address */
-	local_sapic_info_t      *si_local_info;
-	io_sapic_info_t         *si_io_info;
-	extint_info_t           *si_extint_info;/* External Intr info      */
-};
-
-#endif /* IA64 */
+#ifndef _ASM_PARISC_ROPES_H_
+#define _ASM_PARISC_ROPES_H_
+
+#ifdef CONFIG_64BIT
+/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
+#define ZX1_SUPPORT
+#endif
+
+#ifdef CONFIG_PROC_FS
+/* depends on proc fs support. But costs CPU performance */
+#undef SBA_COLLECT_STATS
+#endif
+
+/*
+** The number of pdir entries to "free" before issueing
+** a read to PCOM register to flush out PCOM writes.
+** Interacts with allocation granularity (ie 4 or 8 entries
+** allocated and free'd/purged at a time might make this
+** less interesting).
+*/
+#define DELAYED_RESOURCE_CNT	16
+
+#define MAX_IOC		2	/* per Ike. Pluto/Astro only have 1. */
+#define ROPES_PER_IOC	8	/* per Ike half or Pluto/Astro */
+
+struct ioc {
+	void __iomem	*ioc_hpa;	/* I/O MMU base address */
+	char		*res_map;	/* resource map, bit == pdir entry */
+	u64		*pdir_base;	/* physical base address */
+	unsigned long	ibase;		/* pdir IOV Space base - shared w/lba_pci */
+	unsigned long	imask;		/* pdir IOV Space mask - shared w/lba_pci */
+#ifdef ZX1_SUPPORT
+	unsigned long	iovp_mask;	/* help convert IOVA to IOVP */
+#endif
+	unsigned long	*res_hint;	/* next avail IOVP - circular search */
+	spinlock_t	res_lock;
+	unsigned int	res_bitshift;	/* from the LEFT! */
+	unsigned int	res_size;	/* size of resource map in bytes */
+#ifdef SBA_HINT_SUPPORT
+/* FIXME : DMA HINTs not used */
+	unsigned long	hint_mask_pdir; /* bits used for DMA hints */
+	unsigned int	hint_shift_pdir;
+#endif
+#if DELAYED_RESOURCE_CNT > 0
+	int		saved_cnt;
+	struct sba_dma_pair {
+			dma_addr_t	iova;
+			size_t		size;
+        } saved[DELAYED_RESOURCE_CNT];
+#endif
+
+#ifdef SBA_COLLECT_STATS
+#define SBA_SEARCH_SAMPLE	0x100
+	unsigned long	avg_search[SBA_SEARCH_SAMPLE];
+	unsigned long	avg_idx;	/* current index into avg_search */
+	unsigned long	used_pages;
+	unsigned long	msingle_calls;
+	unsigned long	msingle_pages;
+	unsigned long	msg_calls;
+	unsigned long	msg_pages;
+	unsigned long	usingle_calls;
+	unsigned long	usingle_pages;
+	unsigned long	usg_calls;
+	unsigned long	usg_pages;
+#endif
+        /* STUFF We don't need in performance path */
+	unsigned int	pdir_size;	/* in bytes, determined by IOV Space size */
+};
+
+struct sba_device {
+	struct sba_device	*next;  /* list of SBA's in system */
+	struct parisc_device	*dev;   /* dev found in bus walk */
+	const char		*name;
+	void __iomem		*sba_hpa; /* base address */
+	spinlock_t		sba_lock;
+	unsigned int		flags;  /* state/functionality enabled */
+	unsigned int		hw_rev;  /* HW revision of chip */
+
+	struct resource		chip_resv; /* MMIO reserved for chip */
+	struct resource		iommu_resv; /* MMIO reserved for iommu */
+
+	unsigned int		num_ioc;  /* number of on-board IOC's */
+	struct ioc		ioc[MAX_IOC];
+};
+
+#define ASTRO_RUNWAY_PORT	0x582
+#define IKE_MERCED_PORT		0x803
+#define REO_MERCED_PORT		0x804
+#define REOG_MERCED_PORT	0x805
+#define PLUTO_MCKINLEY_PORT	0x880
+
+static inline int IS_ASTRO(struct parisc_device *d) {
+	return d->id.hversion == ASTRO_RUNWAY_PORT;
+}
+
+static inline int IS_IKE(struct parisc_device *d) {
+	return d->id.hversion == IKE_MERCED_PORT;
+}
+
+static inline int IS_PLUTO(struct parisc_device *d) {
+	return d->id.hversion == PLUTO_MCKINLEY_PORT;
+}
+
+#define SBA_IOMMU_COOKIE	0x0000badbadc0ffeeUL
+
+/*
+** lba_device: Per instance Elroy data structure
+*/
+struct lba_device {
+	struct pci_hba_data	hba;
+
+	spinlock_t		lba_lock;
+	void			*iosapic_obj;
+
+#ifdef CONFIG_64BIT
+	void __iomem		*iop_base;	/* PA_VIEW - for IO port accessor funcs */
+#endif
+
+	int			flags;		/* state/functionality enabled */
+	int			hw_rev;		/* HW revision of chip */
+};
+
+#define ELROY_HVERS		0x782
+#define MERCURY_HVERS		0x783
+#define QUICKSILVER_HVERS	0x784
+
+static inline int IS_ELROY(struct parisc_device *d) {
+	return (d->id.hversion == ELROY_HVERS);
+}
+
+static inline int IS_MERCURY(struct parisc_device *d) {
+	return (d->id.hversion == MERCURY_HVERS);
+}
+
+static inline int IS_QUICKSILVER(struct parisc_device *d) {
+	return (d->id.hversion == QUICKSILVER_HVERS);
+}
+
+/*
+** I/O SAPIC init function
+** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
+** Call setup as part of per instance initialization.
+** (ie *not* init_module() function unless only one is present.)
+** fixup_irq is to initialize PCI IRQ line support and
+** virtualize pcidev->irq value. To be called by pci_fixup_bus().
+*/
+extern void *iosapic_register(unsigned long hpa);
+extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
+
+#endif /*_ASM_PARISC_ROPES_H_*/
...	...	@@ -146,7 +146,7 @@
146	146	#include <asm/superio.h>
147	147	#endif
148	148
149		-#include <asm/iosapic.h>
	149	+#include <asm/ropes.h>
150	150	#include "./iosapic_private.h"
151	151
152	152	#define MODULE_NAME "iosapic"
...	...	@@ -46,9 +46,9 @@
46	46	#include <asm/page.h>
47	47	#include <asm/system.h>
48	48
	49	+#include <asm/ropes.h>
49	50	#include <asm/hardware.h> /* for register_parisc_driver() stuff */
50	51	#include <asm/parisc-device.h>
51		-#include <asm/iosapic.h> /* for iosapic_register() */
52	52	#include <asm/io.h> /* read/write stuff */
53	53
54	54	#undef DEBUG_LBA /* general stuff */
...	...	@@ -168,44 +168,6 @@
168	168	/* non-postable I/O port space, densely packed */
169	169	#define LBA_PORT_BASE (PCI_F_EXTEND \| 0xfee00000UL)
170	170	static void __iomem *astro_iop_base __read_mostly;
171		-
172		-#define ELROY_HVERS 0x782
173		-#define MERCURY_HVERS 0x783
174		-#define QUICKSILVER_HVERS 0x784
175		-
176		-static inline int IS_ELROY(struct parisc_device *d)
177		-{
178		- return (d->id.hversion == ELROY_HVERS);
179		-}
180		-
181		-static inline int IS_MERCURY(struct parisc_device *d)
182		-{
183		- return (d->id.hversion == MERCURY_HVERS);
184		-}
185		-
186		-static inline int IS_QUICKSILVER(struct parisc_device *d)
187		-{
188		- return (d->id.hversion == QUICKSILVER_HVERS);
189		-}
190		-
191		-
192		-/*
193		-** lba_device: Per instance Elroy data structure
194		-*/
195		-struct lba_device {
196		- struct pci_hba_data hba;
197		-
198		- spinlock_t lba_lock;
199		- void *iosapic_obj;
200		-
201		-#ifdef CONFIG_64BIT
202		- void __iomem * iop_base; /* PA_VIEW - for IO port accessor funcs */
203		-#endif
204		-
205		- int flags; /* state/functionality enabled */
206		- int hw_rev; /* HW revision of chip */
207		-};
208		-
209	171
210	172	static u32 lba_t32;
211	173
...	...	@@ -38,6 +38,7 @@
38	38	#include <linux/proc_fs.h>
39	39	#include <linux/seq_file.h>
40	40
	41	+#include <asm/ropes.h>
41	42	#include <asm/mckinley.h> /* for proc_mckinley_root */
42	43	#include <asm/runway.h> /* for proc_runway_root */
43	44	#include <asm/pdc.h> /* for PDC_MODEL_* */
...	...	@@ -46,11 +47,6 @@
46	47
47	48	#define MODULE_NAME "SBA"
48	49
49		-#ifdef CONFIG_PROC_FS
50		-/* depends on proc fs support. But costs CPU performance */
51		-#undef SBA_COLLECT_STATS
52		-#endif
53		-
54	50	/*
55	51	** The number of debug flags is a clue - this code is fragile.
56	52	** Don't even think about messing with it unless you have
57	53
58	54
59	55
...	...	@@ -89,46 +85,13 @@
89	85	#define DBG_RES(x...)
90	86	#endif
91	87
92		-#if defined(CONFIG_64BIT)
93		-/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
94		-#define ZX1_SUPPORT
95		-#endif
96		-
97	88	#define SBA_INLINE __inline__
98	89
99		-
100		-/*
101		-** The number of pdir entries to "free" before issueing
102		-** a read to PCOM register to flush out PCOM writes.
103		-** Interacts with allocation granularity (ie 4 or 8 entries
104		-** allocated and free'd/purged at a time might make this
105		-** less interesting).
106		-*/
107		-#define DELAYED_RESOURCE_CNT 16
108		-
109	90	#define DEFAULT_DMA_HINT_REG 0
110	91
111		-#define ASTRO_RUNWAY_PORT 0x582
112		-#define IKE_MERCED_PORT 0x803
113		-#define REO_MERCED_PORT 0x804
114		-#define REOG_MERCED_PORT 0x805
115		-#define PLUTO_MCKINLEY_PORT 0x880
116		-
117	92	#define SBA_FUNC_ID 0x0000 /* function id */
118	93	#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
119	94
120		-static inline int IS_ASTRO(struct parisc_device *d) {
121		- return d->id.hversion == ASTRO_RUNWAY_PORT;
122		-}
123		-
124		-static inline int IS_IKE(struct parisc_device *d) {
125		- return d->id.hversion == IKE_MERCED_PORT;
126		-}
127		-
128		-static inline int IS_PLUTO(struct parisc_device *d) {
129		- return d->id.hversion == PLUTO_MCKINLEY_PORT;
130		-}
131		-
132	95	#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
133	96
134	97	#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
135	98
...	...	@@ -145,11 +108,7 @@
145	108	#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
146	109	#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
147	110
148		-#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
149	111
150		-#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
151		-
152		-
153	112	/*
154	113	** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
155	114	** Firmware programs this stuff. Don't touch it.
156	115
...	...	@@ -196,10 +155,7 @@
196	155	#define IOC_TCNFG 0x318
197	156	#define IOC_PDIR_BASE 0x320
198	157
199		-/* AGP GART driver looks for this */
200		-#define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
201	158
202		-
203	159	/*
204	160	** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
205	161	** It's safer (avoid memory corruption) to keep DMA page mappings
...	...	@@ -227,69 +183,6 @@
227	183	#define SBA_PERF_CNT1 0x200
228	184	#define SBA_PERF_CNT2 0x208
229	185	#define SBA_PERF_CNT3 0x210
230		-
231		-
232		-struct ioc {
233		- void __iomem ioc_hpa; / I/O MMU base address */
234		- char res_map; / resource map, bit == pdir entry */
235		- u64 pdir_base; / physical base address */
236		- unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
237		- unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
238		-#ifdef ZX1_SUPPORT
239		- unsigned long iovp_mask; /* help convert IOVA to IOVP */
240		-#endif
241		- unsigned long res_hint; / next avail IOVP - circular search */
242		- spinlock_t res_lock;
243		- unsigned int res_bitshift; /* from the LEFT! */
244		- unsigned int res_size; /* size of resource map in bytes */
245		-#ifdef SBA_HINT_SUPPORT
246		-/* FIXME : DMA HINTs not used */
247		- unsigned long hint_mask_pdir; /* bits used for DMA hints */
248		- unsigned int hint_shift_pdir;
249		-#endif
250		-#if DELAYED_RESOURCE_CNT > 0
251		- int saved_cnt;
252		- struct sba_dma_pair {
253		- dma_addr_t iova;
254		- size_t size;
255		- } saved[DELAYED_RESOURCE_CNT];
256		-#endif
257		-
258		-#ifdef SBA_COLLECT_STATS
259		-#define SBA_SEARCH_SAMPLE 0x100
260		- unsigned long avg_search[SBA_SEARCH_SAMPLE];
261		- unsigned long avg_idx; /* current index into avg_search */
262		- unsigned long used_pages;
263		- unsigned long msingle_calls;
264		- unsigned long msingle_pages;
265		- unsigned long msg_calls;
266		- unsigned long msg_pages;
267		- unsigned long usingle_calls;
268		- unsigned long usingle_pages;
269		- unsigned long usg_calls;
270		- unsigned long usg_pages;
271		-#endif
272		-
273		- /* STUFF We don't need in performance path */
274		- unsigned int pdir_size; /* in bytes, determined by IOV Space size */
275		-};
276		-
277		-struct sba_device {
278		- struct sba_device next; / list of SBA's in system */
279		- struct parisc_device dev; / dev found in bus walk */
280		- const char *name;
281		- void __iomem sba_hpa; / base address */
282		- spinlock_t sba_lock;
283		- unsigned int flags; /* state/functionality enabled */
284		- unsigned int hw_rev; /* HW revision of chip */
285		-
286		- struct resource chip_resv; /* MMIO reserved for chip */
287		- struct resource iommu_resv; /* MMIO reserved for iommu */
288		-
289		- unsigned int num_ioc; /* number of on-board IOC's */
290		- struct ioc ioc[MAX_IOC];
291		-};
292		-
293	186
294	187	static struct sba_device *sba_list;
295	188
1		-/*
2		-** This file is private to iosapic driver.
3		-** If stuff needs to be used by another driver, move it to a common file.
4		-**
5		-** WARNING: fields most data structures here are ordered to make sure
6		-** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
7		-*/
8		-
9		-
10		-/*
11		-** I/O SAPIC init function
12		-** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
13		-** Call setup as part of per instance initialization.
14		-** (ie not init_module() function unless only one is present.)
15		-** fixup_irq is to initialize PCI IRQ line support and
16		-** virtualize pcidev->irq value. To be called by pci_fixup_bus().
17		-*/
18		-extern void *iosapic_register(unsigned long hpa);
19		-extern int iosapic_fixup_irq(void obj, struct pci_dev pcidev);
20		-
21		-
22		-#ifdef __IA64__
23		-/*
24		-** PA: PIB (Processor Interrupt Block) is handled by Runway bus adapter.
25		-** and is hardcoded to 0xfeeNNNN0 where NNNN is id_eid field.
26		-**
27		-** IA64: PIB is handled by "Local SAPIC" (integrated in the processor).
28		-*/
29		-struct local_sapic_info {
30		- struct local_sapic_info lsi_next; / point to next CPU info */
31		- int lsi_cpu_id; / point to logical CPU id */
32		- unsigned long lsi_id_eid; / point to IA-64 CPU id */
33		- int lsi_status; / point to CPU status */
34		- void lsi_private; / point to special info */
35		-};
36		-
37		-/*
38		-** "root" data structure which ties everything together.
39		-** Should always be able to start with sapic_root and locate
40		-** the desired information.
41		-*/
42		-struct sapic_info {
43		- struct sapic_info si_next; / info is per cell */
44		- int si_cellid; /* cell id */
45		- unsigned int si_status; /* status */
46		- char si_pib_base; / intr blk base address */
47		- local_sapic_info_t *si_local_info;
48		- io_sapic_info_t *si_io_info;
49		- extint_info_t si_extint_info;/ External Intr info */
50		-};
51		-
52		-#endif /* IA64 */
	1	+#ifndef _ASM_PARISC_ROPES_H_
	2	+#define _ASM_PARISC_ROPES_H_
	3	+
	4	+#ifdef CONFIG_64BIT
	5	+/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
	6	+#define ZX1_SUPPORT
	7	+#endif
	8	+
	9	+#ifdef CONFIG_PROC_FS
	10	+/* depends on proc fs support. But costs CPU performance */
	11	+#undef SBA_COLLECT_STATS
	12	+#endif
	13	+
	14	+/*
	15	+** The number of pdir entries to "free" before issueing
	16	+** a read to PCOM register to flush out PCOM writes.
	17	+** Interacts with allocation granularity (ie 4 or 8 entries
	18	+** allocated and free'd/purged at a time might make this
	19	+** less interesting).
	20	+*/
	21	+#define DELAYED_RESOURCE_CNT 16
	22	+
	23	+#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
	24	+#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
	25	+
	26	+struct ioc {
	27	+ void __iomem ioc_hpa; / I/O MMU base address */
	28	+ char res_map; / resource map, bit == pdir entry */
	29	+ u64 pdir_base; / physical base address */
	30	+ unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
	31	+ unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
	32	+#ifdef ZX1_SUPPORT
	33	+ unsigned long iovp_mask; /* help convert IOVA to IOVP */
	34	+#endif
	35	+ unsigned long res_hint; / next avail IOVP - circular search */
	36	+ spinlock_t res_lock;
	37	+ unsigned int res_bitshift; /* from the LEFT! */
	38	+ unsigned int res_size; /* size of resource map in bytes */
	39	+#ifdef SBA_HINT_SUPPORT
	40	+/* FIXME : DMA HINTs not used */
	41	+ unsigned long hint_mask_pdir; /* bits used for DMA hints */
	42	+ unsigned int hint_shift_pdir;
	43	+#endif
	44	+#if DELAYED_RESOURCE_CNT > 0
	45	+ int saved_cnt;
	46	+ struct sba_dma_pair {
	47	+ dma_addr_t iova;
	48	+ size_t size;
	49	+ } saved[DELAYED_RESOURCE_CNT];
	50	+#endif
	51	+
	52	+#ifdef SBA_COLLECT_STATS
	53	+#define SBA_SEARCH_SAMPLE 0x100
	54	+ unsigned long avg_search[SBA_SEARCH_SAMPLE];
	55	+ unsigned long avg_idx; /* current index into avg_search */
	56	+ unsigned long used_pages;
	57	+ unsigned long msingle_calls;
	58	+ unsigned long msingle_pages;
	59	+ unsigned long msg_calls;
	60	+ unsigned long msg_pages;
	61	+ unsigned long usingle_calls;
	62	+ unsigned long usingle_pages;
	63	+ unsigned long usg_calls;
	64	+ unsigned long usg_pages;
	65	+#endif
	66	+ /* STUFF We don't need in performance path */
	67	+ unsigned int pdir_size; /* in bytes, determined by IOV Space size */
	68	+};
	69	+
	70	+struct sba_device {
	71	+ struct sba_device next; / list of SBA's in system */
	72	+ struct parisc_device dev; / dev found in bus walk */
	73	+ const char *name;
	74	+ void __iomem sba_hpa; / base address */
	75	+ spinlock_t sba_lock;
	76	+ unsigned int flags; /* state/functionality enabled */
	77	+ unsigned int hw_rev; /* HW revision of chip */
	78	+
	79	+ struct resource chip_resv; /* MMIO reserved for chip */
	80	+ struct resource iommu_resv; /* MMIO reserved for iommu */
	81	+
	82	+ unsigned int num_ioc; /* number of on-board IOC's */
	83	+ struct ioc ioc[MAX_IOC];
	84	+};
	85	+
	86	+#define ASTRO_RUNWAY_PORT 0x582
	87	+#define IKE_MERCED_PORT 0x803
	88	+#define REO_MERCED_PORT 0x804
	89	+#define REOG_MERCED_PORT 0x805
	90	+#define PLUTO_MCKINLEY_PORT 0x880
	91	+
	92	+static inline int IS_ASTRO(struct parisc_device *d) {
	93	+ return d->id.hversion == ASTRO_RUNWAY_PORT;
	94	+}
	95	+
	96	+static inline int IS_IKE(struct parisc_device *d) {
	97	+ return d->id.hversion == IKE_MERCED_PORT;
	98	+}
	99	+
	100	+static inline int IS_PLUTO(struct parisc_device *d) {
	101	+ return d->id.hversion == PLUTO_MCKINLEY_PORT;
	102	+}
	103	+
	104	+#define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
	105	+
	106	+/*
	107	+** lba_device: Per instance Elroy data structure
	108	+*/
	109	+struct lba_device {
	110	+ struct pci_hba_data hba;
	111	+
	112	+ spinlock_t lba_lock;
	113	+ void *iosapic_obj;
	114	+
	115	+#ifdef CONFIG_64BIT
	116	+ void __iomem iop_base; / PA_VIEW - for IO port accessor funcs */
	117	+#endif
	118	+
	119	+ int flags; /* state/functionality enabled */
	120	+ int hw_rev; /* HW revision of chip */
	121	+};
	122	+
	123	+#define ELROY_HVERS 0x782
	124	+#define MERCURY_HVERS 0x783
	125	+#define QUICKSILVER_HVERS 0x784
	126	+
	127	+static inline int IS_ELROY(struct parisc_device *d) {
	128	+ return (d->id.hversion == ELROY_HVERS);
	129	+}
	130	+
	131	+static inline int IS_MERCURY(struct parisc_device *d) {
	132	+ return (d->id.hversion == MERCURY_HVERS);
	133	+}
	134	+
	135	+static inline int IS_QUICKSILVER(struct parisc_device *d) {
	136	+ return (d->id.hversion == QUICKSILVER_HVERS);
	137	+}
	138	+
	139	+/*
	140	+** I/O SAPIC init function
	141	+** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
	142	+** Call setup as part of per instance initialization.
	143	+** (ie not init_module() function unless only one is present.)
	144	+** fixup_irq is to initialize PCI IRQ line support and
	145	+** virtualize pcidev->irq value. To be called by pci_fixup_bus().
	146	+*/
	147	+extern void *iosapic_register(unsigned long hpa);
	148	+extern int iosapic_fixup_irq(void obj, struct pci_dev pcidev);
	149	+
	150	+#endif /_ASM_PARISC_ROPES_H_/