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Commit 1b20f6a9adaa4b88d520d279c3d605f65b898625

Authored by Sergei Shtylyov
Committed by Tejun Heo
1 parent 8bfbeed586
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

sata_rcar: add 'base' local variable to some functions 

The 'base' field of 'struct sata_rcar_priv' is used very often
throughout the driver, so it seems worth loading it into a local
variable if it's used more than once in a function.

While at it, put some unitialized variables after intialized ones for
aesthetic reasons. :-)

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Tejun Heo <tj@kernel.org>

Showing 1 changed file with 57 additions and 45 deletions Inline Diff

drivers/ata/sata_rcar.c
Diff comments   View file @ 1b20f6a
1 /* 1 /*
2 * Renesas R-Car SATA driver 2 * Renesas R-Car SATA driver
3 * 3 *
4 * Author: Vladimir Barinov <source@cogentembedded.com> 4 * Author: Vladimir Barinov <source@cogentembedded.com>
5 * Copyright (C) 2013 Cogent Embedded, Inc. 5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * Copyright (C) 2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Renesas Solutions Corp.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your 10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14 #include <linux/kernel.h> 14 #include <linux/kernel.h>
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/ata.h> 16 #include <linux/ata.h>
17 #include <linux/libata.h> 17 #include <linux/libata.h>
18 #include <linux/platform_device.h> 18 #include <linux/platform_device.h>
19 #include <linux/clk.h> 19 #include <linux/clk.h>
20 #include <linux/err.h> 20 #include <linux/err.h>
21 21
22 #define DRV_NAME "sata_rcar" 22 #define DRV_NAME "sata_rcar"
23 23
24 /* SH-Navi2G/ATAPI-ATA compatible task registers */ 24 /* SH-Navi2G/ATAPI-ATA compatible task registers */
25 #define DATA_REG 0x100 25 #define DATA_REG 0x100
26 #define SDEVCON_REG 0x138 26 #define SDEVCON_REG 0x138
27 27
28 /* SH-Navi2G/ATAPI module compatible control registers */ 28 /* SH-Navi2G/ATAPI module compatible control registers */
29 #define ATAPI_CONTROL1_REG 0x180 29 #define ATAPI_CONTROL1_REG 0x180
30 #define ATAPI_STATUS_REG 0x184 30 #define ATAPI_STATUS_REG 0x184
31 #define ATAPI_INT_ENABLE_REG 0x188 31 #define ATAPI_INT_ENABLE_REG 0x188
32 #define ATAPI_DTB_ADR_REG 0x198 32 #define ATAPI_DTB_ADR_REG 0x198
33 #define ATAPI_DMA_START_ADR_REG 0x19C 33 #define ATAPI_DMA_START_ADR_REG 0x19C
34 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0 34 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0
35 #define ATAPI_CONTROL2_REG 0x1A4 35 #define ATAPI_CONTROL2_REG 0x1A4
36 #define ATAPI_SIG_ST_REG 0x1B0 36 #define ATAPI_SIG_ST_REG 0x1B0
37 #define ATAPI_BYTE_SWAP_REG 0x1BC 37 #define ATAPI_BYTE_SWAP_REG 0x1BC
38 38
39 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */ 39 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */
40 #define ATAPI_CONTROL1_ISM BIT(16) 40 #define ATAPI_CONTROL1_ISM BIT(16)
41 #define ATAPI_CONTROL1_DTA32M BIT(11) 41 #define ATAPI_CONTROL1_DTA32M BIT(11)
42 #define ATAPI_CONTROL1_RESET BIT(7) 42 #define ATAPI_CONTROL1_RESET BIT(7)
43 #define ATAPI_CONTROL1_DESE BIT(3) 43 #define ATAPI_CONTROL1_DESE BIT(3)
44 #define ATAPI_CONTROL1_RW BIT(2) 44 #define ATAPI_CONTROL1_RW BIT(2)
45 #define ATAPI_CONTROL1_STOP BIT(1) 45 #define ATAPI_CONTROL1_STOP BIT(1)
46 #define ATAPI_CONTROL1_START BIT(0) 46 #define ATAPI_CONTROL1_START BIT(0)
47 47
48 /* ATAPI status register (ATAPI_STATUS) bits */ 48 /* ATAPI status register (ATAPI_STATUS) bits */
49 #define ATAPI_STATUS_SATAINT BIT(11) 49 #define ATAPI_STATUS_SATAINT BIT(11)
50 #define ATAPI_STATUS_DNEND BIT(6) 50 #define ATAPI_STATUS_DNEND BIT(6)
51 #define ATAPI_STATUS_DEVTRM BIT(5) 51 #define ATAPI_STATUS_DEVTRM BIT(5)
52 #define ATAPI_STATUS_DEVINT BIT(4) 52 #define ATAPI_STATUS_DEVINT BIT(4)
53 #define ATAPI_STATUS_ERR BIT(2) 53 #define ATAPI_STATUS_ERR BIT(2)
54 #define ATAPI_STATUS_NEND BIT(1) 54 #define ATAPI_STATUS_NEND BIT(1)
55 #define ATAPI_STATUS_ACT BIT(0) 55 #define ATAPI_STATUS_ACT BIT(0)
56 56
57 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */ 57 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */
58 #define ATAPI_INT_ENABLE_SATAINT BIT(11) 58 #define ATAPI_INT_ENABLE_SATAINT BIT(11)
59 #define ATAPI_INT_ENABLE_DNEND BIT(6) 59 #define ATAPI_INT_ENABLE_DNEND BIT(6)
60 #define ATAPI_INT_ENABLE_DEVTRM BIT(5) 60 #define ATAPI_INT_ENABLE_DEVTRM BIT(5)
61 #define ATAPI_INT_ENABLE_DEVINT BIT(4) 61 #define ATAPI_INT_ENABLE_DEVINT BIT(4)
62 #define ATAPI_INT_ENABLE_ERR BIT(2) 62 #define ATAPI_INT_ENABLE_ERR BIT(2)
63 #define ATAPI_INT_ENABLE_NEND BIT(1) 63 #define ATAPI_INT_ENABLE_NEND BIT(1)
64 #define ATAPI_INT_ENABLE_ACT BIT(0) 64 #define ATAPI_INT_ENABLE_ACT BIT(0)
65 65
66 /* Access control registers for physical layer control register */ 66 /* Access control registers for physical layer control register */
67 #define SATAPHYADDR_REG 0x200 67 #define SATAPHYADDR_REG 0x200
68 #define SATAPHYWDATA_REG 0x204 68 #define SATAPHYWDATA_REG 0x204
69 #define SATAPHYACCEN_REG 0x208 69 #define SATAPHYACCEN_REG 0x208
70 #define SATAPHYRESET_REG 0x20C 70 #define SATAPHYRESET_REG 0x20C
71 #define SATAPHYRDATA_REG 0x210 71 #define SATAPHYRDATA_REG 0x210
72 #define SATAPHYACK_REG 0x214 72 #define SATAPHYACK_REG 0x214
73 73
74 /* Physical layer control address command register (SATAPHYADDR) bits */ 74 /* Physical layer control address command register (SATAPHYADDR) bits */
75 #define SATAPHYADDR_PHYRATEMODE BIT(10) 75 #define SATAPHYADDR_PHYRATEMODE BIT(10)
76 #define SATAPHYADDR_PHYCMD_READ BIT(9) 76 #define SATAPHYADDR_PHYCMD_READ BIT(9)
77 #define SATAPHYADDR_PHYCMD_WRITE BIT(8) 77 #define SATAPHYADDR_PHYCMD_WRITE BIT(8)
78 78
79 /* Physical layer control enable register (SATAPHYACCEN) bits */ 79 /* Physical layer control enable register (SATAPHYACCEN) bits */
80 #define SATAPHYACCEN_PHYLANE BIT(0) 80 #define SATAPHYACCEN_PHYLANE BIT(0)
81 81
82 /* Physical layer control reset register (SATAPHYRESET) bits */ 82 /* Physical layer control reset register (SATAPHYRESET) bits */
83 #define SATAPHYRESET_PHYRST BIT(1) 83 #define SATAPHYRESET_PHYRST BIT(1)
84 #define SATAPHYRESET_PHYSRES BIT(0) 84 #define SATAPHYRESET_PHYSRES BIT(0)
85 85
86 /* Physical layer control acknowledge register (SATAPHYACK) bits */ 86 /* Physical layer control acknowledge register (SATAPHYACK) bits */
87 #define SATAPHYACK_PHYACK BIT(0) 87 #define SATAPHYACK_PHYACK BIT(0)
88 88
89 /* Serial-ATA HOST control registers */ 89 /* Serial-ATA HOST control registers */
90 #define BISTCONF_REG 0x102C 90 #define BISTCONF_REG 0x102C
91 #define SDATA_REG 0x1100 91 #define SDATA_REG 0x1100
92 #define SSDEVCON_REG 0x1204 92 #define SSDEVCON_REG 0x1204
93 93
94 #define SCRSSTS_REG 0x1400 94 #define SCRSSTS_REG 0x1400
95 #define SCRSERR_REG 0x1404 95 #define SCRSERR_REG 0x1404
96 #define SCRSCON_REG 0x1408 96 #define SCRSCON_REG 0x1408
97 #define SCRSACT_REG 0x140C 97 #define SCRSACT_REG 0x140C
98 98
99 #define SATAINTSTAT_REG 0x1508 99 #define SATAINTSTAT_REG 0x1508
100 #define SATAINTMASK_REG 0x150C 100 #define SATAINTMASK_REG 0x150C
101 101
102 /* SATA INT status register (SATAINTSTAT) bits */ 102 /* SATA INT status register (SATAINTSTAT) bits */
103 #define SATAINTSTAT_SERR BIT(3) 103 #define SATAINTSTAT_SERR BIT(3)
104 #define SATAINTSTAT_ATA BIT(0) 104 #define SATAINTSTAT_ATA BIT(0)
105 105
106 /* SATA INT mask register (SATAINTSTAT) bits */ 106 /* SATA INT mask register (SATAINTSTAT) bits */
107 #define SATAINTMASK_SERRMSK BIT(3) 107 #define SATAINTMASK_SERRMSK BIT(3)
108 #define SATAINTMASK_ERRMSK BIT(2) 108 #define SATAINTMASK_ERRMSK BIT(2)
109 #define SATAINTMASK_ERRCRTMSK BIT(1) 109 #define SATAINTMASK_ERRCRTMSK BIT(1)
110 #define SATAINTMASK_ATAMSK BIT(0) 110 #define SATAINTMASK_ATAMSK BIT(0)
111 111
112 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \ 112 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \
113 SATAINTMASK_ATAMSK) 113 SATAINTMASK_ATAMSK)
114 114
115 /* Physical Layer Control Registers */ 115 /* Physical Layer Control Registers */
116 #define SATAPCTLR1_REG 0x43 116 #define SATAPCTLR1_REG 0x43
117 #define SATAPCTLR2_REG 0x52 117 #define SATAPCTLR2_REG 0x52
118 #define SATAPCTLR3_REG 0x5A 118 #define SATAPCTLR3_REG 0x5A
119 #define SATAPCTLR4_REG 0x60 119 #define SATAPCTLR4_REG 0x60
120 120
121 /* Descriptor table word 0 bit (when DTA32M = 1) */ 121 /* Descriptor table word 0 bit (when DTA32M = 1) */
122 #define SATA_RCAR_DTEND BIT(0) 122 #define SATA_RCAR_DTEND BIT(0)
123 123
124 #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL 124 #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
125 125
126 struct sata_rcar_priv { 126 struct sata_rcar_priv {
127 void __iomem *base; 127 void __iomem *base;
128 struct clk *clk; 128 struct clk *clk;
129 }; 129 };
130 130
131 static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv) 131 static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv)
132 { 132 {
133 void __iomem *base = priv->base;
134
133 /* idle state */ 135 /* idle state */
134 iowrite32(0, priv->base + SATAPHYADDR_REG); 136 iowrite32(0, base + SATAPHYADDR_REG);
135 /* reset */ 137 /* reset */
136 iowrite32(SATAPHYRESET_PHYRST, priv->base + SATAPHYRESET_REG); 138 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
137 udelay(10); 139 udelay(10);
138 /* deassert reset */ 140 /* deassert reset */
139 iowrite32(0, priv->base + SATAPHYRESET_REG); 141 iowrite32(0, base + SATAPHYRESET_REG);
140 } 142 }
141 143
142 static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val, 144 static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val,
143 int group) 145 int group)
144 { 146 {
147 void __iomem *base = priv->base;
145 int timeout; 148 int timeout;
146 149
147 /* deassert reset */ 150 /* deassert reset */
148 iowrite32(0, priv->base + SATAPHYRESET_REG); 151 iowrite32(0, base + SATAPHYRESET_REG);
149 /* lane 1 */ 152 /* lane 1 */
150 iowrite32(SATAPHYACCEN_PHYLANE, priv->base + SATAPHYACCEN_REG); 153 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
151 /* write phy register value */ 154 /* write phy register value */
152 iowrite32(val, priv->base + SATAPHYWDATA_REG); 155 iowrite32(val, base + SATAPHYWDATA_REG);
153 /* set register group */ 156 /* set register group */
154 if (group) 157 if (group)
155 reg |= SATAPHYADDR_PHYRATEMODE; 158 reg |= SATAPHYADDR_PHYRATEMODE;
156 /* write command */ 159 /* write command */
157 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, priv->base + SATAPHYADDR_REG); 160 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
158 /* wait for ack */ 161 /* wait for ack */
159 for (timeout = 0; timeout < 100; timeout++) { 162 for (timeout = 0; timeout < 100; timeout++) {
160 val = ioread32(priv->base + SATAPHYACK_REG); 163 val = ioread32(base + SATAPHYACK_REG);
161 if (val & SATAPHYACK_PHYACK) 164 if (val & SATAPHYACK_PHYACK)
162 break; 165 break;
163 } 166 }
164 if (timeout >= 100) 167 if (timeout >= 100)
165 pr_err("%s timeout\n", __func__); 168 pr_err("%s timeout\n", __func__);
166 /* idle state */ 169 /* idle state */
167 iowrite32(0, priv->base + SATAPHYADDR_REG); 170 iowrite32(0, base + SATAPHYADDR_REG);
168 } 171 }
169 172
170 static void sata_rcar_freeze(struct ata_port *ap) 173 static void sata_rcar_freeze(struct ata_port *ap)
171 { 174 {
172 struct sata_rcar_priv *priv = ap->host->private_data; 175 struct sata_rcar_priv *priv = ap->host->private_data;
173 176
174 /* mask */ 177 /* mask */
175 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 178 iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
176 179
177 ata_sff_freeze(ap); 180 ata_sff_freeze(ap);
178 } 181 }
179 182
180 static void sata_rcar_thaw(struct ata_port *ap) 183 static void sata_rcar_thaw(struct ata_port *ap)
181 { 184 {
182 struct sata_rcar_priv *priv = ap->host->private_data; 185 struct sata_rcar_priv *priv = ap->host->private_data;
186 void __iomem *base = priv->base;
183 187
184 /* ack */ 188 /* ack */
185 iowrite32(~SATA_RCAR_INT_MASK, priv->base + SATAINTSTAT_REG); 189 iowrite32(~SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
186 190
187 ata_sff_thaw(ap); 191 ata_sff_thaw(ap);
188 192
189 /* unmask */ 193 /* unmask */
190 iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, priv->base + SATAINTMASK_REG); 194 iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
191 } 195 }
192 196
193 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) 197 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
194 { 198 {
195 u16 *ptr = buffer; 199 u16 *ptr = buffer;
196 200
197 while (count--) { 201 while (count--) {
198 u16 data = ioread32(reg); 202 u16 data = ioread32(reg);
199 203
200 *ptr++ = data; 204 *ptr++ = data;
201 } 205 }
202 } 206 }
203 207
204 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count) 208 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
205 { 209 {
206 const u16 *ptr = buffer; 210 const u16 *ptr = buffer;
207 211
208 while (count--) 212 while (count--)
209 iowrite32(*ptr++, reg); 213 iowrite32(*ptr++, reg);
210 } 214 }
211 215
212 static u8 sata_rcar_check_status(struct ata_port *ap) 216 static u8 sata_rcar_check_status(struct ata_port *ap)
213 { 217 {
214 return ioread32(ap->ioaddr.status_addr); 218 return ioread32(ap->ioaddr.status_addr);
215 } 219 }
216 220
217 static u8 sata_rcar_check_altstatus(struct ata_port *ap) 221 static u8 sata_rcar_check_altstatus(struct ata_port *ap)
218 { 222 {
219 return ioread32(ap->ioaddr.altstatus_addr); 223 return ioread32(ap->ioaddr.altstatus_addr);
220 } 224 }
221 225
222 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl) 226 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
223 { 227 {
224 iowrite32(ctl, ap->ioaddr.ctl_addr); 228 iowrite32(ctl, ap->ioaddr.ctl_addr);
225 } 229 }
226 230
227 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device) 231 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
228 { 232 {
229 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr); 233 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
230 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 234 ata_sff_pause(ap); /* needed; also flushes, for mmio */
231 } 235 }
232 236
233 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap, 237 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
234 unsigned int device) 238 unsigned int device)
235 { 239 {
236 struct ata_ioports *ioaddr = &ap->ioaddr; 240 struct ata_ioports *ioaddr = &ap->ioaddr;
237 u8 nsect, lbal; 241 u8 nsect, lbal;
238 242
239 sata_rcar_dev_select(ap, device); 243 sata_rcar_dev_select(ap, device);
240 244
241 iowrite32(0x55, ioaddr->nsect_addr); 245 iowrite32(0x55, ioaddr->nsect_addr);
242 iowrite32(0xaa, ioaddr->lbal_addr); 246 iowrite32(0xaa, ioaddr->lbal_addr);
243 247
244 iowrite32(0xaa, ioaddr->nsect_addr); 248 iowrite32(0xaa, ioaddr->nsect_addr);
245 iowrite32(0x55, ioaddr->lbal_addr); 249 iowrite32(0x55, ioaddr->lbal_addr);
246 250
247 iowrite32(0x55, ioaddr->nsect_addr); 251 iowrite32(0x55, ioaddr->nsect_addr);
248 iowrite32(0xaa, ioaddr->lbal_addr); 252 iowrite32(0xaa, ioaddr->lbal_addr);
249 253
250 nsect = ioread32(ioaddr->nsect_addr); 254 nsect = ioread32(ioaddr->nsect_addr);
251 lbal = ioread32(ioaddr->lbal_addr); 255 lbal = ioread32(ioaddr->lbal_addr);
252 256
253 if (nsect == 0x55 && lbal == 0xaa) 257 if (nsect == 0x55 && lbal == 0xaa)
254 return 1; /* found a device */ 258 return 1; /* found a device */
255 259
256 return 0; /* nothing found */ 260 return 0; /* nothing found */
257 } 261 }
258 262
259 static int sata_rcar_wait_after_reset(struct ata_link *link, 263 static int sata_rcar_wait_after_reset(struct ata_link *link,
260 unsigned long deadline) 264 unsigned long deadline)
261 { 265 {
262 struct ata_port *ap = link->ap; 266 struct ata_port *ap = link->ap;
263 267
264 ata_msleep(ap, ATA_WAIT_AFTER_RESET); 268 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
265 269
266 return ata_sff_wait_ready(link, deadline); 270 return ata_sff_wait_ready(link, deadline);
267 } 271 }
268 272
269 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline) 273 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
270 { 274 {
271 struct ata_ioports *ioaddr = &ap->ioaddr; 275 struct ata_ioports *ioaddr = &ap->ioaddr;
272 276
273 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); 277 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
274 278
275 /* software reset. causes dev0 to be selected */ 279 /* software reset. causes dev0 to be selected */
276 iowrite32(ap->ctl, ioaddr->ctl_addr); 280 iowrite32(ap->ctl, ioaddr->ctl_addr);
277 udelay(20); 281 udelay(20);
278 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr); 282 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
279 udelay(20); 283 udelay(20);
280 iowrite32(ap->ctl, ioaddr->ctl_addr); 284 iowrite32(ap->ctl, ioaddr->ctl_addr);
281 ap->last_ctl = ap->ctl; 285 ap->last_ctl = ap->ctl;
282 286
283 /* wait the port to become ready */ 287 /* wait the port to become ready */
284 return sata_rcar_wait_after_reset(&ap->link, deadline); 288 return sata_rcar_wait_after_reset(&ap->link, deadline);
285 } 289 }
286 290
287 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes, 291 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
288 unsigned long deadline) 292 unsigned long deadline)
289 { 293 {
290 struct ata_port *ap = link->ap; 294 struct ata_port *ap = link->ap;
291 unsigned int devmask = 0; 295 unsigned int devmask = 0;
292 int rc; 296 int rc;
293 u8 err; 297 u8 err;
294 298
295 /* determine if device 0 is present */ 299 /* determine if device 0 is present */
296 if (sata_rcar_ata_devchk(ap, 0)) 300 if (sata_rcar_ata_devchk(ap, 0))
297 devmask |= 1 << 0; 301 devmask |= 1 << 0;
298 302
299 /* issue bus reset */ 303 /* issue bus reset */
300 DPRINTK("about to softreset, devmask=%x\n", devmask); 304 DPRINTK("about to softreset, devmask=%x\n", devmask);
301 rc = sata_rcar_bus_softreset(ap, deadline); 305 rc = sata_rcar_bus_softreset(ap, deadline);
302 /* if link is occupied, -ENODEV too is an error */ 306 /* if link is occupied, -ENODEV too is an error */
303 if (rc && (rc != -ENODEV || sata_scr_valid(link))) { 307 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
304 ata_link_err(link, "SRST failed (errno=%d)\n", rc); 308 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
305 return rc; 309 return rc;
306 } 310 }
307 311
308 /* determine by signature whether we have ATA or ATAPI devices */ 312 /* determine by signature whether we have ATA or ATAPI devices */
309 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err); 313 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
310 314
311 DPRINTK("classes[0]=%u\n", classes[0]); 315 DPRINTK("classes[0]=%u\n", classes[0]);
312 return 0; 316 return 0;
313 } 317 }
314 318
315 static void sata_rcar_tf_load(struct ata_port *ap, 319 static void sata_rcar_tf_load(struct ata_port *ap,
316 const struct ata_taskfile *tf) 320 const struct ata_taskfile *tf)
317 { 321 {
318 struct ata_ioports *ioaddr = &ap->ioaddr; 322 struct ata_ioports *ioaddr = &ap->ioaddr;
319 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 323 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
320 324
321 if (tf->ctl != ap->last_ctl) { 325 if (tf->ctl != ap->last_ctl) {
322 iowrite32(tf->ctl, ioaddr->ctl_addr); 326 iowrite32(tf->ctl, ioaddr->ctl_addr);
323 ap->last_ctl = tf->ctl; 327 ap->last_ctl = tf->ctl;
324 ata_wait_idle(ap); 328 ata_wait_idle(ap);
325 } 329 }
326 330
327 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 331 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
328 iowrite32(tf->hob_feature, ioaddr->feature_addr); 332 iowrite32(tf->hob_feature, ioaddr->feature_addr);
329 iowrite32(tf->hob_nsect, ioaddr->nsect_addr); 333 iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
330 iowrite32(tf->hob_lbal, ioaddr->lbal_addr); 334 iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
331 iowrite32(tf->hob_lbam, ioaddr->lbam_addr); 335 iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
332 iowrite32(tf->hob_lbah, ioaddr->lbah_addr); 336 iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
333 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 337 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
334 tf->hob_feature, 338 tf->hob_feature,
335 tf->hob_nsect, 339 tf->hob_nsect,
336 tf->hob_lbal, 340 tf->hob_lbal,
337 tf->hob_lbam, 341 tf->hob_lbam,
338 tf->hob_lbah); 342 tf->hob_lbah);
339 } 343 }
340 344
341 if (is_addr) { 345 if (is_addr) {
342 iowrite32(tf->feature, ioaddr->feature_addr); 346 iowrite32(tf->feature, ioaddr->feature_addr);
343 iowrite32(tf->nsect, ioaddr->nsect_addr); 347 iowrite32(tf->nsect, ioaddr->nsect_addr);
344 iowrite32(tf->lbal, ioaddr->lbal_addr); 348 iowrite32(tf->lbal, ioaddr->lbal_addr);
345 iowrite32(tf->lbam, ioaddr->lbam_addr); 349 iowrite32(tf->lbam, ioaddr->lbam_addr);
346 iowrite32(tf->lbah, ioaddr->lbah_addr); 350 iowrite32(tf->lbah, ioaddr->lbah_addr);
347 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 351 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
348 tf->feature, 352 tf->feature,
349 tf->nsect, 353 tf->nsect,
350 tf->lbal, 354 tf->lbal,
351 tf->lbam, 355 tf->lbam,
352 tf->lbah); 356 tf->lbah);
353 } 357 }
354 358
355 if (tf->flags & ATA_TFLAG_DEVICE) { 359 if (tf->flags & ATA_TFLAG_DEVICE) {
356 iowrite32(tf->device, ioaddr->device_addr); 360 iowrite32(tf->device, ioaddr->device_addr);
357 VPRINTK("device 0x%X\n", tf->device); 361 VPRINTK("device 0x%X\n", tf->device);
358 } 362 }
359 363
360 ata_wait_idle(ap); 364 ata_wait_idle(ap);
361 } 365 }
362 366
363 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 367 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
364 { 368 {
365 struct ata_ioports *ioaddr = &ap->ioaddr; 369 struct ata_ioports *ioaddr = &ap->ioaddr;
366 370
367 tf->command = sata_rcar_check_status(ap); 371 tf->command = sata_rcar_check_status(ap);
368 tf->feature = ioread32(ioaddr->error_addr); 372 tf->feature = ioread32(ioaddr->error_addr);
369 tf->nsect = ioread32(ioaddr->nsect_addr); 373 tf->nsect = ioread32(ioaddr->nsect_addr);
370 tf->lbal = ioread32(ioaddr->lbal_addr); 374 tf->lbal = ioread32(ioaddr->lbal_addr);
371 tf->lbam = ioread32(ioaddr->lbam_addr); 375 tf->lbam = ioread32(ioaddr->lbam_addr);
372 tf->lbah = ioread32(ioaddr->lbah_addr); 376 tf->lbah = ioread32(ioaddr->lbah_addr);
373 tf->device = ioread32(ioaddr->device_addr); 377 tf->device = ioread32(ioaddr->device_addr);
374 378
375 if (tf->flags & ATA_TFLAG_LBA48) { 379 if (tf->flags & ATA_TFLAG_LBA48) {
376 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 380 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
377 tf->hob_feature = ioread32(ioaddr->error_addr); 381 tf->hob_feature = ioread32(ioaddr->error_addr);
378 tf->hob_nsect = ioread32(ioaddr->nsect_addr); 382 tf->hob_nsect = ioread32(ioaddr->nsect_addr);
379 tf->hob_lbal = ioread32(ioaddr->lbal_addr); 383 tf->hob_lbal = ioread32(ioaddr->lbal_addr);
380 tf->hob_lbam = ioread32(ioaddr->lbam_addr); 384 tf->hob_lbam = ioread32(ioaddr->lbam_addr);
381 tf->hob_lbah = ioread32(ioaddr->lbah_addr); 385 tf->hob_lbah = ioread32(ioaddr->lbah_addr);
382 iowrite32(tf->ctl, ioaddr->ctl_addr); 386 iowrite32(tf->ctl, ioaddr->ctl_addr);
383 ap->last_ctl = tf->ctl; 387 ap->last_ctl = tf->ctl;
384 } 388 }
385 } 389 }
386 390
387 static void sata_rcar_exec_command(struct ata_port *ap, 391 static void sata_rcar_exec_command(struct ata_port *ap,
388 const struct ata_taskfile *tf) 392 const struct ata_taskfile *tf)
389 { 393 {
390 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 394 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
391 395
392 iowrite32(tf->command, ap->ioaddr.command_addr); 396 iowrite32(tf->command, ap->ioaddr.command_addr);
393 ata_sff_pause(ap); 397 ata_sff_pause(ap);
394 } 398 }
395 399
396 static unsigned int sata_rcar_data_xfer(struct ata_device *dev, 400 static unsigned int sata_rcar_data_xfer(struct ata_device *dev,
397 unsigned char *buf, 401 unsigned char *buf,
398 unsigned int buflen, int rw) 402 unsigned int buflen, int rw)
399 { 403 {
400 struct ata_port *ap = dev->link->ap; 404 struct ata_port *ap = dev->link->ap;
401 void __iomem *data_addr = ap->ioaddr.data_addr; 405 void __iomem *data_addr = ap->ioaddr.data_addr;
402 unsigned int words = buflen >> 1; 406 unsigned int words = buflen >> 1;
403 407
404 /* Transfer multiple of 2 bytes */ 408 /* Transfer multiple of 2 bytes */
405 if (rw == READ) 409 if (rw == READ)
406 sata_rcar_ioread16_rep(data_addr, buf, words); 410 sata_rcar_ioread16_rep(data_addr, buf, words);
407 else 411 else
408 sata_rcar_iowrite16_rep(data_addr, buf, words); 412 sata_rcar_iowrite16_rep(data_addr, buf, words);
409 413
410 /* Transfer trailing byte, if any. */ 414 /* Transfer trailing byte, if any. */
411 if (unlikely(buflen & 0x01)) { 415 if (unlikely(buflen & 0x01)) {
412 unsigned char pad[2] = { }; 416 unsigned char pad[2] = { };
413 417
414 /* Point buf to the tail of buffer */ 418 /* Point buf to the tail of buffer */
415 buf += buflen - 1; 419 buf += buflen - 1;
416 420
417 /* 421 /*
418 * Use io*16_rep() accessors here as well to avoid pointlessly 422 * Use io*16_rep() accessors here as well to avoid pointlessly
419 * swapping bytes to and from on the big endian machines... 423 * swapping bytes to and from on the big endian machines...
420 */ 424 */
421 if (rw == READ) { 425 if (rw == READ) {
422 sata_rcar_ioread16_rep(data_addr, pad, 1); 426 sata_rcar_ioread16_rep(data_addr, pad, 1);
423 *buf = pad[0]; 427 *buf = pad[0];
424 } else { 428 } else {
425 pad[0] = *buf; 429 pad[0] = *buf;
426 sata_rcar_iowrite16_rep(data_addr, pad, 1); 430 sata_rcar_iowrite16_rep(data_addr, pad, 1);
427 } 431 }
428 words++; 432 words++;
429 } 433 }
430 434
431 return words << 1; 435 return words << 1;
432 } 436 }
433 437
434 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc) 438 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
435 { 439 {
436 int count; 440 int count;
437 struct ata_port *ap; 441 struct ata_port *ap;
438 442
439 /* We only need to flush incoming data when a command was running */ 443 /* We only need to flush incoming data when a command was running */
440 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) 444 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
441 return; 445 return;
442 446
443 ap = qc->ap; 447 ap = qc->ap;
444 /* Drain up to 64K of data before we give up this recovery method */ 448 /* Drain up to 64K of data before we give up this recovery method */
445 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) && 449 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
446 count < 65536; count += 2) 450 count < 65536; count += 2)
447 ioread32(ap->ioaddr.data_addr); 451 ioread32(ap->ioaddr.data_addr);
448 452
449 /* Can become DEBUG later */ 453 /* Can become DEBUG later */
450 if (count) 454 if (count)
451 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); 455 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
452 } 456 }
453 457
454 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg, 458 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
455 u32 *val) 459 u32 *val)
456 { 460 {
457 if (sc_reg > SCR_ACTIVE) 461 if (sc_reg > SCR_ACTIVE)
458 return -EINVAL; 462 return -EINVAL;
459 463
460 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2)); 464 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
461 return 0; 465 return 0;
462 } 466 }
463 467
464 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg, 468 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
465 u32 val) 469 u32 val)
466 { 470 {
467 if (sc_reg > SCR_ACTIVE) 471 if (sc_reg > SCR_ACTIVE)
468 return -EINVAL; 472 return -EINVAL;
469 473
470 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2)); 474 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
471 return 0; 475 return 0;
472 } 476 }
473 477
474 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) 478 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
475 { 479 {
476 struct ata_port *ap = qc->ap; 480 struct ata_port *ap = qc->ap;
477 struct ata_bmdma_prd *prd = ap->bmdma_prd; 481 struct ata_bmdma_prd *prd = ap->bmdma_prd;
478 struct scatterlist *sg; 482 struct scatterlist *sg;
479 unsigned int si; 483 unsigned int si;
480 484
481 for_each_sg(qc->sg, sg, qc->n_elem, si) { 485 for_each_sg(qc->sg, sg, qc->n_elem, si) {
482 u32 addr, sg_len; 486 u32 addr, sg_len;
483 487
484 /* 488 /*
485 * Note: h/w doesn't support 64-bit, so we unconditionally 489 * Note: h/w doesn't support 64-bit, so we unconditionally
486 * truncate dma_addr_t to u32. 490 * truncate dma_addr_t to u32.
487 */ 491 */
488 addr = (u32)sg_dma_address(sg); 492 addr = (u32)sg_dma_address(sg);
489 sg_len = sg_dma_len(sg); 493 sg_len = sg_dma_len(sg);
490 494
491 prd[si].addr = cpu_to_le32(addr); 495 prd[si].addr = cpu_to_le32(addr);
492 prd[si].flags_len = cpu_to_le32(sg_len); 496 prd[si].flags_len = cpu_to_le32(sg_len);
493 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len); 497 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
494 } 498 }
495 499
496 /* end-of-table flag */ 500 /* end-of-table flag */
497 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); 501 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
498 } 502 }
499 503
500 static void sata_rcar_qc_prep(struct ata_queued_cmd *qc) 504 static void sata_rcar_qc_prep(struct ata_queued_cmd *qc)
501 { 505 {
502 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 506 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
503 return; 507 return;
504 508
505 sata_rcar_bmdma_fill_sg(qc); 509 sata_rcar_bmdma_fill_sg(qc);
506 } 510 }
507 511
508 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) 512 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
509 { 513 {
510 struct ata_port *ap = qc->ap; 514 struct ata_port *ap = qc->ap;
511 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; 515 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
512 u32 dmactl;
513 struct sata_rcar_priv *priv = ap->host->private_data; 516 struct sata_rcar_priv *priv = ap->host->private_data;
517 void __iomem *base = priv->base;
518 u32 dmactl;
514 519
515 /* load PRD table addr. */ 520 /* load PRD table addr. */
516 mb(); /* make sure PRD table writes are visible to controller */ 521 mb(); /* make sure PRD table writes are visible to controller */
517 iowrite32(ap->bmdma_prd_dma, priv->base + ATAPI_DTB_ADR_REG); 522 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
518 523
519 /* specify data direction, triple-check start bit is clear */ 524 /* specify data direction, triple-check start bit is clear */
520 dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); 525 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
521 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); 526 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
522 if (dmactl & ATAPI_CONTROL1_START) { 527 if (dmactl & ATAPI_CONTROL1_START) {
523 dmactl &= ~ATAPI_CONTROL1_START; 528 dmactl &= ~ATAPI_CONTROL1_START;
524 dmactl |= ATAPI_CONTROL1_STOP; 529 dmactl |= ATAPI_CONTROL1_STOP;
525 } 530 }
526 if (!rw) 531 if (!rw)
527 dmactl |= ATAPI_CONTROL1_RW; 532 dmactl |= ATAPI_CONTROL1_RW;
528 iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); 533 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
529 534
530 /* issue r/w command */ 535 /* issue r/w command */
531 ap->ops->sff_exec_command(ap, &qc->tf); 536 ap->ops->sff_exec_command(ap, &qc->tf);
532 } 537 }
533 538
534 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) 539 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
535 { 540 {
536 struct ata_port *ap = qc->ap; 541 struct ata_port *ap = qc->ap;
537 u32 dmactl;
538 struct sata_rcar_priv *priv = ap->host->private_data; 542 struct sata_rcar_priv *priv = ap->host->private_data;
543 void __iomem *base = priv->base;
544 u32 dmactl;
539 545
540 /* start host DMA transaction */ 546 /* start host DMA transaction */
541 dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); 547 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
542 dmactl |= ATAPI_CONTROL1_START; 548 dmactl |= ATAPI_CONTROL1_START;
543 iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); 549 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
544 } 550 }
545 551
546 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) 552 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
547 { 553 {
548 struct ata_port *ap = qc->ap; 554 struct ata_port *ap = qc->ap;
549 struct sata_rcar_priv *priv = ap->host->private_data; 555 struct sata_rcar_priv *priv = ap->host->private_data;
556 void __iomem *base = priv->base;
550 u32 dmactl; 557 u32 dmactl;
551 558
552 /* force termination of DMA transfer if active */ 559 /* force termination of DMA transfer if active */
553 dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); 560 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
554 if (dmactl & ATAPI_CONTROL1_START) { 561 if (dmactl & ATAPI_CONTROL1_START) {
555 dmactl &= ~ATAPI_CONTROL1_START; 562 dmactl &= ~ATAPI_CONTROL1_START;
556 dmactl |= ATAPI_CONTROL1_STOP; 563 dmactl |= ATAPI_CONTROL1_STOP;
557 iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); 564 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
558 } 565 }
559 566
560 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 567 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
561 ata_sff_dma_pause(ap); 568 ata_sff_dma_pause(ap);
562 } 569 }
563 570
564 static u8 sata_rcar_bmdma_status(struct ata_port *ap) 571 static u8 sata_rcar_bmdma_status(struct ata_port *ap)
565 { 572 {
566 struct sata_rcar_priv *priv = ap->host->private_data; 573 struct sata_rcar_priv *priv = ap->host->private_data;
567 u32 status;
568 u8 host_stat = 0; 574 u8 host_stat = 0;
575 u32 status;
569 576
570 status = ioread32(priv->base + ATAPI_STATUS_REG); 577 status = ioread32(priv->base + ATAPI_STATUS_REG);
571 if (status & ATAPI_STATUS_DEVINT) 578 if (status & ATAPI_STATUS_DEVINT)
572 host_stat |= ATA_DMA_INTR; 579 host_stat |= ATA_DMA_INTR;
573 if (status & ATAPI_STATUS_ACT) 580 if (status & ATAPI_STATUS_ACT)
574 host_stat |= ATA_DMA_ACTIVE; 581 host_stat |= ATA_DMA_ACTIVE;
575 582
576 return host_stat; 583 return host_stat;
577 } 584 }
578 585
579 static struct scsi_host_template sata_rcar_sht = { 586 static struct scsi_host_template sata_rcar_sht = {
580 ATA_BASE_SHT(DRV_NAME), 587 ATA_BASE_SHT(DRV_NAME),
581 /* 588 /*
582 * This controller allows transfer chunks up to 512MB which cross 64KB 589 * This controller allows transfer chunks up to 512MB which cross 64KB
583 * boundaries, therefore the DMA limits are more relaxed than standard 590 * boundaries, therefore the DMA limits are more relaxed than standard
584 * ATA SFF. 591 * ATA SFF.
585 */ 592 */
586 .sg_tablesize = ATA_MAX_PRD, 593 .sg_tablesize = ATA_MAX_PRD,
587 .dma_boundary = SATA_RCAR_DMA_BOUNDARY, 594 .dma_boundary = SATA_RCAR_DMA_BOUNDARY,
588 }; 595 };
589 596
590 static struct ata_port_operations sata_rcar_port_ops = { 597 static struct ata_port_operations sata_rcar_port_ops = {
591 .inherits = &ata_bmdma_port_ops, 598 .inherits = &ata_bmdma_port_ops,
592 599
593 .freeze = sata_rcar_freeze, 600 .freeze = sata_rcar_freeze,
594 .thaw = sata_rcar_thaw, 601 .thaw = sata_rcar_thaw,
595 .softreset = sata_rcar_softreset, 602 .softreset = sata_rcar_softreset,
596 603
597 .scr_read = sata_rcar_scr_read, 604 .scr_read = sata_rcar_scr_read,
598 .scr_write = sata_rcar_scr_write, 605 .scr_write = sata_rcar_scr_write,
599 606
600 .sff_dev_select = sata_rcar_dev_select, 607 .sff_dev_select = sata_rcar_dev_select,
601 .sff_set_devctl = sata_rcar_set_devctl, 608 .sff_set_devctl = sata_rcar_set_devctl,
602 .sff_check_status = sata_rcar_check_status, 609 .sff_check_status = sata_rcar_check_status,
603 .sff_check_altstatus = sata_rcar_check_altstatus, 610 .sff_check_altstatus = sata_rcar_check_altstatus,
604 .sff_tf_load = sata_rcar_tf_load, 611 .sff_tf_load = sata_rcar_tf_load,
605 .sff_tf_read = sata_rcar_tf_read, 612 .sff_tf_read = sata_rcar_tf_read,
606 .sff_exec_command = sata_rcar_exec_command, 613 .sff_exec_command = sata_rcar_exec_command,
607 .sff_data_xfer = sata_rcar_data_xfer, 614 .sff_data_xfer = sata_rcar_data_xfer,
608 .sff_drain_fifo = sata_rcar_drain_fifo, 615 .sff_drain_fifo = sata_rcar_drain_fifo,
609 616
610 .qc_prep = sata_rcar_qc_prep, 617 .qc_prep = sata_rcar_qc_prep,
611 618
612 .bmdma_setup = sata_rcar_bmdma_setup, 619 .bmdma_setup = sata_rcar_bmdma_setup,
613 .bmdma_start = sata_rcar_bmdma_start, 620 .bmdma_start = sata_rcar_bmdma_start,
614 .bmdma_stop = sata_rcar_bmdma_stop, 621 .bmdma_stop = sata_rcar_bmdma_stop,
615 .bmdma_status = sata_rcar_bmdma_status, 622 .bmdma_status = sata_rcar_bmdma_status,
616 }; 623 };
617 624
618 static int sata_rcar_serr_interrupt(struct ata_port *ap) 625 static int sata_rcar_serr_interrupt(struct ata_port *ap)
619 { 626 {
620 struct sata_rcar_priv *priv = ap->host->private_data; 627 struct sata_rcar_priv *priv = ap->host->private_data;
621 struct ata_eh_info *ehi = &ap->link.eh_info; 628 struct ata_eh_info *ehi = &ap->link.eh_info;
622 int freeze = 0; 629 int freeze = 0;
623 int handled = 0; 630 int handled = 0;
624 u32 serror; 631 u32 serror;
625 632
626 serror = ioread32(priv->base + SCRSERR_REG); 633 serror = ioread32(priv->base + SCRSERR_REG);
627 if (!serror) 634 if (!serror)
628 return 0; 635 return 0;
629 636
630 DPRINTK("SError @host_intr: 0x%x\n", serror); 637 DPRINTK("SError @host_intr: 0x%x\n", serror);
631 638
632 /* first, analyze and record host port events */ 639 /* first, analyze and record host port events */
633 ata_ehi_clear_desc(ehi); 640 ata_ehi_clear_desc(ehi);
634 641
635 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) { 642 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
636 /* Setup a soft-reset EH action */ 643 /* Setup a soft-reset EH action */
637 ata_ehi_hotplugged(ehi); 644 ata_ehi_hotplugged(ehi);
638 ata_ehi_push_desc(ehi, "%s", "hotplug"); 645 ata_ehi_push_desc(ehi, "%s", "hotplug");
639 646
640 freeze = serror & SERR_COMM_WAKE ? 0 : 1; 647 freeze = serror & SERR_COMM_WAKE ? 0 : 1;
641 handled = 1; 648 handled = 1;
642 } 649 }
643 650
644 /* freeze or abort */ 651 /* freeze or abort */
645 if (freeze) 652 if (freeze)
646 ata_port_freeze(ap); 653 ata_port_freeze(ap);
647 else 654 else
648 ata_port_abort(ap); 655 ata_port_abort(ap);
649 656
650 return handled; 657 return handled;
651 } 658 }
652 659
653 static int sata_rcar_ata_interrupt(struct ata_port *ap) 660 static int sata_rcar_ata_interrupt(struct ata_port *ap)
654 { 661 {
655 struct ata_queued_cmd *qc; 662 struct ata_queued_cmd *qc;
656 int handled = 0; 663 int handled = 0;
657 664
658 qc = ata_qc_from_tag(ap, ap->link.active_tag); 665 qc = ata_qc_from_tag(ap, ap->link.active_tag);
659 if (qc) 666 if (qc)
660 handled |= ata_bmdma_port_intr(ap, qc); 667 handled |= ata_bmdma_port_intr(ap, qc);
661 668
662 return handled; 669 return handled;
663 } 670 }
664 671
665 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) 672 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
666 { 673 {
667 struct ata_host *host = dev_instance; 674 struct ata_host *host = dev_instance;
668 struct sata_rcar_priv *priv = host->private_data; 675 struct sata_rcar_priv *priv = host->private_data;
669 struct ata_port *ap; 676 void __iomem *base = priv->base;
670 unsigned int handled = 0; 677 unsigned int handled = 0;
678 struct ata_port *ap;
671 u32 sataintstat; 679 u32 sataintstat;
672 unsigned long flags; 680 unsigned long flags;
673 681
674 spin_lock_irqsave(&host->lock, flags); 682 spin_lock_irqsave(&host->lock, flags);
675 683
676 sataintstat = ioread32(priv->base + SATAINTSTAT_REG); 684 sataintstat = ioread32(base + SATAINTSTAT_REG);
677 if (!sataintstat) 685 if (!sataintstat)
678 goto done; 686 goto done;
679 /* ack */ 687 /* ack */
680 iowrite32(sataintstat & ~SATA_RCAR_INT_MASK, 688 iowrite32(sataintstat & ~SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
681 priv->base + SATAINTSTAT_REG);
682 689
683 ap = host->ports[0]; 690 ap = host->ports[0];
684 691
685 if (sataintstat & SATAINTSTAT_ATA) 692 if (sataintstat & SATAINTSTAT_ATA)
686 handled |= sata_rcar_ata_interrupt(ap); 693 handled |= sata_rcar_ata_interrupt(ap);
687 694
688 if (sataintstat & SATAINTSTAT_SERR) 695 if (sataintstat & SATAINTSTAT_SERR)
689 handled |= sata_rcar_serr_interrupt(ap); 696 handled |= sata_rcar_serr_interrupt(ap);
690 697
691 done: 698 done:
692 spin_unlock_irqrestore(&host->lock, flags); 699 spin_unlock_irqrestore(&host->lock, flags);
693 700
694 return IRQ_RETVAL(handled); 701 return IRQ_RETVAL(handled);
695 } 702 }
696 703
697 static void sata_rcar_setup_port(struct ata_host *host) 704 static void sata_rcar_setup_port(struct ata_host *host)
698 { 705 {
699 struct ata_port *ap = host->ports[0]; 706 struct ata_port *ap = host->ports[0];
700 struct ata_ioports *ioaddr = &ap->ioaddr; 707 struct ata_ioports *ioaddr = &ap->ioaddr;
701 struct sata_rcar_priv *priv = host->private_data; 708 struct sata_rcar_priv *priv = host->private_data;
709 void __iomem *base = priv->base;
702 710
703 ap->ops = &sata_rcar_port_ops; 711 ap->ops = &sata_rcar_port_ops;
704 ap->pio_mask = ATA_PIO4; 712 ap->pio_mask = ATA_PIO4;
705 ap->udma_mask = ATA_UDMA6; 713 ap->udma_mask = ATA_UDMA6;
706 ap->flags |= ATA_FLAG_SATA; 714 ap->flags |= ATA_FLAG_SATA;
707 715
708 ioaddr->cmd_addr = priv->base + SDATA_REG; 716 ioaddr->cmd_addr = base + SDATA_REG;
709 ioaddr->ctl_addr = priv->base + SSDEVCON_REG; 717 ioaddr->ctl_addr = base + SSDEVCON_REG;
710 ioaddr->scr_addr = priv->base + SCRSSTS_REG; 718 ioaddr->scr_addr = base + SCRSSTS_REG;
711 ioaddr->altstatus_addr = ioaddr->ctl_addr; 719 ioaddr->altstatus_addr = ioaddr->ctl_addr;
712 720
713 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); 721 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
714 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2); 722 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
715 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2); 723 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
716 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2); 724 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
717 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2); 725 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
718 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2); 726 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
719 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2); 727 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
720 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2); 728 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
721 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2); 729 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
722 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2); 730 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
723 } 731 }
724 732
725 static void sata_rcar_init_controller(struct ata_host *host) 733 static void sata_rcar_init_controller(struct ata_host *host)
726 { 734 {
727 struct sata_rcar_priv *priv = host->private_data; 735 struct sata_rcar_priv *priv = host->private_data;
736 void __iomem *base = priv->base;
728 u32 val; 737 u32 val;
729 738
730 /* reset and setup phy */ 739 /* reset and setup phy */
731 sata_rcar_phy_initialize(priv); 740 sata_rcar_phy_initialize(priv);
732 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); 741 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
733 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); 742 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
734 sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); 743 sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
735 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); 744 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
736 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); 745 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
737 sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); 746 sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
738 747
739 /* SATA-IP reset state */ 748 /* SATA-IP reset state */
740 val = ioread32(priv->base + ATAPI_CONTROL1_REG); 749 val = ioread32(base + ATAPI_CONTROL1_REG);
741 val |= ATAPI_CONTROL1_RESET; 750 val |= ATAPI_CONTROL1_RESET;
742 iowrite32(val, priv->base + ATAPI_CONTROL1_REG); 751 iowrite32(val, base + ATAPI_CONTROL1_REG);
743 752
744 /* ISM mode, PRD mode, DTEND flag at bit 0 */ 753 /* ISM mode, PRD mode, DTEND flag at bit 0 */
745 val = ioread32(priv->base + ATAPI_CONTROL1_REG); 754 val = ioread32(base + ATAPI_CONTROL1_REG);
746 val |= ATAPI_CONTROL1_ISM; 755 val |= ATAPI_CONTROL1_ISM;
747 val |= ATAPI_CONTROL1_DESE; 756 val |= ATAPI_CONTROL1_DESE;
748 val |= ATAPI_CONTROL1_DTA32M; 757 val |= ATAPI_CONTROL1_DTA32M;
749 iowrite32(val, priv->base + ATAPI_CONTROL1_REG); 758 iowrite32(val, base + ATAPI_CONTROL1_REG);
750 759
751 /* Release the SATA-IP from the reset state */ 760 /* Release the SATA-IP from the reset state */
752 val = ioread32(priv->base + ATAPI_CONTROL1_REG); 761 val = ioread32(base + ATAPI_CONTROL1_REG);
753 val &= ~ATAPI_CONTROL1_RESET; 762 val &= ~ATAPI_CONTROL1_RESET;
754 iowrite32(val, priv->base + ATAPI_CONTROL1_REG); 763 iowrite32(val, base + ATAPI_CONTROL1_REG);
755 764
756 /* ack and mask */ 765 /* ack and mask */
757 iowrite32(0, priv->base + SATAINTSTAT_REG); 766 iowrite32(0, base + SATAINTSTAT_REG);
758 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 767 iowrite32(0x7ff, base + SATAINTMASK_REG);
759 /* enable interrupts */ 768 /* enable interrupts */
760 iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); 769 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
761 } 770 }
762 771
763 static int sata_rcar_probe(struct platform_device *pdev) 772 static int sata_rcar_probe(struct platform_device *pdev)
764 { 773 {
765 struct ata_host *host; 774 struct ata_host *host;
766 struct sata_rcar_priv *priv; 775 struct sata_rcar_priv *priv;
767 struct resource *mem; 776 struct resource *mem;
768 int irq; 777 int irq;
769 int ret = 0; 778 int ret = 0;
770 779
771 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 780 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
772 if (mem == NULL) 781 if (mem == NULL)
773 return -EINVAL; 782 return -EINVAL;
774 783
775 irq = platform_get_irq(pdev, 0); 784 irq = platform_get_irq(pdev, 0);
776 if (irq <= 0) 785 if (irq <= 0)
777 return -EINVAL; 786 return -EINVAL;
778 787
779 priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv), 788 priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv),
780 GFP_KERNEL); 789 GFP_KERNEL);
781 if (!priv) 790 if (!priv)
782 return -ENOMEM; 791 return -ENOMEM;
783 792
784 priv->clk = devm_clk_get(&pdev->dev, NULL); 793 priv->clk = devm_clk_get(&pdev->dev, NULL);
785 if (IS_ERR(priv->clk)) { 794 if (IS_ERR(priv->clk)) {
786 dev_err(&pdev->dev, "failed to get access to sata clock\n"); 795 dev_err(&pdev->dev, "failed to get access to sata clock\n");
787 return PTR_ERR(priv->clk); 796 return PTR_ERR(priv->clk);
788 } 797 }
789 clk_enable(priv->clk); 798 clk_enable(priv->clk);
790 799
791 host = ata_host_alloc(&pdev->dev, 1); 800 host = ata_host_alloc(&pdev->dev, 1);
792 if (!host) { 801 if (!host) {
793 dev_err(&pdev->dev, "ata_host_alloc failed\n"); 802 dev_err(&pdev->dev, "ata_host_alloc failed\n");
794 ret = -ENOMEM; 803 ret = -ENOMEM;
795 goto cleanup; 804 goto cleanup;
796 } 805 }
797 806
798 host->private_data = priv; 807 host->private_data = priv;
799 808
800 priv->base = devm_ioremap_resource(&pdev->dev, mem); 809 priv->base = devm_ioremap_resource(&pdev->dev, mem);
801 if (IS_ERR(priv->base)) { 810 if (IS_ERR(priv->base)) {
802 ret = PTR_ERR(priv->base); 811 ret = PTR_ERR(priv->base);
803 goto cleanup; 812 goto cleanup;
804 } 813 }
805 814
806 /* setup port */ 815 /* setup port */
807 sata_rcar_setup_port(host); 816 sata_rcar_setup_port(host);
808 817
809 /* initialize host controller */ 818 /* initialize host controller */
810 sata_rcar_init_controller(host); 819 sata_rcar_init_controller(host);
811 820
812 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0, 821 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
813 &sata_rcar_sht); 822 &sata_rcar_sht);
814 if (!ret) 823 if (!ret)
815 return 0; 824 return 0;
816 825
817 cleanup: 826 cleanup:
818 clk_disable(priv->clk); 827 clk_disable(priv->clk);
819 828
820 return ret; 829 return ret;
821 } 830 }
822 831
823 static int sata_rcar_remove(struct platform_device *pdev) 832 static int sata_rcar_remove(struct platform_device *pdev)
824 { 833 {
825 struct ata_host *host = platform_get_drvdata(pdev); 834 struct ata_host *host = platform_get_drvdata(pdev);
826 struct sata_rcar_priv *priv = host->private_data; 835 struct sata_rcar_priv *priv = host->private_data;
836 void __iomem *base = priv->base;
827 837
828 ata_host_detach(host); 838 ata_host_detach(host);
829 839
830 /* disable interrupts */ 840 /* disable interrupts */
831 iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); 841 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
832 /* ack and mask */ 842 /* ack and mask */
833 iowrite32(0, priv->base + SATAINTSTAT_REG); 843 iowrite32(0, base + SATAINTSTAT_REG);
834 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 844 iowrite32(0x7ff, base + SATAINTMASK_REG);
835 845
836 clk_disable(priv->clk); 846 clk_disable(priv->clk);
837 847
838 return 0; 848 return 0;
839 } 849 }
840 850
841 #ifdef CONFIG_PM 851 #ifdef CONFIG_PM
842 static int sata_rcar_suspend(struct device *dev) 852 static int sata_rcar_suspend(struct device *dev)
843 { 853 {
844 struct ata_host *host = dev_get_drvdata(dev); 854 struct ata_host *host = dev_get_drvdata(dev);
845 struct sata_rcar_priv *priv = host->private_data; 855 struct sata_rcar_priv *priv = host->private_data;
856 void __iomem *base = priv->base;
846 int ret; 857 int ret;
847 858
848 ret = ata_host_suspend(host, PMSG_SUSPEND); 859 ret = ata_host_suspend(host, PMSG_SUSPEND);
849 if (!ret) { 860 if (!ret) {
850 /* disable interrupts */ 861 /* disable interrupts */
851 iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); 862 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
852 /* mask */ 863 /* mask */
853 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 864 iowrite32(0x7ff, base + SATAINTMASK_REG);
854 865
855 clk_disable(priv->clk); 866 clk_disable(priv->clk);
856 } 867 }
857 868
858 return ret; 869 return ret;
859 } 870 }
860 871
861 static int sata_rcar_resume(struct device *dev) 872 static int sata_rcar_resume(struct device *dev)
862 { 873 {
863 struct ata_host *host = dev_get_drvdata(dev); 874 struct ata_host *host = dev_get_drvdata(dev);
864 struct sata_rcar_priv *priv = host->private_data; 875 struct sata_rcar_priv *priv = host->private_data;
876 void __iomem *base = priv->base;
865 877
866 clk_enable(priv->clk); 878 clk_enable(priv->clk);
867 879
868 /* ack and mask */ 880 /* ack and mask */
869 iowrite32(0, priv->base + SATAINTSTAT_REG); 881 iowrite32(0, base + SATAINTSTAT_REG);
870 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 882 iowrite32(0x7ff, base + SATAINTMASK_REG);
871 /* enable interrupts */ 883 /* enable interrupts */
872 iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); 884 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
873 885
874 ata_host_resume(host); 886 ata_host_resume(host);
875 887
876 return 0; 888 return 0;
877 } 889 }
878 890
879 static const struct dev_pm_ops sata_rcar_pm_ops = { 891 static const struct dev_pm_ops sata_rcar_pm_ops = {
880 .suspend = sata_rcar_suspend, 892 .suspend = sata_rcar_suspend,
881 .resume = sata_rcar_resume, 893 .resume = sata_rcar_resume,
882 }; 894 };
883 #endif 895 #endif
884 896
885 static struct of_device_id sata_rcar_match[] = { 897 static struct of_device_id sata_rcar_match[] = {
886 { .compatible = "renesas,rcar-sata", }, 898 { .compatible = "renesas,rcar-sata", },
887 {}, 899 {},
888 }; 900 };
889 MODULE_DEVICE_TABLE(of, sata_rcar_match); 901 MODULE_DEVICE_TABLE(of, sata_rcar_match);
890 902
891 static struct platform_driver sata_rcar_driver = { 903 static struct platform_driver sata_rcar_driver = {
892 .probe = sata_rcar_probe, 904 .probe = sata_rcar_probe,
893 .remove = sata_rcar_remove, 905 .remove = sata_rcar_remove,
894 .driver = { 906 .driver = {
895 .name = DRV_NAME, 907 .name = DRV_NAME,
896 .owner = THIS_MODULE, 908 .owner = THIS_MODULE,
897 .of_match_table = sata_rcar_match, 909 .of_match_table = sata_rcar_match,
898 #ifdef CONFIG_PM 910 #ifdef CONFIG_PM
899 .pm = &sata_rcar_pm_ops, 911 .pm = &sata_rcar_pm_ops,
900 #endif 912 #endif
901 }, 913 },
902 }; 914 };
903 915
904 module_platform_driver(sata_rcar_driver); 916 module_platform_driver(sata_rcar_driver);
905 917