Merge tag 'char-misc-3.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver fixes from Greg Kroah-Hartman: "Here are some small char/misc driver fixes that resolve issues recently reported against the 3.9-rc kernels. All have been in linux-next for a while." * tag 'char-misc-3.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: VMCI: Fix process-to-process DRGAMs. mei: ME hardware reset needs to be synchronized mei: add mei_stop function to stop mei device extcon: max77693: Initialize register of MUIC device to bring up it without platform data extcon: max77693: Fix bug of wrong pointer when platform data is not used extcon: max8997: Check the pointer of platform data to protect null pointer error

Merge tag 'char-misc-3.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver fixes from Greg Kroah-Hartman: "Here are some small char/misc driver fixes that resolve issues recently reported against the 3.9-rc kernels. All have been in linux-next for a while." * tag 'char-misc-3.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: VMCI: Fix process-to-process DRGAMs. mei: ME hardware reset needs to be synchronized mei: add mei_stop function to stop mei device extcon: max77693: Initialize register of MUIC device to bring up it without platform data extcon: max77693: Fix bug of wrong pointer when platform data is not used extcon: max8997: Check the pointer of platform data to protect null pointer error
Linus Torvalds
2 parents dfca53fb16 347e0899b1
Showing 8 changed files Side-by-side Diff
drivers/extcon/extcon-max77693.c
drivers/extcon/extcon-max8997.c
drivers/misc/mei/hw-me.c
drivers/misc/mei/init.c
drivers/misc/mei/mei_dev.h
drivers/misc/mei/pci-me.c
drivers/misc/vmw_vmci/vmci_datagram.c
include/linux/mfd/max77693-private.h
@@ -32,6 +32,38 @@
 #define	DEV_NAME			"max77693-muic"
 #define	DELAY_MS_DEFAULT		20000		/* unit: millisecond */
  
+/*
+ * Default value of MAX77693 register to bring up MUIC device.
+ * If user don't set some initial value for MUIC device through platform data,
+ * extcon-max77693 driver use 'default_init_data' to bring up base operation
+ * of MAX77693 MUIC device.
+ */
+struct max77693_reg_data default_init_data[] = {
+	{
+		/* STATUS2 - [3]ChgDetRun */
+		.addr = MAX77693_MUIC_REG_STATUS2,
+		.data = STATUS2_CHGDETRUN_MASK,
+	}, {
+		/* INTMASK1 - Unmask [3]ADC1KM,[0]ADCM */
+		.addr = MAX77693_MUIC_REG_INTMASK1,
+		.data = INTMASK1_ADC1K_MASK
+			| INTMASK1_ADC_MASK,
+	}, {
+		/* INTMASK2 - Unmask [0]ChgTypM */
+		.addr = MAX77693_MUIC_REG_INTMASK2,
+		.data = INTMASK2_CHGTYP_MASK,
+	}, {
+		/* INTMASK3 - Mask all of interrupts */
+		.addr = MAX77693_MUIC_REG_INTMASK3,
+		.data = 0x0,
+	}, {
+		/* CDETCTRL2 */
+		.addr = MAX77693_MUIC_REG_CDETCTRL2,
+		.data = CDETCTRL2_VIDRMEN_MASK
+			| CDETCTRL2_DXOVPEN_MASK,
+	},
+};
+
 enum max77693_muic_adc_debounce_time {
 	ADC_DEBOUNCE_TIME_5MS = 0,
 	ADC_DEBOUNCE_TIME_10MS,
  
@@ -1045,8 +1077,9 @@
 {
 	struct max77693_dev *max77693 = dev_get_drvdata(pdev->dev.parent);
 	struct max77693_platform_data *pdata = dev_get_platdata(max77693->dev);
-	struct max77693_muic_platform_data *muic_pdata = pdata->muic_data;
 	struct max77693_muic_info *info;
+	struct max77693_reg_data *init_data;
+	int num_init_data;
 	int delay_jiffies;
 	int ret;
 	int i;
  
  
  
@@ -1145,15 +1178,25 @@
 		goto err_irq;
 	}
  
-	/* Initialize MUIC register by using platform data */
-	for (i = 0 ; i < muic_pdata->num_init_data ; i++) {
-		enum max77693_irq_source irq_src = MAX77693_IRQ_GROUP_NR;
  
+	/* Initialize MUIC register by using platform data or default data */
+	if (pdata->muic_data) {
+		init_data = pdata->muic_data->init_data;
+		num_init_data = pdata->muic_data->num_init_data;
+	} else {
+		init_data = default_init_data;
+		num_init_data = ARRAY_SIZE(default_init_data);
+	}
+
+	for (i = 0 ; i < num_init_data ; i++) {
+		enum max77693_irq_source irq_src
+				= MAX77693_IRQ_GROUP_NR;
+
 		max77693_write_reg(info->max77693->regmap_muic,
-				muic_pdata->init_data[i].addr,
-				muic_pdata->init_data[i].data);
+				init_data[i].addr,
+				init_data[i].data);
  
-		switch (muic_pdata->init_data[i].addr) {
+		switch (init_data[i].addr) {
 		case MAX77693_MUIC_REG_INTMASK1:
 			irq_src = MUIC_INT1;
 			break;
  
  
  
@@ -1167,22 +1210,40 @@
  
 		if (irq_src < MAX77693_IRQ_GROUP_NR)
 			info->max77693->irq_masks_cur[irq_src]
-				= muic_pdata->init_data[i].data;
+				= init_data[i].data;
 	}
  
-	/*
-	 * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
-	 * h/w path of COMP2/COMN1 on CONTROL1 register.
-	 */
-	if (muic_pdata->path_uart)
-		info->path_uart = muic_pdata->path_uart;
-	else
-		info->path_uart = CONTROL1_SW_UART;
+	if (pdata->muic_data) {
+		struct max77693_muic_platform_data *muic_pdata = pdata->muic_data;
  
-	if (muic_pdata->path_usb)
-		info->path_usb = muic_pdata->path_usb;
-	else
+		/*
+		 * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
+		 * h/w path of COMP2/COMN1 on CONTROL1 register.
+		 */
+		if (muic_pdata->path_uart)
+			info->path_uart = muic_pdata->path_uart;
+		else
+			info->path_uart = CONTROL1_SW_UART;
+
+		if (muic_pdata->path_usb)
+			info->path_usb = muic_pdata->path_usb;
+		else
+			info->path_usb = CONTROL1_SW_USB;
+
+		/*
+		 * Default delay time for detecting cable state
+		 * after certain time.
+		 */
+		if (muic_pdata->detcable_delay_ms)
+			delay_jiffies =
+				msecs_to_jiffies(muic_pdata->detcable_delay_ms);
+		else
+			delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
+	} else {
 		info->path_usb = CONTROL1_SW_USB;
+		info->path_uart = CONTROL1_SW_UART;
+		delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
+	}
  
 	/* Set initial path for UART */
 	 max77693_muic_set_path(info, info->path_uart, true);
@@ -1208,10 +1269,6 @@
 	 * driver should notify cable state to upper layer.
 	 */
 	INIT_DELAYED_WORK(&info->wq_detcable, max77693_muic_detect_cable_wq);
-	if (muic_pdata->detcable_delay_ms)
-		delay_jiffies = msecs_to_jiffies(muic_pdata->detcable_delay_ms);
-	else
-		delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
 	schedule_delayed_work(&info->wq_detcable, delay_jiffies);
  
 	return ret;
@@ -712,29 +712,45 @@
 		goto err_irq;
 	}
  
-	/* Initialize registers according to platform data */
 	if (pdata->muic_pdata) {
-		struct max8997_muic_platform_data *mdata = info->muic_pdata;
+		struct max8997_muic_platform_data *muic_pdata
+			= pdata->muic_pdata;
  
-		for (i = 0; i < mdata->num_init_data; i++) {
-			max8997_write_reg(info->muic, mdata->init_data[i].addr,
-					mdata->init_data[i].data);
+		/* Initialize registers according to platform data */
+		for (i = 0; i < muic_pdata->num_init_data; i++) {
+			max8997_write_reg(info->muic,
+					muic_pdata->init_data[i].addr,
+					muic_pdata->init_data[i].data);
 		}
-	}
  
-	/*
-	 * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
-	 * h/w path of COMP2/COMN1 on CONTROL1 register.
-	 */
-	if (pdata->muic_pdata->path_uart)
-		info->path_uart = pdata->muic_pdata->path_uart;
-	else
-		info->path_uart = CONTROL1_SW_UART;
+		/*
+		 * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
+		 * h/w path of COMP2/COMN1 on CONTROL1 register.
+		 */
+		if (muic_pdata->path_uart)
+			info->path_uart = muic_pdata->path_uart;
+		else
+			info->path_uart = CONTROL1_SW_UART;
  
-	if (pdata->muic_pdata->path_usb)
-		info->path_usb = pdata->muic_pdata->path_usb;
-	else
+		if (muic_pdata->path_usb)
+			info->path_usb = muic_pdata->path_usb;
+		else
+			info->path_usb = CONTROL1_SW_USB;
+
+		/*
+		 * Default delay time for detecting cable state
+		 * after certain time.
+		 */
+		if (muic_pdata->detcable_delay_ms)
+			delay_jiffies =
+				msecs_to_jiffies(muic_pdata->detcable_delay_ms);
+		else
+			delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
+	} else {
+		info->path_uart = CONTROL1_SW_UART;
 		info->path_usb = CONTROL1_SW_USB;
+		delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
+	}
  
 	/* Set initial path for UART */
 	 max8997_muic_set_path(info, info->path_uart, true);
@@ -751,10 +767,6 @@
 	 * driver should notify cable state to upper layer.
 	 */
 	INIT_DELAYED_WORK(&info->wq_detcable, max8997_muic_detect_cable_wq);
-	if (pdata->muic_pdata->detcable_delay_ms)
-		delay_jiffies = msecs_to_jiffies(pdata->muic_pdata->detcable_delay_ms);
-	else
-		delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
 	schedule_delayed_work(&info->wq_detcable, delay_jiffies);
  
 	return 0;
@@ -152,6 +152,20 @@
 }
  
 /**
+ * mei_me_hw_reset_release - release device from the reset
+ *
+ * @dev: the device structure
+ */
+static void mei_me_hw_reset_release(struct mei_device *dev)
+{
+	struct mei_me_hw *hw = to_me_hw(dev);
+	u32 hcsr = mei_hcsr_read(hw);
+
+	hcsr |= H_IG;
+	hcsr &= ~H_RST;
+	mei_hcsr_set(hw, hcsr);
+}
+/**
  * mei_me_hw_reset - resets fw via mei csr register.
  *
  * @dev: the device structure
  
  
@@ -169,18 +183,14 @@
 	if (intr_enable)
 		hcsr |= H_IE;
 	else
-		hcsr &= ~H_IE;
+		hcsr |= ~H_IE;
  
 	mei_hcsr_set(hw, hcsr);
  
-	hcsr = mei_hcsr_read(hw) | H_IG;
-	hcsr &= ~H_RST;
+	if (dev->dev_state == MEI_DEV_POWER_DOWN)
+		mei_me_hw_reset_release(dev);
  
-	mei_hcsr_set(hw, hcsr);
-
-	hcsr = mei_hcsr_read(hw);
-
-	dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", hcsr);
+	dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", mei_hcsr_read(hw));
 }
  
 /**
@@ -466,7 +476,8 @@
 			mutex_unlock(&dev->device_lock);
 			return IRQ_HANDLED;
 		} else {
-			dev_dbg(&dev->pdev->dev, "FW not ready.\n");
+			dev_dbg(&dev->pdev->dev, "Reset Completed.\n");
+			mei_me_hw_reset_release(dev);
 			mutex_unlock(&dev->device_lock);
 			return IRQ_HANDLED;
 		}
@@ -182,4 +182,22 @@
 	/* remove all waiting requests */
 	mei_cl_all_write_clear(dev);
 }
+
+void mei_stop(struct mei_device *dev)
+{
+	dev_dbg(&dev->pdev->dev, "stopping the device.\n");
+
+	mutex_lock(&dev->device_lock);
+
+	cancel_delayed_work(&dev->timer_work);
+
+	mei_wd_stop(dev);
+
+	dev->dev_state = MEI_DEV_POWER_DOWN;
+	mei_reset(dev, 0);
+
+	mutex_unlock(&dev->device_lock);
+
+	flush_scheduled_work();
+}
@@ -381,6 +381,7 @@
 void mei_device_init(struct mei_device *dev);
 void mei_reset(struct mei_device *dev, int interrupts);
 int mei_hw_init(struct mei_device *dev);
+void mei_stop(struct mei_device *dev);
  
 /*
  *  MEI interrupt functions prototype
@@ -247,44 +247,14 @@
  
 	hw = to_me_hw(dev);
  
-	mutex_lock(&dev->device_lock);
  
-	cancel_delayed_work(&dev->timer_work);
+	dev_err(&pdev->dev, "stop\n");
+	mei_stop(dev);
  
-	mei_wd_stop(dev);
-
 	mei_pdev = NULL;
  
-	if (dev->iamthif_cl.state == MEI_FILE_CONNECTED) {
-		dev->iamthif_cl.state = MEI_FILE_DISCONNECTING;
-		mei_cl_disconnect(&dev->iamthif_cl);
-	}
-	if (dev->wd_cl.state == MEI_FILE_CONNECTED) {
-		dev->wd_cl.state = MEI_FILE_DISCONNECTING;
-		mei_cl_disconnect(&dev->wd_cl);
-	}
-
-	/* Unregistering watchdog device */
 	mei_watchdog_unregister(dev);
  
-	/* remove entry if already in list */
-	dev_dbg(&pdev->dev, "list del iamthif and wd file list.\n");
-
-	if (dev->open_handle_count > 0)
-		dev->open_handle_count--;
-	mei_cl_unlink(&dev->wd_cl);
-
-	if (dev->open_handle_count > 0)
-		dev->open_handle_count--;
-	mei_cl_unlink(&dev->iamthif_cl);
-
-	dev->iamthif_current_cb = NULL;
-	dev->me_clients_num = 0;
-
-	mutex_unlock(&dev->device_lock);
-
-	flush_scheduled_work();
-
 	/* disable interrupts */
 	mei_disable_interrupts(dev);
  
  
  
  
  
  
@@ -308,28 +278,20 @@
 {
 	struct pci_dev *pdev = to_pci_dev(device);
 	struct mei_device *dev = pci_get_drvdata(pdev);
-	int err;
  
 	if (!dev)
 		return -ENODEV;
-	mutex_lock(&dev->device_lock);
  
-	cancel_delayed_work(&dev->timer_work);
+	dev_err(&pdev->dev, "suspend\n");
  
-	/* Stop watchdog if exists */
-	err = mei_wd_stop(dev);
-	/* Set new mei state */
-	if (dev->dev_state == MEI_DEV_ENABLED ||
-	    dev->dev_state == MEI_DEV_RECOVERING_FROM_RESET) {
-		dev->dev_state = MEI_DEV_POWER_DOWN;
-		mei_reset(dev, 0);
-	}
-	mutex_unlock(&dev->device_lock);
+	mei_stop(dev);
  
+	mei_disable_interrupts(dev);
+
 	free_irq(pdev->irq, dev);
 	pci_disable_msi(pdev);
  
-	return err;
+	return 0;
 }
  
 static int mei_pci_resume(struct device *device)
@@ -42,9 +42,11 @@
  
 struct delayed_datagram_info {
 	struct datagram_entry *entry;
-	struct vmci_datagram msg;
 	struct work_struct work;
 	bool in_dg_host_queue;
+	/* msg and msg_payload must be together. */
+	struct vmci_datagram msg;
+	u8 msg_payload[];
 };
  
 /* Number of in-flight host->host datagrams */
@@ -106,6 +106,29 @@
 	MAX77693_MUIC_REG_END,
 };
  
+/* MAX77693 INTMASK1~2 Register */
+#define INTMASK1_ADC1K_SHIFT		3
+#define INTMASK1_ADCERR_SHIFT		2
+#define INTMASK1_ADCLOW_SHIFT		1
+#define INTMASK1_ADC_SHIFT		0
+#define INTMASK1_ADC1K_MASK		(1 << INTMASK1_ADC1K_SHIFT)
+#define INTMASK1_ADCERR_MASK		(1 << INTMASK1_ADCERR_SHIFT)
+#define INTMASK1_ADCLOW_MASK		(1 << INTMASK1_ADCLOW_SHIFT)
+#define INTMASK1_ADC_MASK		(1 << INTMASK1_ADC_SHIFT)
+
+#define INTMASK2_VIDRM_SHIFT		5
+#define INTMASK2_VBVOLT_SHIFT		4
+#define INTMASK2_DXOVP_SHIFT		3
+#define INTMASK2_DCDTMR_SHIFT		2
+#define INTMASK2_CHGDETRUN_SHIFT	1
+#define INTMASK2_CHGTYP_SHIFT		0
+#define INTMASK2_VIDRM_MASK		(1 << INTMASK2_VIDRM_SHIFT)
+#define INTMASK2_VBVOLT_MASK		(1 << INTMASK2_VBVOLT_SHIFT)
+#define INTMASK2_DXOVP_MASK		(1 << INTMASK2_DXOVP_SHIFT)
+#define INTMASK2_DCDTMR_MASK		(1 << INTMASK2_DCDTMR_SHIFT)
+#define INTMASK2_CHGDETRUN_MASK		(1 << INTMASK2_CHGDETRUN_SHIFT)
+#define INTMASK2_CHGTYP_MASK		(1 << INTMASK2_CHGTYP_SHIFT)
+
 /* MAX77693 MUIC - STATUS1~3 Register */
 #define STATUS1_ADC_SHIFT		(0)
 #define STATUS1_ADCLOW_SHIFT		(5)
...	...	@@ -32,6 +32,38 @@
32	32	#define DEV_NAME "max77693-muic"
33	33	#define DELAY_MS_DEFAULT 20000 /* unit: millisecond */
34	34
	35	+/*
	36	+ * Default value of MAX77693 register to bring up MUIC device.
	37	+ * If user don't set some initial value for MUIC device through platform data,
	38	+ * extcon-max77693 driver use 'default_init_data' to bring up base operation
	39	+ * of MAX77693 MUIC device.
	40	+ */
	41	+struct max77693_reg_data default_init_data[] = {
	42	+ {
	43	+ /* STATUS2 - [3]ChgDetRun */
	44	+ .addr = MAX77693_MUIC_REG_STATUS2,
	45	+ .data = STATUS2_CHGDETRUN_MASK,
	46	+ }, {
	47	+ /* INTMASK1 - Unmask [3]ADC1KM,[0]ADCM */
	48	+ .addr = MAX77693_MUIC_REG_INTMASK1,
	49	+ .data = INTMASK1_ADC1K_MASK
	50	+ \| INTMASK1_ADC_MASK,
	51	+ }, {
	52	+ /* INTMASK2 - Unmask [0]ChgTypM */
	53	+ .addr = MAX77693_MUIC_REG_INTMASK2,
	54	+ .data = INTMASK2_CHGTYP_MASK,
	55	+ }, {
	56	+ /* INTMASK3 - Mask all of interrupts */
	57	+ .addr = MAX77693_MUIC_REG_INTMASK3,
	58	+ .data = 0x0,
	59	+ }, {
	60	+ /* CDETCTRL2 */
	61	+ .addr = MAX77693_MUIC_REG_CDETCTRL2,
	62	+ .data = CDETCTRL2_VIDRMEN_MASK
	63	+ \| CDETCTRL2_DXOVPEN_MASK,
	64	+ },
	65	+};
	66	+
35	67	enum max77693_muic_adc_debounce_time {
36	68	ADC_DEBOUNCE_TIME_5MS = 0,
37	69	ADC_DEBOUNCE_TIME_10MS,
38	70
...	...	@@ -1045,8 +1077,9 @@
1045	1077	{
1046	1078	struct max77693_dev *max77693 = dev_get_drvdata(pdev->dev.parent);
1047	1079	struct max77693_platform_data *pdata = dev_get_platdata(max77693->dev);
1048		- struct max77693_muic_platform_data *muic_pdata = pdata->muic_data;
1049	1080	struct max77693_muic_info *info;
	1081	+ struct max77693_reg_data *init_data;
	1082	+ int num_init_data;
1050	1083	int delay_jiffies;
1051	1084	int ret;
1052	1085	int i;
1053	1086
1054	1087
1055	1088
...	...	@@ -1145,15 +1178,25 @@
1145	1178	goto err_irq;
1146	1179	}
1147	1180
1148		- /* Initialize MUIC register by using platform data */
1149		- for (i = 0 ; i < muic_pdata->num_init_data ; i++) {
1150		- enum max77693_irq_source irq_src = MAX77693_IRQ_GROUP_NR;
1151	1181
	1182	+ /* Initialize MUIC register by using platform data or default data */
	1183	+ if (pdata->muic_data) {
	1184	+ init_data = pdata->muic_data->init_data;
	1185	+ num_init_data = pdata->muic_data->num_init_data;
	1186	+ } else {
	1187	+ init_data = default_init_data;
	1188	+ num_init_data = ARRAY_SIZE(default_init_data);
	1189	+ }
	1190	+
	1191	+ for (i = 0 ; i < num_init_data ; i++) {
	1192	+ enum max77693_irq_source irq_src
	1193	+ = MAX77693_IRQ_GROUP_NR;
	1194	+
1152	1195	max77693_write_reg(info->max77693->regmap_muic,
1153		- muic_pdata->init_data[i].addr,
1154		- muic_pdata->init_data[i].data);
	1196	+ init_data[i].addr,
	1197	+ init_data[i].data);
1155	1198
1156		- switch (muic_pdata->init_data[i].addr) {
	1199	+ switch (init_data[i].addr) {
1157	1200	case MAX77693_MUIC_REG_INTMASK1:
1158	1201	irq_src = MUIC_INT1;
1159	1202	break;
1160	1203
1161	1204
1162	1205
...	...	@@ -1167,22 +1210,40 @@
1167	1210
1168	1211	if (irq_src < MAX77693_IRQ_GROUP_NR)
1169	1212	info->max77693->irq_masks_cur[irq_src]
1170		- = muic_pdata->init_data[i].data;
	1213	+ = init_data[i].data;
1171	1214	}
1172	1215
1173		- /*
1174		- * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
1175		- * h/w path of COMP2/COMN1 on CONTROL1 register.
1176		- */
1177		- if (muic_pdata->path_uart)
1178		- info->path_uart = muic_pdata->path_uart;
1179		- else
1180		- info->path_uart = CONTROL1_SW_UART;
	1216	+ if (pdata->muic_data) {
	1217	+ struct max77693_muic_platform_data *muic_pdata = pdata->muic_data;
1181	1218
1182		- if (muic_pdata->path_usb)
1183		- info->path_usb = muic_pdata->path_usb;
1184		- else
	1219	+ /*
	1220	+ * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
	1221	+ * h/w path of COMP2/COMN1 on CONTROL1 register.
	1222	+ */
	1223	+ if (muic_pdata->path_uart)
	1224	+ info->path_uart = muic_pdata->path_uart;
	1225	+ else
	1226	+ info->path_uart = CONTROL1_SW_UART;
	1227	+
	1228	+ if (muic_pdata->path_usb)
	1229	+ info->path_usb = muic_pdata->path_usb;
	1230	+ else
	1231	+ info->path_usb = CONTROL1_SW_USB;
	1232	+
	1233	+ /*
	1234	+ * Default delay time for detecting cable state
	1235	+ * after certain time.
	1236	+ */
	1237	+ if (muic_pdata->detcable_delay_ms)
	1238	+ delay_jiffies =
	1239	+ msecs_to_jiffies(muic_pdata->detcable_delay_ms);
	1240	+ else
	1241	+ delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
	1242	+ } else {
1185	1243	info->path_usb = CONTROL1_SW_USB;
	1244	+ info->path_uart = CONTROL1_SW_UART;
	1245	+ delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
	1246	+ }
1186	1247
1187	1248	/* Set initial path for UART */
1188	1249	max77693_muic_set_path(info, info->path_uart, true);
...	...	@@ -1208,10 +1269,6 @@
1208	1269	* driver should notify cable state to upper layer.
1209	1270	*/
1210	1271	INIT_DELAYED_WORK(&info->wq_detcable, max77693_muic_detect_cable_wq);
1211		- if (muic_pdata->detcable_delay_ms)
1212		- delay_jiffies = msecs_to_jiffies(muic_pdata->detcable_delay_ms);
1213		- else
1214		- delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
1215	1272	schedule_delayed_work(&info->wq_detcable, delay_jiffies);
1216	1273
1217	1274	return ret;
...	...	@@ -712,29 +712,45 @@
712	712	goto err_irq;
713	713	}
714	714
715		- /* Initialize registers according to platform data */
716	715	if (pdata->muic_pdata) {
717		- struct max8997_muic_platform_data *mdata = info->muic_pdata;
	716	+ struct max8997_muic_platform_data *muic_pdata
	717	+ = pdata->muic_pdata;
718	718
719		- for (i = 0; i < mdata->num_init_data; i++) {
720		- max8997_write_reg(info->muic, mdata->init_data[i].addr,
721		- mdata->init_data[i].data);
	719	+ /* Initialize registers according to platform data */
	720	+ for (i = 0; i < muic_pdata->num_init_data; i++) {
	721	+ max8997_write_reg(info->muic,
	722	+ muic_pdata->init_data[i].addr,
	723	+ muic_pdata->init_data[i].data);
722	724	}
723		- }
724	725
725		- /*
726		- * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
727		- * h/w path of COMP2/COMN1 on CONTROL1 register.
728		- */
729		- if (pdata->muic_pdata->path_uart)
730		- info->path_uart = pdata->muic_pdata->path_uart;
731		- else
732		- info->path_uart = CONTROL1_SW_UART;
	726	+ /*
	727	+ * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
	728	+ * h/w path of COMP2/COMN1 on CONTROL1 register.
	729	+ */
	730	+ if (muic_pdata->path_uart)
	731	+ info->path_uart = muic_pdata->path_uart;
	732	+ else
	733	+ info->path_uart = CONTROL1_SW_UART;
733	734
734		- if (pdata->muic_pdata->path_usb)
735		- info->path_usb = pdata->muic_pdata->path_usb;
736		- else
	735	+ if (muic_pdata->path_usb)
	736	+ info->path_usb = muic_pdata->path_usb;
	737	+ else
	738	+ info->path_usb = CONTROL1_SW_USB;
	739	+
	740	+ /*
	741	+ * Default delay time for detecting cable state
	742	+ * after certain time.
	743	+ */
	744	+ if (muic_pdata->detcable_delay_ms)
	745	+ delay_jiffies =
	746	+ msecs_to_jiffies(muic_pdata->detcable_delay_ms);
	747	+ else
	748	+ delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
	749	+ } else {
	750	+ info->path_uart = CONTROL1_SW_UART;
737	751	info->path_usb = CONTROL1_SW_USB;
	752	+ delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
	753	+ }
738	754
739	755	/* Set initial path for UART */
740	756	max8997_muic_set_path(info, info->path_uart, true);
...	...	@@ -751,10 +767,6 @@
751	767	* driver should notify cable state to upper layer.
752	768	*/
753	769	INIT_DELAYED_WORK(&info->wq_detcable, max8997_muic_detect_cable_wq);
754		- if (pdata->muic_pdata->detcable_delay_ms)
755		- delay_jiffies = msecs_to_jiffies(pdata->muic_pdata->detcable_delay_ms);
756		- else
757		- delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
758	770	schedule_delayed_work(&info->wq_detcable, delay_jiffies);
759	771
760	772	return 0;
...	...	@@ -152,6 +152,20 @@
152	152	}
153	153
154	154	/**
	155	+ * mei_me_hw_reset_release - release device from the reset
	156	+ *
	157	+ * @dev: the device structure
	158	+ */
	159	+static void mei_me_hw_reset_release(struct mei_device *dev)
	160	+{
	161	+ struct mei_me_hw *hw = to_me_hw(dev);
	162	+ u32 hcsr = mei_hcsr_read(hw);
	163	+
	164	+ hcsr \|= H_IG;
	165	+ hcsr &= ~H_RST;
	166	+ mei_hcsr_set(hw, hcsr);
	167	+}
	168	+/**
155	169	* mei_me_hw_reset - resets fw via mei csr register.
156	170	*
157	171	* @dev: the device structure
158	172
159	173
...	...	@@ -169,18 +183,14 @@
169	183	if (intr_enable)
170	184	hcsr \|= H_IE;
171	185	else
172		- hcsr &= ~H_IE;
	186	+ hcsr \|= ~H_IE;
173	187
174	188	mei_hcsr_set(hw, hcsr);
175	189
176		- hcsr = mei_hcsr_read(hw) \| H_IG;
177		- hcsr &= ~H_RST;
	190	+ if (dev->dev_state == MEI_DEV_POWER_DOWN)
	191	+ mei_me_hw_reset_release(dev);
178	192
179		- mei_hcsr_set(hw, hcsr);
180		-
181		- hcsr = mei_hcsr_read(hw);
182		-
183		- dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", hcsr);
	193	+ dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", mei_hcsr_read(hw));
184	194	}
185	195
186	196	/**
...	...	@@ -466,7 +476,8 @@
466	476	mutex_unlock(&dev->device_lock);
467	477	return IRQ_HANDLED;
468	478	} else {
469		- dev_dbg(&dev->pdev->dev, "FW not ready.\n");
	479	+ dev_dbg(&dev->pdev->dev, "Reset Completed.\n");
	480	+ mei_me_hw_reset_release(dev);
470	481	mutex_unlock(&dev->device_lock);
471	482	return IRQ_HANDLED;
472	483	}
...	...	@@ -182,4 +182,22 @@
182	182	/* remove all waiting requests */
183	183	mei_cl_all_write_clear(dev);
184	184	}
	185	+
	186	+void mei_stop(struct mei_device *dev)
	187	+{
	188	+ dev_dbg(&dev->pdev->dev, "stopping the device.\n");
	189	+
	190	+ mutex_lock(&dev->device_lock);
	191	+
	192	+ cancel_delayed_work(&dev->timer_work);
	193	+
	194	+ mei_wd_stop(dev);
	195	+
	196	+ dev->dev_state = MEI_DEV_POWER_DOWN;
	197	+ mei_reset(dev, 0);
	198	+
	199	+ mutex_unlock(&dev->device_lock);
	200	+
	201	+ flush_scheduled_work();
	202	+}
...	...	@@ -381,6 +381,7 @@
381	381	void mei_device_init(struct mei_device *dev);
382	382	void mei_reset(struct mei_device *dev, int interrupts);
383	383	int mei_hw_init(struct mei_device *dev);
	384	+void mei_stop(struct mei_device *dev);
384	385
385	386	/*
386	387	* MEI interrupt functions prototype
...	...	@@ -247,44 +247,14 @@
247	247
248	248	hw = to_me_hw(dev);
249	249
250		- mutex_lock(&dev->device_lock);
251	250
252		- cancel_delayed_work(&dev->timer_work);
	251	+ dev_err(&pdev->dev, "stop\n");
	252	+ mei_stop(dev);
253	253
254		- mei_wd_stop(dev);
255		-
256	254	mei_pdev = NULL;
257	255
258		- if (dev->iamthif_cl.state == MEI_FILE_CONNECTED) {
259		- dev->iamthif_cl.state = MEI_FILE_DISCONNECTING;
260		- mei_cl_disconnect(&dev->iamthif_cl);
261		- }
262		- if (dev->wd_cl.state == MEI_FILE_CONNECTED) {
263		- dev->wd_cl.state = MEI_FILE_DISCONNECTING;
264		- mei_cl_disconnect(&dev->wd_cl);
265		- }
266		-
267		- /* Unregistering watchdog device */
268	256	mei_watchdog_unregister(dev);
269	257
270		- /* remove entry if already in list */
271		- dev_dbg(&pdev->dev, "list del iamthif and wd file list.\n");
272		-
273		- if (dev->open_handle_count > 0)
274		- dev->open_handle_count--;
275		- mei_cl_unlink(&dev->wd_cl);
276		-
277		- if (dev->open_handle_count > 0)
278		- dev->open_handle_count--;
279		- mei_cl_unlink(&dev->iamthif_cl);
280		-
281		- dev->iamthif_current_cb = NULL;
282		- dev->me_clients_num = 0;
283		-
284		- mutex_unlock(&dev->device_lock);
285		-
286		- flush_scheduled_work();
287		-
288	258	/* disable interrupts */
289	259	mei_disable_interrupts(dev);
290	260
291	261
292	262
293	263
294	264
295	265
...	...	@@ -308,28 +278,20 @@
308	278	{
309	279	struct pci_dev *pdev = to_pci_dev(device);
310	280	struct mei_device *dev = pci_get_drvdata(pdev);
311		- int err;
312	281
313	282	if (!dev)
314	283	return -ENODEV;
315		- mutex_lock(&dev->device_lock);
316	284
317		- cancel_delayed_work(&dev->timer_work);
	285	+ dev_err(&pdev->dev, "suspend\n");
318	286
319		- /* Stop watchdog if exists */
320		- err = mei_wd_stop(dev);
321		- /* Set new mei state */
322		- if (dev->dev_state == MEI_DEV_ENABLED \|\|
323		- dev->dev_state == MEI_DEV_RECOVERING_FROM_RESET) {
324		- dev->dev_state = MEI_DEV_POWER_DOWN;
325		- mei_reset(dev, 0);
326		- }
327		- mutex_unlock(&dev->device_lock);
	287	+ mei_stop(dev);
328	288
	289	+ mei_disable_interrupts(dev);
	290	+
329	291	free_irq(pdev->irq, dev);
330	292	pci_disable_msi(pdev);
331	293
332		- return err;
	294	+ return 0;
333	295	}
334	296
335	297	static int mei_pci_resume(struct device *device)
...	...	@@ -42,9 +42,11 @@
42	42
43	43	struct delayed_datagram_info {
44	44	struct datagram_entry *entry;
45		- struct vmci_datagram msg;
46	45	struct work_struct work;
47	46	bool in_dg_host_queue;
	47	+ /* msg and msg_payload must be together. */
	48	+ struct vmci_datagram msg;
	49	+ u8 msg_payload[];
48	50	};
49	51
50	52	/* Number of in-flight host->host datagrams */
...	...	@@ -106,6 +106,29 @@
106	106	MAX77693_MUIC_REG_END,
107	107	};
108	108
	109	+/* MAX77693 INTMASK1~2 Register */
	110	+#define INTMASK1_ADC1K_SHIFT 3
	111	+#define INTMASK1_ADCERR_SHIFT 2
	112	+#define INTMASK1_ADCLOW_SHIFT 1
	113	+#define INTMASK1_ADC_SHIFT 0
	114	+#define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
	115	+#define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
	116	+#define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
	117	+#define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
	118	+
	119	+#define INTMASK2_VIDRM_SHIFT 5
	120	+#define INTMASK2_VBVOLT_SHIFT 4
	121	+#define INTMASK2_DXOVP_SHIFT 3
	122	+#define INTMASK2_DCDTMR_SHIFT 2
	123	+#define INTMASK2_CHGDETRUN_SHIFT 1
	124	+#define INTMASK2_CHGTYP_SHIFT 0
	125	+#define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
	126	+#define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
	127	+#define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
	128	+#define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
	129	+#define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
	130	+#define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
	131	+
109	132	/* MAX77693 MUIC - STATUS1~3 Register */
110	133	#define STATUS1_ADC_SHIFT (0)
111	134	#define STATUS1_ADCLOW_SHIFT (5)