Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit 1d7f83d5ad6c30b385ba549c1c3a287cc872b7ae

Authored by Arnd Bergmann 2009-02-26 07:51:42 +0800

Committed by Ingo Molnar 2009-03-27 01:14:18 +0800

Exists in master and in 7 other branches

make drm headers use strict integer types

The drm headers are traditionally shared with BSD and
could not use the strict linux integer types. This is
over now, so we can use our own types now.

Cc: David Airlie <airlied@linux.ie>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

Showing 6 changed files with 190 additions and 188 deletions Inline Diff

include/drm/drm.h
include/drm/drm_mode.h
include/drm/i915_drm.h
include/drm/mga_drm.h
include/drm/radeon_drm.h
include/drm/via_drm.h

include/drm/drm.h

Diff comments View file @ 1d7f83d

 /**
  * \file drm.h
  * Header for the Direct Rendering Manager
  *
  * \author Rickard E. (Rik) Faith <faith@valinux.com>
  *
  * \par Acknowledgments:
  * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
  */
 /*
  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 #ifndef _DRM_H_
 #define _DRM_H_
-#if defined(__KERNEL__)
+#include <linux/types.h>
-#endif
 #include <asm/ioctl.h>		/* For _IO* macros */
 #define DRM_IOCTL_NR(n)		_IOC_NR(n)
 #define DRM_IOC_VOID		_IOC_NONE
 #define DRM_IOC_READ		_IOC_READ
 #define DRM_IOC_WRITE		_IOC_WRITE
 #define DRM_IOC_READWRITE	_IOC_READ|_IOC_WRITE
 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
 #define DRM_MAJOR       226
 #define DRM_MAX_MINOR   15
 #define DRM_NAME	"drm"	  /**< Name in kernel, /dev, and /proc */
 #define DRM_MIN_ORDER	5	  /**< At least 2^5 bytes = 32 bytes */
 #define DRM_MAX_ORDER	22	  /**< Up to 2^22 bytes = 4MB */
 #define DRM_RAM_PERCENT 10	  /**< How much system ram can we lock? */
 #define _DRM_LOCK_HELD	0x80000000U /**< Hardware lock is held */
 #define _DRM_LOCK_CONT	0x40000000U /**< Hardware lock is contended */
 #define _DRM_LOCK_IS_HELD(lock)	   ((lock) & _DRM_LOCK_HELD)
 #define _DRM_LOCK_IS_CONT(lock)	   ((lock) & _DRM_LOCK_CONT)
 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
 typedef unsigned int drm_handle_t;
 typedef unsigned int drm_context_t;
 typedef unsigned int drm_drawable_t;
 typedef unsigned int drm_magic_t;
 /**
  * Cliprect.
  *
  * \warning: If you change this structure, make sure you change
  * XF86DRIClipRectRec in the server as well
  *
  * \note KW: Actually it's illegal to change either for
  * backwards-compatibility reasons.
  */
 struct drm_clip_rect {
 	unsigned short x1;
 	unsigned short y1;
 	unsigned short x2;
 	unsigned short y2;
 };
 /**
  * Drawable information.
  */
 struct drm_drawable_info {
 	unsigned int num_rects;
 	struct drm_clip_rect *rects;
 };
 /**
  * Texture region,
  */
 struct drm_tex_region {
 	unsigned char next;
 	unsigned char prev;
 	unsigned char in_use;
 	unsigned char padding;
 	unsigned int age;
 };
 /**
  * Hardware lock.
  *
  * The lock structure is a simple cache-line aligned integer.  To avoid
  * processor bus contention on a multiprocessor system, there should not be any
  * other data stored in the same cache line.
  */
 struct drm_hw_lock {
 	__volatile__ unsigned int lock;		/**< lock variable */
 	char padding[60];			/**< Pad to cache line */
 };
 /**
  * DRM_IOCTL_VERSION ioctl argument type.
  *
  * \sa drmGetVersion().
  */
 struct drm_version {
 	int version_major;	  /**< Major version */
 	int version_minor;	  /**< Minor version */
 	int version_patchlevel;	  /**< Patch level */
 	size_t name_len;	  /**< Length of name buffer */
 	char __user *name;	  /**< Name of driver */
 	size_t date_len;	  /**< Length of date buffer */
 	char __user *date;	  /**< User-space buffer to hold date */
 	size_t desc_len;	  /**< Length of desc buffer */
 	char __user *desc;	  /**< User-space buffer to hold desc */
 };
 /**
  * DRM_IOCTL_GET_UNIQUE ioctl argument type.
  *
  * \sa drmGetBusid() and drmSetBusId().
  */
 struct drm_unique {
 	size_t unique_len;	  /**< Length of unique */
 	char __user *unique;	  /**< Unique name for driver instantiation */
 };
 struct drm_list {
 	int count;		  /**< Length of user-space structures */
 	struct drm_version __user *version;
 };
 struct drm_block {
 	int unused;
 };
 /**
  * DRM_IOCTL_CONTROL ioctl argument type.
  *
  * \sa drmCtlInstHandler() and drmCtlUninstHandler().
  */
 struct drm_control {
 	enum {
 		DRM_ADD_COMMAND,
 		DRM_RM_COMMAND,
 		DRM_INST_HANDLER,
 		DRM_UNINST_HANDLER
 	} func;
 	int irq;
 };
 /**
  * Type of memory to map.
  */
 enum drm_map_type {
 	_DRM_FRAME_BUFFER = 0,	  /**< WC (no caching), no core dump */
 	_DRM_REGISTERS = 1,	  /**< no caching, no core dump */
 	_DRM_SHM = 2,		  /**< shared, cached */
 	_DRM_AGP = 3,		  /**< AGP/GART */
 	_DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
 	_DRM_CONSISTENT = 5,	  /**< Consistent memory for PCI DMA */
 	_DRM_GEM = 6,		  /**< GEM object */
 };
 /**
  * Memory mapping flags.
  */
 enum drm_map_flags {
 	_DRM_RESTRICTED = 0x01,	     /**< Cannot be mapped to user-virtual */
 	_DRM_READ_ONLY = 0x02,
 	_DRM_LOCKED = 0x04,	     /**< shared, cached, locked */
 	_DRM_KERNEL = 0x08,	     /**< kernel requires access */
 	_DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
 	_DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
 	_DRM_REMOVABLE = 0x40,	     /**< Removable mapping */
 	_DRM_DRIVER = 0x80	     /**< Managed by driver */
 };
 struct drm_ctx_priv_map {
 	unsigned int ctx_id;	 /**< Context requesting private mapping */
 	void *handle;		 /**< Handle of map */
 };
 /**
  * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
  * argument type.
  *
  * \sa drmAddMap().
  */
 struct drm_map {
 	unsigned long offset;	 /**< Requested physical address (0 for SAREA)*/
 	unsigned long size;	 /**< Requested physical size (bytes) */
 	enum drm_map_type type;	 /**< Type of memory to map */
 	enum drm_map_flags flags;	 /**< Flags */
 	void *handle;		 /**< User-space: "Handle" to pass to mmap() */
 				 /**< Kernel-space: kernel-virtual address */
 	int mtrr;		 /**< MTRR slot used */
 	/*   Private data */
 };
 /**
  * DRM_IOCTL_GET_CLIENT ioctl argument type.
  */
 struct drm_client {
 	int idx;		/**< Which client desired? */
 	int auth;		/**< Is client authenticated? */
 	unsigned long pid;	/**< Process ID */
 	unsigned long uid;	/**< User ID */
 	unsigned long magic;	/**< Magic */
 	unsigned long iocs;	/**< Ioctl count */
 };
 enum drm_stat_type {
 	_DRM_STAT_LOCK,
 	_DRM_STAT_OPENS,
 	_DRM_STAT_CLOSES,
 	_DRM_STAT_IOCTLS,
 	_DRM_STAT_LOCKS,
 	_DRM_STAT_UNLOCKS,
 	_DRM_STAT_VALUE,	/**< Generic value */
 	_DRM_STAT_BYTE,		/**< Generic byte counter (1024bytes/K) */
 	_DRM_STAT_COUNT,	/**< Generic non-byte counter (1000/k) */
 	_DRM_STAT_IRQ,		/**< IRQ */
 	_DRM_STAT_PRIMARY,	/**< Primary DMA bytes */
 	_DRM_STAT_SECONDARY,	/**< Secondary DMA bytes */
 	_DRM_STAT_DMA,		/**< DMA */
 	_DRM_STAT_SPECIAL,	/**< Special DMA (e.g., priority or polled) */
 	_DRM_STAT_MISSED	/**< Missed DMA opportunity */
 	    /* Add to the *END* of the list */
 };
 /**
  * DRM_IOCTL_GET_STATS ioctl argument type.
  */
 struct drm_stats {
 	unsigned long count;
 	struct {
 		unsigned long value;
 		enum drm_stat_type type;
 	} data[15];
 };
 /**
  * Hardware locking flags.
  */
 enum drm_lock_flags {
 	_DRM_LOCK_READY = 0x01,	     /**< Wait until hardware is ready for DMA */
 	_DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
 	_DRM_LOCK_FLUSH = 0x04,	     /**< Flush this context's DMA queue first */
 	_DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
 	/* These *HALT* flags aren't supported yet
 	   -- they will be used to support the
 	   full-screen DGA-like mode. */
 	_DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
 	_DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
 };
 /**
  * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
  *
  * \sa drmGetLock() and drmUnlock().
  */
 struct drm_lock {
 	int context;
 	enum drm_lock_flags flags;
 };
 /**
  * DMA flags
  *
  * \warning
  * These values \e must match xf86drm.h.
  *
  * \sa drm_dma.
  */
 enum drm_dma_flags {
 	/* Flags for DMA buffer dispatch */
 	_DRM_DMA_BLOCK = 0x01,	      /**<
 				       * Block until buffer dispatched.
 				       *
 				       * \note The buffer may not yet have
 				       * been processed by the hardware --
 				       * getting a hardware lock with the
 				       * hardware quiescent will ensure
 				       * that the buffer has been
 				       * processed.
 				       */
 	_DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
 	_DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
 	/* Flags for DMA buffer request */
 	_DRM_DMA_WAIT = 0x10,	      /**< Wait for free buffers */
 	_DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
 	_DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
 };
 /**
  * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
  *
  * \sa drmAddBufs().
  */
 struct drm_buf_desc {
 	int count;		 /**< Number of buffers of this size */
 	int size;		 /**< Size in bytes */
 	int low_mark;		 /**< Low water mark */
 	int high_mark;		 /**< High water mark */
 	enum {
 		_DRM_PAGE_ALIGN = 0x01,	/**< Align on page boundaries for DMA */
 		_DRM_AGP_BUFFER = 0x02,	/**< Buffer is in AGP space */
 		_DRM_SG_BUFFER = 0x04,	/**< Scatter/gather memory buffer */
 		_DRM_FB_BUFFER = 0x08,	/**< Buffer is in frame buffer */
 		_DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
 	} flags;
 	unsigned long agp_start; /**<
 				  * Start address of where the AGP buffers are
 				  * in the AGP aperture
 				  */
 };
 /**
  * DRM_IOCTL_INFO_BUFS ioctl argument type.
  */
 struct drm_buf_info {
 	int count;		/**< Entries in list */
 	struct drm_buf_desc __user *list;
 };
 /**
  * DRM_IOCTL_FREE_BUFS ioctl argument type.
  */
 struct drm_buf_free {
 	int count;
 	int __user *list;
 };
 /**
  * Buffer information
  *
  * \sa drm_buf_map.
  */
 struct drm_buf_pub {
 	int idx;		       /**< Index into the master buffer list */
 	int total;		       /**< Buffer size */
 	int used;		       /**< Amount of buffer in use (for DMA) */
 	void __user *address;	       /**< Address of buffer */
 };
 /**
  * DRM_IOCTL_MAP_BUFS ioctl argument type.
  */
 struct drm_buf_map {
 	int count;		/**< Length of the buffer list */
 	void __user *virtual;		/**< Mmap'd area in user-virtual */
 	struct drm_buf_pub __user *list;	/**< Buffer information */
 };
 /**
  * DRM_IOCTL_DMA ioctl argument type.
  *
  * Indices here refer to the offset into the buffer list in drm_buf_get.
  *
  * \sa drmDMA().
  */
 struct drm_dma {
 	int context;			  /**< Context handle */
 	int send_count;			  /**< Number of buffers to send */
 	int __user *send_indices;	  /**< List of handles to buffers */
 	int __user *send_sizes;		  /**< Lengths of data to send */
 	enum drm_dma_flags flags;	  /**< Flags */
 	int request_count;		  /**< Number of buffers requested */
 	int request_size;		  /**< Desired size for buffers */
 	int __user *request_indices;	  /**< Buffer information */
 	int __user *request_sizes;
 	int granted_count;		  /**< Number of buffers granted */
 };
 enum drm_ctx_flags {
 	_DRM_CONTEXT_PRESERVED = 0x01,
 	_DRM_CONTEXT_2DONLY = 0x02
 };
 /**
  * DRM_IOCTL_ADD_CTX ioctl argument type.
  *
  * \sa drmCreateContext() and drmDestroyContext().
  */
 struct drm_ctx {
 	drm_context_t handle;
 	enum drm_ctx_flags flags;
 };
 /**
  * DRM_IOCTL_RES_CTX ioctl argument type.
  */
 struct drm_ctx_res {
 	int count;
 	struct drm_ctx __user *contexts;
 };
 /**
  * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
  */
 struct drm_draw {
 	drm_drawable_t handle;
 };
 /**
  * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
  */
 typedef enum {
 	DRM_DRAWABLE_CLIPRECTS,
 } drm_drawable_info_type_t;
 struct drm_update_draw {
 	drm_drawable_t handle;
 	unsigned int type;
 	unsigned int num;
 	unsigned long long data;
 };
 /**
  * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
  */
 struct drm_auth {
 	drm_magic_t magic;
 };
 /**
  * DRM_IOCTL_IRQ_BUSID ioctl argument type.
  *
  * \sa drmGetInterruptFromBusID().
  */
 struct drm_irq_busid {
 	int irq;	/**< IRQ number */
 	int busnum;	/**< bus number */
 	int devnum;	/**< device number */
 	int funcnum;	/**< function number */
 };
 enum drm_vblank_seq_type {
 	_DRM_VBLANK_ABSOLUTE = 0x0,	/**< Wait for specific vblank sequence number */
 	_DRM_VBLANK_RELATIVE = 0x1,	/**< Wait for given number of vblanks */
 	_DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
 	_DRM_VBLANK_NEXTONMISS = 0x10000000,	/**< If missed, wait for next vblank */
 	_DRM_VBLANK_SECONDARY = 0x20000000,	/**< Secondary display controller */
 	_DRM_VBLANK_SIGNAL = 0x40000000	/**< Send signal instead of blocking, unsupported */
 };
 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
 				_DRM_VBLANK_NEXTONMISS)
 struct drm_wait_vblank_request {
 	enum drm_vblank_seq_type type;
 	unsigned int sequence;
 	unsigned long signal;
 };
 struct drm_wait_vblank_reply {
 	enum drm_vblank_seq_type type;
 	unsigned int sequence;
 	long tval_sec;
 	long tval_usec;
 };
 /**
  * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
  *
  * \sa drmWaitVBlank().
  */
 union drm_wait_vblank {
 	struct drm_wait_vblank_request request;
 	struct drm_wait_vblank_reply reply;
 };
 #define _DRM_PRE_MODESET 1
 #define _DRM_POST_MODESET 2
 /**
  * DRM_IOCTL_MODESET_CTL ioctl argument type
  *
  * \sa drmModesetCtl().
  */
 struct drm_modeset_ctl {
-	uint32_t crtc;
+	__u32 crtc;
-	uint32_t cmd;
+	__u32 cmd;
 };
 /**
  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
  *
  * \sa drmAgpEnable().
  */
 struct drm_agp_mode {
 	unsigned long mode;	/**< AGP mode */
 };
 /**
  * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
  *
  * \sa drmAgpAlloc() and drmAgpFree().
  */
 struct drm_agp_buffer {
 	unsigned long size;	/**< In bytes -- will round to page boundary */
 	unsigned long handle;	/**< Used for binding / unbinding */
 	unsigned long type;	/**< Type of memory to allocate */
 	unsigned long physical;	/**< Physical used by i810 */
 };
 /**
  * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
  *
  * \sa drmAgpBind() and drmAgpUnbind().
  */
 struct drm_agp_binding {
 	unsigned long handle;	/**< From drm_agp_buffer */
 	unsigned long offset;	/**< In bytes -- will round to page boundary */
 };
 /**
  * DRM_IOCTL_AGP_INFO ioctl argument type.
  *
  * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
  * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
  * drmAgpVendorId() and drmAgpDeviceId().
  */
 struct drm_agp_info {
 	int agp_version_major;
 	int agp_version_minor;
 	unsigned long mode;
 	unsigned long aperture_base;	/* physical address */
 	unsigned long aperture_size;	/* bytes */
 	unsigned long memory_allowed;	/* bytes */
 	unsigned long memory_used;
 	/* PCI information */
 	unsigned short id_vendor;
 	unsigned short id_device;
 };
 /**
  * DRM_IOCTL_SG_ALLOC ioctl argument type.
  */
 struct drm_scatter_gather {
 	unsigned long size;	/**< In bytes -- will round to page boundary */
 	unsigned long handle;	/**< Used for mapping / unmapping */
 };
 /**
  * DRM_IOCTL_SET_VERSION ioctl argument type.
  */
 struct drm_set_version {
 	int drm_di_major;
 	int drm_di_minor;
 	int drm_dd_major;
 	int drm_dd_minor;
 };
 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */
 struct drm_gem_close {
 	/** Handle of the object to be closed. */
-	uint32_t handle;
+	__u32 handle;
-	uint32_t pad;
+	__u32 pad;
 };
 /** DRM_IOCTL_GEM_FLINK ioctl argument type */
 struct drm_gem_flink {
 	/** Handle for the object being named */
-	uint32_t handle;
+	__u32 handle;
 	/** Returned global name */
-	uint32_t name;
+	__u32 name;
 };
 /** DRM_IOCTL_GEM_OPEN ioctl argument type */
 struct drm_gem_open {
 	/** Name of object being opened */
-	uint32_t name;
+	__u32 name;
 	/** Returned handle for the object */
-	uint32_t handle;
+	__u32 handle;
 	/** Returned size of the object */
-	uint64_t size;
+	__u64 size;
 };
 #include "drm_mode.h"
 #define DRM_IOCTL_BASE			'd'
 #define DRM_IO(nr)			_IO(DRM_IOCTL_BASE,nr)
 #define DRM_IOR(nr,type)		_IOR(DRM_IOCTL_BASE,nr,type)
 #define DRM_IOW(nr,type)		_IOW(DRM_IOCTL_BASE,nr,type)
 #define DRM_IOWR(nr,type)		_IOWR(DRM_IOCTL_BASE,nr,type)
 #define DRM_IOCTL_VERSION		DRM_IOWR(0x00, struct drm_version)
 #define DRM_IOCTL_GET_UNIQUE		DRM_IOWR(0x01, struct drm_unique)
 #define DRM_IOCTL_GET_MAGIC		DRM_IOR( 0x02, struct drm_auth)
 #define DRM_IOCTL_IRQ_BUSID		DRM_IOWR(0x03, struct drm_irq_busid)
 #define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, struct drm_map)
 #define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
 #define DRM_IOCTL_SET_VERSION		DRM_IOWR(0x07, struct drm_set_version)
 #define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
 #define DRM_IOCTL_GEM_CLOSE		DRM_IOW (0x09, struct drm_gem_close)
 #define DRM_IOCTL_GEM_FLINK		DRM_IOWR(0x0a, struct drm_gem_flink)
 #define DRM_IOCTL_GEM_OPEN		DRM_IOWR(0x0b, struct drm_gem_open)
 #define DRM_IOCTL_SET_UNIQUE		DRM_IOW( 0x10, struct drm_unique)
 #define DRM_IOCTL_AUTH_MAGIC		DRM_IOW( 0x11, struct drm_auth)
 #define DRM_IOCTL_BLOCK			DRM_IOWR(0x12, struct drm_block)
 #define DRM_IOCTL_UNBLOCK		DRM_IOWR(0x13, struct drm_block)
 #define DRM_IOCTL_CONTROL		DRM_IOW( 0x14, struct drm_control)
 #define DRM_IOCTL_ADD_MAP		DRM_IOWR(0x15, struct drm_map)
 #define DRM_IOCTL_ADD_BUFS		DRM_IOWR(0x16, struct drm_buf_desc)
 #define DRM_IOCTL_MARK_BUFS		DRM_IOW( 0x17, struct drm_buf_desc)
 #define DRM_IOCTL_INFO_BUFS		DRM_IOWR(0x18, struct drm_buf_info)
 #define DRM_IOCTL_MAP_BUFS		DRM_IOWR(0x19, struct drm_buf_map)
 #define DRM_IOCTL_FREE_BUFS		DRM_IOW( 0x1a, struct drm_buf_free)
 #define DRM_IOCTL_RM_MAP		DRM_IOW( 0x1b, struct drm_map)
 #define DRM_IOCTL_SET_SAREA_CTX		DRM_IOW( 0x1c, struct drm_ctx_priv_map)
 #define DRM_IOCTL_GET_SAREA_CTX 	DRM_IOWR(0x1d, struct drm_ctx_priv_map)
 #define DRM_IOCTL_SET_MASTER            DRM_IO(0x1e)
 #define DRM_IOCTL_DROP_MASTER           DRM_IO(0x1f)
 #define DRM_IOCTL_ADD_CTX		DRM_IOWR(0x20, struct drm_ctx)
 #define DRM_IOCTL_RM_CTX		DRM_IOWR(0x21, struct drm_ctx)
 #define DRM_IOCTL_MOD_CTX		DRM_IOW( 0x22, struct drm_ctx)
 #define DRM_IOCTL_GET_CTX		DRM_IOWR(0x23, struct drm_ctx)
 #define DRM_IOCTL_SWITCH_CTX		DRM_IOW( 0x24, struct drm_ctx)
 #define DRM_IOCTL_NEW_CTX		DRM_IOW( 0x25, struct drm_ctx)
 #define DRM_IOCTL_RES_CTX		DRM_IOWR(0x26, struct drm_ctx_res)
 #define DRM_IOCTL_ADD_DRAW		DRM_IOWR(0x27, struct drm_draw)
 #define DRM_IOCTL_RM_DRAW		DRM_IOWR(0x28, struct drm_draw)
 #define DRM_IOCTL_DMA			DRM_IOWR(0x29, struct drm_dma)
 #define DRM_IOCTL_LOCK			DRM_IOW( 0x2a, struct drm_lock)
 #define DRM_IOCTL_UNLOCK		DRM_IOW( 0x2b, struct drm_lock)
 #define DRM_IOCTL_FINISH		DRM_IOW( 0x2c, struct drm_lock)
 #define DRM_IOCTL_AGP_ACQUIRE		DRM_IO(  0x30)
 #define DRM_IOCTL_AGP_RELEASE		DRM_IO(  0x31)
 #define DRM_IOCTL_AGP_ENABLE		DRM_IOW( 0x32, struct drm_agp_mode)
 #define DRM_IOCTL_AGP_INFO		DRM_IOR( 0x33, struct drm_agp_info)
 #define DRM_IOCTL_AGP_ALLOC		DRM_IOWR(0x34, struct drm_agp_buffer)
 #define DRM_IOCTL_AGP_FREE		DRM_IOW( 0x35, struct drm_agp_buffer)
 #define DRM_IOCTL_AGP_BIND		DRM_IOW( 0x36, struct drm_agp_binding)
 #define DRM_IOCTL_AGP_UNBIND		DRM_IOW( 0x37, struct drm_agp_binding)
 #define DRM_IOCTL_SG_ALLOC		DRM_IOWR(0x38, struct drm_scatter_gather)
 #define DRM_IOCTL_SG_FREE		DRM_IOW( 0x39, struct drm_scatter_gather)
 #define DRM_IOCTL_WAIT_VBLANK		DRM_IOWR(0x3a, union drm_wait_vblank)
 #define DRM_IOCTL_UPDATE_DRAW		DRM_IOW(0x3f, struct drm_update_draw)
 #define DRM_IOCTL_MODE_GETRESOURCES	DRM_IOWR(0xA0, struct drm_mode_card_res)
 #define DRM_IOCTL_MODE_GETCRTC		DRM_IOWR(0xA1, struct drm_mode_crtc)
 #define DRM_IOCTL_MODE_SETCRTC		DRM_IOWR(0xA2, struct drm_mode_crtc)
 #define DRM_IOCTL_MODE_CURSOR		DRM_IOWR(0xA3, struct drm_mode_cursor)
 #define DRM_IOCTL_MODE_GETGAMMA		DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
 #define DRM_IOCTL_MODE_SETGAMMA		DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
 #define DRM_IOCTL_MODE_GETENCODER	DRM_IOWR(0xA6, struct drm_mode_get_encoder)
 #define DRM_IOCTL_MODE_GETCONNECTOR	DRM_IOWR(0xA7, struct drm_mode_get_connector)
 #define DRM_IOCTL_MODE_ATTACHMODE	DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
 #define DRM_IOCTL_MODE_DETACHMODE	DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
 #define DRM_IOCTL_MODE_GETPROPERTY	DRM_IOWR(0xAA, struct drm_mode_get_property)
 #define DRM_IOCTL_MODE_SETPROPERTY	DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
 #define DRM_IOCTL_MODE_GETPROPBLOB	DRM_IOWR(0xAC, struct drm_mode_get_blob)
 #define DRM_IOCTL_MODE_GETFB		DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
 #define DRM_IOCTL_MODE_ADDFB		DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
 #define DRM_IOCTL_MODE_RMFB		DRM_IOWR(0xAF, unsigned int)
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x99.
  * Generic IOCTLS restart at 0xA0.
  *
  * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
  * drmCommandReadWrite().
  */
 #define DRM_COMMAND_BASE                0x40
 #define DRM_COMMAND_END			0xA0
 /* typedef area */
 #ifndef __KERNEL__
 typedef struct drm_clip_rect drm_clip_rect_t;
 typedef struct drm_drawable_info drm_drawable_info_t;
 typedef struct drm_tex_region drm_tex_region_t;
 typedef struct drm_hw_lock drm_hw_lock_t;
 typedef struct drm_version drm_version_t;
 typedef struct drm_unique drm_unique_t;
 typedef struct drm_list drm_list_t;
 typedef struct drm_block drm_block_t;
 typedef struct drm_control drm_control_t;
 typedef enum drm_map_type drm_map_type_t;
 typedef enum drm_map_flags drm_map_flags_t;
 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
 typedef struct drm_map drm_map_t;
 typedef struct drm_client drm_client_t;
 typedef enum drm_stat_type drm_stat_type_t;
 typedef struct drm_stats drm_stats_t;
 typedef enum drm_lock_flags drm_lock_flags_t;
 typedef struct drm_lock drm_lock_t;
 typedef enum drm_dma_flags drm_dma_flags_t;
 typedef struct drm_buf_desc drm_buf_desc_t;
 typedef struct drm_buf_info drm_buf_info_t;
 typedef struct drm_buf_free drm_buf_free_t;
 typedef struct drm_buf_pub drm_buf_pub_t;
 typedef struct drm_buf_map drm_buf_map_t;
 typedef struct drm_dma drm_dma_t;
 typedef union drm_wait_vblank drm_wait_vblank_t;
 typedef struct drm_agp_mode drm_agp_mode_t;
 typedef enum drm_ctx_flags drm_ctx_flags_t;
 typedef struct drm_ctx drm_ctx_t;
 typedef struct drm_ctx_res drm_ctx_res_t;
 typedef struct drm_draw drm_draw_t;
 typedef struct drm_update_draw drm_update_draw_t;
 typedef struct drm_auth drm_auth_t;
 typedef struct drm_irq_busid drm_irq_busid_t;
 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
 typedef struct drm_agp_buffer drm_agp_buffer_t;
 typedef struct drm_agp_binding drm_agp_binding_t;
 typedef struct drm_agp_info drm_agp_info_t;
 typedef struct drm_scatter_gather drm_scatter_gather_t;
 typedef struct drm_set_version drm_set_version_t;
 #endif
 #endif

include/drm/drm_mode.h

Diff comments View file @ 1d7f83d

 /*
  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
  * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
  * Copyright (c) 2008 Red Hat Inc.
  * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
  * Copyright (c) 2007-2008 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
  */
 #ifndef _DRM_MODE_H
 #define _DRM_MODE_H
-#if !defined(__KERNEL__) && !defined(_KERNEL)
-#include <stdint.h>
-#else
 #include <linux/kernel.h>
-#endif
+#include <linux/types.h>
 #define DRM_DISPLAY_INFO_LEN	32
 #define DRM_CONNECTOR_NAME_LEN	32
 #define DRM_DISPLAY_MODE_LEN	32
 #define DRM_PROP_NAME_LEN	32
 #define DRM_MODE_TYPE_BUILTIN	(1<<0)
 #define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
 #define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
 #define DRM_MODE_TYPE_PREFERRED	(1<<3)
 #define DRM_MODE_TYPE_DEFAULT	(1<<4)
 #define DRM_MODE_TYPE_USERDEF	(1<<5)
 #define DRM_MODE_TYPE_DRIVER	(1<<6)
 /* Video mode flags */
 /* bit compatible with the xorg definitions. */
 #define DRM_MODE_FLAG_PHSYNC	(1<<0)
 #define DRM_MODE_FLAG_NHSYNC	(1<<1)
 #define DRM_MODE_FLAG_PVSYNC	(1<<2)
 #define DRM_MODE_FLAG_NVSYNC	(1<<3)
 #define DRM_MODE_FLAG_INTERLACE	(1<<4)
 #define DRM_MODE_FLAG_DBLSCAN	(1<<5)
 #define DRM_MODE_FLAG_CSYNC	(1<<6)
 #define DRM_MODE_FLAG_PCSYNC	(1<<7)
 #define DRM_MODE_FLAG_NCSYNC	(1<<8)
 #define DRM_MODE_FLAG_HSKEW	(1<<9) /* hskew provided */
 #define DRM_MODE_FLAG_BCAST	(1<<10)
 #define DRM_MODE_FLAG_PIXMUX	(1<<11)
 #define DRM_MODE_FLAG_DBLCLK	(1<<12)
 #define DRM_MODE_FLAG_CLKDIV2	(1<<13)
 /* DPMS flags */
 /* bit compatible with the xorg definitions. */
 #define DRM_MODE_DPMS_ON	0
 #define DRM_MODE_DPMS_STANDBY	1
 #define DRM_MODE_DPMS_SUSPEND	2
 #define DRM_MODE_DPMS_OFF	3
 /* Scaling mode options */
 #define DRM_MODE_SCALE_NON_GPU		0
 #define DRM_MODE_SCALE_FULLSCREEN	1
 #define DRM_MODE_SCALE_NO_SCALE		2
 #define DRM_MODE_SCALE_ASPECT		3
 /* Dithering mode options */
 #define DRM_MODE_DITHERING_OFF	0
 #define DRM_MODE_DITHERING_ON	1
 struct drm_mode_modeinfo {
-	uint32_t clock;
+	__u32 clock;
-	uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew;
+	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
-	uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan;
+	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
-	uint32_t vrefresh; /* vertical refresh * 1000 */
+	__u32 vrefresh; /* vertical refresh * 1000 */
-	uint32_t flags;
+	__u32 flags;
-	uint32_t type;
+	__u32 type;
 	char name[DRM_DISPLAY_MODE_LEN];
 };
 struct drm_mode_card_res {
-	uint64_t fb_id_ptr;
+	__u64 fb_id_ptr;
-	uint64_t crtc_id_ptr;
+	__u64 crtc_id_ptr;
-	uint64_t connector_id_ptr;
+	__u64 connector_id_ptr;
-	uint64_t encoder_id_ptr;
+	__u64 encoder_id_ptr;
-	uint32_t count_fbs;
+	__u32 count_fbs;
-	uint32_t count_crtcs;
+	__u32 count_crtcs;
-	uint32_t count_connectors;
+	__u32 count_connectors;
-	uint32_t count_encoders;
+	__u32 count_encoders;
-	uint32_t min_width, max_width;
+	__u32 min_width, max_width;
-	uint32_t min_height, max_height;
+	__u32 min_height, max_height;
 };
 struct drm_mode_crtc {
-	uint64_t set_connectors_ptr;
+	__u64 set_connectors_ptr;
-	uint32_t count_connectors;
+	__u32 count_connectors;
-	uint32_t crtc_id; /**< Id */
+	__u32 crtc_id; /**< Id */
-	uint32_t fb_id; /**< Id of framebuffer */
+	__u32 fb_id; /**< Id of framebuffer */
-	uint32_t x, y; /**< Position on the frameuffer */
+	__u32 x, y; /**< Position on the frameuffer */
-	uint32_t gamma_size;
+	__u32 gamma_size;
-	uint32_t mode_valid;
+	__u32 mode_valid;
 	struct drm_mode_modeinfo mode;
 };
 #define DRM_MODE_ENCODER_NONE	0
 #define DRM_MODE_ENCODER_DAC	1
 #define DRM_MODE_ENCODER_TMDS	2
 #define DRM_MODE_ENCODER_LVDS	3
 #define DRM_MODE_ENCODER_TVDAC	4
 struct drm_mode_get_encoder {
-	uint32_t encoder_id;
+	__u32 encoder_id;
-	uint32_t encoder_type;
+	__u32 encoder_type;
-	uint32_t crtc_id; /**< Id of crtc */
+	__u32 crtc_id; /**< Id of crtc */
-	uint32_t possible_crtcs;
+	__u32 possible_crtcs;
-	uint32_t possible_clones;
+	__u32 possible_clones;
 };
 /* This is for connectors with multiple signal types. */
 /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
 #define DRM_MODE_SUBCONNECTOR_Automatic	0
 #define DRM_MODE_SUBCONNECTOR_Unknown	0
 #define DRM_MODE_SUBCONNECTOR_DVID	3
 #define DRM_MODE_SUBCONNECTOR_DVIA	4
 #define DRM_MODE_SUBCONNECTOR_Composite	5
 #define DRM_MODE_SUBCONNECTOR_SVIDEO	6
 #define DRM_MODE_SUBCONNECTOR_Component	8
 #define DRM_MODE_CONNECTOR_Unknown	0
 #define DRM_MODE_CONNECTOR_VGA		1
 #define DRM_MODE_CONNECTOR_DVII		2
 #define DRM_MODE_CONNECTOR_DVID		3
 #define DRM_MODE_CONNECTOR_DVIA		4
 #define DRM_MODE_CONNECTOR_Composite	5
 #define DRM_MODE_CONNECTOR_SVIDEO	6
 #define DRM_MODE_CONNECTOR_LVDS		7
 #define DRM_MODE_CONNECTOR_Component	8
 #define DRM_MODE_CONNECTOR_9PinDIN	9
 #define DRM_MODE_CONNECTOR_DisplayPort	10
 #define DRM_MODE_CONNECTOR_HDMIA	11
 #define DRM_MODE_CONNECTOR_HDMIB	12
 struct drm_mode_get_connector {
-	uint64_t encoders_ptr;
+	__u64 encoders_ptr;
-	uint64_t modes_ptr;
+	__u64 modes_ptr;
-	uint64_t props_ptr;
+	__u64 props_ptr;
-	uint64_t prop_values_ptr;
+	__u64 prop_values_ptr;
-	uint32_t count_modes;
+	__u32 count_modes;
-	uint32_t count_props;
+	__u32 count_props;
-	uint32_t count_encoders;
+	__u32 count_encoders;
-	uint32_t encoder_id; /**< Current Encoder */
+	__u32 encoder_id; /**< Current Encoder */
-	uint32_t connector_id; /**< Id */
+	__u32 connector_id; /**< Id */
-	uint32_t connector_type;
+	__u32 connector_type;
-	uint32_t connector_type_id;
+	__u32 connector_type_id;
-	uint32_t connection;
+	__u32 connection;
-	uint32_t mm_width, mm_height; /**< HxW in millimeters */
+	__u32 mm_width, mm_height; /**< HxW in millimeters */
-	uint32_t subpixel;
+	__u32 subpixel;
 };
 #define DRM_MODE_PROP_PENDING	(1<<0)
 #define DRM_MODE_PROP_RANGE	(1<<1)
 #define DRM_MODE_PROP_IMMUTABLE	(1<<2)
 #define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
 #define DRM_MODE_PROP_BLOB	(1<<4)
 struct drm_mode_property_enum {
-	uint64_t value;
+	__u64 value;
 	char name[DRM_PROP_NAME_LEN];
 };
 struct drm_mode_get_property {
-	uint64_t values_ptr; /* values and blob lengths */
+	__u64 values_ptr; /* values and blob lengths */
-	uint64_t enum_blob_ptr; /* enum and blob id ptrs */
+	__u64 enum_blob_ptr; /* enum and blob id ptrs */
-	uint32_t prop_id;
+	__u32 prop_id;
-	uint32_t flags;
+	__u32 flags;
 	char name[DRM_PROP_NAME_LEN];
-	uint32_t count_values;
+	__u32 count_values;
-	uint32_t count_enum_blobs;
+	__u32 count_enum_blobs;
 };
 struct drm_mode_connector_set_property {
-	uint64_t value;
+	__u64 value;
-	uint32_t prop_id;
+	__u32 prop_id;
-	uint32_t connector_id;
+	__u32 connector_id;
 };
 struct drm_mode_get_blob {
-	uint32_t blob_id;
+	__u32 blob_id;
-	uint32_t length;
+	__u32 length;
-	uint64_t data;
+	__u64 data;
 };
 struct drm_mode_fb_cmd {
-	uint32_t fb_id;
+	__u32 fb_id;
-	uint32_t width, height;
+	__u32 width, height;
-	uint32_t pitch;
+	__u32 pitch;
-	uint32_t bpp;
+	__u32 bpp;
-	uint32_t depth;
+	__u32 depth;
 	/* driver specific handle */
-	uint32_t handle;
+	__u32 handle;
 };
 struct drm_mode_mode_cmd {
-	uint32_t connector_id;
+	__u32 connector_id;
 	struct drm_mode_modeinfo mode;
 };
 #define DRM_MODE_CURSOR_BO	(1<<0)
 #define DRM_MODE_CURSOR_MOVE	(1<<1)
 /*
  * depending on the value in flags diffrent members are used.
  *
  * CURSOR_BO uses
  *    crtc
  *    width
  *    height
  *    handle - if 0 turns the cursor of
  *
  * CURSOR_MOVE uses
  *    crtc
  *    x
  *    y
  */
 struct drm_mode_cursor {
-	uint32_t flags;
+	__u32 flags;
-	uint32_t crtc_id;
+	__u32 crtc_id;
-	int32_t x;
+	__s32 x;
-	int32_t y;
+	__s32 y;
-	uint32_t width;
+	__u32 width;
-	uint32_t height;
+	__u32 height;
 	/* driver specific handle */
-	uint32_t handle;
+	__u32 handle;
 };
 struct drm_mode_crtc_lut {
-	uint32_t crtc_id;
+	__u32 crtc_id;
-	uint32_t gamma_size;
+	__u32 gamma_size;
 	/* pointers to arrays */
-	uint64_t red;
+	__u64 red;
-	uint64_t green;
+	__u64 green;
-	uint64_t blue;
+	__u64 blue;
 };
 #endif

include/drm/i915_drm.h

Diff comments View file @ 1d7f83d

1	/*	1	/*
2	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.	2	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3	* All Rights Reserved.	3	* All Rights Reserved.
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the	6	* copy of this software and associated documentation files (the
7	* "Software"), to deal in the Software without restriction, including	7	* "Software"), to deal in the Software without restriction, including
8	* without limitation the rights to use, copy, modify, merge, publish,	8	* without limitation the rights to use, copy, modify, merge, publish,
9	* distribute, sub license, and/or sell copies of the Software, and to	9	* distribute, sub license, and/or sell copies of the Software, and to
10	* permit persons to whom the Software is furnished to do so, subject to	10	* permit persons to whom the Software is furnished to do so, subject to
11	* the following conditions:	11	* the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice (including the	13	* The above copyright notice and this permission notice (including the
14	* next paragraph) shall be included in all copies or substantial portions	14	* next paragraph) shall be included in all copies or substantial portions
15	* of the Software.	15	* of the Software.
16	*	16	*
17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF	18	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR	20	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,	21	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE	22	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.	23	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24	*	24	*
25	*/	25	*/
26		26
27	#ifndef _I915_DRM_H_	27	#ifndef _I915_DRM_H_
28	#define _I915_DRM_H_	28	#define _I915_DRM_H_
29		29
30	/* Please note that modifications to all structs defined here are	30	/* Please note that modifications to all structs defined here are
31	* subject to backwards-compatibility constraints.	31	* subject to backwards-compatibility constraints.
32	*/	32	*/
33		33	#include <linux/types.h>
34	#include "drm.h"	34	#include "drm.h"
35		35
36	/* Each region is a minimum of 16k, and there are at most 255 of them.	36	/* Each region is a minimum of 16k, and there are at most 255 of them.
37	*/	37	*/
38	#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use	38	#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39	* of chars for next/prev indices */	39	* of chars for next/prev indices */
40	#define I915_LOG_MIN_TEX_REGION_SIZE 14	40	#define I915_LOG_MIN_TEX_REGION_SIZE 14
41		41
42	typedef struct _drm_i915_init {	42	typedef struct _drm_i915_init {
43	enum {	43	enum {
44	I915_INIT_DMA = 0x01,	44	I915_INIT_DMA = 0x01,
45	I915_CLEANUP_DMA = 0x02,	45	I915_CLEANUP_DMA = 0x02,
46	I915_RESUME_DMA = 0x03	46	I915_RESUME_DMA = 0x03
47	} func;	47	} func;
48	unsigned int mmio_offset;	48	unsigned int mmio_offset;
49	int sarea_priv_offset;	49	int sarea_priv_offset;
50	unsigned int ring_start;	50	unsigned int ring_start;
51	unsigned int ring_end;	51	unsigned int ring_end;
52	unsigned int ring_size;	52	unsigned int ring_size;
53	unsigned int front_offset;	53	unsigned int front_offset;
54	unsigned int back_offset;	54	unsigned int back_offset;
55	unsigned int depth_offset;	55	unsigned int depth_offset;
56	unsigned int w;	56	unsigned int w;
57	unsigned int h;	57	unsigned int h;
58	unsigned int pitch;	58	unsigned int pitch;
59	unsigned int pitch_bits;	59	unsigned int pitch_bits;
60	unsigned int back_pitch;	60	unsigned int back_pitch;
61	unsigned int depth_pitch;	61	unsigned int depth_pitch;
62	unsigned int cpp;	62	unsigned int cpp;
63	unsigned int chipset;	63	unsigned int chipset;
64	} drm_i915_init_t;	64	} drm_i915_init_t;
65		65
66	typedef struct _drm_i915_sarea {	66	typedef struct _drm_i915_sarea {
67	struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];	67	struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
68	int last_upload; /* last time texture was uploaded */	68	int last_upload; /* last time texture was uploaded */
69	int last_enqueue; /* last time a buffer was enqueued */	69	int last_enqueue; /* last time a buffer was enqueued */
70	int last_dispatch; /* age of the most recently dispatched buffer */	70	int last_dispatch; /* age of the most recently dispatched buffer */
71	int ctxOwner; /* last context to upload state */	71	int ctxOwner; /* last context to upload state */
72	int texAge;	72	int texAge;
73	int pf_enabled; /* is pageflipping allowed? */	73	int pf_enabled; /* is pageflipping allowed? */
74	int pf_active;	74	int pf_active;
75	int pf_current_page; /* which buffer is being displayed? */	75	int pf_current_page; /* which buffer is being displayed? */
76	int perf_boxes; /* performance boxes to be displayed */	76	int perf_boxes; /* performance boxes to be displayed */
77	int width, height; /* screen size in pixels */	77	int width, height; /* screen size in pixels */
78		78
79	drm_handle_t front_handle;	79	drm_handle_t front_handle;
80	int front_offset;	80	int front_offset;
81	int front_size;	81	int front_size;
82		82
83	drm_handle_t back_handle;	83	drm_handle_t back_handle;
84	int back_offset;	84	int back_offset;
85	int back_size;	85	int back_size;
86		86
87	drm_handle_t depth_handle;	87	drm_handle_t depth_handle;
88	int depth_offset;	88	int depth_offset;
89	int depth_size;	89	int depth_size;
90		90
91	drm_handle_t tex_handle;	91	drm_handle_t tex_handle;
92	int tex_offset;	92	int tex_offset;
93	int tex_size;	93	int tex_size;
94	int log_tex_granularity;	94	int log_tex_granularity;
95	int pitch;	95	int pitch;
96	int rotation; /* 0, 90, 180 or 270 */	96	int rotation; /* 0, 90, 180 or 270 */
97	int rotated_offset;	97	int rotated_offset;
98	int rotated_size;	98	int rotated_size;
99	int rotated_pitch;	99	int rotated_pitch;
100	int virtualX, virtualY;	100	int virtualX, virtualY;
101		101
102	unsigned int front_tiled;	102	unsigned int front_tiled;
103	unsigned int back_tiled;	103	unsigned int back_tiled;
104	unsigned int depth_tiled;	104	unsigned int depth_tiled;
105	unsigned int rotated_tiled;	105	unsigned int rotated_tiled;
106	unsigned int rotated2_tiled;	106	unsigned int rotated2_tiled;
107		107
108	int pipeA_x;	108	int pipeA_x;
109	int pipeA_y;	109	int pipeA_y;
110	int pipeA_w;	110	int pipeA_w;
111	int pipeA_h;	111	int pipeA_h;
112	int pipeB_x;	112	int pipeB_x;
113	int pipeB_y;	113	int pipeB_y;
114	int pipeB_w;	114	int pipeB_w;
115	int pipeB_h;	115	int pipeB_h;
116		116
117	/* fill out some space for old userspace triple buffer */	117	/* fill out some space for old userspace triple buffer */
118	drm_handle_t unused_handle;	118	drm_handle_t unused_handle;
119	uint32_t unused1, unused2, unused3;	119	__u32 unused1, unused2, unused3;
120		120
121	/* buffer object handles for static buffers. May change	121	/* buffer object handles for static buffers. May change
122	* over the lifetime of the client.	122	* over the lifetime of the client.
123	*/	123	*/
124	uint32_t front_bo_handle;	124	__u32 front_bo_handle;
125	uint32_t back_bo_handle;	125	__u32 back_bo_handle;
126	uint32_t unused_bo_handle;	126	__u32 unused_bo_handle;
127	uint32_t depth_bo_handle;	127	__u32 depth_bo_handle;
128		128
129	} drm_i915_sarea_t;	129	} drm_i915_sarea_t;
130		130
131	/* due to userspace building against these headers we need some compat here */	131	/* due to userspace building against these headers we need some compat here */
132	#define planeA_x pipeA_x	132	#define planeA_x pipeA_x
133	#define planeA_y pipeA_y	133	#define planeA_y pipeA_y
134	#define planeA_w pipeA_w	134	#define planeA_w pipeA_w
135	#define planeA_h pipeA_h	135	#define planeA_h pipeA_h
136	#define planeB_x pipeB_x	136	#define planeB_x pipeB_x
137	#define planeB_y pipeB_y	137	#define planeB_y pipeB_y
138	#define planeB_w pipeB_w	138	#define planeB_w pipeB_w
139	#define planeB_h pipeB_h	139	#define planeB_h pipeB_h
140		140
141	/* Flags for perf_boxes	141	/* Flags for perf_boxes
142	*/	142	*/
143	#define I915_BOX_RING_EMPTY 0x1	143	#define I915_BOX_RING_EMPTY 0x1
144	#define I915_BOX_FLIP 0x2	144	#define I915_BOX_FLIP 0x2
145	#define I915_BOX_WAIT 0x4	145	#define I915_BOX_WAIT 0x4
146	#define I915_BOX_TEXTURE_LOAD 0x8	146	#define I915_BOX_TEXTURE_LOAD 0x8
147	#define I915_BOX_LOST_CONTEXT 0x10	147	#define I915_BOX_LOST_CONTEXT 0x10
148		148
149	/* I915 specific ioctls	149	/* I915 specific ioctls
150	* The device specific ioctl range is 0x40 to 0x79.	150	* The device specific ioctl range is 0x40 to 0x79.
151	*/	151	*/
152	#define DRM_I915_INIT 0x00	152	#define DRM_I915_INIT 0x00
153	#define DRM_I915_FLUSH 0x01	153	#define DRM_I915_FLUSH 0x01
154	#define DRM_I915_FLIP 0x02	154	#define DRM_I915_FLIP 0x02
155	#define DRM_I915_BATCHBUFFER 0x03	155	#define DRM_I915_BATCHBUFFER 0x03
156	#define DRM_I915_IRQ_EMIT 0x04	156	#define DRM_I915_IRQ_EMIT 0x04
157	#define DRM_I915_IRQ_WAIT 0x05	157	#define DRM_I915_IRQ_WAIT 0x05
158	#define DRM_I915_GETPARAM 0x06	158	#define DRM_I915_GETPARAM 0x06
159	#define DRM_I915_SETPARAM 0x07	159	#define DRM_I915_SETPARAM 0x07
160	#define DRM_I915_ALLOC 0x08	160	#define DRM_I915_ALLOC 0x08
161	#define DRM_I915_FREE 0x09	161	#define DRM_I915_FREE 0x09
162	#define DRM_I915_INIT_HEAP 0x0a	162	#define DRM_I915_INIT_HEAP 0x0a
163	#define DRM_I915_CMDBUFFER 0x0b	163	#define DRM_I915_CMDBUFFER 0x0b
164	#define DRM_I915_DESTROY_HEAP 0x0c	164	#define DRM_I915_DESTROY_HEAP 0x0c
165	#define DRM_I915_SET_VBLANK_PIPE 0x0d	165	#define DRM_I915_SET_VBLANK_PIPE 0x0d
166	#define DRM_I915_GET_VBLANK_PIPE 0x0e	166	#define DRM_I915_GET_VBLANK_PIPE 0x0e
167	#define DRM_I915_VBLANK_SWAP 0x0f	167	#define DRM_I915_VBLANK_SWAP 0x0f
168	#define DRM_I915_HWS_ADDR 0x11	168	#define DRM_I915_HWS_ADDR 0x11
169	#define DRM_I915_GEM_INIT 0x13	169	#define DRM_I915_GEM_INIT 0x13
170	#define DRM_I915_GEM_EXECBUFFER 0x14	170	#define DRM_I915_GEM_EXECBUFFER 0x14
171	#define DRM_I915_GEM_PIN 0x15	171	#define DRM_I915_GEM_PIN 0x15
172	#define DRM_I915_GEM_UNPIN 0x16	172	#define DRM_I915_GEM_UNPIN 0x16
173	#define DRM_I915_GEM_BUSY 0x17	173	#define DRM_I915_GEM_BUSY 0x17
174	#define DRM_I915_GEM_THROTTLE 0x18	174	#define DRM_I915_GEM_THROTTLE 0x18
175	#define DRM_I915_GEM_ENTERVT 0x19	175	#define DRM_I915_GEM_ENTERVT 0x19
176	#define DRM_I915_GEM_LEAVEVT 0x1a	176	#define DRM_I915_GEM_LEAVEVT 0x1a
177	#define DRM_I915_GEM_CREATE 0x1b	177	#define DRM_I915_GEM_CREATE 0x1b
178	#define DRM_I915_GEM_PREAD 0x1c	178	#define DRM_I915_GEM_PREAD 0x1c
179	#define DRM_I915_GEM_PWRITE 0x1d	179	#define DRM_I915_GEM_PWRITE 0x1d
180	#define DRM_I915_GEM_MMAP 0x1e	180	#define DRM_I915_GEM_MMAP 0x1e
181	#define DRM_I915_GEM_SET_DOMAIN 0x1f	181	#define DRM_I915_GEM_SET_DOMAIN 0x1f
182	#define DRM_I915_GEM_SW_FINISH 0x20	182	#define DRM_I915_GEM_SW_FINISH 0x20
183	#define DRM_I915_GEM_SET_TILING 0x21	183	#define DRM_I915_GEM_SET_TILING 0x21
184	#define DRM_I915_GEM_GET_TILING 0x22	184	#define DRM_I915_GEM_GET_TILING 0x22
185	#define DRM_I915_GEM_GET_APERTURE 0x23	185	#define DRM_I915_GEM_GET_APERTURE 0x23
186	#define DRM_I915_GEM_MMAP_GTT 0x24	186	#define DRM_I915_GEM_MMAP_GTT 0x24
187		187
188	#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)	188	#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
189	#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)	189	#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
190	#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)	190	#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
191	#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)	191	#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
192	#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)	192	#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
193	#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)	193	#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
194	#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)	194	#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
195	#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)	195	#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
196	#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)	196	#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
197	#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)	197	#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
198	#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)	198	#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
199	#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)	199	#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
200	#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)	200	#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
201	#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)	201	#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
202	#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)	202	#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
203	#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)	203	#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
204	#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)	204	#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
205	#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)	205	#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
206	#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)	206	#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
207	#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)	207	#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
208	#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)	208	#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
209	#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)	209	#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
210	#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)	210	#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
211	#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)	211	#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
212	#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)	212	#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
213	#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)	213	#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
214	#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)	214	#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
215	#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)	215	#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
216	#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)	216	#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
217	#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)	217	#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
218	#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)	218	#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
219	#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)	219	#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
220	#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)	220	#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
221	#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)	221	#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
222		222
223	/* Allow drivers to submit batchbuffers directly to hardware, relying	223	/* Allow drivers to submit batchbuffers directly to hardware, relying
224	* on the security mechanisms provided by hardware.	224	* on the security mechanisms provided by hardware.
225	*/	225	*/
226	typedef struct drm_i915_batchbuffer {	226	typedef struct drm_i915_batchbuffer {
227	int start; /* agp offset */	227	int start; /* agp offset */
228	int used; /* nr bytes in use */	228	int used; /* nr bytes in use */
229	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */	229	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
230	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */	230	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
231	int num_cliprects; /* mulitpass with multiple cliprects? */	231	int num_cliprects; /* mulitpass with multiple cliprects? */
232	struct drm_clip_rect __user cliprects; / pointer to userspace cliprects */	232	struct drm_clip_rect __user cliprects; / pointer to userspace cliprects */
233	} drm_i915_batchbuffer_t;	233	} drm_i915_batchbuffer_t;
234		234
235	/* As above, but pass a pointer to userspace buffer which can be	235	/* As above, but pass a pointer to userspace buffer which can be
236	* validated by the kernel prior to sending to hardware.	236	* validated by the kernel prior to sending to hardware.
237	*/	237	*/
238	typedef struct _drm_i915_cmdbuffer {	238	typedef struct _drm_i915_cmdbuffer {
239	char __user buf; / pointer to userspace command buffer */	239	char __user buf; / pointer to userspace command buffer */
240	int sz; /* nr bytes in buf */	240	int sz; /* nr bytes in buf */
241	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */	241	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
242	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */	242	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
243	int num_cliprects; /* mulitpass with multiple cliprects? */	243	int num_cliprects; /* mulitpass with multiple cliprects? */
244	struct drm_clip_rect __user cliprects; / pointer to userspace cliprects */	244	struct drm_clip_rect __user cliprects; / pointer to userspace cliprects */
245	} drm_i915_cmdbuffer_t;	245	} drm_i915_cmdbuffer_t;
246		246
247	/* Userspace can request & wait on irq's:	247	/* Userspace can request & wait on irq's:
248	*/	248	*/
249	typedef struct drm_i915_irq_emit {	249	typedef struct drm_i915_irq_emit {
250	int __user *irq_seq;	250	int __user *irq_seq;
251	} drm_i915_irq_emit_t;	251	} drm_i915_irq_emit_t;
252		252
253	typedef struct drm_i915_irq_wait {	253	typedef struct drm_i915_irq_wait {
254	int irq_seq;	254	int irq_seq;
255	} drm_i915_irq_wait_t;	255	} drm_i915_irq_wait_t;
256		256
257	/* Ioctl to query kernel params:	257	/* Ioctl to query kernel params:
258	*/	258	*/
259	#define I915_PARAM_IRQ_ACTIVE 1	259	#define I915_PARAM_IRQ_ACTIVE 1
260	#define I915_PARAM_ALLOW_BATCHBUFFER 2	260	#define I915_PARAM_ALLOW_BATCHBUFFER 2
261	#define I915_PARAM_LAST_DISPATCH 3	261	#define I915_PARAM_LAST_DISPATCH 3
262	#define I915_PARAM_CHIPSET_ID 4	262	#define I915_PARAM_CHIPSET_ID 4
263	#define I915_PARAM_HAS_GEM 5	263	#define I915_PARAM_HAS_GEM 5
264		264
265	typedef struct drm_i915_getparam {	265	typedef struct drm_i915_getparam {
266	int param;	266	int param;
267	int __user *value;	267	int __user *value;
268	} drm_i915_getparam_t;	268	} drm_i915_getparam_t;
269		269
270	/* Ioctl to set kernel params:	270	/* Ioctl to set kernel params:
271	*/	271	*/
272	#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1	272	#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
273	#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2	273	#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
274	#define I915_SETPARAM_ALLOW_BATCHBUFFER 3	274	#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
275		275
276	typedef struct drm_i915_setparam {	276	typedef struct drm_i915_setparam {
277	int param;	277	int param;
278	int value;	278	int value;
279	} drm_i915_setparam_t;	279	} drm_i915_setparam_t;
280		280
281	/* A memory manager for regions of shared memory:	281	/* A memory manager for regions of shared memory:
282	*/	282	*/
283	#define I915_MEM_REGION_AGP 1	283	#define I915_MEM_REGION_AGP 1
284		284
285	typedef struct drm_i915_mem_alloc {	285	typedef struct drm_i915_mem_alloc {
286	int region;	286	int region;
287	int alignment;	287	int alignment;
288	int size;	288	int size;
289	int __user region_offset; / offset from start of fb or agp */	289	int __user region_offset; / offset from start of fb or agp */
290	} drm_i915_mem_alloc_t;	290	} drm_i915_mem_alloc_t;
291		291
292	typedef struct drm_i915_mem_free {	292	typedef struct drm_i915_mem_free {
293	int region;	293	int region;
294	int region_offset;	294	int region_offset;
295	} drm_i915_mem_free_t;	295	} drm_i915_mem_free_t;
296		296
297	typedef struct drm_i915_mem_init_heap {	297	typedef struct drm_i915_mem_init_heap {
298	int region;	298	int region;
299	int size;	299	int size;
300	int start;	300	int start;
301	} drm_i915_mem_init_heap_t;	301	} drm_i915_mem_init_heap_t;
302		302
303	/* Allow memory manager to be torn down and re-initialized (eg on	303	/* Allow memory manager to be torn down and re-initialized (eg on
304	* rotate):	304	* rotate):
305	*/	305	*/
306	typedef struct drm_i915_mem_destroy_heap {	306	typedef struct drm_i915_mem_destroy_heap {
307	int region;	307	int region;
308	} drm_i915_mem_destroy_heap_t;	308	} drm_i915_mem_destroy_heap_t;
309		309
310	/* Allow X server to configure which pipes to monitor for vblank signals	310	/* Allow X server to configure which pipes to monitor for vblank signals
311	*/	311	*/
312	#define DRM_I915_VBLANK_PIPE_A 1	312	#define DRM_I915_VBLANK_PIPE_A 1
313	#define DRM_I915_VBLANK_PIPE_B 2	313	#define DRM_I915_VBLANK_PIPE_B 2
314		314
315	typedef struct drm_i915_vblank_pipe {	315	typedef struct drm_i915_vblank_pipe {
316	int pipe;	316	int pipe;
317	} drm_i915_vblank_pipe_t;	317	} drm_i915_vblank_pipe_t;
318		318
319	/* Schedule buffer swap at given vertical blank:	319	/* Schedule buffer swap at given vertical blank:
320	*/	320	*/
321	typedef struct drm_i915_vblank_swap {	321	typedef struct drm_i915_vblank_swap {
322	drm_drawable_t drawable;	322	drm_drawable_t drawable;
323	enum drm_vblank_seq_type seqtype;	323	enum drm_vblank_seq_type seqtype;
324	unsigned int sequence;	324	unsigned int sequence;
325	} drm_i915_vblank_swap_t;	325	} drm_i915_vblank_swap_t;
326		326
327	typedef struct drm_i915_hws_addr {	327	typedef struct drm_i915_hws_addr {
328	uint64_t addr;	328	__u64 addr;
329	} drm_i915_hws_addr_t;	329	} drm_i915_hws_addr_t;
330		330
331	struct drm_i915_gem_init {	331	struct drm_i915_gem_init {
332	/**	332	/**
333	* Beginning offset in the GTT to be managed by the DRM memory	333	* Beginning offset in the GTT to be managed by the DRM memory
334	* manager.	334	* manager.
335	*/	335	*/
336	uint64_t gtt_start;	336	__u64 gtt_start;
337	/**	337	/**
338	* Ending offset in the GTT to be managed by the DRM memory	338	* Ending offset in the GTT to be managed by the DRM memory
339	* manager.	339	* manager.
340	*/	340	*/
341	uint64_t gtt_end;	341	__u64 gtt_end;
342	};	342	};
343		343
344	struct drm_i915_gem_create {	344	struct drm_i915_gem_create {
345	/**	345	/**
346	* Requested size for the object.	346	* Requested size for the object.
347	*	347	*
348	* The (page-aligned) allocated size for the object will be returned.	348	* The (page-aligned) allocated size for the object will be returned.
349	*/	349	*/
350	uint64_t size;	350	__u64 size;
351	/**	351	/**
352	* Returned handle for the object.	352	* Returned handle for the object.
353	*	353	*
354	* Object handles are nonzero.	354	* Object handles are nonzero.
355	*/	355	*/
356	uint32_t handle;	356	__u32 handle;
357	uint32_t pad;	357	__u32 pad;
358	};	358	};
359		359
360	struct drm_i915_gem_pread {	360	struct drm_i915_gem_pread {
361	/** Handle for the object being read. */	361	/** Handle for the object being read. */
362	uint32_t handle;	362	__u32 handle;
363	uint32_t pad;	363	__u32 pad;
364	/** Offset into the object to read from */	364	/** Offset into the object to read from */
365	uint64_t offset;	365	__u64 offset;
366	/** Length of data to read */	366	/** Length of data to read */
367	uint64_t size;	367	__u64 size;
368	/**	368	/**
369	* Pointer to write the data into.	369	* Pointer to write the data into.
370	*	370	*
371	* This is a fixed-size type for 32/64 compatibility.	371	* This is a fixed-size type for 32/64 compatibility.
372	*/	372	*/
373	uint64_t data_ptr;	373	__u64 data_ptr;
374	};	374	};
375		375
376	struct drm_i915_gem_pwrite {	376	struct drm_i915_gem_pwrite {
377	/** Handle for the object being written to. */	377	/** Handle for the object being written to. */
378	uint32_t handle;	378	__u32 handle;
379	uint32_t pad;	379	__u32 pad;
380	/** Offset into the object to write to */	380	/** Offset into the object to write to */
381	uint64_t offset;	381	__u64 offset;
382	/** Length of data to write */	382	/** Length of data to write */
383	uint64_t size;	383	__u64 size;
384	/**	384	/**
385	* Pointer to read the data from.	385	* Pointer to read the data from.
386	*	386	*
387	* This is a fixed-size type for 32/64 compatibility.	387	* This is a fixed-size type for 32/64 compatibility.
388	*/	388	*/
389	uint64_t data_ptr;	389	__u64 data_ptr;
390	};	390	};
391		391
392	struct drm_i915_gem_mmap {	392	struct drm_i915_gem_mmap {
393	/** Handle for the object being mapped. */	393	/** Handle for the object being mapped. */
394	uint32_t handle;	394	__u32 handle;
395	uint32_t pad;	395	__u32 pad;
396	/** Offset in the object to map. */	396	/** Offset in the object to map. */
397	uint64_t offset;	397	__u64 offset;
398	/**	398	/**
399	* Length of data to map.	399	* Length of data to map.
400	*	400	*
401	* The value will be page-aligned.	401	* The value will be page-aligned.
402	*/	402	*/
403	uint64_t size;	403	__u64 size;
404	/**	404	/**
405	* Returned pointer the data was mapped at.	405	* Returned pointer the data was mapped at.
406	*	406	*
407	* This is a fixed-size type for 32/64 compatibility.	407	* This is a fixed-size type for 32/64 compatibility.
408	*/	408	*/
409	uint64_t addr_ptr;	409	__u64 addr_ptr;
410	};	410	};
411		411
412	struct drm_i915_gem_mmap_gtt {	412	struct drm_i915_gem_mmap_gtt {
413	/** Handle for the object being mapped. */	413	/** Handle for the object being mapped. */
414	uint32_t handle;	414	__u32 handle;
415	uint32_t pad;	415	__u32 pad;
416	/**	416	/**
417	* Fake offset to use for subsequent mmap call	417	* Fake offset to use for subsequent mmap call
418	*	418	*
419	* This is a fixed-size type for 32/64 compatibility.	419	* This is a fixed-size type for 32/64 compatibility.
420	*/	420	*/
421	uint64_t offset;	421	__u64 offset;
422	};	422	};
423		423
424	struct drm_i915_gem_set_domain {	424	struct drm_i915_gem_set_domain {
425	/** Handle for the object */	425	/** Handle for the object */
426	uint32_t handle;	426	__u32 handle;
427		427
428	/** New read domains */	428	/** New read domains */
429	uint32_t read_domains;	429	__u32 read_domains;
430		430
431	/** New write domain */	431	/** New write domain */
432	uint32_t write_domain;	432	__u32 write_domain;
433	};	433	};
434		434
435	struct drm_i915_gem_sw_finish {	435	struct drm_i915_gem_sw_finish {
436	/** Handle for the object */	436	/** Handle for the object */
437	uint32_t handle;	437	__u32 handle;
438	};	438	};
439		439
440	struct drm_i915_gem_relocation_entry {	440	struct drm_i915_gem_relocation_entry {
441	/**	441	/**
442	* Handle of the buffer being pointed to by this relocation entry.	442	* Handle of the buffer being pointed to by this relocation entry.
443	*	443	*
444	* It's appealing to make this be an index into the mm_validate_entry	444	* It's appealing to make this be an index into the mm_validate_entry
445	* list to refer to the buffer, but this allows the driver to create	445	* list to refer to the buffer, but this allows the driver to create
446	* a relocation list for state buffers and not re-write it per	446	* a relocation list for state buffers and not re-write it per
447	* exec using the buffer.	447	* exec using the buffer.
448	*/	448	*/
449	uint32_t target_handle;	449	__u32 target_handle;
450		450
451	/**	451	/**
452	* Value to be added to the offset of the target buffer to make up	452	* Value to be added to the offset of the target buffer to make up
453	* the relocation entry.	453	* the relocation entry.
454	*/	454	*/
455	uint32_t delta;	455	__u32 delta;
456		456
457	/** Offset in the buffer the relocation entry will be written into */	457	/** Offset in the buffer the relocation entry will be written into */
458	uint64_t offset;	458	__u64 offset;
459		459
460	/**	460	/**
461	* Offset value of the target buffer that the relocation entry was last	461	* Offset value of the target buffer that the relocation entry was last
462	* written as.	462	* written as.
463	*	463	*
464	* If the buffer has the same offset as last time, we can skip syncing	464	* If the buffer has the same offset as last time, we can skip syncing
465	* and writing the relocation. This value is written back out by	465	* and writing the relocation. This value is written back out by
466	* the execbuffer ioctl when the relocation is written.	466	* the execbuffer ioctl when the relocation is written.
467	*/	467	*/
468	uint64_t presumed_offset;	468	__u64 presumed_offset;
469		469
470	/**	470	/**
471	* Target memory domains read by this operation.	471	* Target memory domains read by this operation.
472	*/	472	*/
473	uint32_t read_domains;	473	__u32 read_domains;
474		474
475	/**	475	/**
476	* Target memory domains written by this operation.	476	* Target memory domains written by this operation.
477	*	477	*
478	* Note that only one domain may be written by the whole	478	* Note that only one domain may be written by the whole
479	* execbuffer operation, so that where there are conflicts,	479	* execbuffer operation, so that where there are conflicts,
480	* the application will get -EINVAL back.	480	* the application will get -EINVAL back.
481	*/	481	*/
482	uint32_t write_domain;	482	__u32 write_domain;
483	};	483	};
484		484
485	/** @{	485	/** @{
486	* Intel memory domains	486	* Intel memory domains
487	*	487	*
488	* Most of these just align with the various caches in	488	* Most of these just align with the various caches in
489	* the system and are used to flush and invalidate as	489	* the system and are used to flush and invalidate as
490	* objects end up cached in different domains.	490	* objects end up cached in different domains.
491	*/	491	*/
492	/** CPU cache */	492	/** CPU cache */
493	#define I915_GEM_DOMAIN_CPU 0x00000001	493	#define I915_GEM_DOMAIN_CPU 0x00000001
494	/** Render cache, used by 2D and 3D drawing */	494	/** Render cache, used by 2D and 3D drawing */
495	#define I915_GEM_DOMAIN_RENDER 0x00000002	495	#define I915_GEM_DOMAIN_RENDER 0x00000002
496	/** Sampler cache, used by texture engine */	496	/** Sampler cache, used by texture engine */
497	#define I915_GEM_DOMAIN_SAMPLER 0x00000004	497	#define I915_GEM_DOMAIN_SAMPLER 0x00000004
498	/** Command queue, used to load batch buffers */	498	/** Command queue, used to load batch buffers */
499	#define I915_GEM_DOMAIN_COMMAND 0x00000008	499	#define I915_GEM_DOMAIN_COMMAND 0x00000008
500	/** Instruction cache, used by shader programs */	500	/** Instruction cache, used by shader programs */
501	#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010	501	#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
502	/** Vertex address cache */	502	/** Vertex address cache */
503	#define I915_GEM_DOMAIN_VERTEX 0x00000020	503	#define I915_GEM_DOMAIN_VERTEX 0x00000020
504	/** GTT domain - aperture and scanout */	504	/** GTT domain - aperture and scanout */
505	#define I915_GEM_DOMAIN_GTT 0x00000040	505	#define I915_GEM_DOMAIN_GTT 0x00000040
506	/** @} */	506	/** @} */
507		507
508	struct drm_i915_gem_exec_object {	508	struct drm_i915_gem_exec_object {
509	/**	509	/**
510	* User's handle for a buffer to be bound into the GTT for this	510	* User's handle for a buffer to be bound into the GTT for this
511	* operation.	511	* operation.
512	*/	512	*/
513	uint32_t handle;	513	__u32 handle;
514		514
515	/** Number of relocations to be performed on this buffer */	515	/** Number of relocations to be performed on this buffer */
516	uint32_t relocation_count;	516	__u32 relocation_count;
517	/**	517	/**
518	* Pointer to array of struct drm_i915_gem_relocation_entry containing	518	* Pointer to array of struct drm_i915_gem_relocation_entry containing
519	* the relocations to be performed in this buffer.	519	* the relocations to be performed in this buffer.
520	*/	520	*/
521	uint64_t relocs_ptr;	521	__u64 relocs_ptr;
522		522
523	/** Required alignment in graphics aperture */	523	/** Required alignment in graphics aperture */
524	uint64_t alignment;	524	__u64 alignment;
525		525
526	/**	526	/**
527	* Returned value of the updated offset of the object, for future	527	* Returned value of the updated offset of the object, for future
528	* presumed_offset writes.	528	* presumed_offset writes.
529	*/	529	*/
530	uint64_t offset;	530	__u64 offset;
531	};	531	};
532		532
533	struct drm_i915_gem_execbuffer {	533	struct drm_i915_gem_execbuffer {
534	/**	534	/**
535	* List of buffers to be validated with their relocations to be	535	* List of buffers to be validated with their relocations to be
536	* performend on them.	536	* performend on them.
537	*	537	*
538	* This is a pointer to an array of struct drm_i915_gem_validate_entry.	538	* This is a pointer to an array of struct drm_i915_gem_validate_entry.
539	*	539	*
540	* These buffers must be listed in an order such that all relocations	540	* These buffers must be listed in an order such that all relocations
541	* a buffer is performing refer to buffers that have already appeared	541	* a buffer is performing refer to buffers that have already appeared
542	* in the validate list.	542	* in the validate list.
543	*/	543	*/
544	uint64_t buffers_ptr;	544	__u64 buffers_ptr;
545	uint32_t buffer_count;	545	__u32 buffer_count;
546		546
547	/** Offset in the batchbuffer to start execution from. */	547	/** Offset in the batchbuffer to start execution from. */
548	uint32_t batch_start_offset;	548	__u32 batch_start_offset;
549	/** Bytes used in batchbuffer from batch_start_offset */	549	/** Bytes used in batchbuffer from batch_start_offset */
550	uint32_t batch_len;	550	__u32 batch_len;
551	uint32_t DR1;	551	__u32 DR1;
552	uint32_t DR4;	552	__u32 DR4;
553	uint32_t num_cliprects;	553	__u32 num_cliprects;
554	/** This is a struct drm_clip_rect cliprects /	554	/** This is a struct drm_clip_rect cliprects /
555	uint64_t cliprects_ptr;	555	__u64 cliprects_ptr;
556	};	556	};
557		557
558	struct drm_i915_gem_pin {	558	struct drm_i915_gem_pin {
559	/** Handle of the buffer to be pinned. */	559	/** Handle of the buffer to be pinned. */
560	uint32_t handle;	560	__u32 handle;
561	uint32_t pad;	561	__u32 pad;
562		562
563	/** alignment required within the aperture */	563	/** alignment required within the aperture */
564	uint64_t alignment;	564	__u64 alignment;
565		565
566	/** Returned GTT offset of the buffer. */	566	/** Returned GTT offset of the buffer. */
567	uint64_t offset;	567	__u64 offset;
568	};	568	};
569		569
570	struct drm_i915_gem_unpin {	570	struct drm_i915_gem_unpin {
571	/** Handle of the buffer to be unpinned. */	571	/** Handle of the buffer to be unpinned. */
572	uint32_t handle;	572	__u32 handle;
573	uint32_t pad;	573	__u32 pad;
574	};	574	};
575		575
576	struct drm_i915_gem_busy {	576	struct drm_i915_gem_busy {
577	/** Handle of the buffer to check for busy */	577	/** Handle of the buffer to check for busy */
578	uint32_t handle;	578	__u32 handle;
579		579
580	/** Return busy status (1 if busy, 0 if idle) */	580	/** Return busy status (1 if busy, 0 if idle) */
581	uint32_t busy;	581	__u32 busy;
582	};	582	};
583		583
584	#define I915_TILING_NONE 0	584	#define I915_TILING_NONE 0
585	#define I915_TILING_X 1	585	#define I915_TILING_X 1
586	#define I915_TILING_Y 2	586	#define I915_TILING_Y 2
587		587
588	#define I915_BIT_6_SWIZZLE_NONE 0	588	#define I915_BIT_6_SWIZZLE_NONE 0
589	#define I915_BIT_6_SWIZZLE_9 1	589	#define I915_BIT_6_SWIZZLE_9 1
590	#define I915_BIT_6_SWIZZLE_9_10 2	590	#define I915_BIT_6_SWIZZLE_9_10 2
591	#define I915_BIT_6_SWIZZLE_9_11 3	591	#define I915_BIT_6_SWIZZLE_9_11 3
592	#define I915_BIT_6_SWIZZLE_9_10_11 4	592	#define I915_BIT_6_SWIZZLE_9_10_11 4
593	/* Not seen by userland */	593	/* Not seen by userland */
594	#define I915_BIT_6_SWIZZLE_UNKNOWN 5	594	#define I915_BIT_6_SWIZZLE_UNKNOWN 5
595		595
596	struct drm_i915_gem_set_tiling {	596	struct drm_i915_gem_set_tiling {
597	/** Handle of the buffer to have its tiling state updated */	597	/** Handle of the buffer to have its tiling state updated */
598	uint32_t handle;	598	__u32 handle;
599		599
600	/**	600	/**
601	* Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,	601	* Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
602	* I915_TILING_Y).	602	* I915_TILING_Y).
603	*	603	*
604	* This value is to be set on request, and will be updated by the	604	* This value is to be set on request, and will be updated by the
605	* kernel on successful return with the actual chosen tiling layout.	605	* kernel on successful return with the actual chosen tiling layout.
606	*	606	*
607	* The tiling mode may be demoted to I915_TILING_NONE when the system	607	* The tiling mode may be demoted to I915_TILING_NONE when the system
608	* has bit 6 swizzling that can't be managed correctly by GEM.	608	* has bit 6 swizzling that can't be managed correctly by GEM.
609	*	609	*
610	* Buffer contents become undefined when changing tiling_mode.	610	* Buffer contents become undefined when changing tiling_mode.
611	*/	611	*/
612	uint32_t tiling_mode;	612	__u32 tiling_mode;
613		613
614	/**	614	/**
615	* Stride in bytes for the object when in I915_TILING_X or	615	* Stride in bytes for the object when in I915_TILING_X or
616	* I915_TILING_Y.	616	* I915_TILING_Y.
617	*/	617	*/
618	uint32_t stride;	618	__u32 stride;
619		619
620	/**	620	/**
621	* Returned address bit 6 swizzling required for CPU access through	621	* Returned address bit 6 swizzling required for CPU access through
622	* mmap mapping.	622	* mmap mapping.
623	*/	623	*/
624	uint32_t swizzle_mode;	624	__u32 swizzle_mode;
625	};	625	};
626		626
627	struct drm_i915_gem_get_tiling {	627	struct drm_i915_gem_get_tiling {
628	/** Handle of the buffer to get tiling state for. */	628	/** Handle of the buffer to get tiling state for. */
629	uint32_t handle;	629	__u32 handle;
630		630
631	/**	631	/**
632	* Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,	632	* Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
633	* I915_TILING_Y).	633	* I915_TILING_Y).
634	*/	634	*/
635	uint32_t tiling_mode;	635	__u32 tiling_mode;
636		636
637	/**	637	/**
638	* Returned address bit 6 swizzling required for CPU access through	638	* Returned address bit 6 swizzling required for CPU access through
639	* mmap mapping.	639	* mmap mapping.
640	*/	640	*/
641	uint32_t swizzle_mode;	641	__u32 swizzle_mode;
642	};	642	};
643		643
644	struct drm_i915_gem_get_aperture {	644	struct drm_i915_gem_get_aperture {
645	/** Total size of the aperture used by i915_gem_execbuffer, in bytes */	645	/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
646	uint64_t aper_size;	646	__u64 aper_size;
647		647
648	/**	648	/**
649	* Available space in the aperture used by i915_gem_execbuffer, in	649	* Available space in the aperture used by i915_gem_execbuffer, in
650	* bytes	650	* bytes
651	*/	651	*/
652	uint64_t aper_available_size;	652	__u64 aper_available_size;
653	};	653	};
654		654
655	#endif /* _I915_DRM_H_ */	655	#endif /* _I915_DRM_H_ */
656		656

include/drm/mga_drm.h

Diff comments View file @ 1d7f83d

 /* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
  * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
  *
  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors:
  *    Jeff Hartmann <jhartmann@valinux.com>
  *    Keith Whitwell <keith@tungstengraphics.com>
  *
  * Rewritten by:
  *    Gareth Hughes <gareth@valinux.com>
  */
 #ifndef __MGA_DRM_H__
 #define __MGA_DRM_H__
+#include <linux/types.h>
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (mga_sarea.h)
  */
 #ifndef __MGA_SAREA_DEFINES__
 #define __MGA_SAREA_DEFINES__
 /* WARP pipe flags
  */
 #define MGA_F			0x1	/* fog */
 #define MGA_A			0x2	/* alpha */
 #define MGA_S			0x4	/* specular */
 #define MGA_T2			0x8	/* multitexture */
 #define MGA_WARP_TGZ		0
 #define MGA_WARP_TGZF		(MGA_F)
 #define MGA_WARP_TGZA		(MGA_A)
 #define MGA_WARP_TGZAF		(MGA_F|MGA_A)
 #define MGA_WARP_TGZS		(MGA_S)
 #define MGA_WARP_TGZSF		(MGA_S|MGA_F)
 #define MGA_WARP_TGZSA		(MGA_S|MGA_A)
 #define MGA_WARP_TGZSAF		(MGA_S|MGA_F|MGA_A)
 #define MGA_WARP_T2GZ		(MGA_T2)
 #define MGA_WARP_T2GZF		(MGA_T2|MGA_F)
 #define MGA_WARP_T2GZA		(MGA_T2|MGA_A)
 #define MGA_WARP_T2GZAF		(MGA_T2|MGA_A|MGA_F)
 #define MGA_WARP_T2GZS		(MGA_T2|MGA_S)
 #define MGA_WARP_T2GZSF		(MGA_T2|MGA_S|MGA_F)
 #define MGA_WARP_T2GZSA		(MGA_T2|MGA_S|MGA_A)
 #define MGA_WARP_T2GZSAF	(MGA_T2|MGA_S|MGA_F|MGA_A)
 #define MGA_MAX_G200_PIPES	8	/* no multitex */
 #define MGA_MAX_G400_PIPES	16
 #define MGA_MAX_WARP_PIPES	MGA_MAX_G400_PIPES
 #define MGA_WARP_UCODE_SIZE	32768	/* in bytes */
 #define MGA_CARD_TYPE_G200	1
 #define MGA_CARD_TYPE_G400	2
 #define MGA_CARD_TYPE_G450	3	/* not currently used */
 #define MGA_CARD_TYPE_G550	4
 #define MGA_FRONT		0x1
 #define MGA_BACK		0x2
 #define MGA_DEPTH		0x4
 /* What needs to be changed for the current vertex dma buffer?
  */
 #define MGA_UPLOAD_CONTEXT	0x1
 #define MGA_UPLOAD_TEX0		0x2
 #define MGA_UPLOAD_TEX1		0x4
 #define MGA_UPLOAD_PIPE		0x8
 #define MGA_UPLOAD_TEX0IMAGE	0x10	/* handled client-side */
 #define MGA_UPLOAD_TEX1IMAGE	0x20	/* handled client-side */
 #define MGA_UPLOAD_2D		0x40
 #define MGA_WAIT_AGE		0x80	/* handled client-side */
 #define MGA_UPLOAD_CLIPRECTS	0x100	/* handled client-side */
 #if 0
 #define MGA_DMA_FLUSH		0x200	/* set when someone gets the lock
 					   quiescent */
 #endif
 /* 32 buffers of 64k each, total 2 meg.
  */
 #define MGA_BUFFER_SIZE		(1 << 16)
 #define MGA_NUM_BUFFERS		128
 /* Keep these small for testing.
  */
 #define MGA_NR_SAREA_CLIPRECTS	8
 /* 2 heaps (1 for card, 1 for agp), each divided into upto 128
  * regions, subject to a minimum region size of (1<<16) == 64k.
  *
  * Clients may subdivide regions internally, but when sharing between
  * clients, the region size is the minimum granularity.
  */
 #define MGA_CARD_HEAP			0
 #define MGA_AGP_HEAP			1
 #define MGA_NR_TEX_HEAPS		2
 #define MGA_NR_TEX_REGIONS		16
 #define MGA_LOG_MIN_TEX_REGION_SIZE	16
 #define  DRM_MGA_IDLE_RETRY          2048
 #endif				/* __MGA_SAREA_DEFINES__ */
 /* Setup registers for 3D context
  */
 typedef struct {
 	unsigned int dstorg;
 	unsigned int maccess;
 	unsigned int plnwt;
 	unsigned int dwgctl;
 	unsigned int alphactrl;
 	unsigned int fogcolor;
 	unsigned int wflag;
 	unsigned int tdualstage0;
 	unsigned int tdualstage1;
 	unsigned int fcol;
 	unsigned int stencil;
 	unsigned int stencilctl;
 } drm_mga_context_regs_t;
 /* Setup registers for 2D, X server
  */
 typedef struct {
 	unsigned int pitch;
 } drm_mga_server_regs_t;
 /* Setup registers for each texture unit
  */
 typedef struct {
 	unsigned int texctl;
 	unsigned int texctl2;
 	unsigned int texfilter;
 	unsigned int texbordercol;
 	unsigned int texorg;
 	unsigned int texwidth;
 	unsigned int texheight;
 	unsigned int texorg1;
 	unsigned int texorg2;
 	unsigned int texorg3;
 	unsigned int texorg4;
 } drm_mga_texture_regs_t;
 /* General aging mechanism
  */
 typedef struct {
 	unsigned int head;	/* Position of head pointer          */
 	unsigned int wrap;	/* Primary DMA wrap count            */
 } drm_mga_age_t;
 typedef struct _drm_mga_sarea {
 	/* The channel for communication of state information to the kernel
 	 * on firing a vertex dma buffer.
 	 */
 	drm_mga_context_regs_t context_state;
 	drm_mga_server_regs_t server_state;
 	drm_mga_texture_regs_t tex_state[2];
 	unsigned int warp_pipe;
 	unsigned int dirty;
 	unsigned int vertsize;
 	/* The current cliprects, or a subset thereof.
 	 */
 	struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
 	unsigned int nbox;
 	/* Information about the most recently used 3d drawable.  The
 	 * client fills in the req_* fields, the server fills in the
 	 * exported_ fields and puts the cliprects into boxes, above.
 	 *
 	 * The client clears the exported_drawable field before
 	 * clobbering the boxes data.
 	 */
 	unsigned int req_drawable;	/* the X drawable id */
 	unsigned int req_draw_buffer;	/* MGA_FRONT or MGA_BACK */
 	unsigned int exported_drawable;
 	unsigned int exported_index;
 	unsigned int exported_stamp;
 	unsigned int exported_buffers;
 	unsigned int exported_nfront;
 	unsigned int exported_nback;
 	int exported_back_x, exported_front_x, exported_w;
 	int exported_back_y, exported_front_y, exported_h;
 	struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
 	/* Counters for aging textures and for client-side throttling.
 	 */
 	unsigned int status[4];
 	unsigned int last_wrap;
 	drm_mga_age_t last_frame;
 	unsigned int last_enqueue;	/* last time a buffer was enqueued */
 	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
 	unsigned int last_quiescent;	/*  */
 	/* LRU lists for texture memory in agp space and on the card.
 	 */
 	struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
 	unsigned int texAge[MGA_NR_TEX_HEAPS];
 	/* Mechanism to validate card state.
 	 */
 	int ctxOwner;
 } drm_mga_sarea_t;
 /* MGA specific ioctls
  * The device specific ioctl range is 0x40 to 0x79.
  */
 #define DRM_MGA_INIT     0x00
 #define DRM_MGA_FLUSH    0x01
 #define DRM_MGA_RESET    0x02
 #define DRM_MGA_SWAP     0x03
 #define DRM_MGA_CLEAR    0x04
 #define DRM_MGA_VERTEX   0x05
 #define DRM_MGA_INDICES  0x06
 #define DRM_MGA_ILOAD    0x07
 #define DRM_MGA_BLIT     0x08
 #define DRM_MGA_GETPARAM 0x09
 /* 3.2:
  * ioctls for operating on fences.
  */
 #define DRM_MGA_SET_FENCE      0x0a
 #define DRM_MGA_WAIT_FENCE     0x0b
 #define DRM_MGA_DMA_BOOTSTRAP  0x0c
 #define DRM_IOCTL_MGA_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
 #define DRM_IOCTL_MGA_FLUSH    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
 #define DRM_IOCTL_MGA_RESET    DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_RESET)
 #define DRM_IOCTL_MGA_SWAP     DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_SWAP)
 #define DRM_IOCTL_MGA_CLEAR    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
 #define DRM_IOCTL_MGA_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
 #define DRM_IOCTL_MGA_INDICES  DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
 #define DRM_IOCTL_MGA_ILOAD    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
 #define DRM_IOCTL_MGA_BLIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
 #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
-#define DRM_IOCTL_MGA_SET_FENCE     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
+#define DRM_IOCTL_MGA_SET_FENCE     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
-#define DRM_IOCTL_MGA_WAIT_FENCE    DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
+#define DRM_IOCTL_MGA_WAIT_FENCE    DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
 #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
 typedef struct _drm_mga_warp_index {
 	int installed;
 	unsigned long phys_addr;
 	int size;
 } drm_mga_warp_index_t;
 typedef struct drm_mga_init {
 	enum {
 		MGA_INIT_DMA = 0x01,
 		MGA_CLEANUP_DMA = 0x02
 	} func;
 	unsigned long sarea_priv_offset;
 	int chipset;
 	int sgram;
 	unsigned int maccess;
 	unsigned int fb_cpp;
 	unsigned int front_offset, front_pitch;
 	unsigned int back_offset, back_pitch;
 	unsigned int depth_cpp;
 	unsigned int depth_offset, depth_pitch;
 	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
 	unsigned int texture_size[MGA_NR_TEX_HEAPS];
 	unsigned long fb_offset;
 	unsigned long mmio_offset;
 	unsigned long status_offset;
 	unsigned long warp_offset;
 	unsigned long primary_offset;
 	unsigned long buffers_offset;
 } drm_mga_init_t;
 typedef struct drm_mga_dma_bootstrap {
 	/**
 	 * \name AGP texture region
 	 *
 	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
 	 * be filled in with the actual AGP texture settings.
 	 *
 	 * \warning
 	 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
 	 * is zero, it means that PCI memory (most likely through the use of
 	 * an IOMMU) is being used for "AGP" textures.
 	 */
 	/*@{ */
 	unsigned long texture_handle; /**< Handle used to map AGP textures. */
-	uint32_t texture_size;	      /**< Size of the AGP texture region. */
+	__u32 texture_size;	      /**< Size of the AGP texture region. */
 	/*@} */
 	/**
 	 * Requested size of the primary DMA region.
 	 *
 	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
 	 * filled in with the actual AGP mode.  If AGP was not available
 	 */
-	uint32_t primary_size;
+	__u32 primary_size;
 	/**
 	 * Requested number of secondary DMA buffers.
 	 *
 	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
 	 * filled in with the actual number of secondary DMA buffers
 	 * allocated.  Particularly when PCI DMA is used, this may be
 	 * (subtantially) less than the number requested.
 	 */
-	uint32_t secondary_bin_count;
+	__u32 secondary_bin_count;
 	/**
 	 * Requested size of each secondary DMA buffer.
 	 *
 	 * While the kernel \b is free to reduce
 	 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
 	 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
 	 */
-	uint32_t secondary_bin_size;
+	__u32 secondary_bin_size;
 	/**
 	 * Bit-wise mask of AGPSTAT2_* values.  Currently only \c AGPSTAT2_1X,
 	 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported.  If this value is
 	 * zero, it means that PCI DMA should be used, even if AGP is
 	 * possible.
 	 *
 	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
 	 * filled in with the actual AGP mode.  If AGP was not available
 	 * (i.e., PCI DMA was used), this value will be zero.
 	 */
-	uint32_t agp_mode;
+	__u32 agp_mode;
 	/**
 	 * Desired AGP GART size, measured in megabytes.
 	 */
-	uint8_t agp_size;
+	__u8 agp_size;
 } drm_mga_dma_bootstrap_t;
 typedef struct drm_mga_clear {
 	unsigned int flags;
 	unsigned int clear_color;
 	unsigned int clear_depth;
 	unsigned int color_mask;
 	unsigned int depth_mask;
 } drm_mga_clear_t;
 typedef struct drm_mga_vertex {
 	int idx;		/* buffer to queue */
 	int used;		/* bytes in use */
 	int discard;		/* client finished with buffer?  */
 } drm_mga_vertex_t;
 typedef struct drm_mga_indices {
 	int idx;		/* buffer to queue */
 	unsigned int start;
 	unsigned int end;
 	int discard;		/* client finished with buffer?  */
 } drm_mga_indices_t;
 typedef struct drm_mga_iload {
 	int idx;
 	unsigned int dstorg;
 	unsigned int length;
 } drm_mga_iload_t;
 typedef struct _drm_mga_blit {
 	unsigned int planemask;
 	unsigned int srcorg;
 	unsigned int dstorg;
 	int src_pitch, dst_pitch;
 	int delta_sx, delta_sy;
 	int delta_dx, delta_dy;
 	int height, ydir;	/* flip image vertically */
 	int source_pitch, dest_pitch;
 } drm_mga_blit_t;
 /* 3.1: An ioctl to get parameters that aren't available to the 3d
  * client any other way.
  */
 #define MGA_PARAM_IRQ_NR            1
 /* 3.2: Query the actual card type.  The DDX only distinguishes between
  * G200 chips and non-G200 chips, which it calls G400.  It turns out that
  * there are some very sublte differences between the G4x0 chips and the G550
  * chips.  Using this parameter query, a client-side driver can detect the
  * difference between a G4x0 and a G550.
  */
 #define MGA_PARAM_CARD_TYPE         2
 typedef struct drm_mga_getparam {
 	int param;
 	void __user *value;
 } drm_mga_getparam_t;
 #endif

include/drm/radeon_drm.h

Diff comments View file @ 1d7f83d

 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
  *
  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  *
  * Authors:
  *    Kevin E. Martin <martin@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *    Keith Whitwell <keith@tungstengraphics.com>
  */
 #ifndef __RADEON_DRM_H__
 #define __RADEON_DRM_H__
+#include <linux/types.h>
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the X server file (radeon_sarea.h)
  */
 #ifndef __RADEON_SAREA_DEFINES__
 #define __RADEON_SAREA_DEFINES__
 /* Old style state flags, required for sarea interface (1.1 and 1.2
  * clears) and 1.2 drm_vertex2 ioctl.
  */
 #define RADEON_UPLOAD_CONTEXT		0x00000001
 #define RADEON_UPLOAD_VERTFMT		0x00000002
 #define RADEON_UPLOAD_LINE		0x00000004
 #define RADEON_UPLOAD_BUMPMAP		0x00000008
 #define RADEON_UPLOAD_MASKS		0x00000010
 #define RADEON_UPLOAD_VIEWPORT		0x00000020
 #define RADEON_UPLOAD_SETUP		0x00000040
 #define RADEON_UPLOAD_TCL		0x00000080
 #define RADEON_UPLOAD_MISC		0x00000100
 #define RADEON_UPLOAD_TEX0		0x00000200
 #define RADEON_UPLOAD_TEX1		0x00000400
 #define RADEON_UPLOAD_TEX2		0x00000800
 #define RADEON_UPLOAD_TEX0IMAGES	0x00001000
 #define RADEON_UPLOAD_TEX1IMAGES	0x00002000
 #define RADEON_UPLOAD_TEX2IMAGES	0x00004000
 #define RADEON_UPLOAD_CLIPRECTS		0x00008000	/* handled client-side */
 #define RADEON_REQUIRE_QUIESCENCE	0x00010000
 #define RADEON_UPLOAD_ZBIAS		0x00020000	/* version 1.2 and newer */
 #define RADEON_UPLOAD_ALL		0x003effff
 #define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
 /* New style per-packet identifiers for use in cmd_buffer ioctl with
  * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
  * state bits and the packet size:
  */
 #define RADEON_EMIT_PP_MISC                         0	/* context/7 */
 #define RADEON_EMIT_PP_CNTL                         1	/* context/3 */
 #define RADEON_EMIT_RB3D_COLORPITCH                 2	/* context/1 */
 #define RADEON_EMIT_RE_LINE_PATTERN                 3	/* line/2 */
 #define RADEON_EMIT_SE_LINE_WIDTH                   4	/* line/1 */
 #define RADEON_EMIT_PP_LUM_MATRIX                   5	/* bumpmap/1 */
 #define RADEON_EMIT_PP_ROT_MATRIX_0                 6	/* bumpmap/2 */
 #define RADEON_EMIT_RB3D_STENCILREFMASK             7	/* masks/3 */
 #define RADEON_EMIT_SE_VPORT_XSCALE                 8	/* viewport/6 */
 #define RADEON_EMIT_SE_CNTL                         9	/* setup/2 */
 #define RADEON_EMIT_SE_CNTL_STATUS                  10	/* setup/1 */
 #define RADEON_EMIT_RE_MISC                         11	/* misc/1 */
 #define RADEON_EMIT_PP_TXFILTER_0                   12	/* tex0/6 */
 #define RADEON_EMIT_PP_BORDER_COLOR_0               13	/* tex0/1 */
 #define RADEON_EMIT_PP_TXFILTER_1                   14	/* tex1/6 */
 #define RADEON_EMIT_PP_BORDER_COLOR_1               15	/* tex1/1 */
 #define RADEON_EMIT_PP_TXFILTER_2                   16	/* tex2/6 */
 #define RADEON_EMIT_PP_BORDER_COLOR_2               17	/* tex2/1 */
 #define RADEON_EMIT_SE_ZBIAS_FACTOR                 18	/* zbias/2 */
 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19	/* tcl/11 */
 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20	/* material/17 */
 #define R200_EMIT_PP_TXCBLEND_0                     21	/* tex0/4 */
 #define R200_EMIT_PP_TXCBLEND_1                     22	/* tex1/4 */
 #define R200_EMIT_PP_TXCBLEND_2                     23	/* tex2/4 */
 #define R200_EMIT_PP_TXCBLEND_3                     24	/* tex3/4 */
 #define R200_EMIT_PP_TXCBLEND_4                     25	/* tex4/4 */
 #define R200_EMIT_PP_TXCBLEND_5                     26	/* tex5/4 */
 #define R200_EMIT_PP_TXCBLEND_6                     27	/* /4 */
 #define R200_EMIT_PP_TXCBLEND_7                     28	/* /4 */
 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29	/* tcl/7 */
 #define R200_EMIT_TFACTOR_0                         30	/* tf/7 */
 #define R200_EMIT_VTX_FMT_0                         31	/* vtx/5 */
 #define R200_EMIT_VAP_CTL                           32	/* vap/1 */
 #define R200_EMIT_MATRIX_SELECT_0                   33	/* msl/5 */
 #define R200_EMIT_TEX_PROC_CTL_2                    34	/* tcg/5 */
 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35	/* tcl/1 */
 #define R200_EMIT_PP_TXFILTER_0                     36	/* tex0/6 */
 #define R200_EMIT_PP_TXFILTER_1                     37	/* tex1/6 */
 #define R200_EMIT_PP_TXFILTER_2                     38	/* tex2/6 */
 #define R200_EMIT_PP_TXFILTER_3                     39	/* tex3/6 */
 #define R200_EMIT_PP_TXFILTER_4                     40	/* tex4/6 */
 #define R200_EMIT_PP_TXFILTER_5                     41	/* tex5/6 */
 #define R200_EMIT_PP_TXOFFSET_0                     42	/* tex0/1 */
 #define R200_EMIT_PP_TXOFFSET_1                     43	/* tex1/1 */
 #define R200_EMIT_PP_TXOFFSET_2                     44	/* tex2/1 */
 #define R200_EMIT_PP_TXOFFSET_3                     45	/* tex3/1 */
 #define R200_EMIT_PP_TXOFFSET_4                     46	/* tex4/1 */
 #define R200_EMIT_PP_TXOFFSET_5                     47	/* tex5/1 */
 #define R200_EMIT_VTE_CNTL                          48	/* vte/1 */
 #define R200_EMIT_OUTPUT_VTX_COMP_SEL               49	/* vtx/1 */
 #define R200_EMIT_PP_TAM_DEBUG3                     50	/* tam/1 */
 #define R200_EMIT_PP_CNTL_X                         51	/* cst/1 */
 #define R200_EMIT_RB3D_DEPTHXY_OFFSET               52	/* cst/1 */
 #define R200_EMIT_RE_AUX_SCISSOR_CNTL               53	/* cst/1 */
 #define R200_EMIT_RE_SCISSOR_TL_0                   54	/* cst/2 */
 #define R200_EMIT_RE_SCISSOR_TL_1                   55	/* cst/2 */
 #define R200_EMIT_RE_SCISSOR_TL_2                   56	/* cst/2 */
 #define R200_EMIT_SE_VAP_CNTL_STATUS                57	/* cst/1 */
 #define R200_EMIT_SE_VTX_STATE_CNTL                 58	/* cst/1 */
 #define R200_EMIT_RE_POINTSIZE                      59	/* cst/1 */
 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60	/* cst/4 */
 #define R200_EMIT_PP_CUBIC_FACES_0                  61
 #define R200_EMIT_PP_CUBIC_OFFSETS_0                62
 #define R200_EMIT_PP_CUBIC_FACES_1                  63
 #define R200_EMIT_PP_CUBIC_OFFSETS_1                64
 #define R200_EMIT_PP_CUBIC_FACES_2                  65
 #define R200_EMIT_PP_CUBIC_OFFSETS_2                66
 #define R200_EMIT_PP_CUBIC_FACES_3                  67
 #define R200_EMIT_PP_CUBIC_OFFSETS_3                68
 #define R200_EMIT_PP_CUBIC_FACES_4                  69
 #define R200_EMIT_PP_CUBIC_OFFSETS_4                70
 #define R200_EMIT_PP_CUBIC_FACES_5                  71
 #define R200_EMIT_PP_CUBIC_OFFSETS_5                72
 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
 #define R200_EMIT_RB3D_BLENDCOLOR                   76
 #define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
 #define RADEON_EMIT_PP_CUBIC_FACES_0                78
 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
 #define RADEON_EMIT_PP_CUBIC_FACES_1                80
 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
 #define RADEON_EMIT_PP_CUBIC_FACES_2                82
 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
 #define R200_EMIT_PP_TRI_PERF_CNTL                  84
 #define R200_EMIT_PP_AFS_0                          85
 #define R200_EMIT_PP_AFS_1                          86
 #define R200_EMIT_ATF_TFACTOR                       87
 #define R200_EMIT_PP_TXCTLALL_0                     88
 #define R200_EMIT_PP_TXCTLALL_1                     89
 #define R200_EMIT_PP_TXCTLALL_2                     90
 #define R200_EMIT_PP_TXCTLALL_3                     91
 #define R200_EMIT_PP_TXCTLALL_4                     92
 #define R200_EMIT_PP_TXCTLALL_5                     93
 #define R200_EMIT_VAP_PVS_CNTL                      94
 #define RADEON_MAX_STATE_PACKETS                    95
 /* Commands understood by cmd_buffer ioctl.  More can be added but
  * obviously these can't be removed or changed:
  */
 #define RADEON_CMD_PACKET      1	/* emit one of the register packets above */
 #define RADEON_CMD_SCALARS     2	/* emit scalar data */
 #define RADEON_CMD_VECTORS     3	/* emit vector data */
 #define RADEON_CMD_DMA_DISCARD 4	/* discard current dma buf */
 #define RADEON_CMD_PACKET3     5	/* emit hw packet */
 #define RADEON_CMD_PACKET3_CLIP 6	/* emit hw packet wrapped in cliprects */
 #define RADEON_CMD_SCALARS2     7	/* r200 stopgap */
 #define RADEON_CMD_WAIT         8	/* emit hw wait commands -- note:
 					 *  doesn't make the cpu wait, just
 					 *  the graphics hardware */
 #define RADEON_CMD_VECLINEAR	9       /* another r200 stopgap */
 typedef union {
 	int i;
 	struct {
 		unsigned char cmd_type, pad0, pad1, pad2;
 	} header;
 	struct {
 		unsigned char cmd_type, packet_id, pad0, pad1;
 	} packet;
 	struct {
 		unsigned char cmd_type, offset, stride, count;
 	} scalars;
 	struct {
 		unsigned char cmd_type, offset, stride, count;
 	} vectors;
 	struct {
 		unsigned char cmd_type, addr_lo, addr_hi, count;
 	} veclinear;
 	struct {
 		unsigned char cmd_type, buf_idx, pad0, pad1;
 	} dma;
 	struct {
 		unsigned char cmd_type, flags, pad0, pad1;
 	} wait;
 } drm_radeon_cmd_header_t;
 #define RADEON_WAIT_2D  0x1
 #define RADEON_WAIT_3D  0x2
 /* Allowed parameters for R300_CMD_PACKET3
  */
 #define R300_CMD_PACKET3_CLEAR		0
 #define R300_CMD_PACKET3_RAW		1
 /* Commands understood by cmd_buffer ioctl for R300.
  * The interface has not been stabilized, so some of these may be removed
  * and eventually reordered before stabilization.
  */
 #define R300_CMD_PACKET0		1
 #define R300_CMD_VPU			2	/* emit vertex program upload */
 #define R300_CMD_PACKET3		3	/* emit a packet3 */
 #define R300_CMD_END3D			4	/* emit sequence ending 3d rendering */
 #define R300_CMD_CP_DELAY		5
 #define R300_CMD_DMA_DISCARD		6
 #define R300_CMD_WAIT			7
 #	define R300_WAIT_2D		0x1
 #	define R300_WAIT_3D		0x2
 /* these two defines are DOING IT WRONG - however
  * we have userspace which relies on using these.
  * The wait interface is backwards compat new
  * code should use the NEW_WAIT defines below
  * THESE ARE NOT BIT FIELDS
  */
 #	define R300_WAIT_2D_CLEAN	0x3
 #	define R300_WAIT_3D_CLEAN	0x4
 #	define R300_NEW_WAIT_2D_3D	0x3
 #	define R300_NEW_WAIT_2D_2D_CLEAN	0x4
 #	define R300_NEW_WAIT_3D_3D_CLEAN	0x6
 #	define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN	0x8
 #define R300_CMD_SCRATCH		8
 #define R300_CMD_R500FP                 9
 typedef union {
 	unsigned int u;
 	struct {
 		unsigned char cmd_type, pad0, pad1, pad2;
 	} header;
 	struct {
 		unsigned char cmd_type, count, reglo, reghi;
 	} packet0;
 	struct {
 		unsigned char cmd_type, count, adrlo, adrhi;
 	} vpu;
 	struct {
 		unsigned char cmd_type, packet, pad0, pad1;
 	} packet3;
 	struct {
 		unsigned char cmd_type, packet;
 		unsigned short count;	/* amount of packet2 to emit */
 	} delay;
 	struct {
 		unsigned char cmd_type, buf_idx, pad0, pad1;
 	} dma;
 	struct {
 		unsigned char cmd_type, flags, pad0, pad1;
 	} wait;
 	struct {
 		unsigned char cmd_type, reg, n_bufs, flags;
 	} scratch;
 	struct {
 		unsigned char cmd_type, count, adrlo, adrhi_flags;
 	} r500fp;
 } drm_r300_cmd_header_t;
 #define RADEON_FRONT			0x1
 #define RADEON_BACK			0x2
 #define RADEON_DEPTH			0x4
 #define RADEON_STENCIL			0x8
 #define RADEON_CLEAR_FASTZ		0x80000000
 #define RADEON_USE_HIERZ		0x40000000
 #define RADEON_USE_COMP_ZBUF		0x20000000
 #define R500FP_CONSTANT_TYPE  (1 << 1)
 #define R500FP_CONSTANT_CLAMP (1 << 2)
 /* Primitive types
  */
 #define RADEON_POINTS			0x1
 #define RADEON_LINES			0x2
 #define RADEON_LINE_STRIP		0x3
 #define RADEON_TRIANGLES		0x4
 #define RADEON_TRIANGLE_FAN		0x5
 #define RADEON_TRIANGLE_STRIP		0x6
 /* Vertex/indirect buffer size
  */
 #define RADEON_BUFFER_SIZE		65536
 /* Byte offsets for indirect buffer data
  */
 #define RADEON_INDEX_PRIM_OFFSET	20
 #define RADEON_SCRATCH_REG_OFFSET	32
 #define RADEON_NR_SAREA_CLIPRECTS	12
 /* There are 2 heaps (local/GART).  Each region within a heap is a
  * minimum of 64k, and there are at most 64 of them per heap.
  */
 #define RADEON_LOCAL_TEX_HEAP		0
 #define RADEON_GART_TEX_HEAP		1
 #define RADEON_NR_TEX_HEAPS		2
 #define RADEON_NR_TEX_REGIONS		64
 #define RADEON_LOG_TEX_GRANULARITY	16
 #define RADEON_MAX_TEXTURE_LEVELS	12
 #define RADEON_MAX_TEXTURE_UNITS	3
 #define RADEON_MAX_SURFACES		8
 /* Blits have strict offset rules.  All blit offset must be aligned on
  * a 1K-byte boundary.
  */
 #define RADEON_OFFSET_SHIFT             10
 #define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
 #define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
 #endif				/* __RADEON_SAREA_DEFINES__ */
 typedef struct {
 	unsigned int red;
 	unsigned int green;
 	unsigned int blue;
 	unsigned int alpha;
 } radeon_color_regs_t;
 typedef struct {
 	/* Context state */
 	unsigned int pp_misc;	/* 0x1c14 */
 	unsigned int pp_fog_color;
 	unsigned int re_solid_color;
 	unsigned int rb3d_blendcntl;
 	unsigned int rb3d_depthoffset;
 	unsigned int rb3d_depthpitch;
 	unsigned int rb3d_zstencilcntl;
 	unsigned int pp_cntl;	/* 0x1c38 */
 	unsigned int rb3d_cntl;
 	unsigned int rb3d_coloroffset;
 	unsigned int re_width_height;
 	unsigned int rb3d_colorpitch;
 	unsigned int se_cntl;
 	/* Vertex format state */
 	unsigned int se_coord_fmt;	/* 0x1c50 */
 	/* Line state */
 	unsigned int re_line_pattern;	/* 0x1cd0 */
 	unsigned int re_line_state;
 	unsigned int se_line_width;	/* 0x1db8 */
 	/* Bumpmap state */
 	unsigned int pp_lum_matrix;	/* 0x1d00 */
 	unsigned int pp_rot_matrix_0;	/* 0x1d58 */
 	unsigned int pp_rot_matrix_1;
 	/* Mask state */
 	unsigned int rb3d_stencilrefmask;	/* 0x1d7c */
 	unsigned int rb3d_ropcntl;
 	unsigned int rb3d_planemask;
 	/* Viewport state */
 	unsigned int se_vport_xscale;	/* 0x1d98 */
 	unsigned int se_vport_xoffset;
 	unsigned int se_vport_yscale;
 	unsigned int se_vport_yoffset;
 	unsigned int se_vport_zscale;
 	unsigned int se_vport_zoffset;
 	/* Setup state */
 	unsigned int se_cntl_status;	/* 0x2140 */
 	/* Misc state */
 	unsigned int re_top_left;	/* 0x26c0 */
 	unsigned int re_misc;
 } drm_radeon_context_regs_t;
 typedef struct {
 	/* Zbias state */
 	unsigned int se_zbias_factor;	/* 0x1dac */
 	unsigned int se_zbias_constant;
 } drm_radeon_context2_regs_t;
 /* Setup registers for each texture unit
  */
 typedef struct {
 	unsigned int pp_txfilter;
 	unsigned int pp_txformat;
 	unsigned int pp_txoffset;
 	unsigned int pp_txcblend;
 	unsigned int pp_txablend;
 	unsigned int pp_tfactor;
 	unsigned int pp_border_color;
 } drm_radeon_texture_regs_t;
 typedef struct {
 	unsigned int start;
 	unsigned int finish;
 	unsigned int prim:8;
 	unsigned int stateidx:8;
 	unsigned int numverts:16;	/* overloaded as offset/64 for elt prims */
 	unsigned int vc_format;	/* vertex format */
 } drm_radeon_prim_t;
 typedef struct {
 	drm_radeon_context_regs_t context;
 	drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
 	drm_radeon_context2_regs_t context2;
 	unsigned int dirty;
 } drm_radeon_state_t;
 typedef struct {
 	/* The channel for communication of state information to the
 	 * kernel on firing a vertex buffer with either of the
 	 * obsoleted vertex/index ioctls.
 	 */
 	drm_radeon_context_regs_t context_state;
 	drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
 	unsigned int dirty;
 	unsigned int vertsize;
 	unsigned int vc_format;
 	/* The current cliprects, or a subset thereof.
 	 */
 	struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
 	unsigned int nbox;
 	/* Counters for client-side throttling of rendering clients.
 	 */
 	unsigned int last_frame;
 	unsigned int last_dispatch;
 	unsigned int last_clear;
 	struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
 						       1];
 	unsigned int tex_age[RADEON_NR_TEX_HEAPS];
 	int ctx_owner;
 	int pfState;		/* number of 3d windows (0,1,2ormore) */
 	int pfCurrentPage;	/* which buffer is being displayed? */
 	int crtc2_base;		/* CRTC2 frame offset */
 	int tiling_enabled;	/* set by drm, read by 2d + 3d clients */
 } drm_radeon_sarea_t;
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmRadeon.h)
  *
  * KW: actually it's illegal to change any of this (backwards compatibility).
  */
 /* Radeon specific ioctls
  * The device specific ioctl range is 0x40 to 0x79.
  */
 #define DRM_RADEON_CP_INIT    0x00
 #define DRM_RADEON_CP_START   0x01
 #define DRM_RADEON_CP_STOP    0x02
 #define DRM_RADEON_CP_RESET   0x03
 #define DRM_RADEON_CP_IDLE    0x04
 #define DRM_RADEON_RESET      0x05
 #define DRM_RADEON_FULLSCREEN 0x06
 #define DRM_RADEON_SWAP       0x07
 #define DRM_RADEON_CLEAR      0x08
 #define DRM_RADEON_VERTEX     0x09
 #define DRM_RADEON_INDICES    0x0A
 #define DRM_RADEON_NOT_USED
 #define DRM_RADEON_STIPPLE    0x0C
 #define DRM_RADEON_INDIRECT   0x0D
 #define DRM_RADEON_TEXTURE    0x0E
 #define DRM_RADEON_VERTEX2    0x0F
 #define DRM_RADEON_CMDBUF     0x10
 #define DRM_RADEON_GETPARAM   0x11
 #define DRM_RADEON_FLIP       0x12
 #define DRM_RADEON_ALLOC      0x13
 #define DRM_RADEON_FREE       0x14
 #define DRM_RADEON_INIT_HEAP  0x15
 #define DRM_RADEON_IRQ_EMIT   0x16
 #define DRM_RADEON_IRQ_WAIT   0x17
 #define DRM_RADEON_CP_RESUME  0x18
 #define DRM_RADEON_SETPARAM   0x19
 #define DRM_RADEON_SURF_ALLOC 0x1a
 #define DRM_RADEON_SURF_FREE  0x1b
 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
 #define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
 #define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
 #define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
 #define DRM_IOCTL_RADEON_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_RESET)
 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
 #define DRM_IOCTL_RADEON_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_SWAP)
 #define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
 #define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
 #define DRM_IOCTL_RADEON_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
 #define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
 #define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
 #define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
 #define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
 #define DRM_IOCTL_RADEON_CMDBUF     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
 #define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
 #define DRM_IOCTL_RADEON_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_FLIP)
 #define DRM_IOCTL_RADEON_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
 #define DRM_IOCTL_RADEON_FREE       DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
 #define DRM_IOCTL_RADEON_INIT_HEAP  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
 #define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
 #define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
 #define DRM_IOCTL_RADEON_CP_RESUME  DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
 #define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
 #define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
 typedef struct drm_radeon_init {
 	enum {
 		RADEON_INIT_CP = 0x01,
 		RADEON_CLEANUP_CP = 0x02,
 		RADEON_INIT_R200_CP = 0x03,
 		RADEON_INIT_R300_CP = 0x04
 	} func;
 	unsigned long sarea_priv_offset;
 	int is_pci;
 	int cp_mode;
 	int gart_size;
 	int ring_size;
 	int usec_timeout;
 	unsigned int fb_bpp;
 	unsigned int front_offset, front_pitch;
 	unsigned int back_offset, back_pitch;
 	unsigned int depth_bpp;
 	unsigned int depth_offset, depth_pitch;
 	unsigned long fb_offset;
 	unsigned long mmio_offset;
 	unsigned long ring_offset;
 	unsigned long ring_rptr_offset;
 	unsigned long buffers_offset;
 	unsigned long gart_textures_offset;
 } drm_radeon_init_t;
 typedef struct drm_radeon_cp_stop {
 	int flush;
 	int idle;
 } drm_radeon_cp_stop_t;
 typedef struct drm_radeon_fullscreen {
 	enum {
 		RADEON_INIT_FULLSCREEN = 0x01,
 		RADEON_CLEANUP_FULLSCREEN = 0x02
 	} func;
 } drm_radeon_fullscreen_t;
 #define CLEAR_X1	0
 #define CLEAR_Y1	1
 #define CLEAR_X2	2
 #define CLEAR_Y2	3
 #define CLEAR_DEPTH	4
 typedef union drm_radeon_clear_rect {
 	float f[5];
 	unsigned int ui[5];
 } drm_radeon_clear_rect_t;
 typedef struct drm_radeon_clear {
 	unsigned int flags;
 	unsigned int clear_color;
 	unsigned int clear_depth;
 	unsigned int color_mask;
 	unsigned int depth_mask;	/* misnamed field:  should be stencil */
 	drm_radeon_clear_rect_t __user *depth_boxes;
 } drm_radeon_clear_t;
 typedef struct drm_radeon_vertex {
 	int prim;
 	int idx;		/* Index of vertex buffer */
 	int count;		/* Number of vertices in buffer */
 	int discard;		/* Client finished with buffer? */
 } drm_radeon_vertex_t;
 typedef struct drm_radeon_indices {
 	int prim;
 	int idx;
 	int start;
 	int end;
 	int discard;		/* Client finished with buffer? */
 } drm_radeon_indices_t;
 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
  *      - allows multiple primitives and state changes in a single ioctl
  *      - supports driver change to emit native primitives
  */
 typedef struct drm_radeon_vertex2 {
 	int idx;		/* Index of vertex buffer */
 	int discard;		/* Client finished with buffer? */
 	int nr_states;
 	drm_radeon_state_t __user *state;
 	int nr_prims;
 	drm_radeon_prim_t __user *prim;
 } drm_radeon_vertex2_t;
 /* v1.3 - obsoletes drm_radeon_vertex2
  *      - allows arbitarily large cliprect list
  *      - allows updating of tcl packet, vector and scalar state
  *      - allows memory-efficient description of state updates
  *      - allows state to be emitted without a primitive
  *           (for clears, ctx switches)
  *      - allows more than one dma buffer to be referenced per ioctl
  *      - supports tcl driver
  *      - may be extended in future versions with new cmd types, packets
  */
 typedef struct drm_radeon_cmd_buffer {
 	int bufsz;
 	char __user *buf;
 	int nbox;
 	struct drm_clip_rect __user *boxes;
 } drm_radeon_cmd_buffer_t;
 typedef struct drm_radeon_tex_image {
 	unsigned int x, y;	/* Blit coordinates */
 	unsigned int width, height;
 	const void __user *data;
 } drm_radeon_tex_image_t;
 typedef struct drm_radeon_texture {
 	unsigned int offset;
 	int pitch;
 	int format;
 	int width;		/* Texture image coordinates */
 	int height;
 	drm_radeon_tex_image_t __user *image;
 } drm_radeon_texture_t;
 typedef struct drm_radeon_stipple {
 	unsigned int __user *mask;
 } drm_radeon_stipple_t;
 typedef struct drm_radeon_indirect {
 	int idx;
 	int start;
 	int end;
 	int discard;
 } drm_radeon_indirect_t;
 /* enum for card type parameters */
 #define RADEON_CARD_PCI 0
 #define RADEON_CARD_AGP 1
 #define RADEON_CARD_PCIE 2
 /* 1.3: An ioctl to get parameters that aren't available to the 3d
  * client any other way.
  */
 #define RADEON_PARAM_GART_BUFFER_OFFSET    1	/* card offset of 1st GART buffer */
 #define RADEON_PARAM_LAST_FRAME            2
 #define RADEON_PARAM_LAST_DISPATCH         3
 #define RADEON_PARAM_LAST_CLEAR            4
 /* Added with DRM version 1.6. */
 #define RADEON_PARAM_IRQ_NR                5
 #define RADEON_PARAM_GART_BASE             6	/* card offset of GART base */
 /* Added with DRM version 1.8. */
 #define RADEON_PARAM_REGISTER_HANDLE       7	/* for drmMap() */
 #define RADEON_PARAM_STATUS_HANDLE         8
 #define RADEON_PARAM_SAREA_HANDLE          9
 #define RADEON_PARAM_GART_TEX_HANDLE       10
 #define RADEON_PARAM_SCRATCH_OFFSET        11
 #define RADEON_PARAM_CARD_TYPE             12
 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
 #define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
 typedef struct drm_radeon_getparam {
 	int param;
 	void __user *value;
 } drm_radeon_getparam_t;
 /* 1.6: Set up a memory manager for regions of shared memory:
  */
 #define RADEON_MEM_REGION_GART 1
 #define RADEON_MEM_REGION_FB   2
 typedef struct drm_radeon_mem_alloc {
 	int region;
 	int alignment;
 	int size;
 	int __user *region_offset;	/* offset from start of fb or GART */
 } drm_radeon_mem_alloc_t;
 typedef struct drm_radeon_mem_free {
 	int region;
 	int region_offset;
 } drm_radeon_mem_free_t;
 typedef struct drm_radeon_mem_init_heap {
 	int region;
 	int size;
 	int start;
 } drm_radeon_mem_init_heap_t;
 /* 1.6: Userspace can request & wait on irq's:
  */
 typedef struct drm_radeon_irq_emit {
 	int __user *irq_seq;
 } drm_radeon_irq_emit_t;
 typedef struct drm_radeon_irq_wait {
 	int irq_seq;
 } drm_radeon_irq_wait_t;
 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
  * the card's address space, via a new generic ioctl to set parameters
  */
 typedef struct drm_radeon_setparam {
 	unsigned int param;
-	int64_t value;
+	__s64 value;
 } drm_radeon_setparam_t;
 #define RADEON_SETPARAM_FB_LOCATION    1	/* determined framebuffer location */
 #define RADEON_SETPARAM_SWITCH_TILING  2	/* enable/disable color tiling */
 #define RADEON_SETPARAM_PCIGART_LOCATION 3	/* PCI Gart Location */
 #define RADEON_SETPARAM_NEW_MEMMAP 4		/* Use new memory map */
 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
 #define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
 /* 1.14: Clients can allocate/free a surface
  */
 typedef struct drm_radeon_surface_alloc {
 	unsigned int address;
 	unsigned int size;
 	unsigned int flags;
 } drm_radeon_surface_alloc_t;
 typedef struct drm_radeon_surface_free {
 	unsigned int address;
 } drm_radeon_surface_free_t;
 #define	DRM_RADEON_VBLANK_CRTC1		1
 #define	DRM_RADEON_VBLANK_CRTC2		2
 #endif

include/drm/via_drm.h

Diff comments View file @ 1d7f83d

 /*
  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
 #ifndef _VIA_DRM_H_
 #define _VIA_DRM_H_
+#include <linux/types.h>
 /* WARNING: These defines must be the same as what the Xserver uses.
  * if you change them, you must change the defines in the Xserver.
  */
 #ifndef _VIA_DEFINES_
 #define _VIA_DEFINES_
 #ifndef __KERNEL__
 #include "via_drmclient.h"
 #endif
 #define VIA_NR_SAREA_CLIPRECTS		8
 #define VIA_NR_XVMC_PORTS               10
 #define VIA_NR_XVMC_LOCKS               5
 #define VIA_MAX_CACHELINE_SIZE          64
 #define XVMCLOCKPTR(saPriv,lockNo)					\
 	((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
 				      (VIA_MAX_CACHELINE_SIZE - 1)) &	\
 				     ~(VIA_MAX_CACHELINE_SIZE - 1)) +	\
 				    VIA_MAX_CACHELINE_SIZE*(lockNo)))
 /* Each region is a minimum of 64k, and there are at most 64 of them.
  */
 #define VIA_NR_TEX_REGIONS 64
 #define VIA_LOG_MIN_TEX_REGION_SIZE 16
 #endif
 #define VIA_UPLOAD_TEX0IMAGE  0x1	/* handled clientside */
 #define VIA_UPLOAD_TEX1IMAGE  0x2	/* handled clientside */
 #define VIA_UPLOAD_CTX        0x4
 #define VIA_UPLOAD_BUFFERS    0x8
 #define VIA_UPLOAD_TEX0       0x10
 #define VIA_UPLOAD_TEX1       0x20
 #define VIA_UPLOAD_CLIPRECTS  0x40
 #define VIA_UPLOAD_ALL        0xff
 /* VIA specific ioctls */
 #define DRM_VIA_ALLOCMEM	0x00
 #define DRM_VIA_FREEMEM	        0x01
 #define DRM_VIA_AGP_INIT	0x02
 #define DRM_VIA_FB_INIT	        0x03
 #define DRM_VIA_MAP_INIT	0x04
 #define DRM_VIA_DEC_FUTEX       0x05
 #define NOT_USED
 #define DRM_VIA_DMA_INIT	0x07
 #define DRM_VIA_CMDBUFFER	0x08
 #define DRM_VIA_FLUSH	        0x09
 #define DRM_VIA_PCICMD	        0x0a
 #define DRM_VIA_CMDBUF_SIZE	0x0b
 #define NOT_USED
 #define DRM_VIA_WAIT_IRQ        0x0d
 #define DRM_VIA_DMA_BLIT        0x0e
 #define DRM_VIA_BLIT_SYNC       0x0f
 #define DRM_IOCTL_VIA_ALLOCMEM	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
 #define DRM_IOCTL_VIA_FREEMEM	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
 #define DRM_IOCTL_VIA_AGP_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
 #define DRM_IOCTL_VIA_FB_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
 #define DRM_IOCTL_VIA_MAP_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
 #define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
 #define DRM_IOCTL_VIA_DMA_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
 #define DRM_IOCTL_VIA_CMDBUFFER	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
 #define DRM_IOCTL_VIA_FLUSH	  DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
 #define DRM_IOCTL_VIA_PCICMD	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
 #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
 					    drm_via_cmdbuf_size_t)
 #define DRM_IOCTL_VIA_WAIT_IRQ    DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
 #define DRM_IOCTL_VIA_DMA_BLIT    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
 #define DRM_IOCTL_VIA_BLIT_SYNC   DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
 /* Indices into buf.Setup where various bits of state are mirrored per
  * context and per buffer.  These can be fired at the card as a unit,
  * or in a piecewise fashion as required.
  */
 #define VIA_TEX_SETUP_SIZE 8
 /* Flags for clear ioctl
  */
 #define VIA_FRONT   0x1
 #define VIA_BACK    0x2
 #define VIA_DEPTH   0x4
 #define VIA_STENCIL 0x8
 #define VIA_MEM_VIDEO   0	/* matches drm constant */
 #define VIA_MEM_AGP     1	/* matches drm constant */
 #define VIA_MEM_SYSTEM  2
 #define VIA_MEM_MIXED   3
 #define VIA_MEM_UNKNOWN 4
 typedef struct {
-	uint32_t offset;
+	__u32 offset;
-	uint32_t size;
+	__u32 size;
 } drm_via_agp_t;
 typedef struct {
-	uint32_t offset;
+	__u32 offset;
-	uint32_t size;
+	__u32 size;
 } drm_via_fb_t;
 typedef struct {
-	uint32_t context;
+	__u32 context;
-	uint32_t type;
+	__u32 type;
-	uint32_t size;
+	__u32 size;
 	unsigned long index;
 	unsigned long offset;
 } drm_via_mem_t;
 typedef struct _drm_via_init {
 	enum {
 		VIA_INIT_MAP = 0x01,
 		VIA_CLEANUP_MAP = 0x02
 	} func;
 	unsigned long sarea_priv_offset;
 	unsigned long fb_offset;
 	unsigned long mmio_offset;
 	unsigned long agpAddr;
 } drm_via_init_t;
 typedef struct _drm_via_futex {
 	enum {
 		VIA_FUTEX_WAIT = 0x00,
 		VIA_FUTEX_WAKE = 0X01
 	} func;
-	uint32_t ms;
+	__u32 ms;
-	uint32_t lock;
+	__u32 lock;
-	uint32_t val;
+	__u32 val;
 } drm_via_futex_t;
 typedef struct _drm_via_dma_init {
 	enum {
 		VIA_INIT_DMA = 0x01,
 		VIA_CLEANUP_DMA = 0x02,
 		VIA_DMA_INITIALIZED = 0x03
 	} func;
 	unsigned long offset;
 	unsigned long size;
 	unsigned long reg_pause_addr;
 } drm_via_dma_init_t;
 typedef struct _drm_via_cmdbuffer {
 	char __user *buf;
 	unsigned long size;
 } drm_via_cmdbuffer_t;
 /* Warning: If you change the SAREA structure you must change the Xserver
  * structure as well */
 typedef struct _drm_via_tex_region {
 	unsigned char next, prev;	/* indices to form a circular LRU  */
 	unsigned char inUse;	/* owned by a client, or free? */
 	int age;		/* tracked by clients to update local LRU's */
 } drm_via_tex_region_t;
 typedef struct _drm_via_sarea {
 	unsigned int dirty;
 	unsigned int nbox;
 	struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
 	drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
 	int texAge;		/* last time texture was uploaded */
 	int ctxOwner;		/* last context to upload state */
 	int vertexPrim;
 	/*
 	 * Below is for XvMC.
 	 * We want the lock integers alone on, and aligned to, a cache line.
 	 * Therefore this somewhat strange construct.
 	 */
 	char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
 	unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
 	unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
 	unsigned int XvMCCtxNoGrabbed;	/* Last context to hold decoder */
 	/* Used by the 3d driver only at this point, for pageflipping:
 	 */
 	unsigned int pfCurrentOffset;
 } drm_via_sarea_t;
 typedef struct _drm_via_cmdbuf_size {
 	enum {
 		VIA_CMDBUF_SPACE = 0x01,
 		VIA_CMDBUF_LAG = 0x02
 	} func;
 	int wait;
-	uint32_t size;
+	__u32 size;
 } drm_via_cmdbuf_size_t;
 typedef enum {
 	VIA_IRQ_ABSOLUTE = 0x0,
 	VIA_IRQ_RELATIVE = 0x1,
 	VIA_IRQ_SIGNAL = 0x10000000,
 	VIA_IRQ_FORCE_SEQUENCE = 0x20000000
 } via_irq_seq_type_t;
 #define VIA_IRQ_FLAGS_MASK 0xF0000000
 enum drm_via_irqs {
 	drm_via_irq_hqv0 = 0,
 	drm_via_irq_hqv1,
 	drm_via_irq_dma0_dd,
 	drm_via_irq_dma0_td,
 	drm_via_irq_dma1_dd,
 	drm_via_irq_dma1_td,
 	drm_via_irq_num
 };
 struct drm_via_wait_irq_request {
 	unsigned irq;
 	via_irq_seq_type_t type;
-	uint32_t sequence;
+	__u32 sequence;
-	uint32_t signal;
+	__u32 signal;
 };
 typedef union drm_via_irqwait {
 	struct drm_via_wait_irq_request request;
 	struct drm_wait_vblank_reply reply;
 } drm_via_irqwait_t;
 typedef struct drm_via_blitsync {
-	uint32_t sync_handle;
+	__u32 sync_handle;
 	unsigned engine;
 } drm_via_blitsync_t;
 /* - * Below,"flags" is currently unused but will be used for possible future
  * extensions like kernel space bounce buffers for bad alignments and
  * blit engine busy-wait polling for better latency in the absence of
  * interrupts.
  */
 typedef struct drm_via_dmablit {
-	uint32_t num_lines;
+	__u32 num_lines;
-	uint32_t line_length;
+	__u32 line_length;
-	uint32_t fb_addr;
+	__u32 fb_addr;
-	uint32_t fb_stride;
+	__u32 fb_stride;
 	unsigned char *mem_addr;
-	uint32_t mem_stride;
+	__u32 mem_stride;
-	uint32_t flags;
+	__u32 flags;
 	int to_fb;
 	drm_via_blitsync_t sync;
 } drm_via_dmablit_t;
 #endif				/* _VIA_DRM_H_ */