make drm headers use strict integer types

The drm headers are traditionally shared with BSD and could not use the strict linux integer types. This is over now, so we can use our own types now. Cc: David Airlie <airlied@linux.ie> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>

make drm headers use strict integer types
The drm headers are traditionally shared with BSD and could not use the strict linux integer types. This is over now, so we can use our own types now. Cc: David Airlie <airlied@linux.ie> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Arnd Bergmann · Ingo Molnar
1 parent ccef7ab534
Showing 6 changed files with 190 additions and 188 deletions Side-by-side Diff
include/drm/drm.h
include/drm/drm_mode.h
include/drm/i915_drm.h
include/drm/mga_drm.h
include/drm/radeon_drm.h
include/drm/via_drm.h
@@ -36,8 +36,7 @@
 #ifndef _DRM_H_
 #define _DRM_H_
  
-#if defined(__KERNEL__)
-#endif
+#include <linux/types.h>
 #include <asm/ioctl.h>		/* For _IO* macros */
 #define DRM_IOCTL_NR(n)		_IOC_NR(n)
 #define DRM_IOC_VOID		_IOC_NONE
@@ -497,8 +496,8 @@
  * \sa drmModesetCtl().
  */
 struct drm_modeset_ctl {
-	uint32_t crtc;
-	uint32_t cmd;
+	__u32 crtc;
+	__u32 cmd;
 };
  
 /**
  
  
  
  
  
@@ -574,29 +573,29 @@
 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */
 struct drm_gem_close {
 	/** Handle of the object to be closed. */
-	uint32_t handle;
-	uint32_t pad;
+	__u32 handle;
+	__u32 pad;
 };
  
 /** DRM_IOCTL_GEM_FLINK ioctl argument type */
 struct drm_gem_flink {
 	/** Handle for the object being named */
-	uint32_t handle;
+	__u32 handle;
  
 	/** Returned global name */
-	uint32_t name;
+	__u32 name;
 };
  
 /** DRM_IOCTL_GEM_OPEN ioctl argument type */
 struct drm_gem_open {
 	/** Name of object being opened */
-	uint32_t name;
+	__u32 name;
  
 	/** Returned handle for the object */
-	uint32_t handle;
+	__u32 handle;
  
 	/** Returned size of the object */
-	uint64_t size;
+	__u64 size;
 };
  
 #include "drm_mode.h"
@@ -27,11 +27,8 @@
 #ifndef _DRM_MODE_H
 #define _DRM_MODE_H
  
-#if !defined(__KERNEL__) && !defined(_KERNEL)
-#include <stdint.h>
-#else
 #include <linux/kernel.h>
-#endif
+#include <linux/types.h>
  
 #define DRM_DISPLAY_INFO_LEN	32
 #define DRM_CONNECTOR_NAME_LEN	32
  
  
  
  
  
  
  
@@ -81,41 +78,41 @@
 #define DRM_MODE_DITHERING_ON	1
  
 struct drm_mode_modeinfo {
-	uint32_t clock;
-	uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew;
-	uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan;
+	__u32 clock;
+	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
+	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
  
-	uint32_t vrefresh; /* vertical refresh * 1000 */
+	__u32 vrefresh; /* vertical refresh * 1000 */
  
-	uint32_t flags;
-	uint32_t type;
+	__u32 flags;
+	__u32 type;
 	char name[DRM_DISPLAY_MODE_LEN];
 };
  
 struct drm_mode_card_res {
-	uint64_t fb_id_ptr;
-	uint64_t crtc_id_ptr;
-	uint64_t connector_id_ptr;
-	uint64_t encoder_id_ptr;
-	uint32_t count_fbs;
-	uint32_t count_crtcs;
-	uint32_t count_connectors;
-	uint32_t count_encoders;
-	uint32_t min_width, max_width;
-	uint32_t min_height, max_height;
+	__u64 fb_id_ptr;
+	__u64 crtc_id_ptr;
+	__u64 connector_id_ptr;
+	__u64 encoder_id_ptr;
+	__u32 count_fbs;
+	__u32 count_crtcs;
+	__u32 count_connectors;
+	__u32 count_encoders;
+	__u32 min_width, max_width;
+	__u32 min_height, max_height;
 };
  
 struct drm_mode_crtc {
-	uint64_t set_connectors_ptr;
-	uint32_t count_connectors;
+	__u64 set_connectors_ptr;
+	__u32 count_connectors;
  
-	uint32_t crtc_id; /**< Id */
-	uint32_t fb_id; /**< Id of framebuffer */
+	__u32 crtc_id; /**< Id */
+	__u32 fb_id; /**< Id of framebuffer */
  
-	uint32_t x, y; /**< Position on the frameuffer */
+	__u32 x, y; /**< Position on the frameuffer */
  
-	uint32_t gamma_size;
-	uint32_t mode_valid;
+	__u32 gamma_size;
+	__u32 mode_valid;
 	struct drm_mode_modeinfo mode;
 };
  
  
  
@@ -126,13 +123,13 @@
 #define DRM_MODE_ENCODER_TVDAC	4
  
 struct drm_mode_get_encoder {
-	uint32_t encoder_id;
-	uint32_t encoder_type;
+	__u32 encoder_id;
+	__u32 encoder_type;
  
-	uint32_t crtc_id; /**< Id of crtc */
+	__u32 crtc_id; /**< Id of crtc */
  
-	uint32_t possible_crtcs;
-	uint32_t possible_clones;
+	__u32 possible_crtcs;
+	__u32 possible_clones;
 };
  
 /* This is for connectors with multiple signal types. */
  
  
  
@@ -161,23 +158,23 @@
  
 struct drm_mode_get_connector {
  
-	uint64_t encoders_ptr;
-	uint64_t modes_ptr;
-	uint64_t props_ptr;
-	uint64_t prop_values_ptr;
+	__u64 encoders_ptr;
+	__u64 modes_ptr;
+	__u64 props_ptr;
+	__u64 prop_values_ptr;
  
-	uint32_t count_modes;
-	uint32_t count_props;
-	uint32_t count_encoders;
+	__u32 count_modes;
+	__u32 count_props;
+	__u32 count_encoders;
  
-	uint32_t encoder_id; /**< Current Encoder */
-	uint32_t connector_id; /**< Id */
-	uint32_t connector_type;
-	uint32_t connector_type_id;
+	__u32 encoder_id; /**< Current Encoder */
+	__u32 connector_id; /**< Id */
+	__u32 connector_type;
+	__u32 connector_type_id;
  
-	uint32_t connection;
-	uint32_t mm_width, mm_height; /**< HxW in millimeters */
-	uint32_t subpixel;
+	__u32 connection;
+	__u32 mm_width, mm_height; /**< HxW in millimeters */
+	__u32 subpixel;
 };
  
 #define DRM_MODE_PROP_PENDING	(1<<0)
  
  
  
  
  
  
  
  
@@ -187,46 +184,46 @@
 #define DRM_MODE_PROP_BLOB	(1<<4)
  
 struct drm_mode_property_enum {
-	uint64_t value;
+	__u64 value;
 	char name[DRM_PROP_NAME_LEN];
 };
  
 struct drm_mode_get_property {
-	uint64_t values_ptr; /* values and blob lengths */
-	uint64_t enum_blob_ptr; /* enum and blob id ptrs */
+	__u64 values_ptr; /* values and blob lengths */
+	__u64 enum_blob_ptr; /* enum and blob id ptrs */
  
-	uint32_t prop_id;
-	uint32_t flags;
+	__u32 prop_id;
+	__u32 flags;
 	char name[DRM_PROP_NAME_LEN];
  
-	uint32_t count_values;
-	uint32_t count_enum_blobs;
+	__u32 count_values;
+	__u32 count_enum_blobs;
 };
  
 struct drm_mode_connector_set_property {
-	uint64_t value;
-	uint32_t prop_id;
-	uint32_t connector_id;
+	__u64 value;
+	__u32 prop_id;
+	__u32 connector_id;
 };
  
 struct drm_mode_get_blob {
-	uint32_t blob_id;
-	uint32_t length;
-	uint64_t data;
+	__u32 blob_id;
+	__u32 length;
+	__u64 data;
 };
  
 struct drm_mode_fb_cmd {
-	uint32_t fb_id;
-	uint32_t width, height;
-	uint32_t pitch;
-	uint32_t bpp;
-	uint32_t depth;
+	__u32 fb_id;
+	__u32 width, height;
+	__u32 pitch;
+	__u32 bpp;
+	__u32 depth;
 	/* driver specific handle */
-	uint32_t handle;
+	__u32 handle;
 };
  
 struct drm_mode_mode_cmd {
-	uint32_t connector_id;
+	__u32 connector_id;
 	struct drm_mode_modeinfo mode;
 };
  
  
  
  
@@ -248,24 +245,24 @@
  *    y
  */
 struct drm_mode_cursor {
-	uint32_t flags;
-	uint32_t crtc_id;
-	int32_t x;
-	int32_t y;
-	uint32_t width;
-	uint32_t height;
+	__u32 flags;
+	__u32 crtc_id;
+	__s32 x;
+	__s32 y;
+	__u32 width;
+	__u32 height;
 	/* driver specific handle */
-	uint32_t handle;
+	__u32 handle;
 };
  
 struct drm_mode_crtc_lut {
-	uint32_t crtc_id;
-	uint32_t gamma_size;
+	__u32 crtc_id;
+	__u32 gamma_size;
  
 	/* pointers to arrays */
-	uint64_t red;
-	uint64_t green;
-	uint64_t blue;
+	__u64 red;
+	__u64 green;
+	__u64 blue;
 };
  
 #endif
@@ -30,7 +30,7 @@
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
  */
-
+#include <linux/types.h>
 #include "drm.h"
  
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  
@@ -116,15 +116,15 @@
  
 	/* fill out some space for old userspace triple buffer */
 	drm_handle_t unused_handle;
-	uint32_t unused1, unused2, unused3;
+	__u32 unused1, unused2, unused3;
  
 	/* buffer object handles for static buffers. May change
 	 * over the lifetime of the client.
 	 */
-	uint32_t front_bo_handle;
-	uint32_t back_bo_handle;
-	uint32_t unused_bo_handle;
-	uint32_t depth_bo_handle;
+	__u32 front_bo_handle;
+	__u32 back_bo_handle;
+	__u32 unused_bo_handle;
+	__u32 depth_bo_handle;
  
 } drm_i915_sarea_t;
  
@@ -325,7 +325,7 @@
 } drm_i915_vblank_swap_t;
  
 typedef struct drm_i915_hws_addr {
-	uint64_t addr;
+	__u64 addr;
 } drm_i915_hws_addr_t;
  
 struct drm_i915_gem_init {
  
@@ -333,12 +333,12 @@
 	 * Beginning offset in the GTT to be managed by the DRM memory
 	 * manager.
 	 */
-	uint64_t gtt_start;
+	__u64 gtt_start;
 	/**
 	 * Ending offset in the GTT to be managed by the DRM memory
 	 * manager.
 	 */
-	uint64_t gtt_end;
+	__u64 gtt_end;
 };
  
 struct drm_i915_gem_create {
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -347,94 +347,94 @@
 	 *
 	 * The (page-aligned) allocated size for the object will be returned.
 	 */
-	uint64_t size;
+	__u64 size;
 	/**
 	 * Returned handle for the object.
 	 *
 	 * Object handles are nonzero.
 	 */
-	uint32_t handle;
-	uint32_t pad;
+	__u32 handle;
+	__u32 pad;
 };
  
 struct drm_i915_gem_pread {
 	/** Handle for the object being read. */
-	uint32_t handle;
-	uint32_t pad;
+	__u32 handle;
+	__u32 pad;
 	/** Offset into the object to read from */
-	uint64_t offset;
+	__u64 offset;
 	/** Length of data to read */
-	uint64_t size;
+	__u64 size;
 	/**
 	 * Pointer to write the data into.
 	 *
 	 * This is a fixed-size type for 32/64 compatibility.
 	 */
-	uint64_t data_ptr;
+	__u64 data_ptr;
 };
  
 struct drm_i915_gem_pwrite {
 	/** Handle for the object being written to. */
-	uint32_t handle;
-	uint32_t pad;
+	__u32 handle;
+	__u32 pad;
 	/** Offset into the object to write to */
-	uint64_t offset;
+	__u64 offset;
 	/** Length of data to write */
-	uint64_t size;
+	__u64 size;
 	/**
 	 * Pointer to read the data from.
 	 *
 	 * This is a fixed-size type for 32/64 compatibility.
 	 */
-	uint64_t data_ptr;
+	__u64 data_ptr;
 };
  
 struct drm_i915_gem_mmap {
 	/** Handle for the object being mapped. */
-	uint32_t handle;
-	uint32_t pad;
+	__u32 handle;
+	__u32 pad;
 	/** Offset in the object to map. */
-	uint64_t offset;
+	__u64 offset;
 	/**
 	 * Length of data to map.
 	 *
 	 * The value will be page-aligned.
 	 */
-	uint64_t size;
+	__u64 size;
 	/**
 	 * Returned pointer the data was mapped at.
 	 *
 	 * This is a fixed-size type for 32/64 compatibility.
 	 */
-	uint64_t addr_ptr;
+	__u64 addr_ptr;
 };
  
 struct drm_i915_gem_mmap_gtt {
 	/** Handle for the object being mapped. */
-	uint32_t handle;
-	uint32_t pad;
+	__u32 handle;
+	__u32 pad;
 	/**
 	 * Fake offset to use for subsequent mmap call
 	 *
 	 * This is a fixed-size type for 32/64 compatibility.
 	 */
-	uint64_t offset;
+	__u64 offset;
 };
  
 struct drm_i915_gem_set_domain {
 	/** Handle for the object */
-	uint32_t handle;
+	__u32 handle;
  
 	/** New read domains */
-	uint32_t read_domains;
+	__u32 read_domains;
  
 	/** New write domain */
-	uint32_t write_domain;
+	__u32 write_domain;
 };
  
 struct drm_i915_gem_sw_finish {
 	/** Handle for the object */
-	uint32_t handle;
+	__u32 handle;
 };
  
 struct drm_i915_gem_relocation_entry {
  
  
@@ -446,16 +446,16 @@
 	 * a relocation list for state buffers and not re-write it per
 	 * exec using the buffer.
 	 */
-	uint32_t target_handle;
+	__u32 target_handle;
  
 	/**
 	 * Value to be added to the offset of the target buffer to make up
 	 * the relocation entry.
 	 */
-	uint32_t delta;
+	__u32 delta;
  
 	/** Offset in the buffer the relocation entry will be written into */
-	uint64_t offset;
+	__u64 offset;
  
 	/**
 	 * Offset value of the target buffer that the relocation entry was last
  
@@ -465,12 +465,12 @@
 	 * and writing the relocation.  This value is written back out by
 	 * the execbuffer ioctl when the relocation is written.
 	 */
-	uint64_t presumed_offset;
+	__u64 presumed_offset;
  
 	/**
 	 * Target memory domains read by this operation.
 	 */
-	uint32_t read_domains;
+	__u32 read_domains;
  
 	/**
 	 * Target memory domains written by this operation.
@@ -479,7 +479,7 @@
 	 * execbuffer operation, so that where there are conflicts,
 	 * the application will get -EINVAL back.
 	 */
-	uint32_t write_domain;
+	__u32 write_domain;
 };
  
 /** @{
  
  
  
  
@@ -510,24 +510,24 @@
 	 * User's handle for a buffer to be bound into the GTT for this
 	 * operation.
 	 */
-	uint32_t handle;
+	__u32 handle;
  
 	/** Number of relocations to be performed on this buffer */
-	uint32_t relocation_count;
+	__u32 relocation_count;
 	/**
 	 * Pointer to array of struct drm_i915_gem_relocation_entry containing
 	 * the relocations to be performed in this buffer.
 	 */
-	uint64_t relocs_ptr;
+	__u64 relocs_ptr;
  
 	/** Required alignment in graphics aperture */
-	uint64_t alignment;
+	__u64 alignment;
  
 	/**
 	 * Returned value of the updated offset of the object, for future
 	 * presumed_offset writes.
 	 */
-	uint64_t offset;
+	__u64 offset;
 };
  
 struct drm_i915_gem_execbuffer {
  
  
  
  
  
  
  
  
  
@@ -541,44 +541,44 @@
 	 * a buffer is performing refer to buffers that have already appeared
 	 * in the validate list.
 	 */
-	uint64_t buffers_ptr;
-	uint32_t buffer_count;
+	__u64 buffers_ptr;
+	__u32 buffer_count;
  
 	/** Offset in the batchbuffer to start execution from. */
-	uint32_t batch_start_offset;
+	__u32 batch_start_offset;
 	/** Bytes used in batchbuffer from batch_start_offset */
-	uint32_t batch_len;
-	uint32_t DR1;
-	uint32_t DR4;
-	uint32_t num_cliprects;
+	__u32 batch_len;
+	__u32 DR1;
+	__u32 DR4;
+	__u32 num_cliprects;
 	/** This is a struct drm_clip_rect *cliprects */
-	uint64_t cliprects_ptr;
+	__u64 cliprects_ptr;
 };
  
 struct drm_i915_gem_pin {
 	/** Handle of the buffer to be pinned. */
-	uint32_t handle;
-	uint32_t pad;
+	__u32 handle;
+	__u32 pad;
  
 	/** alignment required within the aperture */
-	uint64_t alignment;
+	__u64 alignment;
  
 	/** Returned GTT offset of the buffer. */
-	uint64_t offset;
+	__u64 offset;
 };
  
 struct drm_i915_gem_unpin {
 	/** Handle of the buffer to be unpinned. */
-	uint32_t handle;
-	uint32_t pad;
+	__u32 handle;
+	__u32 pad;
 };
  
 struct drm_i915_gem_busy {
 	/** Handle of the buffer to check for busy */
-	uint32_t handle;
+	__u32 handle;
  
 	/** Return busy status (1 if busy, 0 if idle) */
-	uint32_t busy;
+	__u32 busy;
 };
  
 #define I915_TILING_NONE	0
@@ -595,7 +595,7 @@
  
 struct drm_i915_gem_set_tiling {
 	/** Handle of the buffer to have its tiling state updated */
-	uint32_t handle;
+	__u32 handle;
  
 	/**
 	 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
  
  
  
  
  
  
  
@@ -609,47 +609,47 @@
 	 *
 	 * Buffer contents become undefined when changing tiling_mode.
 	 */
-	uint32_t tiling_mode;
+	__u32 tiling_mode;
  
 	/**
 	 * Stride in bytes for the object when in I915_TILING_X or
 	 * I915_TILING_Y.
 	 */
-	uint32_t stride;
+	__u32 stride;
  
 	/**
 	 * Returned address bit 6 swizzling required for CPU access through
 	 * mmap mapping.
 	 */
-	uint32_t swizzle_mode;
+	__u32 swizzle_mode;
 };
  
 struct drm_i915_gem_get_tiling {
 	/** Handle of the buffer to get tiling state for. */
-	uint32_t handle;
+	__u32 handle;
  
 	/**
 	 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 	 * I915_TILING_Y).
 	 */
-	uint32_t tiling_mode;
+	__u32 tiling_mode;
  
 	/**
 	 * Returned address bit 6 swizzling required for CPU access through
 	 * mmap mapping.
 	 */
-	uint32_t swizzle_mode;
+	__u32 swizzle_mode;
 };
  
 struct drm_i915_gem_get_aperture {
 	/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
-	uint64_t aper_size;
+	__u64 aper_size;
  
 	/**
 	 * Available space in the aperture used by i915_gem_execbuffer, in
 	 * bytes
 	 */
-	uint64_t aper_available_size;
+	__u64 aper_available_size;
 };
  
 #endif				/* _I915_DRM_H_ */
@@ -35,6 +35,8 @@
 #ifndef __MGA_DRM_H__
 #define __MGA_DRM_H__
  
+#include <linux/types.h>
+
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (mga_sarea.h)
  */
@@ -255,8 +257,8 @@
 #define DRM_IOCTL_MGA_ILOAD    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
 #define DRM_IOCTL_MGA_BLIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
 #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
-#define DRM_IOCTL_MGA_SET_FENCE     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
-#define DRM_IOCTL_MGA_WAIT_FENCE    DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
+#define DRM_IOCTL_MGA_SET_FENCE     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
+#define DRM_IOCTL_MGA_WAIT_FENCE    DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
 #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
  
 typedef struct _drm_mga_warp_index {
@@ -310,7 +312,7 @@
 	 */
 	/*@{ */
 	unsigned long texture_handle; /**< Handle used to map AGP textures. */
-	uint32_t texture_size;	      /**< Size of the AGP texture region. */
+	__u32 texture_size;	      /**< Size of the AGP texture region. */
 	/*@} */
  
 	/**
@@ -319,7 +321,7 @@
 	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
 	 * filled in with the actual AGP mode.  If AGP was not available
 	 */
-	uint32_t primary_size;
+	__u32 primary_size;
  
 	/**
 	 * Requested number of secondary DMA buffers.
@@ -329,7 +331,7 @@
 	 * allocated.  Particularly when PCI DMA is used, this may be
 	 * (subtantially) less than the number requested.
 	 */
-	uint32_t secondary_bin_count;
+	__u32 secondary_bin_count;
  
 	/**
 	 * Requested size of each secondary DMA buffer.
@@ -338,7 +340,7 @@
 	 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
 	 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
 	 */
-	uint32_t secondary_bin_size;
+	__u32 secondary_bin_size;
  
 	/**
 	 * Bit-wise mask of AGPSTAT2_* values.  Currently only \c AGPSTAT2_1X,
  
@@ -350,12 +352,12 @@
 	 * filled in with the actual AGP mode.  If AGP was not available
 	 * (i.e., PCI DMA was used), this value will be zero.
 	 */
-	uint32_t agp_mode;
+	__u32 agp_mode;
  
 	/**
 	 * Desired AGP GART size, measured in megabytes.
 	 */
-	uint8_t agp_size;
+	__u8 agp_size;
 } drm_mga_dma_bootstrap_t;
  
 typedef struct drm_mga_clear {
@@ -33,6 +33,8 @@
 #ifndef __RADEON_DRM_H__
 #define __RADEON_DRM_H__
  
+#include <linux/types.h>
+
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the X server file (radeon_sarea.h)
  */
@@ -722,7 +724,7 @@
  
 typedef struct drm_radeon_setparam {
 	unsigned int param;
-	int64_t value;
+	__s64 value;
 } drm_radeon_setparam_t;
  
 #define RADEON_SETPARAM_FB_LOCATION    1	/* determined framebuffer location */
@@ -24,6 +24,8 @@
 #ifndef _VIA_DRM_H_
 #define _VIA_DRM_H_
  
+#include <linux/types.h>
+
 /* WARNING: These defines must be the same as what the Xserver uses.
  * if you change them, you must change the defines in the Xserver.
  */
  
  
@@ -114,19 +116,19 @@
 #define VIA_MEM_UNKNOWN 4
  
 typedef struct {
-	uint32_t offset;
-	uint32_t size;
+	__u32 offset;
+	__u32 size;
 } drm_via_agp_t;
  
 typedef struct {
-	uint32_t offset;
-	uint32_t size;
+	__u32 offset;
+	__u32 size;
 } drm_via_fb_t;
  
 typedef struct {
-	uint32_t context;
-	uint32_t type;
-	uint32_t size;
+	__u32 context;
+	__u32 type;
+	__u32 size;
 	unsigned long index;
 	unsigned long offset;
 } drm_via_mem_t;
@@ -148,9 +150,9 @@
 		VIA_FUTEX_WAIT = 0x00,
 		VIA_FUTEX_WAKE = 0X01
 	} func;
-	uint32_t ms;
-	uint32_t lock;
-	uint32_t val;
+	__u32 ms;
+	__u32 lock;
+	__u32 val;
 } drm_via_futex_t;
  
 typedef struct _drm_via_dma_init {
@@ -211,7 +213,7 @@
 		VIA_CMDBUF_LAG = 0x02
 	} func;
 	int wait;
-	uint32_t size;
+	__u32 size;
 } drm_via_cmdbuf_size_t;
  
 typedef enum {
@@ -236,8 +238,8 @@
 struct drm_via_wait_irq_request {
 	unsigned irq;
 	via_irq_seq_type_t type;
-	uint32_t sequence;
-	uint32_t signal;
+	__u32 sequence;
+	__u32 signal;
 };
  
 typedef union drm_via_irqwait {
@@ -246,7 +248,7 @@
 } drm_via_irqwait_t;
  
 typedef struct drm_via_blitsync {
-	uint32_t sync_handle;
+	__u32 sync_handle;
 	unsigned engine;
 } drm_via_blitsync_t;
  
  
  
  
@@ -257,16 +259,16 @@
  */
  
 typedef struct drm_via_dmablit {
-	uint32_t num_lines;
-	uint32_t line_length;
+	__u32 num_lines;
+	__u32 line_length;
  
-	uint32_t fb_addr;
-	uint32_t fb_stride;
+	__u32 fb_addr;
+	__u32 fb_stride;
  
 	unsigned char *mem_addr;
-	uint32_t mem_stride;
+	__u32 mem_stride;
  
-	uint32_t flags;
+	__u32 flags;
 	int to_fb;
  
 	drm_via_blitsync_t sync;
...	...	@@ -36,8 +36,7 @@
36	36	#ifndef _DRM_H_
37	37	#define _DRM_H_
38	38
39		-#if defined(__KERNEL__)
40		-#endif
	39	+#include <linux/types.h>
41	40	#include <asm/ioctl.h> /* For _IO* macros */
42	41	#define DRM_IOCTL_NR(n) _IOC_NR(n)
43	42	#define DRM_IOC_VOID _IOC_NONE
...	...	@@ -497,8 +496,8 @@
497	496	* \sa drmModesetCtl().
498	497	*/
499	498	struct drm_modeset_ctl {
500		- uint32_t crtc;
501		- uint32_t cmd;
	499	+ __u32 crtc;
	500	+ __u32 cmd;
502	501	};
503	502
504	503	/**
505	504
506	505
507	506
508	507
509	508
...	...	@@ -574,29 +573,29 @@
574	573	/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
575	574	struct drm_gem_close {
576	575	/** Handle of the object to be closed. */
577		- uint32_t handle;
578		- uint32_t pad;
	576	+ __u32 handle;
	577	+ __u32 pad;
579	578	};
580	579
581	580	/** DRM_IOCTL_GEM_FLINK ioctl argument type */
582	581	struct drm_gem_flink {
583	582	/** Handle for the object being named */
584		- uint32_t handle;
	583	+ __u32 handle;
585	584
586	585	/** Returned global name */
587		- uint32_t name;
	586	+ __u32 name;
588	587	};
589	588
590	589	/** DRM_IOCTL_GEM_OPEN ioctl argument type */
591	590	struct drm_gem_open {
592	591	/** Name of object being opened */
593		- uint32_t name;
	592	+ __u32 name;
594	593
595	594	/** Returned handle for the object */
596		- uint32_t handle;
	595	+ __u32 handle;
597	596
598	597	/** Returned size of the object */
599		- uint64_t size;
	598	+ __u64 size;
600	599	};
601	600
602	601	#include "drm_mode.h"
...	...	@@ -27,11 +27,8 @@
27	27	#ifndef _DRM_MODE_H
28	28	#define _DRM_MODE_H
29	29
30		-#if !defined(__KERNEL__) && !defined(_KERNEL)
31		-#include <stdint.h>
32		-#else
33	30	#include <linux/kernel.h>
34		-#endif
	31	+#include <linux/types.h>
35	32
36	33	#define DRM_DISPLAY_INFO_LEN 32
37	34	#define DRM_CONNECTOR_NAME_LEN 32
38	35
39	36
40	37
41	38
42	39
43	40
44	41
...	...	@@ -81,41 +78,41 @@
81	78	#define DRM_MODE_DITHERING_ON 1
82	79
83	80	struct drm_mode_modeinfo {
84		- uint32_t clock;
85		- uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew;
86		- uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan;
	81	+ __u32 clock;
	82	+ __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	83	+ __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
87	84
88		- uint32_t vrefresh; /* vertical refresh * 1000 */
	85	+ __u32 vrefresh; /* vertical refresh * 1000 */
89	86
90		- uint32_t flags;
91		- uint32_t type;
	87	+ __u32 flags;
	88	+ __u32 type;
92	89	char name[DRM_DISPLAY_MODE_LEN];
93	90	};
94	91
95	92	struct drm_mode_card_res {
96		- uint64_t fb_id_ptr;
97		- uint64_t crtc_id_ptr;
98		- uint64_t connector_id_ptr;
99		- uint64_t encoder_id_ptr;
100		- uint32_t count_fbs;
101		- uint32_t count_crtcs;
102		- uint32_t count_connectors;
103		- uint32_t count_encoders;
104		- uint32_t min_width, max_width;
105		- uint32_t min_height, max_height;
	93	+ __u64 fb_id_ptr;
	94	+ __u64 crtc_id_ptr;
	95	+ __u64 connector_id_ptr;
	96	+ __u64 encoder_id_ptr;
	97	+ __u32 count_fbs;
	98	+ __u32 count_crtcs;
	99	+ __u32 count_connectors;
	100	+ __u32 count_encoders;
	101	+ __u32 min_width, max_width;
	102	+ __u32 min_height, max_height;
106	103	};
107	104
108	105	struct drm_mode_crtc {
109		- uint64_t set_connectors_ptr;
110		- uint32_t count_connectors;
	106	+ __u64 set_connectors_ptr;
	107	+ __u32 count_connectors;
111	108
112		- uint32_t crtc_id; /*< Id /
113		- uint32_t fb_id; /*< Id of framebuffer /
	109	+ __u32 crtc_id; /*< Id /
	110	+ __u32 fb_id; /*< Id of framebuffer /
114	111
115		- uint32_t x, y; /*< Position on the frameuffer /
	112	+ __u32 x, y; /*< Position on the frameuffer /
116	113
117		- uint32_t gamma_size;
118		- uint32_t mode_valid;
	114	+ __u32 gamma_size;
	115	+ __u32 mode_valid;
119	116	struct drm_mode_modeinfo mode;
120	117	};
121	118
122	119
123	120
...	...	@@ -126,13 +123,13 @@
126	123	#define DRM_MODE_ENCODER_TVDAC 4
127	124
128	125	struct drm_mode_get_encoder {
129		- uint32_t encoder_id;
130		- uint32_t encoder_type;
	126	+ __u32 encoder_id;
	127	+ __u32 encoder_type;
131	128
132		- uint32_t crtc_id; /*< Id of crtc /
	129	+ __u32 crtc_id; /*< Id of crtc /
133	130
134		- uint32_t possible_crtcs;
135		- uint32_t possible_clones;
	131	+ __u32 possible_crtcs;
	132	+ __u32 possible_clones;
136	133	};
137	134
138	135	/* This is for connectors with multiple signal types. */
139	136
140	137
141	138
...	...	@@ -161,23 +158,23 @@
161	158
162	159	struct drm_mode_get_connector {
163	160
164		- uint64_t encoders_ptr;
165		- uint64_t modes_ptr;
166		- uint64_t props_ptr;
167		- uint64_t prop_values_ptr;
	161	+ __u64 encoders_ptr;
	162	+ __u64 modes_ptr;
	163	+ __u64 props_ptr;
	164	+ __u64 prop_values_ptr;
168	165
169		- uint32_t count_modes;
170		- uint32_t count_props;
171		- uint32_t count_encoders;
	166	+ __u32 count_modes;
	167	+ __u32 count_props;
	168	+ __u32 count_encoders;
172	169
173		- uint32_t encoder_id; /*< Current Encoder /
174		- uint32_t connector_id; /*< Id /
175		- uint32_t connector_type;
176		- uint32_t connector_type_id;
	170	+ __u32 encoder_id; /*< Current Encoder /
	171	+ __u32 connector_id; /*< Id /
	172	+ __u32 connector_type;
	173	+ __u32 connector_type_id;
177	174
178		- uint32_t connection;
179		- uint32_t mm_width, mm_height; /*< HxW in millimeters /
180		- uint32_t subpixel;
	175	+ __u32 connection;
	176	+ __u32 mm_width, mm_height; /*< HxW in millimeters /
	177	+ __u32 subpixel;
181	178	};
182	179
183	180	#define DRM_MODE_PROP_PENDING (1<<0)
184	181
185	182
186	183
187	184
188	185
189	186
190	187
191	188
...	...	@@ -187,46 +184,46 @@
187	184	#define DRM_MODE_PROP_BLOB (1<<4)
188	185
189	186	struct drm_mode_property_enum {
190		- uint64_t value;
	187	+ __u64 value;
191	188	char name[DRM_PROP_NAME_LEN];
192	189	};
193	190
194	191	struct drm_mode_get_property {
195		- uint64_t values_ptr; /* values and blob lengths */
196		- uint64_t enum_blob_ptr; /* enum and blob id ptrs */
	192	+ __u64 values_ptr; /* values and blob lengths */
	193	+ __u64 enum_blob_ptr; /* enum and blob id ptrs */
197	194
198		- uint32_t prop_id;
199		- uint32_t flags;
	195	+ __u32 prop_id;
	196	+ __u32 flags;
200	197	char name[DRM_PROP_NAME_LEN];
201	198
202		- uint32_t count_values;
203		- uint32_t count_enum_blobs;
	199	+ __u32 count_values;
	200	+ __u32 count_enum_blobs;
204	201	};
205	202
206	203	struct drm_mode_connector_set_property {
207		- uint64_t value;
208		- uint32_t prop_id;
209		- uint32_t connector_id;
	204	+ __u64 value;
	205	+ __u32 prop_id;
	206	+ __u32 connector_id;
210	207	};
211	208
212	209	struct drm_mode_get_blob {
213		- uint32_t blob_id;
214		- uint32_t length;
215		- uint64_t data;
	210	+ __u32 blob_id;
	211	+ __u32 length;
	212	+ __u64 data;
216	213	};
217	214
218	215	struct drm_mode_fb_cmd {
219		- uint32_t fb_id;
220		- uint32_t width, height;
221		- uint32_t pitch;
222		- uint32_t bpp;
223		- uint32_t depth;
	216	+ __u32 fb_id;
	217	+ __u32 width, height;
	218	+ __u32 pitch;
	219	+ __u32 bpp;
	220	+ __u32 depth;
224	221	/* driver specific handle */
225		- uint32_t handle;
	222	+ __u32 handle;
226	223	};
227	224
228	225	struct drm_mode_mode_cmd {
229		- uint32_t connector_id;
	226	+ __u32 connector_id;
230	227	struct drm_mode_modeinfo mode;
231	228	};
232	229
233	230
234	231
235	232
...	...	@@ -248,24 +245,24 @@
248	245	* y
249	246	*/
250	247	struct drm_mode_cursor {
251		- uint32_t flags;
252		- uint32_t crtc_id;
253		- int32_t x;
254		- int32_t y;
255		- uint32_t width;
256		- uint32_t height;
	248	+ __u32 flags;
	249	+ __u32 crtc_id;
	250	+ __s32 x;
	251	+ __s32 y;
	252	+ __u32 width;
	253	+ __u32 height;
257	254	/* driver specific handle */
258		- uint32_t handle;
	255	+ __u32 handle;
259	256	};
260	257
261	258	struct drm_mode_crtc_lut {
262		- uint32_t crtc_id;
263		- uint32_t gamma_size;
	259	+ __u32 crtc_id;
	260	+ __u32 gamma_size;
264	261
265	262	/* pointers to arrays */
266		- uint64_t red;
267		- uint64_t green;
268		- uint64_t blue;
	263	+ __u64 red;
	264	+ __u64 green;
	265	+ __u64 blue;
269	266	};
270	267
271	268	#endif
...	...	@@ -30,7 +30,7 @@
30	30	/* Please note that modifications to all structs defined here are
31	31	* subject to backwards-compatibility constraints.
32	32	*/
33		-
	33	+#include <linux/types.h>
34	34	#include "drm.h"
35	35
36	36	/* Each region is a minimum of 16k, and there are at most 255 of them.
37	37
...	...	@@ -116,15 +116,15 @@
116	116
117	117	/* fill out some space for old userspace triple buffer */
118	118	drm_handle_t unused_handle;
119		- uint32_t unused1, unused2, unused3;
	119	+ __u32 unused1, unused2, unused3;
120	120
121	121	/* buffer object handles for static buffers. May change
122	122	* over the lifetime of the client.
123	123	*/
124		- uint32_t front_bo_handle;
125		- uint32_t back_bo_handle;
126		- uint32_t unused_bo_handle;
127		- uint32_t depth_bo_handle;
	124	+ __u32 front_bo_handle;
	125	+ __u32 back_bo_handle;
	126	+ __u32 unused_bo_handle;
	127	+ __u32 depth_bo_handle;
128	128
129	129	} drm_i915_sarea_t;
130	130
...	...	@@ -325,7 +325,7 @@
325	325	} drm_i915_vblank_swap_t;
326	326
327	327	typedef struct drm_i915_hws_addr {
328		- uint64_t addr;
	328	+ __u64 addr;
329	329	} drm_i915_hws_addr_t;
330	330
331	331	struct drm_i915_gem_init {
332	332
...	...	@@ -333,12 +333,12 @@
333	333	* Beginning offset in the GTT to be managed by the DRM memory
334	334	* manager.
335	335	*/
336		- uint64_t gtt_start;
	336	+ __u64 gtt_start;
337	337	/**
338	338	* Ending offset in the GTT to be managed by the DRM memory
339	339	* manager.
340	340	*/
341		- uint64_t gtt_end;
	341	+ __u64 gtt_end;
342	342	};
343	343
344	344	struct drm_i915_gem_create {
345	345
346	346
347	347
348	348
349	349
350	350
351	351
352	352
353	353
354	354
355	355
356	356
357	357
358	358
359	359
360	360
361	361
362	362
363	363
...	...	@@ -347,94 +347,94 @@
347	347	*
348	348	* The (page-aligned) allocated size for the object will be returned.
349	349	*/
350		- uint64_t size;
	350	+ __u64 size;
351	351	/**
352	352	* Returned handle for the object.
353	353	*
354	354	* Object handles are nonzero.
355	355	*/
356		- uint32_t handle;
357		- uint32_t pad;
	356	+ __u32 handle;
	357	+ __u32 pad;
358	358	};
359	359
360	360	struct drm_i915_gem_pread {
361	361	/** Handle for the object being read. */
362		- uint32_t handle;
363		- uint32_t pad;
	362	+ __u32 handle;
	363	+ __u32 pad;
364	364	/** Offset into the object to read from */
365		- uint64_t offset;
	365	+ __u64 offset;
366	366	/** Length of data to read */
367		- uint64_t size;
	367	+ __u64 size;
368	368	/**
369	369	* Pointer to write the data into.
370	370	*
371	371	* This is a fixed-size type for 32/64 compatibility.
372	372	*/
373		- uint64_t data_ptr;
	373	+ __u64 data_ptr;
374	374	};
375	375
376	376	struct drm_i915_gem_pwrite {
377	377	/** Handle for the object being written to. */
378		- uint32_t handle;
379		- uint32_t pad;
	378	+ __u32 handle;
	379	+ __u32 pad;
380	380	/** Offset into the object to write to */
381		- uint64_t offset;
	381	+ __u64 offset;
382	382	/** Length of data to write */
383		- uint64_t size;
	383	+ __u64 size;
384	384	/**
385	385	* Pointer to read the data from.
386	386	*
387	387	* This is a fixed-size type for 32/64 compatibility.
388	388	*/
389		- uint64_t data_ptr;
	389	+ __u64 data_ptr;
390	390	};
391	391
392	392	struct drm_i915_gem_mmap {
393	393	/** Handle for the object being mapped. */
394		- uint32_t handle;
395		- uint32_t pad;
	394	+ __u32 handle;
	395	+ __u32 pad;
396	396	/** Offset in the object to map. */
397		- uint64_t offset;
	397	+ __u64 offset;
398	398	/**
399	399	* Length of data to map.
400	400	*
401	401	* The value will be page-aligned.
402	402	*/
403		- uint64_t size;
	403	+ __u64 size;
404	404	/**
405	405	* Returned pointer the data was mapped at.
406	406	*
407	407	* This is a fixed-size type for 32/64 compatibility.
408	408	*/
409		- uint64_t addr_ptr;
	409	+ __u64 addr_ptr;
410	410	};
411	411
412	412	struct drm_i915_gem_mmap_gtt {
413	413	/** Handle for the object being mapped. */
414		- uint32_t handle;
415		- uint32_t pad;
	414	+ __u32 handle;
	415	+ __u32 pad;
416	416	/**
417	417	* Fake offset to use for subsequent mmap call
418	418	*
419	419	* This is a fixed-size type for 32/64 compatibility.
420	420	*/
421		- uint64_t offset;
	421	+ __u64 offset;
422	422	};
423	423
424	424	struct drm_i915_gem_set_domain {
425	425	/** Handle for the object */
426		- uint32_t handle;
	426	+ __u32 handle;
427	427
428	428	/** New read domains */
429		- uint32_t read_domains;
	429	+ __u32 read_domains;
430	430
431	431	/** New write domain */
432		- uint32_t write_domain;
	432	+ __u32 write_domain;
433	433	};
434	434
435	435	struct drm_i915_gem_sw_finish {
436	436	/** Handle for the object */
437		- uint32_t handle;
	437	+ __u32 handle;
438	438	};
439	439
440	440	struct drm_i915_gem_relocation_entry {
441	441
442	442
...	...	@@ -446,16 +446,16 @@
446	446	* a relocation list for state buffers and not re-write it per
447	447	* exec using the buffer.
448	448	*/
449		- uint32_t target_handle;
	449	+ __u32 target_handle;
450	450
451	451	/**
452	452	* Value to be added to the offset of the target buffer to make up
453	453	* the relocation entry.
454	454	*/
455		- uint32_t delta;
	455	+ __u32 delta;
456	456
457	457	/** Offset in the buffer the relocation entry will be written into */
458		- uint64_t offset;
	458	+ __u64 offset;
459	459
460	460	/**
461	461	* Offset value of the target buffer that the relocation entry was last
462	462
...	...	@@ -465,12 +465,12 @@
465	465	* and writing the relocation. This value is written back out by
466	466	* the execbuffer ioctl when the relocation is written.
467	467	*/
468		- uint64_t presumed_offset;
	468	+ __u64 presumed_offset;
469	469
470	470	/**
471	471	* Target memory domains read by this operation.
472	472	*/
473		- uint32_t read_domains;
	473	+ __u32 read_domains;
474	474
475	475	/**
476	476	* Target memory domains written by this operation.
...	...	@@ -479,7 +479,7 @@
479	479	* execbuffer operation, so that where there are conflicts,
480	480	* the application will get -EINVAL back.
481	481	*/
482		- uint32_t write_domain;
	482	+ __u32 write_domain;
483	483	};
484	484
485	485	/** @{
486	486
487	487
488	488
489	489
...	...	@@ -510,24 +510,24 @@
510	510	* User's handle for a buffer to be bound into the GTT for this
511	511	* operation.
512	512	*/
513		- uint32_t handle;
	513	+ __u32 handle;
514	514
515	515	/** Number of relocations to be performed on this buffer */
516		- uint32_t relocation_count;
	516	+ __u32 relocation_count;
517	517	/**
518	518	* Pointer to array of struct drm_i915_gem_relocation_entry containing
519	519	* the relocations to be performed in this buffer.
520	520	*/
521		- uint64_t relocs_ptr;
	521	+ __u64 relocs_ptr;
522	522
523	523	/** Required alignment in graphics aperture */
524		- uint64_t alignment;
	524	+ __u64 alignment;
525	525
526	526	/**
527	527	* Returned value of the updated offset of the object, for future
528	528	* presumed_offset writes.
529	529	*/
530		- uint64_t offset;
	530	+ __u64 offset;
531	531	};
532	532
533	533	struct drm_i915_gem_execbuffer {
534	534
535	535
536	536
537	537
538	538
539	539
540	540
541	541
542	542
...	...	@@ -541,44 +541,44 @@
541	541	* a buffer is performing refer to buffers that have already appeared
542	542	* in the validate list.
543	543	*/
544		- uint64_t buffers_ptr;
545		- uint32_t buffer_count;
	544	+ __u64 buffers_ptr;
	545	+ __u32 buffer_count;
546	546
547	547	/** Offset in the batchbuffer to start execution from. */
548		- uint32_t batch_start_offset;
	548	+ __u32 batch_start_offset;
549	549	/** Bytes used in batchbuffer from batch_start_offset */
550		- uint32_t batch_len;
551		- uint32_t DR1;
552		- uint32_t DR4;
553		- uint32_t num_cliprects;
	550	+ __u32 batch_len;
	551	+ __u32 DR1;
	552	+ __u32 DR4;
	553	+ __u32 num_cliprects;
554	554	/** This is a struct drm_clip_rect cliprects /
555		- uint64_t cliprects_ptr;
	555	+ __u64 cliprects_ptr;
556	556	};
557	557
558	558	struct drm_i915_gem_pin {
559	559	/** Handle of the buffer to be pinned. */
560		- uint32_t handle;
561		- uint32_t pad;
	560	+ __u32 handle;
	561	+ __u32 pad;
562	562
563	563	/** alignment required within the aperture */
564		- uint64_t alignment;
	564	+ __u64 alignment;
565	565
566	566	/** Returned GTT offset of the buffer. */
567		- uint64_t offset;
	567	+ __u64 offset;
568	568	};
569	569
570	570	struct drm_i915_gem_unpin {
571	571	/** Handle of the buffer to be unpinned. */
572		- uint32_t handle;
573		- uint32_t pad;
	572	+ __u32 handle;
	573	+ __u32 pad;
574	574	};
575	575
576	576	struct drm_i915_gem_busy {
577	577	/** Handle of the buffer to check for busy */
578		- uint32_t handle;
	578	+ __u32 handle;
579	579
580	580	/** Return busy status (1 if busy, 0 if idle) */
581		- uint32_t busy;
	581	+ __u32 busy;
582	582	};
583	583
584	584	#define I915_TILING_NONE 0
...	...	@@ -595,7 +595,7 @@
595	595
596	596	struct drm_i915_gem_set_tiling {
597	597	/** Handle of the buffer to have its tiling state updated */
598		- uint32_t handle;
	598	+ __u32 handle;
599	599
600	600	/**
601	601	* Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
602	602
603	603
604	604
605	605
606	606
607	607
608	608
...	...	@@ -609,47 +609,47 @@
609	609	*
610	610	* Buffer contents become undefined when changing tiling_mode.
611	611	*/
612		- uint32_t tiling_mode;
	612	+ __u32 tiling_mode;
613	613
614	614	/**
615	615	* Stride in bytes for the object when in I915_TILING_X or
616	616	* I915_TILING_Y.
617	617	*/
618		- uint32_t stride;
	618	+ __u32 stride;
619	619
620	620	/**
621	621	* Returned address bit 6 swizzling required for CPU access through
622	622	* mmap mapping.
623	623	*/
624		- uint32_t swizzle_mode;
	624	+ __u32 swizzle_mode;
625	625	};
626	626
627	627	struct drm_i915_gem_get_tiling {
628	628	/** Handle of the buffer to get tiling state for. */
629		- uint32_t handle;
	629	+ __u32 handle;
630	630
631	631	/**
632	632	* Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
633	633	* I915_TILING_Y).
634	634	*/
635		- uint32_t tiling_mode;
	635	+ __u32 tiling_mode;
636	636
637	637	/**
638	638	* Returned address bit 6 swizzling required for CPU access through
639	639	* mmap mapping.
640	640	*/
641		- uint32_t swizzle_mode;
	641	+ __u32 swizzle_mode;
642	642	};
643	643
644	644	struct drm_i915_gem_get_aperture {
645	645	/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
646		- uint64_t aper_size;
	646	+ __u64 aper_size;
647	647
648	648	/**
649	649	* Available space in the aperture used by i915_gem_execbuffer, in
650	650	* bytes
651	651	*/
652		- uint64_t aper_available_size;
	652	+ __u64 aper_available_size;
653	653	};
654	654
655	655	#endif /* _I915_DRM_H_ */
...	...	@@ -35,6 +35,8 @@
35	35	#ifndef __MGA_DRM_H__
36	36	#define __MGA_DRM_H__
37	37
	38	+#include <linux/types.h>
	39	+
38	40	/* WARNING: If you change any of these defines, make sure to change the
39	41	* defines in the Xserver file (mga_sarea.h)
40	42	*/
...	...	@@ -255,8 +257,8 @@
255	257	#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
256	258	#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
257	259	#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
258		-#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
259		-#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
	260	+#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
	261	+#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
260	262	#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
261	263
262	264	typedef struct _drm_mga_warp_index {
...	...	@@ -310,7 +312,7 @@
310	312	*/
311	313	/@{ /
312	314	unsigned long texture_handle; /*< Handle used to map AGP textures. /
313		- uint32_t texture_size; /*< Size of the AGP texture region. /
	315	+ __u32 texture_size; /*< Size of the AGP texture region. /
314	316	/@} /
315	317
316	318	/**
...	...	@@ -319,7 +321,7 @@
319	321	* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
320	322	* filled in with the actual AGP mode. If AGP was not available
321	323	*/
322		- uint32_t primary_size;
	324	+ __u32 primary_size;
323	325
324	326	/**
325	327	* Requested number of secondary DMA buffers.
...	...	@@ -329,7 +331,7 @@
329	331	* allocated. Particularly when PCI DMA is used, this may be
330	332	* (subtantially) less than the number requested.
331	333	*/
332		- uint32_t secondary_bin_count;
	334	+ __u32 secondary_bin_count;
333	335
334	336	/**
335	337	* Requested size of each secondary DMA buffer.
...	...	@@ -338,7 +340,7 @@
338	340	* dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
339	341	* to reduce dma_mga_dma_bootstrap::secondary_bin_size.
340	342	*/
341		- uint32_t secondary_bin_size;
	343	+ __u32 secondary_bin_size;
342	344
343	345	/**
344	346	* Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
345	347
...	...	@@ -350,12 +352,12 @@
350	352	* filled in with the actual AGP mode. If AGP was not available
351	353	* (i.e., PCI DMA was used), this value will be zero.
352	354	*/
353		- uint32_t agp_mode;
	355	+ __u32 agp_mode;
354	356
355	357	/**
356	358	* Desired AGP GART size, measured in megabytes.
357	359	*/
358		- uint8_t agp_size;
	360	+ __u8 agp_size;
359	361	} drm_mga_dma_bootstrap_t;
360	362
361	363	typedef struct drm_mga_clear {
...	...	@@ -33,6 +33,8 @@
33	33	#ifndef __RADEON_DRM_H__
34	34	#define __RADEON_DRM_H__
35	35
	36	+#include <linux/types.h>
	37	+
36	38	/* WARNING: If you change any of these defines, make sure to change the
37	39	* defines in the X server file (radeon_sarea.h)
38	40	*/
...	...	@@ -722,7 +724,7 @@
722	724
723	725	typedef struct drm_radeon_setparam {
724	726	unsigned int param;
725		- int64_t value;
	727	+ __s64 value;
726	728	} drm_radeon_setparam_t;
727	729
728	730	#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
...	...	@@ -24,6 +24,8 @@
24	24	#ifndef _VIA_DRM_H_
25	25	#define _VIA_DRM_H_
26	26
	27	+#include <linux/types.h>
	28	+
27	29	/* WARNING: These defines must be the same as what the Xserver uses.
28	30	* if you change them, you must change the defines in the Xserver.
29	31	*/
30	32
31	33
...	...	@@ -114,19 +116,19 @@
114	116	#define VIA_MEM_UNKNOWN 4
115	117
116	118	typedef struct {
117		- uint32_t offset;
118		- uint32_t size;
	119	+ __u32 offset;
	120	+ __u32 size;
119	121	} drm_via_agp_t;
120	122
121	123	typedef struct {
122		- uint32_t offset;
123		- uint32_t size;
	124	+ __u32 offset;
	125	+ __u32 size;
124	126	} drm_via_fb_t;
125	127
126	128	typedef struct {
127		- uint32_t context;
128		- uint32_t type;
129		- uint32_t size;
	129	+ __u32 context;
	130	+ __u32 type;
	131	+ __u32 size;
130	132	unsigned long index;
131	133	unsigned long offset;
132	134	} drm_via_mem_t;
...	...	@@ -148,9 +150,9 @@
148	150	VIA_FUTEX_WAIT = 0x00,
149	151	VIA_FUTEX_WAKE = 0X01
150	152	} func;
151		- uint32_t ms;
152		- uint32_t lock;
153		- uint32_t val;
	153	+ __u32 ms;
	154	+ __u32 lock;
	155	+ __u32 val;
154	156	} drm_via_futex_t;
155	157
156	158	typedef struct _drm_via_dma_init {
...	...	@@ -211,7 +213,7 @@
211	213	VIA_CMDBUF_LAG = 0x02
212	214	} func;
213	215	int wait;
214		- uint32_t size;
	216	+ __u32 size;
215	217	} drm_via_cmdbuf_size_t;
216	218
217	219	typedef enum {
...	...	@@ -236,8 +238,8 @@
236	238	struct drm_via_wait_irq_request {
237	239	unsigned irq;
238	240	via_irq_seq_type_t type;
239		- uint32_t sequence;
240		- uint32_t signal;
	241	+ __u32 sequence;
	242	+ __u32 signal;
241	243	};
242	244
243	245	typedef union drm_via_irqwait {
...	...	@@ -246,7 +248,7 @@
246	248	} drm_via_irqwait_t;
247	249
248	250	typedef struct drm_via_blitsync {
249		- uint32_t sync_handle;
	251	+ __u32 sync_handle;
250	252	unsigned engine;
251	253	} drm_via_blitsync_t;
252	254
253	255
254	256
255	257
...	...	@@ -257,16 +259,16 @@
257	259	*/
258	260
259	261	typedef struct drm_via_dmablit {
260		- uint32_t num_lines;
261		- uint32_t line_length;
	262	+ __u32 num_lines;
	263	+ __u32 line_length;
262	264
263		- uint32_t fb_addr;
264		- uint32_t fb_stride;
	265	+ __u32 fb_addr;
	266	+ __u32 fb_stride;
265	267
266	268	unsigned char *mem_addr;
267		- uint32_t mem_stride;
	269	+ __u32 mem_stride;
268	270
269		- uint32_t flags;
	271	+ __u32 flags;
270	272	int to_fb;
271	273
272	274	drm_via_blitsync_t sync;