ARM: imx: build i.MX6 functions only when needed

The head-v7.S contains a call to the generic cpu_suspend function, which is only available when selected by the i.MX6 code. As pointed out by Shawn Guo, i.MX5 does not actually use any functions defined in head-v7.S. It is also needed only for the i.MX6 power management code and for the SMP code, so we can restrict building this file to situations in which at least one of those two is present. Finally, other platforms with a similar file call it headsmp.S, so we can rename it to the same for consistency. Without this patch, building imx5 standalone results in: arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume': arch/arm/mach-imx/head-v7.S:104: undefined reference to `cpu_resume' Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: Eric Miao <eric.miao@linaro.org> Cc: stable@vger.kernel.org

ARM: imx: build i.MX6 functions only when needed
The head-v7.S contains a call to the generic cpu_suspend function, which is only available when selected by the i.MX6 code. As pointed out by Shawn Guo, i.MX5 does not actually use any functions defined in head-v7.S. It is also needed only for the i.MX6 power management code and for the SMP code, so we can restrict building this file to situations in which at least one of those two is present. Finally, other platforms with a similar file call it headsmp.S, so we can rename it to the same for consistency. Without this patch, building imx5 standalone results in: arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume': arch/arm/mach-imx/head-v7.S:104: undefined reference to `cpu_resume' Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: Eric Miao <eric.miao@linaro.org> Cc: stable@vger.kernel.org
Arnd Bergmann
1 parent f637c4c940
Showing 3 changed files with 109 additions and 110 deletions Side-by-side Diff
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/head-v7.S
arch/arm/mach-imx/headsmp.S
@@ -71,14 +71,13 @@
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-obj-$(CONFIG_CPU_V7) += head-v7.o
-AFLAGS_head-v7.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_SMP) += platsmp.o
+AFLAGS_headsmp.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
  
 ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
 endif
  
 # i.MX5 based machines
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
-
-	.section ".text.head", "ax"
-
-/*
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor.  We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
-	mcr	p15, 2, r0, c0, c0, 0
-	mrc	p15, 1, r0, c0, c0, 0
-
-	ldr	r1, =0x7fff
-	and	r2, r1, r0, lsr #13
-
-	ldr	r1, =0x3ff
-
-	and	r3, r1, r0, lsr #3	@ NumWays - 1
-	add	r2, r2, #1		@ NumSets
-
-	and	r0, r0, #0x7
-	add	r0, r0, #4	@ SetShift
-
-	clz	r1, r3		@ WayShift
-	add	r4, r3, #1	@ NumWays
-1:	sub	r2, r2, #1	@ NumSets--
-	mov	r3, r4		@ Temp = NumWays
-2:	subs	r3, r3, #1	@ Temp--
-	mov	r5, r3, lsl r1
-	mov	r6, r2, lsl r0
-	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-	mcr	p15, 0, r5, c7, c6, 2
-	bgt	2b
-	cmp	r2, #0
-	bgt	1b
-	dsb
-	isb
-	mov	pc, lr
-ENDPROC(v7_invalidate_l1)
-
-#ifdef CONFIG_SMP
-ENTRY(v7_secondary_startup)
-	bl	v7_invalidate_l1
-	b	secondary_startup
-ENDPROC(v7_secondary_startup)
-#endif
-
-#ifdef CONFIG_PM
-/*
- * The following code is located into the .data section.  This is to
- * allow phys_l2x0_saved_regs to be accessed with a relative load
- * as we are running on physical address here.
- */
-	.data
-	.align
-
-#ifdef CONFIG_CACHE_L2X0
-	.macro	pl310_resume
-	ldr	r2, phys_l2x0_saved_regs
-	ldr	r0, [r2, #L2X0_R_PHY_BASE]	@ get physical base of l2x0
-	ldr	r1, [r2, #L2X0_R_AUX_CTRL]	@ get aux_ctrl value
-	str	r1, [r0, #L2X0_AUX_CTRL]	@ restore aux_ctrl
-	mov	r1, #0x1
-	str	r1, [r0, #L2X0_CTRL]		@ re-enable L2
-	.endm
-
-	.globl	phys_l2x0_saved_regs
-phys_l2x0_saved_regs:
-        .long   0
-#else
-	.macro	pl310_resume
-	.endm
-#endif
-
-ENTRY(v7_cpu_resume)
-	bl	v7_invalidate_l1
-	pl310_resume
-	b	cpu_resume
-ENDPROC(v7_cpu_resume)
-#endif
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+
+	.section ".text.head", "ax"
+
+/*
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor.  We fix this by performing an invalidate, rather than a
+ * clean + invalidate, before jumping into the kernel.
+ *
+ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
+ */
+ENTRY(v7_invalidate_l1)
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
+	mcr	p15, 2, r0, c0, c0, 0
+	mrc	p15, 1, r0, c0, c0, 0
+
+	ldr	r1, =0x7fff
+	and	r2, r1, r0, lsr #13
+
+	ldr	r1, =0x3ff
+
+	and	r3, r1, r0, lsr #3	@ NumWays - 1
+	add	r2, r2, #1		@ NumSets
+
+	and	r0, r0, #0x7
+	add	r0, r0, #4	@ SetShift
+
+	clz	r1, r3		@ WayShift
+	add	r4, r3, #1	@ NumWays
+1:	sub	r2, r2, #1	@ NumSets--
+	mov	r3, r4		@ Temp = NumWays
+2:	subs	r3, r3, #1	@ Temp--
+	mov	r5, r3, lsl r1
+	mov	r6, r2, lsl r0
+	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+	mcr	p15, 0, r5, c7, c6, 2
+	bgt	2b
+	cmp	r2, #0
+	bgt	1b
+	dsb
+	isb
+	mov	pc, lr
+ENDPROC(v7_invalidate_l1)
+
+#ifdef CONFIG_SMP
+ENTRY(v7_secondary_startup)
+	bl	v7_invalidate_l1
+	b	secondary_startup
+ENDPROC(v7_secondary_startup)
+#endif
+
+#ifdef CONFIG_PM
+/*
+ * The following code is located into the .data section.  This is to
+ * allow phys_l2x0_saved_regs to be accessed with a relative load
+ * as we are running on physical address here.
+ */
+	.data
+	.align
+
+#ifdef CONFIG_CACHE_L2X0
+	.macro	pl310_resume
+	ldr	r2, phys_l2x0_saved_regs
+	ldr	r0, [r2, #L2X0_R_PHY_BASE]	@ get physical base of l2x0
+	ldr	r1, [r2, #L2X0_R_AUX_CTRL]	@ get aux_ctrl value
+	str	r1, [r0, #L2X0_AUX_CTRL]	@ restore aux_ctrl
+	mov	r1, #0x1
+	str	r1, [r0, #L2X0_CTRL]		@ re-enable L2
+	.endm
+
+	.globl	phys_l2x0_saved_regs
+phys_l2x0_saved_regs:
+        .long   0
+#else
+	.macro	pl310_resume
+	.endm
+#endif
+
+ENTRY(v7_cpu_resume)
+	bl	v7_invalidate_l1
+	pl310_resume
+	b	cpu_resume
+ENDPROC(v7_cpu_resume)
+#endif
...	...	@@ -71,14 +71,13 @@
71	71	obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
72	72	obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
73	73	obj-$(CONFIG_HAVE_IMX_SRC) += src.o
74		-obj-$(CONFIG_CPU_V7) += head-v7.o
75		-AFLAGS_head-v7.o :=-Wa,-march=armv7-a
76		-obj-$(CONFIG_SMP) += platsmp.o
	74	+AFLAGS_headsmp.o :=-Wa,-march=armv7-a
	75	+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
77	76	obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
78	77	obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
79	78
80	79	ifeq ($(CONFIG_PM),y)
81		-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
	80	+obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
82	81	endif
83	82
84	83	# i.MX5 based machines
1		-/*
2		- * Copyright 2011 Freescale Semiconductor, Inc.
3		- * Copyright 2011 Linaro Ltd.
4		- *
5		- * The code contained herein is licensed under the GNU General Public
6		- * License. You may obtain a copy of the GNU General Public License
7		- * Version 2 or later at the following locations:
8		- *
9		- * http://www.opensource.org/licenses/gpl-license.html
10		- * http://www.gnu.org/copyleft/gpl.html
11		- */
12		-
13		-#include <linux/linkage.h>
14		-#include <linux/init.h>
15		-#include <asm/asm-offsets.h>
16		-#include <asm/hardware/cache-l2x0.h>
17		-
18		- .section ".text.head", "ax"
19		-
20		-/*
21		- * The secondary kernel init calls v7_flush_dcache_all before it enables
22		- * the L1; however, the L1 comes out of reset in an undefined state, so
23		- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
24		- * of cache lines with uninitialized data and uninitialized tags to get
25		- * written out to memory, which does really unpleasant things to the main
26		- * processor. We fix this by performing an invalidate, rather than a
27		- * clean + invalidate, before jumping into the kernel.
28		- *
29		- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
30		- * to be called for both secondary cores startup and primary core resume
31		- * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
32		- */
33		-ENTRY(v7_invalidate_l1)
34		- mov r0, #0
35		- mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
36		- mcr p15, 2, r0, c0, c0, 0
37		- mrc p15, 1, r0, c0, c0, 0
38		-
39		- ldr r1, =0x7fff
40		- and r2, r1, r0, lsr #13
41		-
42		- ldr r1, =0x3ff
43		-
44		- and r3, r1, r0, lsr #3 @ NumWays - 1
45		- add r2, r2, #1 @ NumSets
46		-
47		- and r0, r0, #0x7
48		- add r0, r0, #4 @ SetShift
49		-
50		- clz r1, r3 @ WayShift
51		- add r4, r3, #1 @ NumWays
52		-1: sub r2, r2, #1 @ NumSets--
53		- mov r3, r4 @ Temp = NumWays
54		-2: subs r3, r3, #1 @ Temp--
55		- mov r5, r3, lsl r1
56		- mov r6, r2, lsl r0
57		- orr r5, r5, r6 @ Reg = (Temp<<WayShift)\|(NumSets<<SetShift)
58		- mcr p15, 0, r5, c7, c6, 2
59		- bgt 2b
60		- cmp r2, #0
61		- bgt 1b
62		- dsb
63		- isb
64		- mov pc, lr
65		-ENDPROC(v7_invalidate_l1)
66		-
67		-#ifdef CONFIG_SMP
68		-ENTRY(v7_secondary_startup)
69		- bl v7_invalidate_l1
70		- b secondary_startup
71		-ENDPROC(v7_secondary_startup)
72		-#endif
73		-
74		-#ifdef CONFIG_PM
75		-/*
76		- * The following code is located into the .data section. This is to
77		- * allow phys_l2x0_saved_regs to be accessed with a relative load
78		- * as we are running on physical address here.
79		- */
80		- .data
81		- .align
82		-
83		-#ifdef CONFIG_CACHE_L2X0
84		- .macro pl310_resume
85		- ldr r2, phys_l2x0_saved_regs
86		- ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
87		- ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value
88		- str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl
89		- mov r1, #0x1
90		- str r1, [r0, #L2X0_CTRL] @ re-enable L2
91		- .endm
92		-
93		- .globl phys_l2x0_saved_regs
94		-phys_l2x0_saved_regs:
95		- .long 0
96		-#else
97		- .macro pl310_resume
98		- .endm
99		-#endif
100		-
101		-ENTRY(v7_cpu_resume)
102		- bl v7_invalidate_l1
103		- pl310_resume
104		- b cpu_resume
105		-ENDPROC(v7_cpu_resume)
106		-#endif
	1	+/*
	2	+ * Copyright 2011 Freescale Semiconductor, Inc.
	3	+ * Copyright 2011 Linaro Ltd.
	4	+ *
	5	+ * The code contained herein is licensed under the GNU General Public
	6	+ * License. You may obtain a copy of the GNU General Public License
	7	+ * Version 2 or later at the following locations:
	8	+ *
	9	+ * http://www.opensource.org/licenses/gpl-license.html
	10	+ * http://www.gnu.org/copyleft/gpl.html
	11	+ */
	12	+
	13	+#include <linux/linkage.h>
	14	+#include <linux/init.h>
	15	+#include <asm/asm-offsets.h>
	16	+#include <asm/hardware/cache-l2x0.h>
	17	+
	18	+ .section ".text.head", "ax"
	19	+
	20	+/*
	21	+ * The secondary kernel init calls v7_flush_dcache_all before it enables
	22	+ * the L1; however, the L1 comes out of reset in an undefined state, so
	23	+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
	24	+ * of cache lines with uninitialized data and uninitialized tags to get
	25	+ * written out to memory, which does really unpleasant things to the main
	26	+ * processor. We fix this by performing an invalidate, rather than a
	27	+ * clean + invalidate, before jumping into the kernel.
	28	+ *
	29	+ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
	30	+ * to be called for both secondary cores startup and primary core resume
	31	+ * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
	32	+ */
	33	+ENTRY(v7_invalidate_l1)
	34	+ mov r0, #0
	35	+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	36	+ mcr p15, 2, r0, c0, c0, 0
	37	+ mrc p15, 1, r0, c0, c0, 0
	38	+
	39	+ ldr r1, =0x7fff
	40	+ and r2, r1, r0, lsr #13
	41	+
	42	+ ldr r1, =0x3ff
	43	+
	44	+ and r3, r1, r0, lsr #3 @ NumWays - 1
	45	+ add r2, r2, #1 @ NumSets
	46	+
	47	+ and r0, r0, #0x7
	48	+ add r0, r0, #4 @ SetShift
	49	+
	50	+ clz r1, r3 @ WayShift
	51	+ add r4, r3, #1 @ NumWays
	52	+1: sub r2, r2, #1 @ NumSets--
	53	+ mov r3, r4 @ Temp = NumWays
	54	+2: subs r3, r3, #1 @ Temp--
	55	+ mov r5, r3, lsl r1
	56	+ mov r6, r2, lsl r0
	57	+ orr r5, r5, r6 @ Reg = (Temp<<WayShift)\|(NumSets<<SetShift)
	58	+ mcr p15, 0, r5, c7, c6, 2
	59	+ bgt 2b
	60	+ cmp r2, #0
	61	+ bgt 1b
	62	+ dsb
	63	+ isb
	64	+ mov pc, lr
	65	+ENDPROC(v7_invalidate_l1)
	66	+
	67	+#ifdef CONFIG_SMP
	68	+ENTRY(v7_secondary_startup)
	69	+ bl v7_invalidate_l1
	70	+ b secondary_startup
	71	+ENDPROC(v7_secondary_startup)
	72	+#endif
	73	+
	74	+#ifdef CONFIG_PM
	75	+/*
	76	+ * The following code is located into the .data section. This is to
	77	+ * allow phys_l2x0_saved_regs to be accessed with a relative load
	78	+ * as we are running on physical address here.
	79	+ */
	80	+ .data
	81	+ .align
	82	+
	83	+#ifdef CONFIG_CACHE_L2X0
	84	+ .macro pl310_resume
	85	+ ldr r2, phys_l2x0_saved_regs
	86	+ ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
	87	+ ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value
	88	+ str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl
	89	+ mov r1, #0x1
	90	+ str r1, [r0, #L2X0_CTRL] @ re-enable L2
	91	+ .endm
	92	+
	93	+ .globl phys_l2x0_saved_regs
	94	+phys_l2x0_saved_regs:
	95	+ .long 0
	96	+#else
	97	+ .macro pl310_resume
	98	+ .endm
	99	+#endif
	100	+
	101	+ENTRY(v7_cpu_resume)
	102	+ bl v7_invalidate_l1
	103	+ pl310_resume
	104	+ b cpu_resume
	105	+ENDPROC(v7_cpu_resume)
	106	+#endif