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Commit 2431a8154634027ce3915200699f26fb3725a1f2

Authored by Scott Jiang
Committed by Grant Likely
1 parent 128465ca7c
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

spi/spi-bfin5xx: Fix flush of last bit after each spi transfer 

This patch ensures that the last bit of a transfer gets correctly
flushed out of the register.

Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Showing 1 changed file with 4 additions and 1 deletions Side-by-side Diff

drivers/spi/spi-bfin5xx.c
Diff comments   View file @ 2431a81
... ... @@ -587,6 +587,7 @@
587 587 if (message->state == DONE_STATE) {
588 588 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
589 589 message->status = 0;
  590 + bfin_spi_flush(drv_data);
590 591 bfin_spi_giveback(drv_data);
591 592 return;
592 593 }
593 594  
... ... @@ -870,8 +871,10 @@
870 871 message->actual_length += drv_data->len_in_bytes;
871 872 /* Move to next transfer of this msg */
872 873 message->state = bfin_spi_next_transfer(drv_data);
873   - if (drv_data->cs_change)
  874 + if (drv_data->cs_change && message->state != DONE_STATE) {
  875 + bfin_spi_flush(drv_data);
874 876 bfin_spi_cs_deactive(drv_data, chip);
  877 + }
875 878 }
876 879  
877 880 /* Schedule next transfer tasklet */