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Commit 25db711df3258d125dc1209800317e5c0ef3c870

Authored by Benoit Cousson
1 parent 384ebe1c28
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

gpio/omap: Fix IRQ handling for SPARSE_IRQ 

The driver is still relying on internal OMAP IRQ defines that
are not relevant anymore if OMAP is built with SPARSE_IRQ.

Replace the defines with the proper IRQ base number.
Clean some comment style issue.
Remove some hidden and ugly cpu_class_is_omap1() inside the
gpio header.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Tested-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>

Showing 2 changed files with 20 additions and 35 deletions Side-by-side Diff

arch/arm/plat-omap/include/plat/gpio.h
Diff comments   View file @ 25db711
... ... @@ -218,31 +218,15 @@
218 218 extern void omap_set_gpio_debounce_time(int gpio, int enable);
219 219 /*-------------------------------------------------------------------------*/
220 220  
221   -/* Wrappers for "new style" GPIO calls, using the new infrastructure
  221 +/*
  222 + * Wrappers for "new style" GPIO calls, using the new infrastructure
222 223 * which lets us plug in FPGA, I2C, and other implementations.
223   - * *
  224 + *
224 225 * The original OMAP-specific calls should eventually be removed.
225 226 */
226 227  
227 228 #include <linux/errno.h>
228 229 #include <asm-generic/gpio.h>
229   -
230   -static inline int irq_to_gpio(unsigned irq)
231   -{
232   - int tmp;
233   -
234   - /* omap1 SOC mpuio */
235   - if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
236   - return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
237   -
238   - /* SOC gpio */
239   - tmp = irq - IH_GPIO_BASE;
240   - if (tmp < OMAP_MAX_GPIO_LINES)
241   - return tmp;
242   -
243   - /* we don't supply reverse mappings for non-SOC gpios */
244   - return -EIO;
245   -}
246 230  
247 231 #endif
drivers/gpio/gpio-omap.c
Diff comments   View file @ 25db711
... ... @@ -93,6 +93,11 @@
93 93 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
94 94 #define GPIO_MOD_CTRL_BIT BIT(0)
95 95  
  96 +static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
  97 +{
  98 + return gpio_irq - bank->irq_base + bank->chip.base;
  99 +}
  100 +
96 101 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
97 102 {
98 103 void __iomem *reg = bank->base;
... ... @@ -369,7 +374,7 @@
369 374  
370 375 static int gpio_irq_type(struct irq_data *d, unsigned type)
371 376 {
372   - struct gpio_bank *bank;
  377 + struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
373 378 unsigned gpio;
374 379 int retval;
375 380 unsigned long flags;
376 381  
... ... @@ -377,13 +382,11 @@
377 382 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
378 383 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
379 384 else
380   - gpio = d->irq - IH_GPIO_BASE;
  385 + gpio = irq_to_gpio(bank, d->irq);
381 386  
382 387 if (type & ~IRQ_TYPE_SENSE_MASK)
383 388 return -EINVAL;
384 389  
385   - bank = irq_data_get_irq_chip_data(d);
386   -
387 390 if (!bank->regs->leveldetect0 &&
388 391 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
389 392 return -EINVAL;
390 393  
... ... @@ -524,14 +527,10 @@
524 527 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
525 528 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
526 529 {
527   - unsigned int gpio = d->irq - IH_GPIO_BASE;
528   - struct gpio_bank *bank;
529   - int retval;
  530 + struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  531 + unsigned int gpio = irq_to_gpio(bank, d->irq);
530 532  
531   - bank = irq_data_get_irq_chip_data(d);
532   - retval = _set_gpio_wakeup(bank, gpio, enable);
533   -
534   - return retval;
  533 + return _set_gpio_wakeup(bank, gpio, enable);
535 534 }
536 535  
537 536 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
538 537  
... ... @@ -675,11 +674,13 @@
675 674  
676 675 gpio_irq = bank->irq_base;
677 676 for (; isr != 0; isr >>= 1, gpio_irq++) {
678   - gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
  677 + int gpio = irq_to_gpio(bank, gpio_irq);
679 678  
680 679 if (!(isr & 1))
681 680 continue;
682 681  
  682 + gpio_index = GPIO_INDEX(bank, gpio);
  683 +
683 684 /*
684 685 * Some chips can't respond to both rising and falling
685 686 * at the same time. If this irq was requested with
686 687  
... ... @@ -705,8 +706,8 @@
705 706  
706 707 static void gpio_irq_shutdown(struct irq_data *d)
707 708 {
708   - unsigned int gpio = d->irq - IH_GPIO_BASE;
709 709 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  710 + unsigned int gpio = irq_to_gpio(bank, d->irq);
710 711 unsigned long flags;
711 712  
712 713 spin_lock_irqsave(&bank->lock, flags);
713 714  
714 715  
715 716  
... ... @@ -716,16 +717,16 @@
716 717  
717 718 static void gpio_ack_irq(struct irq_data *d)
718 719 {
719   - unsigned int gpio = d->irq - IH_GPIO_BASE;
720 720 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  721 + unsigned int gpio = irq_to_gpio(bank, d->irq);
721 722  
722 723 _clear_gpio_irqstatus(bank, gpio);
723 724 }
724 725  
725 726 static void gpio_mask_irq(struct irq_data *d)
726 727 {
727   - unsigned int gpio = d->irq - IH_GPIO_BASE;
728 728 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  729 + unsigned int gpio = irq_to_gpio(bank, d->irq);
729 730 unsigned long flags;
730 731  
731 732 spin_lock_irqsave(&bank->lock, flags);
732 733  
... ... @@ -736,8 +737,8 @@
736 737  
737 738 static void gpio_unmask_irq(struct irq_data *d)
738 739 {
739   - unsigned int gpio = d->irq - IH_GPIO_BASE;
740 740 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  741 + unsigned int gpio = irq_to_gpio(bank, d->irq);
741 742 unsigned int irq_mask = GPIO_BIT(bank, gpio);
742 743 u32 trigger = irqd_get_trigger_type(d);
743 744 unsigned long flags;