[POWERPC] Add briq support to CHRP

The support for Briq machines has been floating around as patches for ages. This cleans it up and adds it once for all. Some of this is based on initial code provided by Karsten Jeppesen <karsten@jeppesens.com> and mostly rewritten from scratch by me. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>

[POWERPC] Add briq support to CHRP
The support for Briq machines has been floating around as patches for ages. This cleans it up and adds it once for all. Some of this is based on initial code provided by Karsten Jeppesen <karsten@jeppesens.com> and mostly rewritten from scratch by me. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Benjamin Herrenschmidt · Paul Mackerras
1 parent f704b8d1f0
Showing 4 changed files with 73 additions and 7 deletions Side-by-side Diff
arch/powerpc/kernel/prom_init.c
arch/powerpc/platforms/chrp/pci.c
arch/powerpc/platforms/chrp/setup.c
include/asm-powerpc/processor.h
@@ -2033,16 +2033,22 @@
 #endif
  
 #ifdef CONFIG_PPC_CHRP
-/* Pegasos lacks the "ranges" property in the isa node */
+/* Pegasos and BriQ lacks the "ranges" property in the isa node */
 static void __init fixup_device_tree_chrp(void)
 {
 	phandle isa;
 	u32 isa_ranges[6];
+	u32 rloc = 0x01006000; /* IO space; PCI device = 12 */
 	char *name;
 	int rc;
  
 	name = "/pci@80000000/isa@c";
 	isa = call_prom("finddevice", 1, 1, ADDR(name));
+	if (!PHANDLE_VALID(isa)) {
+		name = "/pci@ff500000/isa@6";
+		isa = call_prom("finddevice", 1, 1, ADDR(name));
+		rloc = 0x01003000; /* IO space; PCI device = 6 */
+	}
 	if (!PHANDLE_VALID(isa))
 		return;
  
@@ -2054,7 +2060,7 @@
  
 	isa_ranges[0] = 0x1;
 	isa_ranges[1] = 0x0;
-	isa_ranges[2] = 0x01006000;
+	isa_ranges[2] = rloc;
 	isa_ranges[3] = 0x0;
 	isa_ranges[4] = 0x0;
 	isa_ranges[5] = 0x00010000;
@@ -257,7 +257,7 @@
 		else
 			printk(KERN_INFO "PCI buses %d..%d",
 			       bus_range[0], bus_range[1]);
-		printk(" controlled by %s", dev->type);
+		printk(" controlled by %s", dev->full_name);
 		if (!is_longtrail)
 			printk(" at %llx", (unsigned long long)r.start);
 		printk("\n");
@@ -289,6 +289,19 @@
 			setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
 		} else if (is_pegasos == 2) {
 			setup_peg2(hose, dev);
+		} else if (!strncmp(model, "IBM,CPC710", 10)) {
+			setup_indirect_pci(hose,
+					   r.start + 0x000f8000,
+					   r.start + 0x000f8010);
+			if (index == 0) {
+				dma = get_property(dev, "system-dma-base",&len);
+				if (dma && len >= sizeof(*dma)) {
+					dma = (unsigned int *)
+						(((unsigned long)dma) +
+						len - sizeof(*dma));
+						pci_dram_offset = *dma;
+				}
+			}
 		} else {
 			printk("No methods for %s (model %s), using RTAS\n",
 			       dev->full_name, model);
  
  
@@ -306,9 +319,30 @@
 			printk("pci_dram_offset = %lx\n", pci_dram_offset);
 		}
 	}
+}
  
-	/* Do not fixup interrupts from OF tree on pegasos */
-	if (is_pegasos)
-		ppc_md.pcibios_fixup = NULL;
+/* SL82C105 IDE Control/Status Register */
+#define SL82C105_IDECSR                0x40
+
+/* Fixup for Winbond ATA quirk, required for briq */
+void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
+{
+	u8 progif;
+
+	/* If non-briq machines need that fixup too, please speak up */
+	if (!machine_is(chrp) || _chrp_type != _CHRP_briq)
+		return;
+
+	if ((sl82c105->class & 5) != 5) {
+		printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
+		/* Enable SL82C105 PCI native IDE mode */
+		pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
+		pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
+		sl82c105->class |= 0x05;
+		/* Disable SL82C105 second port */
+		pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
+	}
 }
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
+		chrp_pci_fixup_winbond_ata);
@@ -74,6 +74,9 @@
  
 extern unsigned long loops_per_jiffy;
  
+/* To be replaced by RTAS when available */
+static unsigned int *briq_SPOR;
+
 #ifdef CONFIG_SMP
 extern struct smp_ops_t chrp_smp_ops;
 #endif
@@ -92,6 +95,15 @@
 	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
 };
  
+static const char *chrp_names[] = {
+	"Unknown",
+	"","","",
+	"Motorola",
+	"IBM or Longtrail",
+	"Genesi Pegasos",
+	"Total Impact Briq"
+};
+
 void chrp_show_cpuinfo(struct seq_file *m)
 {
 	int i, sdramen;
@@ -229,6 +241,14 @@
 	}
 }
  
+static void briq_restart(char *cmd)
+{
+	local_irq_disable();
+	if (briq_SPOR)
+		out_be32(briq_SPOR, 0);
+	for(;;);
+}
+
 void __init chrp_setup_arch(void)
 {
 	struct device_node *root = find_path_device ("/");
  
@@ -245,11 +265,16 @@
 		_chrp_type = _CHRP_IBM;
 	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
 		_chrp_type = _CHRP_Motorola;
+	} else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
+		_chrp_type = _CHRP_briq;
+		/* Map the SPOR register on briq and change the restart hook */
+		briq_SPOR = (unsigned int *)ioremap(0xff0000e8, 4);
+		ppc_md.restart = briq_restart;
 	} else {
 		/* Let's assume it is an IBM chrp if all else fails */
 		_chrp_type = _CHRP_IBM;
 	}
-	printk("chrp type = %x\n", _chrp_type);
+	printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
  
 	rtas_initialize();
 	if (rtas_token("display-character") >= 0)
@@ -32,6 +32,7 @@
 #define _CHRP_Motorola	0x04	/* motorola chrp, the cobra */
 #define _CHRP_IBM	0x05	/* IBM chrp, the longtrail and longtrail 2 */
 #define _CHRP_Pegasos	0x06	/* Genesi/bplan's Pegasos and Pegasos2 */
+#define _CHRP_briq	0x07	/* TotalImpact's briQ */
  
 #if defined(__KERNEL__) && defined(CONFIG_PPC32)
...	...	@@ -2033,16 +2033,22 @@
2033	2033	#endif
2034	2034
2035	2035	#ifdef CONFIG_PPC_CHRP
2036		-/* Pegasos lacks the "ranges" property in the isa node */
	2036	+/* Pegasos and BriQ lacks the "ranges" property in the isa node */
2037	2037	static void __init fixup_device_tree_chrp(void)
2038	2038	{
2039	2039	phandle isa;
2040	2040	u32 isa_ranges[6];
	2041	+ u32 rloc = 0x01006000; /* IO space; PCI device = 12 */
2041	2042	char *name;
2042	2043	int rc;
2043	2044
2044	2045	name = "/pci@80000000/isa@c";
2045	2046	isa = call_prom("finddevice", 1, 1, ADDR(name));
	2047	+ if (!PHANDLE_VALID(isa)) {
	2048	+ name = "/pci@ff500000/isa@6";
	2049	+ isa = call_prom("finddevice", 1, 1, ADDR(name));
	2050	+ rloc = 0x01003000; /* IO space; PCI device = 6 */
	2051	+ }
2046	2052	if (!PHANDLE_VALID(isa))
2047	2053	return;
2048	2054
...	...	@@ -2054,7 +2060,7 @@
2054	2060
2055	2061	isa_ranges[0] = 0x1;
2056	2062	isa_ranges[1] = 0x0;
2057		- isa_ranges[2] = 0x01006000;
	2063	+ isa_ranges[2] = rloc;
2058	2064	isa_ranges[3] = 0x0;
2059	2065	isa_ranges[4] = 0x0;
2060	2066	isa_ranges[5] = 0x00010000;
...	...	@@ -257,7 +257,7 @@
257	257	else
258	258	printk(KERN_INFO "PCI buses %d..%d",
259	259	bus_range[0], bus_range[1]);
260		- printk(" controlled by %s", dev->type);
	260	+ printk(" controlled by %s", dev->full_name);
261	261	if (!is_longtrail)
262	262	printk(" at %llx", (unsigned long long)r.start);
263	263	printk("\n");
...	...	@@ -289,6 +289,19 @@
289	289	setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
290	290	} else if (is_pegasos == 2) {
291	291	setup_peg2(hose, dev);
	292	+ } else if (!strncmp(model, "IBM,CPC710", 10)) {
	293	+ setup_indirect_pci(hose,
	294	+ r.start + 0x000f8000,
	295	+ r.start + 0x000f8010);
	296	+ if (index == 0) {
	297	+ dma = get_property(dev, "system-dma-base",&len);
	298	+ if (dma && len >= sizeof(*dma)) {
	299	+ dma = (unsigned int *)
	300	+ (((unsigned long)dma) +
	301	+ len - sizeof(*dma));
	302	+ pci_dram_offset = *dma;
	303	+ }
	304	+ }
292	305	} else {
293	306	printk("No methods for %s (model %s), using RTAS\n",
294	307	dev->full_name, model);
295	308
296	309
...	...	@@ -306,9 +319,30 @@
306	319	printk("pci_dram_offset = %lx\n", pci_dram_offset);
307	320	}
308	321	}
	322	+}
309	323
310		- /* Do not fixup interrupts from OF tree on pegasos */
311		- if (is_pegasos)
312		- ppc_md.pcibios_fixup = NULL;
	324	+/* SL82C105 IDE Control/Status Register */
	325	+#define SL82C105_IDECSR 0x40
	326	+
	327	+/* Fixup for Winbond ATA quirk, required for briq */
	328	+void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
	329	+{
	330	+ u8 progif;
	331	+
	332	+ /* If non-briq machines need that fixup too, please speak up */
	333	+ if (!machine_is(chrp) \|\| _chrp_type != _CHRP_briq)
	334	+ return;
	335	+
	336	+ if ((sl82c105->class & 5) != 5) {
	337	+ printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
	338	+ /* Enable SL82C105 PCI native IDE mode */
	339	+ pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
	340	+ pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif \| 0x05);
	341	+ sl82c105->class \|= 0x05;
	342	+ /* Disable SL82C105 second port */
	343	+ pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
	344	+ }
313	345	}
	346	+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
	347	+ chrp_pci_fixup_winbond_ata);
...	...	@@ -74,6 +74,9 @@
74	74
75	75	extern unsigned long loops_per_jiffy;
76	76
	77	+/* To be replaced by RTAS when available */
	78	+static unsigned int *briq_SPOR;
	79	+
77	80	#ifdef CONFIG_SMP
78	81	extern struct smp_ops_t chrp_smp_ops;
79	82	#endif
...	...	@@ -92,6 +95,15 @@
92	95	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
93	96	};
94	97
	98	+static const char *chrp_names[] = {
	99	+ "Unknown",
	100	+ "","","",
	101	+ "Motorola",
	102	+ "IBM or Longtrail",
	103	+ "Genesi Pegasos",
	104	+ "Total Impact Briq"
	105	+};
	106	+
95	107	void chrp_show_cpuinfo(struct seq_file *m)
96	108	{
97	109	int i, sdramen;
...	...	@@ -229,6 +241,14 @@
229	241	}
230	242	}
231	243
	244	+static void briq_restart(char *cmd)
	245	+{
	246	+ local_irq_disable();
	247	+ if (briq_SPOR)
	248	+ out_be32(briq_SPOR, 0);
	249	+ for(;;);
	250	+}
	251	+
232	252	void __init chrp_setup_arch(void)
233	253	{
234	254	struct device_node *root = find_path_device ("/");
235	255
...	...	@@ -245,11 +265,16 @@
245	265	_chrp_type = _CHRP_IBM;
246	266	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
247	267	_chrp_type = _CHRP_Motorola;
	268	+ } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
	269	+ _chrp_type = _CHRP_briq;
	270	+ /* Map the SPOR register on briq and change the restart hook */
	271	+ briq_SPOR = (unsigned int *)ioremap(0xff0000e8, 4);
	272	+ ppc_md.restart = briq_restart;
248	273	} else {
249	274	/* Let's assume it is an IBM chrp if all else fails */
250	275	_chrp_type = _CHRP_IBM;
251	276	}
252		- printk("chrp type = %x\n", _chrp_type);
	277	+ printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
253	278
254	279	rtas_initialize();
255	280	if (rtas_token("display-character") >= 0)
...	...	@@ -32,6 +32,7 @@
32	32	#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
33	33	#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
34	34	#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
	35	+#define _CHRP_briq 0x07 /* TotalImpact's briQ */
35	36
36	37	#if defined(__KERNEL__) && defined(CONFIG_PPC32)
37	38