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Commit 2981795cc0c02d12d0e231bfe22480564b937cd5

Authored by Martyn Welch
Committed by Greg Kroah-Hartman
1 parent e31c51e4a1
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

vme: tsi148: CR/CSR logic arround the wrong way 

The logic in the init routine for the TSI148 is inverted. It isn't switching
on the CR/CSR space when it should be and is reporting it's on when its not.

Correct the logic to do the right thing.

Reported-by: De Roo, Steven <steven.deroo@arcelormittal.com>
Signed-off-by: Martyn Welch <martyn.welch@ge.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 1 changed file with 4 additions and 3 deletions Side-by-side Diff

drivers/vme/bridges/vme_tsi148.c
Diff comments   View file @ 2981795
... ... @@ -2300,12 +2300,13 @@
2300 2300 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
2301 2301  
2302 2302 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2303   - if (crat & TSI148_LCSR_CRAT_EN) {
  2303 + if (crat & TSI148_LCSR_CRAT_EN)
  2304 + dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
  2305 + else {
2304 2306 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
2305 2307 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2306 2308 bridge->base + TSI148_LCSR_CRAT);
2307   - } else
2308   - dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
  2309 + }
2309 2310  
2310 2311 /* If we want flushed, error-checked writes, set up a window
2311 2312 * over the CR/CSR registers. We read from here to safely flush