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Commit 2a5dbead29a7c081a47133eb428440147a6d8d5a

Authored by Vipin Kumar
Committed by David Woodhouse
1 parent 4774fb0a48
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

mtd: nand/fsmc: Remove sparse warnings and errors 

This patch removes the sparse below warnings and errors for nand/fsmc driver
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
warning: incorrect type in initializer (different address spaces)
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
expected struct fsmc_regs *regs
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
got void [noderef] <asn:2>*regs_va

[...]

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

Showing 2 changed files with 111 additions and 123 deletions Side-by-side Diff

drivers/mtd/nand/fsmc_nand.c
Diff comments   View file @ 2a5dbea
... ... @@ -360,28 +360,29 @@
360 360 struct nand_chip *this = mtd->priv;
361 361 struct fsmc_nand_data *host = container_of(mtd,
362 362 struct fsmc_nand_data, mtd);
363   - struct fsmc_regs *regs = host->regs_va;
  363 + void *__iomem *regs = host->regs_va;
364 364 unsigned int bank = host->bank;
365 365  
366 366 if (ctrl & NAND_CTRL_CHANGE) {
  367 + u32 pc;
  368 +
367 369 if (ctrl & NAND_CLE) {
368   - this->IO_ADDR_R = (void __iomem *)host->cmd_va;
369   - this->IO_ADDR_W = (void __iomem *)host->cmd_va;
  370 + this->IO_ADDR_R = host->cmd_va;
  371 + this->IO_ADDR_W = host->cmd_va;
370 372 } else if (ctrl & NAND_ALE) {
371   - this->IO_ADDR_R = (void __iomem *)host->addr_va;
372   - this->IO_ADDR_W = (void __iomem *)host->addr_va;
  373 + this->IO_ADDR_R = host->addr_va;
  374 + this->IO_ADDR_W = host->addr_va;
373 375 } else {
374   - this->IO_ADDR_R = (void __iomem *)host->data_va;
375   - this->IO_ADDR_W = (void __iomem *)host->data_va;
  376 + this->IO_ADDR_R = host->data_va;
  377 + this->IO_ADDR_W = host->data_va;
376 378 }
377 379  
378   - if (ctrl & NAND_NCE) {
379   - writel(readl(&regs->bank_regs[bank].pc) | FSMC_ENABLE,
380   - &regs->bank_regs[bank].pc);
381   - } else {
382   - writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ENABLE,
383   - &regs->bank_regs[bank].pc);
384   - }
  380 + pc = readl(FSMC_NAND_REG(regs, bank, PC));
  381 + if (ctrl & NAND_NCE)
  382 + pc |= FSMC_ENABLE;
  383 + else
  384 + pc &= ~FSMC_ENABLE;
  385 + writel(pc, FSMC_NAND_REG(regs, bank, PC));
385 386 }
386 387  
387 388 mb();
... ... @@ -396,7 +397,7 @@
396 397 * This routine initializes timing parameters related to NAND memory access in
397 398 * FSMC registers
398 399 */
399   -static void fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
  400 +static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
400 401 uint32_t busw, struct fsmc_nand_timings *timings)
401 402 {
402 403 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
403 404  
404 405  
... ... @@ -424,14 +425,14 @@
424 425 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
425 426  
426 427 if (busw)
427   - writel(value | FSMC_DEVWID_16, &regs->bank_regs[bank].pc);
  428 + writel(value | FSMC_DEVWID_16, FSMC_NAND_REG(regs, bank, PC));
428 429 else
429   - writel(value | FSMC_DEVWID_8, &regs->bank_regs[bank].pc);
  430 + writel(value | FSMC_DEVWID_8, FSMC_NAND_REG(regs, bank, PC));
430 431  
431   - writel(readl(&regs->bank_regs[bank].pc) | tclr | tar,
432   - &regs->bank_regs[bank].pc);
433   - writel(thiz | thold | twait | tset, &regs->bank_regs[bank].comm);
434   - writel(thiz | thold | twait | tset, &regs->bank_regs[bank].attrib);
  432 + writel(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
  433 + FSMC_NAND_REG(regs, bank, PC));
  434 + writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, COMM));
  435 + writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, ATTRIB));
435 436 }
436 437  
437 438 /*
438 439  
... ... @@ -441,15 +442,15 @@
441 442 {
442 443 struct fsmc_nand_data *host = container_of(mtd,
443 444 struct fsmc_nand_data, mtd);
444   - struct fsmc_regs *regs = host->regs_va;
  445 + void __iomem *regs = host->regs_va;
445 446 uint32_t bank = host->bank;
446 447  
447   - writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
448   - &regs->bank_regs[bank].pc);
449   - writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCEN,
450   - &regs->bank_regs[bank].pc);
451   - writel(readl(&regs->bank_regs[bank].pc) | FSMC_ECCEN,
452   - &regs->bank_regs[bank].pc);
  448 + writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
  449 + FSMC_NAND_REG(regs, bank, PC));
  450 + writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
  451 + FSMC_NAND_REG(regs, bank, PC));
  452 + writel(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
  453 + FSMC_NAND_REG(regs, bank, PC));
453 454 }
454 455  
455 456 /*
456 457  
... ... @@ -462,13 +463,13 @@
462 463 {
463 464 struct fsmc_nand_data *host = container_of(mtd,
464 465 struct fsmc_nand_data, mtd);
465   - struct fsmc_regs *regs = host->regs_va;
  466 + void __iomem *regs = host->regs_va;
466 467 uint32_t bank = host->bank;
467 468 uint32_t ecc_tmp;
468 469 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
469 470  
470 471 do {
471   - if (readl(&regs->bank_regs[bank].sts) & FSMC_CODE_RDY)
  472 + if (readl(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
472 473 break;
473 474 else
474 475 cond_resched();
475 476  
476 477  
477 478  
... ... @@ -479,25 +480,25 @@
479 480 return -ETIMEDOUT;
480 481 }
481 482  
482   - ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
  483 + ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
483 484 ecc[0] = (uint8_t) (ecc_tmp >> 0);
484 485 ecc[1] = (uint8_t) (ecc_tmp >> 8);
485 486 ecc[2] = (uint8_t) (ecc_tmp >> 16);
486 487 ecc[3] = (uint8_t) (ecc_tmp >> 24);
487 488  
488   - ecc_tmp = readl(&regs->bank_regs[bank].ecc2);
  489 + ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC2));
489 490 ecc[4] = (uint8_t) (ecc_tmp >> 0);
490 491 ecc[5] = (uint8_t) (ecc_tmp >> 8);
491 492 ecc[6] = (uint8_t) (ecc_tmp >> 16);
492 493 ecc[7] = (uint8_t) (ecc_tmp >> 24);
493 494  
494   - ecc_tmp = readl(&regs->bank_regs[bank].ecc3);
  495 + ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC3));
495 496 ecc[8] = (uint8_t) (ecc_tmp >> 0);
496 497 ecc[9] = (uint8_t) (ecc_tmp >> 8);
497 498 ecc[10] = (uint8_t) (ecc_tmp >> 16);
498 499 ecc[11] = (uint8_t) (ecc_tmp >> 24);
499 500  
500   - ecc_tmp = readl(&regs->bank_regs[bank].sts);
  501 + ecc_tmp = readl(FSMC_NAND_REG(regs, bank, STS));
501 502 ecc[12] = (uint8_t) (ecc_tmp >> 16);
502 503  
503 504 return 0;
504 505  
... ... @@ -513,11 +514,11 @@
513 514 {
514 515 struct fsmc_nand_data *host = container_of(mtd,
515 516 struct fsmc_nand_data, mtd);
516   - struct fsmc_regs *regs = host->regs_va;
  517 + void __iomem *regs = host->regs_va;
517 518 uint32_t bank = host->bank;
518 519 uint32_t ecc_tmp;
519 520  
520   - ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
  521 + ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
521 522 ecc[0] = (uint8_t) (ecc_tmp >> 0);
522 523 ecc[1] = (uint8_t) (ecc_tmp >> 8);
523 524 ecc[2] = (uint8_t) (ecc_tmp >> 16);
524 525  
... ... @@ -771,13 +772,13 @@
771 772 struct fsmc_nand_data *host = container_of(mtd,
772 773 struct fsmc_nand_data, mtd);
773 774 struct nand_chip *chip = mtd->priv;
774   - struct fsmc_regs *regs = host->regs_va;
  775 + void __iomem *regs = host->regs_va;
775 776 unsigned int bank = host->bank;
776 777 uint32_t err_idx[8];
777 778 uint32_t num_err, i;
778 779 uint32_t ecc1, ecc2, ecc3, ecc4;
779 780  
780   - num_err = (readl(&regs->bank_regs[bank].sts) >> 10) & 0xF;
  781 + num_err = (readl(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
781 782  
782 783 /* no bit flipping */
783 784 if (likely(num_err == 0))
... ... @@ -820,10 +821,10 @@
820 821 * uint64_t array and error offset indexes are populated in err_idx
821 822 * array
822 823 */
823   - ecc1 = readl(&regs->bank_regs[bank].ecc1);
824   - ecc2 = readl(&regs->bank_regs[bank].ecc2);
825   - ecc3 = readl(&regs->bank_regs[bank].ecc3);
826   - ecc4 = readl(&regs->bank_regs[bank].sts);
  824 + ecc1 = readl(FSMC_NAND_REG(regs, bank, ECC1));
  825 + ecc2 = readl(FSMC_NAND_REG(regs, bank, ECC2));
  826 + ecc3 = readl(FSMC_NAND_REG(regs, bank, ECC3));
  827 + ecc4 = readl(FSMC_NAND_REG(regs, bank, STS));
827 828  
828 829 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
829 830 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
... ... @@ -863,7 +864,6 @@
863 864 struct fsmc_nand_data *host;
864 865 struct mtd_info *mtd;
865 866 struct nand_chip *nand;
866   - struct fsmc_regs *regs;
867 867 struct resource *res;
868 868 dma_cap_mask_t mask;
869 869 int ret = 0;
... ... @@ -976,8 +976,6 @@
976 976 if (host->mode == USE_DMA_ACCESS)
977 977 init_completion(&host->dma_access_complete);
978 978  
979   - regs = host->regs_va;
980   -
981 979 /* Link all private pointers */
982 980 mtd = &host->mtd;
983 981 nand = &host->nand;
... ... @@ -1027,7 +1025,8 @@
1027 1025 break;
1028 1026 }
1029 1027  
1030   - fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16,
  1028 + fsmc_nand_setup(host->regs_va, host->bank,
  1029 + nand->options & NAND_BUSWIDTH_16,
1031 1030 host->dev_timings);
1032 1031  
1033 1032 if (AMBA_REV_BITS(host->pid) >= 8) {
include/linux/mtd/fsmc.h
Diff comments   View file @ 2a5dbea
... ... @@ -32,87 +32,76 @@
32 32 #define FSMC_FLASH_WIDTH8 1
33 33 #define FSMC_FLASH_WIDTH16 2
34 34  
35   -struct fsmc_nor_bank_regs {
36   - uint32_t ctrl;
37   - uint32_t ctrl_tim;
38   -};
  35 +/* fsmc controller registers for NOR flash */
  36 +#define CTRL 0x0
  37 + /* ctrl register definitions */
  38 + #define BANK_ENABLE (1 << 0)
  39 + #define MUXED (1 << 1)
  40 + #define NOR_DEV (2 << 2)
  41 + #define WIDTH_8 (0 << 4)
  42 + #define WIDTH_16 (1 << 4)
  43 + #define RSTPWRDWN (1 << 6)
  44 + #define WPROT (1 << 7)
  45 + #define WRT_ENABLE (1 << 12)
  46 + #define WAIT_ENB (1 << 13)
39 47  
40   -/* ctrl register definitions */
41   -#define BANK_ENABLE (1 << 0)
42   -#define MUXED (1 << 1)
43   -#define NOR_DEV (2 << 2)
44   -#define WIDTH_8 (0 << 4)
45   -#define WIDTH_16 (1 << 4)
46   -#define RSTPWRDWN (1 << 6)
47   -#define WPROT (1 << 7)
48   -#define WRT_ENABLE (1 << 12)
49   -#define WAIT_ENB (1 << 13)
  48 +#define CTRL_TIM 0x4
  49 + /* ctrl_tim register definitions */
50 50  
51   -/* ctrl_tim register definitions */
52   -
53   -struct fsmc_nand_bank_regs {
54   - uint32_t pc;
55   - uint32_t sts;
56   - uint32_t comm;
57   - uint32_t attrib;
58   - uint32_t ioata;
59   - uint32_t ecc1;
60   - uint32_t ecc2;
61   - uint32_t ecc3;
62   -};
63   -
  51 +#define FSMC_NOR_BANK_SZ 0x8
64 52 #define FSMC_NOR_REG_SIZE 0x40
65 53  
66   -struct fsmc_regs {
67   - struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
68   - uint8_t reserved_1[0x40 - 0x20];
69   - struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
70   - uint8_t reserved_2[0xfe0 - 0xc0];
71   - uint32_t peripid0; /* 0xfe0 */
72   - uint32_t peripid1; /* 0xfe4 */
73   - uint32_t peripid2; /* 0xfe8 */
74   - uint32_t peripid3; /* 0xfec */
75   - uint32_t pcellid0; /* 0xff0 */
76   - uint32_t pcellid1; /* 0xff4 */
77   - uint32_t pcellid2; /* 0xff8 */
78   - uint32_t pcellid3; /* 0xffc */
79   -};
  54 +#define FSMC_NOR_REG(base, bank, reg) (base + \
  55 + FSMC_NOR_BANK_SZ * (bank) + \
  56 + reg)
80 57  
81   -#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
  58 +/* fsmc controller registers for NAND flash */
  59 +#define PC 0x00
  60 + /* pc register definitions */
  61 + #define FSMC_RESET (1 << 0)
  62 + #define FSMC_WAITON (1 << 1)
  63 + #define FSMC_ENABLE (1 << 2)
  64 + #define FSMC_DEVTYPE_NAND (1 << 3)
  65 + #define FSMC_DEVWID_8 (0 << 4)
  66 + #define FSMC_DEVWID_16 (1 << 4)
  67 + #define FSMC_ECCEN (1 << 6)
  68 + #define FSMC_ECCPLEN_512 (0 << 7)
  69 + #define FSMC_ECCPLEN_256 (1 << 7)
  70 + #define FSMC_TCLR_1 (1)
  71 + #define FSMC_TCLR_SHIFT (9)
  72 + #define FSMC_TCLR_MASK (0xF)
  73 + #define FSMC_TAR_1 (1)
  74 + #define FSMC_TAR_SHIFT (13)
  75 + #define FSMC_TAR_MASK (0xF)
  76 +#define STS 0x04
  77 + /* sts register definitions */
  78 + #define FSMC_CODE_RDY (1 << 15)
  79 +#define COMM 0x08
  80 + /* comm register definitions */
  81 + #define FSMC_TSET_0 0
  82 + #define FSMC_TSET_SHIFT 0
  83 + #define FSMC_TSET_MASK 0xFF
  84 + #define FSMC_TWAIT_6 6
  85 + #define FSMC_TWAIT_SHIFT 8
  86 + #define FSMC_TWAIT_MASK 0xFF
  87 + #define FSMC_THOLD_4 4
  88 + #define FSMC_THOLD_SHIFT 16
  89 + #define FSMC_THOLD_MASK 0xFF
  90 + #define FSMC_THIZ_1 1
  91 + #define FSMC_THIZ_SHIFT 24
  92 + #define FSMC_THIZ_MASK 0xFF
  93 +#define ATTRIB 0x0C
  94 +#define IOATA 0x10
  95 +#define ECC1 0x14
  96 +#define ECC2 0x18
  97 +#define ECC3 0x1C
  98 +#define FSMC_NAND_BANK_SZ 0x20
82 99  
83   -/* pc register definitions */
84   -#define FSMC_RESET (1 << 0)
85   -#define FSMC_WAITON (1 << 1)
86   -#define FSMC_ENABLE (1 << 2)
87   -#define FSMC_DEVTYPE_NAND (1 << 3)
88   -#define FSMC_DEVWID_8 (0 << 4)
89   -#define FSMC_DEVWID_16 (1 << 4)
90   -#define FSMC_ECCEN (1 << 6)
91   -#define FSMC_ECCPLEN_512 (0 << 7)
92   -#define FSMC_ECCPLEN_256 (1 << 7)
93   -#define FSMC_TCLR_1 (1)
94   -#define FSMC_TCLR_SHIFT (9)
95   -#define FSMC_TCLR_MASK (0xF)
96   -#define FSMC_TAR_1 (1)
97   -#define FSMC_TAR_SHIFT (13)
98   -#define FSMC_TAR_MASK (0xF)
  100 +#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
  101 + (FSMC_NAND_BANK_SZ * (bank)) + \
  102 + reg)
99 103  
100   -/* sts register definitions */
101   -#define FSMC_CODE_RDY (1 << 15)
102   -
103   -/* comm register definitions */
104   -#define FSMC_TSET_0 0
105   -#define FSMC_TSET_SHIFT 0
106   -#define FSMC_TSET_MASK 0xFF
107   -#define FSMC_TWAIT_6 6
108   -#define FSMC_TWAIT_SHIFT 8
109   -#define FSMC_TWAIT_MASK 0xFF
110   -#define FSMC_THOLD_4 4
111   -#define FSMC_THOLD_SHIFT 16
112   -#define FSMC_THOLD_MASK 0xFF
113   -#define FSMC_THIZ_1 1
114   -#define FSMC_THIZ_SHIFT 24
115   -#define FSMC_THIZ_MASK 0xFF
  104 +#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
116 105  
117 106 /*
118 107 * There are 13 bytes of ecc for every 512 byte block in FSMC version 8