Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm: VIDEO: amba clcd: don't disable an already disabled clock ARM: Tighten check for allowable CPSR values ARM: 6329/1: wire up sys_accept4() on ARM ARM: 6328/1: Build with -fno-dwarf2-cfi-asm ARM: 6326/1: kgdb: fix GDB_MAX_REGS no longer used

Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: VIDEO: amba clcd: don't disable an already disabled clock ARM: Tighten check for allowable CPSR values ARM: 6329/1: wire up sys_accept4() on ARM ARM: 6328/1: Build with -fno-dwarf2-cfi-asm ARM: 6326/1: kgdb: fix GDB_MAX_REGS no longer used
Linus Torvalds
2 parents a7c8962bfb 99c796df94
Showing 7 changed files Side-by-side Diff
arch/arm/Makefile
arch/arm/include/asm/ptrace.h
arch/arm/include/asm/unistd.h
arch/arm/kernel/calls.S
arch/arm/kernel/kgdb.c
drivers/video/amba-clcd.c
include/linux/amba/clcd.h
@@ -21,6 +21,9 @@
 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
 KBUILD_CFLAGS	+=$(call cc-option,-marm,)
  
+# Never generate .eh_frame
+KBUILD_CFLAGS	+= $(call cc-option,-fno-dwarf2-cfi-asm)
+
 # Do not use arch/arm/defconfig - it's always outdated.
 # Select a platform tht is kept up-to-date
 KBUILD_DEFCONFIG := versatile_defconfig
@@ -158,15 +158,24 @@
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
-	if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
-		regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
-		return 1;
+	unsigned long mode = regs->ARM_cpsr & MODE_MASK;
+
+	/*
+	 * Always clear the F (FIQ) and A (delayed abort) bits
+	 */
+	regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
+
+	if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
+		if (mode == USR_MODE)
+			return 1;
+		if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
+			return 1;
 	}
  
 	/*
 	 * Force CPSR to something logical...
 	 */
-	regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT;
+	regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
 	if (!(elf_hwcap & HWCAP_26BIT))
 		regs->ARM_cpsr |= USR_MODE;
  
@@ -392,6 +392,7 @@
 #define __NR_rt_tgsigqueueinfo		(__NR_SYSCALL_BASE+363)
 #define __NR_perf_event_open		(__NR_SYSCALL_BASE+364)
 #define __NR_recvmmsg			(__NR_SYSCALL_BASE+365)
+#define __NR_accept4			(__NR_SYSCALL_BASE+366)
  
 /*
  * The following SWIs are ARM private.
@@ -375,6 +375,7 @@
 		CALL(sys_rt_tgsigqueueinfo)
 		CALL(sys_perf_event_open)
 /* 365 */	CALL(sys_recvmmsg)
+		CALL(sys_accept4)
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted
@@ -79,7 +79,7 @@
 		return;
  
 	/* Initialize to zero */
-	for (regno = 0; regno < GDB_MAX_REGS; regno++)
+	for (regno = 0; regno < DBG_MAX_REG_NUM; regno++)
 		gdb_regs[regno] = 0;
  
 	/* Otherwise, we have only some registers from switch_to() */
@@ -80,7 +80,10 @@
 	/*
 	 * Disable CLCD clock source.
 	 */
-	clk_disable(fb->clk);
+	if (fb->clk_enabled) {
+		fb->clk_enabled = false;
+		clk_disable(fb->clk);
+	}
 }
  
 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
@@ -88,7 +91,10 @@
 	/*
 	 * Enable the CLCD clock source.
 	 */
-	clk_enable(fb->clk);
+	if (!fb->clk_enabled) {
+		fb->clk_enabled = true;
+		clk_enable(fb->clk);
+	}
  
 	/*
 	 * Bring up by first enabling..
@@ -150,6 +150,7 @@
 	u16			off_cntl;
 	u32			clcd_cntl;
 	u32			cmap[16];
+	bool			clk_enabled;
 };
  
 static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
...	...	@@ -21,6 +21,9 @@
21	21	# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
22	22	KBUILD_CFLAGS +=$(call cc-option,-marm,)
23	23
	24	+# Never generate .eh_frame
	25	+KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
	26	+
24	27	# Do not use arch/arm/defconfig - it's always outdated.
25	28	# Select a platform tht is kept up-to-date
26	29	KBUILD_DEFCONFIG := versatile_defconfig
...	...	@@ -158,15 +158,24 @@
158	158	*/
159	159	static inline int valid_user_regs(struct pt_regs *regs)
160	160	{
161		- if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
162		- regs->ARM_cpsr &= ~(PSR_F_BIT \| PSR_A_BIT);
163		- return 1;
	161	+ unsigned long mode = regs->ARM_cpsr & MODE_MASK;
	162	+
	163	+ /*
	164	+ * Always clear the F (FIQ) and A (delayed abort) bits
	165	+ */
	166	+ regs->ARM_cpsr &= ~(PSR_F_BIT \| PSR_A_BIT);
	167	+
	168	+ if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
	169	+ if (mode == USR_MODE)
	170	+ return 1;
	171	+ if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
	172	+ return 1;
164	173	}
165	174
166	175	/*
167	176	* Force CPSR to something logical...
168	177	*/
169		- regs->ARM_cpsr &= PSR_f \| PSR_s \| (PSR_x & ~PSR_A_BIT) \| PSR_T_BIT \| MODE32_BIT;
	178	+ regs->ARM_cpsr &= PSR_f \| PSR_s \| PSR_x \| PSR_T_BIT \| MODE32_BIT;
170	179	if (!(elf_hwcap & HWCAP_26BIT))
171	180	regs->ARM_cpsr \|= USR_MODE;
172	181
...	...	@@ -392,6 +392,7 @@
392	392	#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363)
393	393	#define __NR_perf_event_open (__NR_SYSCALL_BASE+364)
394	394	#define __NR_recvmmsg (__NR_SYSCALL_BASE+365)
	395	+#define __NR_accept4 (__NR_SYSCALL_BASE+366)
395	396
396	397	/*
397	398	* The following SWIs are ARM private.
...	...	@@ -375,6 +375,7 @@
375	375	CALL(sys_rt_tgsigqueueinfo)
376	376	CALL(sys_perf_event_open)
377	377	/* 365 */ CALL(sys_recvmmsg)
	378	+ CALL(sys_accept4)
378	379	#ifndef syscalls_counted
379	380	.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
380	381	#define syscalls_counted
...	...	@@ -79,7 +79,7 @@
79	79	return;
80	80
81	81	/* Initialize to zero */
82		- for (regno = 0; regno < GDB_MAX_REGS; regno++)
	82	+ for (regno = 0; regno < DBG_MAX_REG_NUM; regno++)
83	83	gdb_regs[regno] = 0;
84	84
85	85	/* Otherwise, we have only some registers from switch_to() */
...	...	@@ -80,7 +80,10 @@
80	80	/*
81	81	* Disable CLCD clock source.
82	82	*/
83		- clk_disable(fb->clk);
	83	+ if (fb->clk_enabled) {
	84	+ fb->clk_enabled = false;
	85	+ clk_disable(fb->clk);
	86	+ }
84	87	}
85	88
86	89	static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
...	...	@@ -88,7 +91,10 @@
88	91	/*
89	92	* Enable the CLCD clock source.
90	93	*/
91		- clk_enable(fb->clk);
	94	+ if (!fb->clk_enabled) {
	95	+ fb->clk_enabled = true;
	96	+ clk_enable(fb->clk);
	97	+ }
92	98
93	99	/*
94	100	* Bring up by first enabling..
...	...	@@ -150,6 +150,7 @@
150	150	u16 off_cntl;
151	151	u32 clcd_cntl;
152	152	u32 cmap[16];
	153	+ bool clk_enabled;
153	154	};
154	155
155	156	static inline void clcdfb_decode(struct clcd_fb fb, struct clcd_regs regs)