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Commit 2c8086a5d073e8e72122a5b84febde236a39845b

Authored by eric miao
Committed by Russell King
1 parent 073ac8fd4a
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] pxa: PXA3xx base support 

Signed-off-by: eric miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 21 changed files with 2942 additions and 9 deletions Side-by-side Diff

... ... @@ -336,14 +336,14 @@
336 336 This enables support for Philips PNX4008 mobile platform.
337 337  
338 338 config ARCH_PXA
339   - bool "PXA2xx-based"
  339 + bool "PXA2xx/PXA3xx-based"
340 340 depends on MMU
341 341 select ARCH_MTD_XIP
342 342 select GENERIC_GPIO
343 343 select GENERIC_TIME
344 344 select GENERIC_CLOCKEVENTS
345 345 help
346   - Support for Intel's PXA2XX processor line.
  346 + Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
347 347  
348 348 config ARCH_RPC
349 349 bool "RiscPC"
... ... @@ -486,7 +486,7 @@
486 486 config IWMMXT
487 487 bool "Enable iWMMXt support"
488 488 depends on CPU_XSCALE || CPU_XSC3
489   - default y if PXA27x
  489 + default y if PXA27x || PXA3xx
490 490 help
491 491 Enable support for iWMMXt context switching at run time if
492 492 running on a CPU that supports it.
arch/arm/mach-pxa/Kconfig
Diff comments   View file @ 2c8086a
1 1 if ARCH_PXA
2 2  
3   -menu "Intel PXA2xx Implementations"
  3 +menu "Intel PXA2xx/PXA3xx Implementations"
4 4  
  5 +if PXA3xx
  6 +
  7 +menu "Supported PXA3xx Processor Variants"
  8 +
  9 +config CPU_PXA300
  10 + bool "PXA300 (codename Monahans-L)"
  11 +
  12 +config CPU_PXA310
  13 + bool "PXA310 (codename Monahans-LV)"
  14 + select CPU_PXA300
  15 +
  16 +config CPU_PXA320
  17 + bool "PXA320 (codename Monahans-P)"
  18 +
  19 +endmenu
  20 +
  21 +endif
  22 +
5 23 choice
6 24 prompt "Select target board"
7 25  
... ... @@ -41,6 +59,10 @@
41 59 bool "CompuLab EM-x270 platform"
42 60 select PXA27x
43 61  
  62 +config MACH_ZYLONITE
  63 + bool "PXA3xx Development Platform"
  64 + select PXA3xx
  65 +
44 66 endchoice
45 67  
46 68 if PXA_SHARPSL
... ... @@ -129,6 +151,11 @@
129 151 bool
130 152 help
131 153 Select code specific to PXA27x variants
  154 +
  155 +config PXA3xx
  156 + bool
  157 + help
  158 + Select code specific to PXA3xx variants
132 159  
133 160 config PXA_SHARP_C7xx
134 161 bool
arch/arm/mach-pxa/Makefile
Diff comments   View file @ 2c8086a
... ... @@ -6,6 +6,9 @@
6 6 obj-y += clock.o generic.o irq.o dma.o time.o
7 7 obj-$(CONFIG_PXA25x) += pxa25x.o
8 8 obj-$(CONFIG_PXA27x) += pxa27x.o
  9 +obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o
  10 +obj-$(CONFIG_CPU_PXA300) += pxa300.o
  11 +obj-$(CONFIG_CPU_PXA320) += pxa320.o
9 12  
10 13 # Specific board support
11 14 obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
... ... @@ -19,6 +22,12 @@
19 22 obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o
20 23 obj-$(CONFIG_MACH_TOSA) += tosa.o
21 24 obj-$(CONFIG_MACH_EM_X270) += em-x270.o
  25 +
  26 +ifeq ($(CONFIG_MACH_ZYLONITE),y)
  27 + obj-y += zylonite.o
  28 + obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o
  29 + obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o
  30 +endif
22 31  
23 32 # Support for blinky lights
24 33 led-y := leds.o
arch/arm/mach-pxa/generic.c
Diff comments   View file @ 2c8086a
... ... @@ -51,8 +51,10 @@
51 51 {
52 52 if (cpu_is_pxa21x() || cpu_is_pxa25x())
53 53 return pxa25x_get_clk_frequency_khz(info);
54   - else
  54 + else if (cpu_is_pxa27x())
55 55 return pxa27x_get_clk_frequency_khz(info);
  56 + else
  57 + return pxa3xx_get_clk_frequency_khz(info);
56 58 }
57 59 EXPORT_SYMBOL(get_clk_frequency_khz);
58 60  
59 61  
... ... @@ -63,8 +65,10 @@
63 65 {
64 66 if (cpu_is_pxa21x() || cpu_is_pxa25x())
65 67 return pxa25x_get_memclk_frequency_10khz();
66   - else
  68 + else if (cpu_is_pxa27x())
67 69 return pxa27x_get_memclk_frequency_10khz();
  70 + else
  71 + return pxa3xx_get_memclk_frequency_10khz();
68 72 }
69 73 EXPORT_SYMBOL(get_memclk_frequency_10khz);
70 74  
arch/arm/mach-pxa/generic.h
Diff comments   View file @ 2c8086a
... ... @@ -18,6 +18,7 @@
18 18 extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int));
19 19 extern void __init pxa25x_init_irq(void);
20 20 extern void __init pxa27x_init_irq(void);
  21 +extern void __init pxa3xx_init_irq(void);
21 22 extern void __init pxa_map_io(void);
22 23  
23 24 extern unsigned int get_clk_frequency_khz(int info);
... ... @@ -42,5 +43,13 @@
42 43 #else
43 44 #define pxa27x_get_clk_frequency_khz(x) (0)
44 45 #define pxa27x_get_memclk_frequency_10khz() (0)
  46 +#endif
  47 +
  48 +#ifdef CONFIG_PXA3xx
  49 +extern unsigned pxa3xx_get_clk_frequency_khz(int);
  50 +extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
  51 +#else
  52 +#define pxa3xx_get_clk_frequency_khz(x) (0)
  53 +#define pxa3xx_get_memclk_frequency_10khz() (0)
45 54 #endif
arch/arm/mach-pxa/irq.c
Diff comments   View file @ 2c8086a
... ... @@ -65,7 +65,7 @@
65 65 }
66 66 }
67 67  
68   -#ifdef CONFIG_PXA27x
  68 +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
69 69  
70 70 /*
71 71 * This is for the second set of internal IRQs as found on the PXA27x.
arch/arm/mach-pxa/mfp.c
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/arch/arm/mach-pxa/mfp.c
  3 + *
  4 + * PXA3xx Multi-Function Pin Support
  5 + *
  6 + * Copyright (C) 2007 Marvell Internation Ltd.
  7 + *
  8 + * 2007-08-21: eric miao <eric.y.miao@gmail.com>
  9 + * initial version
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License version 2 as
  13 + * published by the Free Software Foundation.
  14 + */
  15 +
  16 +#include <linux/module.h>
  17 +#include <linux/kernel.h>
  18 +#include <linux/init.h>
  19 +#include <linux/io.h>
  20 +
  21 +#include <asm/hardware.h>
  22 +#include <asm/arch/mfp.h>
  23 +
  24 +/* mfp_spin_lock is used to ensure that MFP register configuration
  25 + * (most likely a read-modify-write operation) is atomic, and that
  26 + * mfp_table[] is consistent
  27 + */
  28 +static DEFINE_SPINLOCK(mfp_spin_lock);
  29 +
  30 +static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE);
  31 +static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
  32 +
  33 +#define mfpr_readl(off) \
  34 + __raw_readl(mfpr_mmio_base + (off))
  35 +
  36 +#define mfpr_writel(off, val) \
  37 + __raw_writel(val, mfpr_mmio_base + (off))
  38 +
  39 +/*
  40 + * perform a read-back of any MFPR register to make sure the
  41 + * previous writings are finished
  42 + */
  43 +#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0)
  44 +
  45 +static inline void __mfp_config(int pin, unsigned long val)
  46 +{
  47 + unsigned long off = mfp_table[pin].mfpr_off;
  48 +
  49 + mfp_table[pin].mfpr_val = val;
  50 + mfpr_writel(off, val);
  51 +}
  52 +
  53 +void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num)
  54 +{
  55 + int i, pin;
  56 + unsigned long val, flags;
  57 + mfp_cfg_t *mfp_cfg = mfp_cfgs;
  58 +
  59 + spin_lock_irqsave(&mfp_spin_lock, flags);
  60 +
  61 + for (i = 0; i < num; i++, mfp_cfg++) {
  62 + pin = MFP_CFG_PIN(*mfp_cfg);
  63 + val = MFP_CFG_VAL(*mfp_cfg);
  64 +
  65 + BUG_ON(pin >= MFP_PIN_MAX);
  66 +
  67 + __mfp_config(pin, val);
  68 + }
  69 +
  70 + mfpr_sync();
  71 + spin_unlock_irqrestore(&mfp_spin_lock, flags);
  72 +}
  73 +
  74 +unsigned long pxa3xx_mfp_read(int mfp)
  75 +{
  76 + unsigned long val, flags;
  77 +
  78 + BUG_ON(mfp >= MFP_PIN_MAX);
  79 +
  80 + spin_lock_irqsave(&mfp_spin_lock, flags);
  81 + val = mfpr_readl(mfp_table[mfp].mfpr_off);
  82 + spin_unlock_irqrestore(&mfp_spin_lock, flags);
  83 +
  84 + return val;
  85 +}
  86 +
  87 +void pxa3xx_mfp_write(int mfp, unsigned long val)
  88 +{
  89 + unsigned long flags;
  90 +
  91 + BUG_ON(mfp >= MFP_PIN_MAX);
  92 +
  93 + spin_lock_irqsave(&mfp_spin_lock, flags);
  94 + mfpr_writel(mfp_table[mfp].mfpr_off, val);
  95 + mfpr_sync();
  96 + spin_unlock_irqrestore(&mfp_spin_lock, flags);
  97 +}
  98 +
  99 +void pxa3xx_mfp_set_afds(int mfp, int af, int ds)
  100 +{
  101 + uint32_t mfpr_off, mfpr_val;
  102 + unsigned long flags;
  103 +
  104 + BUG_ON(mfp >= MFP_PIN_MAX);
  105 +
  106 + spin_lock_irqsave(&mfp_spin_lock, flags);
  107 + mfpr_off = mfp_table[mfp].mfpr_off;
  108 +
  109 + mfpr_val = mfpr_readl(mfpr_off);
  110 + mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK);
  111 + mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) |
  112 + ((ds & 0x7) << MFPR_DRV_OFFSET));
  113 +
  114 + mfpr_writel(mfpr_off, mfpr_val);
  115 + mfpr_sync();
  116 +
  117 + spin_unlock_irqrestore(&mfp_spin_lock, flags);
  118 +}
  119 +
  120 +void pxa3xx_mfp_set_rdh(int mfp, int rdh)
  121 +{
  122 + uint32_t mfpr_off, mfpr_val;
  123 + unsigned long flags;
  124 +
  125 + BUG_ON(mfp >= MFP_PIN_MAX);
  126 +
  127 + spin_lock_irqsave(&mfp_spin_lock, flags);
  128 +
  129 + mfpr_off = mfp_table[mfp].mfpr_off;
  130 +
  131 + mfpr_val = mfpr_readl(mfpr_off);
  132 + mfpr_val &= ~MFPR_RDH_MASK;
  133 +
  134 + if (likely(rdh))
  135 + mfpr_val |= (1u << MFPR_SS_OFFSET);
  136 +
  137 + mfpr_writel(mfpr_off, mfpr_val);
  138 + mfpr_sync();
  139 +
  140 + spin_unlock_irqrestore(&mfp_spin_lock, flags);
  141 +}
  142 +
  143 +void pxa3xx_mfp_set_lpm(int mfp, int lpm)
  144 +{
  145 + uint32_t mfpr_off, mfpr_val;
  146 + unsigned long flags;
  147 +
  148 + BUG_ON(mfp >= MFP_PIN_MAX);
  149 +
  150 + spin_lock_irqsave(&mfp_spin_lock, flags);
  151 +
  152 + mfpr_off = mfp_table[mfp].mfpr_off;
  153 + mfpr_val = mfpr_readl(mfpr_off);
  154 + mfpr_val &= ~MFPR_LPM_MASK;
  155 +
  156 + if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET;
  157 + if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET;
  158 + if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET;
  159 + if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET;
  160 + if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET;
  161 +
  162 + mfpr_writel(mfpr_off, mfpr_val);
  163 + mfpr_sync();
  164 +
  165 + spin_unlock_irqrestore(&mfp_spin_lock, flags);
  166 +}
  167 +
  168 +void pxa3xx_mfp_set_pull(int mfp, int pull)
  169 +{
  170 + uint32_t mfpr_off, mfpr_val;
  171 + unsigned long flags;
  172 +
  173 + BUG_ON(mfp >= MFP_PIN_MAX);
  174 +
  175 + spin_lock_irqsave(&mfp_spin_lock, flags);
  176 +
  177 + mfpr_off = mfp_table[mfp].mfpr_off;
  178 + mfpr_val = mfpr_readl(mfpr_off);
  179 + mfpr_val &= ~MFPR_PULL_MASK;
  180 + mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET);
  181 +
  182 + mfpr_writel(mfpr_off, mfpr_val);
  183 + mfpr_sync();
  184 +
  185 + spin_unlock_irqrestore(&mfp_spin_lock, flags);
  186 +}
  187 +
  188 +void pxa3xx_mfp_set_edge(int mfp, int edge)
  189 +{
  190 + uint32_t mfpr_off, mfpr_val;
  191 + unsigned long flags;
  192 +
  193 + BUG_ON(mfp >= MFP_PIN_MAX);
  194 +
  195 + spin_lock_irqsave(&mfp_spin_lock, flags);
  196 +
  197 + mfpr_off = mfp_table[mfp].mfpr_off;
  198 + mfpr_val = mfpr_readl(mfpr_off);
  199 +
  200 + mfpr_val &= ~MFPR_EDGE_MASK;
  201 + mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET;
  202 + mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET;
  203 +
  204 + mfpr_writel(mfpr_off, mfpr_val);
  205 + mfpr_sync();
  206 +
  207 + spin_unlock_irqrestore(&mfp_spin_lock, flags);
  208 +}
  209 +
  210 +void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
  211 +{
  212 + struct pxa3xx_mfp_addr_map *p;
  213 + unsigned long offset, flags;
  214 + int i;
  215 +
  216 + spin_lock_irqsave(&mfp_spin_lock, flags);
  217 +
  218 + for (p = map; p->start != MFP_PIN_INVALID; p++) {
  219 + offset = p->offset;
  220 + i = p->start;
  221 +
  222 + do {
  223 + mfp_table[i].mfpr_off = offset;
  224 + mfp_table[i].mfpr_val = 0;
  225 + offset += 4; i++;
  226 + } while ((i <= p->end) && (p->end != -1));
  227 + }
  228 +
  229 + spin_unlock_irqrestore(&mfp_spin_lock, flags);
  230 +}
  231 +
  232 +void __init pxa3xx_init_mfp(void)
  233 +{
  234 + memset(mfp_table, 0, sizeof(mfp_table));
  235 +}
arch/arm/mach-pxa/pxa300.c
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/arch/arm/mach-pxa/pxa300.c
  3 + *
  4 + * Code specific to PXA300/PXA310
  5 + *
  6 + * Copyright (C) 2007 Marvell Internation Ltd.
  7 + *
  8 + * 2007-08-21: eric miao <eric.y.miao@gmail.com>
  9 + * initial version
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License version 2 as
  13 + * published by the Free Software Foundation.
  14 + */
  15 +
  16 +#include <linux/module.h>
  17 +#include <linux/kernel.h>
  18 +
  19 +#include <asm/hardware.h>
  20 +#include <asm/arch/mfp-pxa300.h>
  21 +
  22 +static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
  23 +
  24 + MFP_ADDR_X(GPIO0, GPIO2, 0x00b4),
  25 + MFP_ADDR_X(GPIO3, GPIO26, 0x027c),
  26 + MFP_ADDR_X(GPIO27, GPIO127, 0x0400),
  27 + MFP_ADDR_X(GPIO0_2, GPIO6_2, 0x02ec),
  28 +
  29 + MFP_ADDR(nBE0, 0x0204),
  30 + MFP_ADDR(nBE1, 0x0208),
  31 +
  32 + MFP_ADDR(nLUA, 0x0244),
  33 + MFP_ADDR(nLLA, 0x0254),
  34 +
  35 + MFP_ADDR(DF_CLE_nOE, 0x0240),
  36 + MFP_ADDR(DF_nRE_nOE, 0x0200),
  37 + MFP_ADDR(DF_ALE_nWE, 0x020C),
  38 + MFP_ADDR(DF_INT_RnB, 0x00C8),
  39 + MFP_ADDR(DF_nCS0, 0x0248),
  40 + MFP_ADDR(DF_nCS1, 0x0278),
  41 + MFP_ADDR(DF_nWE, 0x00CC),
  42 +
  43 + MFP_ADDR(DF_ADDR0, 0x0210),
  44 + MFP_ADDR(DF_ADDR1, 0x0214),
  45 + MFP_ADDR(DF_ADDR2, 0x0218),
  46 + MFP_ADDR(DF_ADDR3, 0x021C),
  47 +
  48 + MFP_ADDR(DF_IO0, 0x0220),
  49 + MFP_ADDR(DF_IO1, 0x0228),
  50 + MFP_ADDR(DF_IO2, 0x0230),
  51 + MFP_ADDR(DF_IO3, 0x0238),
  52 + MFP_ADDR(DF_IO4, 0x0258),
  53 + MFP_ADDR(DF_IO5, 0x0260),
  54 + MFP_ADDR(DF_IO6, 0x0268),
  55 + MFP_ADDR(DF_IO7, 0x0270),
  56 + MFP_ADDR(DF_IO8, 0x0224),
  57 + MFP_ADDR(DF_IO9, 0x022C),
  58 + MFP_ADDR(DF_IO10, 0x0234),
  59 + MFP_ADDR(DF_IO11, 0x023C),
  60 + MFP_ADDR(DF_IO12, 0x025C),
  61 + MFP_ADDR(DF_IO13, 0x0264),
  62 + MFP_ADDR(DF_IO14, 0x026C),
  63 + MFP_ADDR(DF_IO15, 0x0274),
  64 +
  65 + MFP_ADDR_END,
  66 +};
  67 +
  68 +/* override pxa300 MFP register addresses */
  69 +static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
  70 + MFP_ADDR_X(GPIO30, GPIO98, 0x0418),
  71 + MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C),
  72 +
  73 + MFP_ADDR(ULPI_STP, 0x040C),
  74 + MFP_ADDR(ULPI_NXT, 0x0410),
  75 + MFP_ADDR(ULPI_DIR, 0x0414),
  76 +
  77 + MFP_ADDR_END,
  78 +};
  79 +
  80 +static int __init pxa300_init(void)
  81 +{
  82 + if (cpu_is_pxa300() || cpu_is_pxa310()) {
  83 + pxa3xx_init_mfp();
  84 + pxa3xx_mfp_init_addr(pxa300_mfp_addr_map);
  85 + }
  86 +
  87 + if (cpu_is_pxa310())
  88 + pxa3xx_mfp_init_addr(pxa310_mfp_addr_map);
  89 +
  90 + return 0;
  91 +}
  92 +
  93 +core_initcall(pxa300_init);
arch/arm/mach-pxa/pxa320.c
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/arch/arm/mach-pxa/pxa320.c
  3 + *
  4 + * Code specific to PXA320
  5 + *
  6 + * Copyright (C) 2007 Marvell Internation Ltd.
  7 + *
  8 + * 2007-08-21: eric miao <eric.y.miao@gmail.com>
  9 + * initial version
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License version 2 as
  13 + * published by the Free Software Foundation.
  14 + */
  15 +
  16 +#include <linux/module.h>
  17 +#include <linux/kernel.h>
  18 +
  19 +#include <asm/hardware.h>
  20 +#include <asm/arch/mfp.h>
  21 +#include <asm/arch/mfp-pxa320.h>
  22 +
  23 +static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
  24 +
  25 + MFP_ADDR_X(GPIO0, GPIO4, 0x0124),
  26 + MFP_ADDR_X(GPIO5, GPIO26, 0x028C),
  27 + MFP_ADDR_X(GPIO27, GPIO62, 0x0400),
  28 + MFP_ADDR_X(GPIO63, GPIO73, 0x04B4),
  29 + MFP_ADDR_X(GPIO74, GPIO98, 0x04F0),
  30 + MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
  31 + MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674),
  32 + MFP_ADDR_X(GPIO6_2, GPIO13_2, 0x0494),
  33 + MFP_ADDR_X(GPIO14_2, GPIO17_2, 0x04E0),
  34 +
  35 + MFP_ADDR(nXCVREN, 0x0138),
  36 + MFP_ADDR(DF_CLE_nOE, 0x0204),
  37 + MFP_ADDR(DF_nADV1_ALE, 0x0208),
  38 + MFP_ADDR(DF_SCLK_S, 0x020C),
  39 + MFP_ADDR(DF_SCLK_E, 0x0210),
  40 + MFP_ADDR(nBE0, 0x0214),
  41 + MFP_ADDR(nBE1, 0x0218),
  42 + MFP_ADDR(DF_nADV2_ALE, 0x021C),
  43 + MFP_ADDR(DF_INT_RnB, 0x0220),
  44 + MFP_ADDR(DF_nCS0, 0x0224),
  45 + MFP_ADDR(DF_nCS1, 0x0228),
  46 + MFP_ADDR(DF_nWE, 0x022C),
  47 + MFP_ADDR(DF_nRE_nOE, 0x0230),
  48 + MFP_ADDR(nLUA, 0x0234),
  49 + MFP_ADDR(nLLA, 0x0238),
  50 + MFP_ADDR(DF_ADDR0, 0x023C),
  51 + MFP_ADDR(DF_ADDR1, 0x0240),
  52 + MFP_ADDR(DF_ADDR2, 0x0244),
  53 + MFP_ADDR(DF_ADDR3, 0x0248),
  54 + MFP_ADDR(DF_IO0, 0x024C),
  55 + MFP_ADDR(DF_IO8, 0x0250),
  56 + MFP_ADDR(DF_IO1, 0x0254),
  57 + MFP_ADDR(DF_IO9, 0x0258),
  58 + MFP_ADDR(DF_IO2, 0x025C),
  59 + MFP_ADDR(DF_IO10, 0x0260),
  60 + MFP_ADDR(DF_IO3, 0x0264),
  61 + MFP_ADDR(DF_IO11, 0x0268),
  62 + MFP_ADDR(DF_IO4, 0x026C),
  63 + MFP_ADDR(DF_IO12, 0x0270),
  64 + MFP_ADDR(DF_IO5, 0x0274),
  65 + MFP_ADDR(DF_IO13, 0x0278),
  66 + MFP_ADDR(DF_IO6, 0x027C),
  67 + MFP_ADDR(DF_IO14, 0x0280),
  68 + MFP_ADDR(DF_IO7, 0x0284),
  69 + MFP_ADDR(DF_IO15, 0x0288),
  70 +
  71 + MFP_ADDR_END,
  72 +};
  73 +
  74 +static void __init pxa320_init_mfp(void)
  75 +{
  76 + pxa3xx_init_mfp();
  77 + pxa3xx_mfp_init_addr(pxa320_mfp_addr_map);
  78 +}
  79 +
  80 +static int __init pxa320_init(void)
  81 +{
  82 + if (cpu_is_pxa320())
  83 + pxa320_init_mfp();
  84 +
  85 + return 0;
  86 +}
  87 +
  88 +core_initcall(pxa320_init);
arch/arm/mach-pxa/pxa3xx.c
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/arch/arm/mach-pxa/pxa3xx.c
  3 + *
  4 + * code specific to pxa3xx aka Monahans
  5 + *
  6 + * Copyright (C) 2006 Marvell International Ltd.
  7 + *
  8 + * 2007-09-02: eric miao <eric.y.miao@gmail.com>
  9 + * initial version
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License version 2 as
  13 + * published by the Free Software Foundation.
  14 + */
  15 +
  16 +#include <linux/module.h>
  17 +#include <linux/kernel.h>
  18 +#include <linux/init.h>
  19 +#include <linux/pm.h>
  20 +#include <linux/platform_device.h>
  21 +#include <linux/irq.h>
  22 +
  23 +#include <asm/hardware.h>
  24 +#include <asm/arch/pxa3xx-regs.h>
  25 +#include <asm/arch/ohci.h>
  26 +#include <asm/arch/pm.h>
  27 +#include <asm/arch/dma.h>
  28 +#include <asm/arch/ssp.h>
  29 +
  30 +#include "generic.h"
  31 +#include "devices.h"
  32 +#include "clock.h"
  33 +
  34 +/* Crystal clock: 13MHz */
  35 +#define BASE_CLK 13000000
  36 +
  37 +/* Ring Oscillator Clock: 60MHz */
  38 +#define RO_CLK 60000000
  39 +
  40 +#define ACCR_D0CS (1 << 26)
  41 +
  42 +/* crystal frequency to static memory controller multiplier (SMCFS) */
  43 +static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
  44 +
  45 +/* crystal frequency to HSIO bus frequency multiplier (HSS) */
  46 +static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
  47 +
  48 +/*
  49 + * Get the clock frequency as reflected by CCSR and the turbo flag.
  50 + * We assume these values have been applied via a fcs.
  51 + * If info is not 0 we also display the current settings.
  52 + */
  53 +unsigned int pxa3xx_get_clk_frequency_khz(int info)
  54 +{
  55 + unsigned long acsr, xclkcfg;
  56 + unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
  57 +
  58 + /* Read XCLKCFG register turbo bit */
  59 + __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
  60 + t = xclkcfg & 0x1;
  61 +
  62 + acsr = ACSR;
  63 +
  64 + xl = acsr & 0x1f;
  65 + xn = (acsr >> 8) & 0x7;
  66 + hss = (acsr >> 14) & 0x3;
  67 +
  68 + XL = xl * BASE_CLK;
  69 + XN = xn * XL;
  70 +
  71 + ro = acsr & ACCR_D0CS;
  72 +
  73 + CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
  74 + HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
  75 +
  76 + if (info) {
  77 + pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
  78 + RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
  79 + (ro) ? "" : "in");
  80 + pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
  81 + XL / 1000000, (XL % 1000000) / 10000, xl);
  82 + pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
  83 + XN / 1000000, (XN % 1000000) / 10000, xn,
  84 + (t) ? "" : "in");
  85 + pr_info("HSIO bus clock: %d.%02dMHz\n",
  86 + HSS / 1000000, (HSS % 1000000) / 10000);
  87 + }
  88 +
  89 + return CLK;
  90 +}
  91 +
  92 +/*
  93 + * Return the current static memory controller clock frequency
  94 + * in units of 10kHz
  95 + */
  96 +unsigned int pxa3xx_get_memclk_frequency_10khz(void)
  97 +{
  98 + unsigned long acsr;
  99 + unsigned int smcfs, clk = 0;
  100 +
  101 + acsr = ACSR;
  102 +
  103 + smcfs = (acsr >> 23) & 0x7;
  104 + clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
  105 +
  106 + return (clk / 10000);
  107 +}
  108 +
  109 +/*
  110 + * Return the current HSIO bus clock frequency
  111 + */
  112 +static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
  113 +{
  114 + unsigned long acsr;
  115 + unsigned int hss, hsio_clk;
  116 +
  117 + acsr = ACSR;
  118 +
  119 + hss = (acsr >> 14) & 0x3;
  120 + hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
  121 +
  122 + return hsio_clk;
  123 +}
  124 +
  125 +static void clk_pxa3xx_cken_enable(struct clk *clk)
  126 +{
  127 + unsigned long mask = 1ul << (clk->cken & 0x1f);
  128 +
  129 + local_irq_disable();
  130 +
  131 + if (clk->cken < 32)
  132 + CKENA |= mask;
  133 + else
  134 + CKENB |= mask;
  135 +
  136 + local_irq_enable();
  137 +}
  138 +
  139 +static void clk_pxa3xx_cken_disable(struct clk *clk)
  140 +{
  141 + unsigned long mask = 1ul << (clk->cken & 0x1f);
  142 +
  143 + local_irq_disable();
  144 +
  145 + if (clk->cken < 32)
  146 + CKENA &= ~mask;
  147 + else
  148 + CKENB &= ~mask;
  149 +
  150 + local_irq_enable();
  151 +}
  152 +
  153 +static const struct clkops clk_pxa3xx_hsio_ops = {
  154 + .enable = clk_pxa3xx_cken_enable,
  155 + .disable = clk_pxa3xx_cken_disable,
  156 + .getrate = clk_pxa3xx_hsio_getrate,
  157 +};
  158 +
  159 +static struct clk pxa3xx_clks[] = {
  160 + INIT_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
  161 + INIT_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
  162 +
  163 + INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
  164 + INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
  165 + INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
  166 +
  167 + INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
  168 + INIT_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
  169 +};
  170 +
  171 +void __init pxa3xx_init_irq(void)
  172 +{
  173 + /* enable CP6 access */
  174 + u32 value;
  175 + __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
  176 + value |= (1 << 6);
  177 + __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
  178 +
  179 + pxa_init_irq_low();
  180 + pxa_init_irq_high();
  181 + pxa_init_irq_gpio(128);
  182 +}
  183 +
  184 +/*
  185 + * device registration specific to PXA3xx.
  186 + */
  187 +
  188 +static struct platform_device *devices[] __initdata = {
  189 + &pxa_device_mci,
  190 + &pxa_device_udc,
  191 + &pxa_device_fb,
  192 + &pxa_device_ffuart,
  193 + &pxa_device_btuart,
  194 + &pxa_device_stuart,
  195 + &pxa_device_i2c,
  196 + &pxa_device_i2s,
  197 + &pxa_device_ficp,
  198 + &pxa_device_rtc,
  199 +};
  200 +
  201 +static int __init pxa3xx_init(void)
  202 +{
  203 + int ret = 0;
  204 +
  205 + if (cpu_is_pxa3xx()) {
  206 + clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
  207 +
  208 + if ((ret = pxa_init_dma(32)))
  209 + return ret;
  210 +
  211 + return platform_add_devices(devices, ARRAY_SIZE(devices));
  212 + }
  213 + return 0;
  214 +}
  215 +
  216 +subsys_initcall(pxa3xx_init);
arch/arm/mach-pxa/zylonite.c
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/arch/arm/mach-pxa/zylonite.c
  3 + *
  4 + * Support for the PXA3xx Development Platform (aka Zylonite)
  5 + *
  6 + * Copyright (C) 2006 Marvell International Ltd.
  7 + *
  8 + * 2007-09-04: eric miao <eric.y.miao@gmail.com>
  9 + * rewrite to align with latest kernel
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License version 2 as
  13 + * published by the Free Software Foundation.
  14 + */
  15 +
  16 +#include <linux/module.h>
  17 +#include <linux/kernel.h>
  18 +#include <linux/interrupt.h>
  19 +#include <linux/init.h>
  20 +#include <linux/platform_device.h>
  21 +
  22 +#include <asm/mach-types.h>
  23 +#include <asm/mach/arch.h>
  24 +#include <asm/hardware.h>
  25 +#include <asm/arch/gpio.h>
  26 +#include <asm/arch/pxafb.h>
  27 +#include <asm/arch/zylonite.h>
  28 +
  29 +#include "generic.h"
  30 +
  31 +int gpio_backlight;
  32 +int gpio_eth_irq;
  33 +
  34 +int lcd_id;
  35 +int lcd_orientation;
  36 +
  37 +static struct resource smc91x_resources[] = {
  38 + [0] = {
  39 + .start = ZYLONITE_ETH_PHYS + 0x300,
  40 + .end = ZYLONITE_ETH_PHYS + 0xfffff,
  41 + .flags = IORESOURCE_MEM,
  42 + },
  43 + [1] = {
  44 + .start = -1, /* for run-time assignment */
  45 + .end = -1,
  46 + .flags = IORESOURCE_IRQ,
  47 + }
  48 +};
  49 +
  50 +static struct platform_device smc91x_device = {
  51 + .name = "smc91x",
  52 + .id = 0,
  53 + .num_resources = ARRAY_SIZE(smc91x_resources),
  54 + .resource = smc91x_resources,
  55 +};
  56 +
  57 +#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULES)
  58 +static void zylonite_backlight_power(int on)
  59 +{
  60 + gpio_set_value(gpio_backlight, on);
  61 +}
  62 +
  63 +static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
  64 + .pixclock = 110000,
  65 + .xres = 240,
  66 + .yres = 320,
  67 + .bpp = 16,
  68 + .hsync_len = 4,
  69 + .left_margin = 6,
  70 + .right_margin = 4,
  71 + .vsync_len = 2,
  72 + .upper_margin = 2,
  73 + .lower_margin = 3,
  74 + .sync = FB_SYNC_VERT_HIGH_ACT,
  75 +};
  76 +
  77 +static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
  78 + .pixclock = 50000,
  79 + .xres = 640,
  80 + .yres = 480,
  81 + .bpp = 16,
  82 + .hsync_len = 1,
  83 + .left_margin = 0x9f,
  84 + .right_margin = 1,
  85 + .vsync_len = 44,
  86 + .upper_margin = 0,
  87 + .lower_margin = 0,
  88 + .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
  89 +};
  90 +
  91 +static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
  92 + .num_modes = 1,
  93 + .lccr0 = LCCR0_Act,
  94 + .lccr3 = LCCR3_PCP,
  95 + .pxafb_backlight_power = zylonite_backlight_power,
  96 +};
  97 +
  98 +static struct pxafb_mode_info sharp_ls037_modes[] = {
  99 + [0] = {
  100 + .pixclock = 158000,
  101 + .xres = 240,
  102 + .yres = 320,
  103 + .bpp = 16,
  104 + .hsync_len = 4,
  105 + .left_margin = 39,
  106 + .right_margin = 39,
  107 + .vsync_len = 1,
  108 + .upper_margin = 2,
  109 + .lower_margin = 3,
  110 + .sync = 0,
  111 + },
  112 + [1] = {
  113 + .pixclock = 39700,
  114 + .xres = 480,
  115 + .yres = 640,
  116 + .bpp = 16,
  117 + .hsync_len = 8,
  118 + .left_margin = 81,
  119 + .right_margin = 81,
  120 + .vsync_len = 1,
  121 + .upper_margin = 2,
  122 + .lower_margin = 7,
  123 + .sync = 0,
  124 + },
  125 +};
  126 +
  127 +static struct pxafb_mach_info zylonite_sharp_lcd_info = {
  128 + .modes = sharp_ls037_modes,
  129 + .num_modes = 2,
  130 + .lccr0 = LCCR0_Act,
  131 + .lccr3 = LCCR3_PCP | LCCR3_HSP | LCCR3_VSP,
  132 + .pxafb_backlight_power = zylonite_backlight_power,
  133 +};
  134 +
  135 +static void __init zylonite_init_lcd(void)
  136 +{
  137 + /* backlight GPIO: output, default on */
  138 + gpio_direction_output(gpio_backlight, 1);
  139 +
  140 + if (lcd_id & 0x20) {
  141 + set_pxa_fb_info(&zylonite_sharp_lcd_info);
  142 + return;
  143 + }
  144 +
  145 + /* legacy LCD panels, it would be handy here if LCD panel type can
  146 + * be decided at run-time
  147 + */
  148 + if (1)
  149 + zylonite_toshiba_lcd_info.modes = &toshiba_ltm035a776c_mode;
  150 + else
  151 + zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode;
  152 +
  153 + set_pxa_fb_info(&zylonite_toshiba_lcd_info);
  154 +}
  155 +#else
  156 +static inline void zylonite_init_lcd(void) {}
  157 +#endif
  158 +
  159 +static void __init zylonite_init(void)
  160 +{
  161 + /* board-processor specific initialization */
  162 + zylonite_pxa300_init();
  163 + zylonite_pxa320_init();
  164 +
  165 + /*
  166 + * Note: We depend that the bootloader set
  167 + * the correct value to MSC register for SMC91x.
  168 + */
  169 + smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq);
  170 + smc91x_resources[1].end = gpio_to_irq(gpio_eth_irq);
  171 + platform_device_register(&smc91x_device);
  172 +
  173 + zylonite_init_lcd();
  174 +}
  175 +
  176 +MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
  177 + .phys_io = 0x40000000,
  178 + .boot_params = 0xa0000100,
  179 + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
  180 + .map_io = pxa_map_io,
  181 + .init_irq = pxa3xx_init_irq,
  182 + .timer = &pxa_timer,
  183 + .init_machine = zylonite_init,
  184 +MACHINE_END
arch/arm/mach-pxa/zylonite_pxa300.c
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/arch/arm/mach-pxa/zylonite_pxa300.c
  3 + *
  4 + * PXA300/PXA310 specific support code for the
  5 + * PXA3xx Development Platform (aka Zylonite)
  6 + *
  7 + * Copyright (C) 2007 Marvell Internation Ltd.
  8 + * 2007-08-21: eric miao <eric.y.miao@gmail.com>
  9 + * initial version
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License version 2 as
  13 + * published by the Free Software Foundation.
  14 + */
  15 +
  16 +#include <linux/module.h>
  17 +#include <linux/kernel.h>
  18 +#include <linux/init.h>
  19 +
  20 +#include <asm/gpio.h>
  21 +#include <asm/arch/mfp-pxa300.h>
  22 +#include <asm/arch/zylonite.h>
  23 +
  24 +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
  25 +
  26 +/* PXA300/PXA310 common configurations */
  27 +static mfp_cfg_t common_mfp_cfg[] __initdata = {
  28 + /* LCD */
  29 + GPIO54_LCD_LDD_0,
  30 + GPIO55_LCD_LDD_1,
  31 + GPIO56_LCD_LDD_2,
  32 + GPIO57_LCD_LDD_3,
  33 + GPIO58_LCD_LDD_4,
  34 + GPIO59_LCD_LDD_5,
  35 + GPIO60_LCD_LDD_6,
  36 + GPIO61_LCD_LDD_7,
  37 + GPIO62_LCD_LDD_8,
  38 + GPIO63_LCD_LDD_9,
  39 + GPIO64_LCD_LDD_10,
  40 + GPIO65_LCD_LDD_11,
  41 + GPIO66_LCD_LDD_12,
  42 + GPIO67_LCD_LDD_13,
  43 + GPIO68_LCD_LDD_14,
  44 + GPIO69_LCD_LDD_15,
  45 + GPIO70_LCD_LDD_16,
  46 + GPIO71_LCD_LDD_17,
  47 + GPIO72_LCD_FCLK,
  48 + GPIO73_LCD_LCLK,
  49 + GPIO74_LCD_PCLK,
  50 + GPIO75_LCD_BIAS,
  51 + GPIO76_LCD_VSYNC,
  52 + GPIO127_LCD_CS_N,
  53 +
  54 + /* BTUART */
  55 + GPIO111_UART2_RTS,
  56 + GPIO112_UART2_RXD,
  57 + GPIO113_UART2_TXD,
  58 + GPIO114_UART2_CTS,
  59 +
  60 + /* STUART */
  61 + GPIO109_UART3_TXD,
  62 + GPIO110_UART3_RXD,
  63 +
  64 + /* AC97 */
  65 + GPIO23_AC97_nACRESET,
  66 + GPIO24_AC97_SYSCLK,
  67 + GPIO29_AC97_BITCLK,
  68 + GPIO25_AC97_SDATA_IN_0,
  69 + GPIO27_AC97_SDATA_OUT,
  70 + GPIO28_AC97_SYNC,
  71 +
  72 + /* Keypad */
  73 + GPIO107_KP_DKIN_0,
  74 + GPIO108_KP_DKIN_1,
  75 + GPIO115_KP_MKIN_0,
  76 + GPIO116_KP_MKIN_1,
  77 + GPIO117_KP_MKIN_2,
  78 + GPIO118_KP_MKIN_3,
  79 + GPIO119_KP_MKIN_4,
  80 + GPIO120_KP_MKIN_5,
  81 + GPIO2_2_KP_MKIN_6,
  82 + GPIO3_2_KP_MKIN_7,
  83 + GPIO121_KP_MKOUT_0,
  84 + GPIO122_KP_MKOUT_1,
  85 + GPIO123_KP_MKOUT_2,
  86 + GPIO124_KP_MKOUT_3,
  87 + GPIO125_KP_MKOUT_4,
  88 + GPIO4_2_KP_MKOUT_5,
  89 + GPIO5_2_KP_MKOUT_6,
  90 + GPIO6_2_KP_MKOUT_7,
  91 +};
  92 +
  93 +static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
  94 + /* FFUART */
  95 + GPIO30_UART1_RXD,
  96 + GPIO31_UART1_TXD,
  97 + GPIO32_UART1_CTS,
  98 + GPIO37_UART1_RTS,
  99 + GPIO33_UART1_DCD,
  100 + GPIO34_UART1_DSR,
  101 + GPIO35_UART1_RI,
  102 + GPIO36_UART1_DTR,
  103 +
  104 + /* Ethernet */
  105 + GPIO2_nCS3,
  106 + GPIO99_GPIO,
  107 +};
  108 +
  109 +static mfp_cfg_t pxa310_mfp_cfg[] __initdata = {
  110 + /* FFUART */
  111 + GPIO99_UART1_RXD,
  112 + GPIO100_UART1_TXD,
  113 + GPIO101_UART1_CTS,
  114 + GPIO106_UART1_RTS,
  115 +
  116 + /* Ethernet */
  117 + GPIO2_nCS3,
  118 + GPIO102_GPIO,
  119 +};
  120 +
  121 +#define NUM_LCD_DETECT_PINS 7
  122 +
  123 +static int lcd_detect_pins[] __initdata = {
  124 + MFP_PIN_GPIO71, /* LCD_LDD_17 - ORIENT */
  125 + MFP_PIN_GPIO70, /* LCD_LDD_16 - LCDID[5] */
  126 + MFP_PIN_GPIO75, /* LCD_BIAS - LCDID[4] */
  127 + MFP_PIN_GPIO73, /* LCD_LCLK - LCDID[3] */
  128 + MFP_PIN_GPIO72, /* LCD_FCLK - LCDID[2] */
  129 + MFP_PIN_GPIO127,/* LCD_CS_N - LCDID[1] */
  130 + MFP_PIN_GPIO76, /* LCD_VSYNC - LCDID[0] */
  131 +};
  132 +
  133 +static void __init zylonite_detect_lcd_panel(void)
  134 +{
  135 + unsigned long mfpr_save[NUM_LCD_DETECT_PINS];
  136 + int i, gpio, id = 0;
  137 +
  138 + /* save the original MFP settings of these pins and configure
  139 + * them as GPIO Input, DS01X, Pull Neither, Edge Clear
  140 + */
  141 + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
  142 + mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
  143 + pxa3xx_mfp_write(lcd_detect_pins[i], 0x8440);
  144 + }
  145 +
  146 + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
  147 + id = id << 1;
  148 + gpio = mfp_to_gpio(lcd_detect_pins[i]);
  149 + gpio_direction_input(gpio);
  150 +
  151 + if (gpio_get_value(gpio))
  152 + id = id | 0x1;
  153 + }
  154 +
  155 + /* lcd id, flush out bit 1 */
  156 + lcd_id = id & 0x3d;
  157 +
  158 + /* lcd orientation, portrait or landscape */
  159 + lcd_orientation = (id >> 6) & 0x1;
  160 +
  161 + /* restore the original MFP settings */
  162 + for (i = 0; i < NUM_LCD_DETECT_PINS; i++)
  163 + pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
  164 +}
  165 +
  166 +void __init zylonite_pxa300_init(void)
  167 +{
  168 + if (cpu_is_pxa300() || cpu_is_pxa310()) {
  169 + /* initialize MFP */
  170 + pxa3xx_mfp_config(ARRAY_AND_SIZE(common_mfp_cfg));
  171 +
  172 + /* detect LCD panel */
  173 + zylonite_detect_lcd_panel();
  174 +
  175 + /* GPIO pin assignment */
  176 + gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
  177 + }
  178 +
  179 + if (cpu_is_pxa300()) {
  180 + pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa300_mfp_cfg));
  181 + gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO99);
  182 + }
  183 +
  184 + if (cpu_is_pxa310()) {
  185 + pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg));
  186 + gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102);
  187 + }
  188 +}
arch/arm/mach-pxa/zylonite_pxa320.c
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/arch/arm/mach-pxa/zylonite_pxa320.c
  3 + *
  4 + * PXA320 specific support code for the
  5 + * PXA3xx Development Platform (aka Zylonite)
  6 + *
  7 + * Copyright (C) 2007 Marvell Internation Ltd.
  8 + * 2007-08-21: eric miao <eric.y.miao@gmail.com>
  9 + * initial version
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License version 2 as
  13 + * published by the Free Software Foundation.
  14 + */
  15 +
  16 +#include <linux/module.h>
  17 +#include <linux/kernel.h>
  18 +#include <linux/init.h>
  19 +
  20 +#include <asm/arch/gpio.h>
  21 +#include <asm/arch/mfp-pxa320.h>
  22 +#include <asm/arch/zylonite.h>
  23 +
  24 +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
  25 +
  26 +static mfp_cfg_t mfp_cfg[] __initdata = {
  27 + /* LCD */
  28 + GPIO6_2_LCD_LDD_0,
  29 + GPIO7_2_LCD_LDD_1,
  30 + GPIO8_2_LCD_LDD_2,
  31 + GPIO9_2_LCD_LDD_3,
  32 + GPIO10_2_LCD_LDD_4,
  33 + GPIO11_2_LCD_LDD_5,
  34 + GPIO12_2_LCD_LDD_6,
  35 + GPIO13_2_LCD_LDD_7,
  36 + GPIO63_LCD_LDD_8,
  37 + GPIO64_LCD_LDD_9,
  38 + GPIO65_LCD_LDD_10,
  39 + GPIO66_LCD_LDD_11,
  40 + GPIO67_LCD_LDD_12,
  41 + GPIO68_LCD_LDD_13,
  42 + GPIO69_LCD_LDD_14,
  43 + GPIO70_LCD_LDD_15,
  44 + GPIO71_LCD_LDD_16,
  45 + GPIO72_LCD_LDD_17,
  46 + GPIO73_LCD_CS_N,
  47 + GPIO74_LCD_VSYNC,
  48 + GPIO14_2_LCD_FCLK,
  49 + GPIO15_2_LCD_LCLK,
  50 + GPIO16_2_LCD_PCLK,
  51 + GPIO17_2_LCD_BIAS,
  52 +
  53 + /* FFUART */
  54 + GPIO41_UART1_RXD,
  55 + GPIO42_UART1_TXD,
  56 + GPIO43_UART1_CTS,
  57 + GPIO44_UART1_DCD,
  58 + GPIO45_UART1_DSR,
  59 + GPIO46_UART1_RI,
  60 + GPIO47_UART1_DTR,
  61 + GPIO48_UART1_RTS,
  62 +
  63 + /* AC97 */
  64 + GPIO34_AC97_SYSCLK,
  65 + GPIO35_AC97_SDATA_IN_0,
  66 + GPIO37_AC97_SDATA_OUT,
  67 + GPIO38_AC97_SYNC,
  68 + GPIO39_AC97_BITCLK,
  69 + GPIO40_AC97_nACRESET,
  70 +
  71 + /* I2C */
  72 + GPIO32_I2C_SCL,
  73 + GPIO33_I2C_SDA,
  74 +
  75 + /* Keypad */
  76 + GPIO105_KP_DKIN_0,
  77 + GPIO106_KP_DKIN_1,
  78 + GPIO113_KP_MKIN_0,
  79 + GPIO114_KP_MKIN_1,
  80 + GPIO115_KP_MKIN_2,
  81 + GPIO116_KP_MKIN_3,
  82 + GPIO117_KP_MKIN_4,
  83 + GPIO118_KP_MKIN_5,
  84 + GPIO119_KP_MKIN_6,
  85 + GPIO120_KP_MKIN_7,
  86 + GPIO121_KP_MKOUT_0,
  87 + GPIO122_KP_MKOUT_1,
  88 + GPIO123_KP_MKOUT_2,
  89 + GPIO124_KP_MKOUT_3,
  90 + GPIO125_KP_MKOUT_4,
  91 + GPIO126_KP_MKOUT_5,
  92 + GPIO127_KP_MKOUT_6,
  93 + GPIO5_2_KP_MKOUT_7,
  94 +
  95 + /* Ethernet */
  96 + GPIO4_nCS3,
  97 + GPIO90_GPIO,
  98 +};
  99 +
  100 +#define NUM_LCD_DETECT_PINS 7
  101 +
  102 +static int lcd_detect_pins[] __initdata = {
  103 + MFP_PIN_GPIO72, /* LCD_LDD_17 - ORIENT */
  104 + MFP_PIN_GPIO71, /* LCD_LDD_16 - LCDID[5] */
  105 + MFP_PIN_GPIO17_2, /* LCD_BIAS - LCDID[4] */
  106 + MFP_PIN_GPIO15_2, /* LCD_LCLK - LCDID[3] */
  107 + MFP_PIN_GPIO14_2, /* LCD_FCLK - LCDID[2] */
  108 + MFP_PIN_GPIO73, /* LCD_CS_N - LCDID[1] */
  109 + MFP_PIN_GPIO74, /* LCD_VSYNC - LCDID[0] */
  110 + /*
  111 + * set the MFP_PIN_GPIO 14/15/17 to alternate function other than
  112 + * GPIO to avoid input level confliction with 14_2, 15_2, 17_2
  113 + */
  114 + MFP_PIN_GPIO14,
  115 + MFP_PIN_GPIO15,
  116 + MFP_PIN_GPIO17,
  117 +};
  118 +
  119 +static int lcd_detect_mfpr[] __initdata = {
  120 + /* AF0, DS 1X, Pull Neither, Edge Clear */
  121 + 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440,
  122 + 0xc442, /* Backlight, Pull-Up, AF2 */
  123 + 0x8445, /* AF5 */
  124 + 0x8445, /* AF5 */
  125 +};
  126 +
  127 +static void __init zylonite_detect_lcd_panel(void)
  128 +{
  129 + unsigned long mfpr_save[ARRAY_SIZE(lcd_detect_pins)];
  130 + int i, gpio, id = 0;
  131 +
  132 + /* save the original MFP settings of these pins and configure them
  133 + * as GPIO Input, DS01X, Pull Neither, Edge Clear
  134 + */
  135 + for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) {
  136 + mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
  137 + pxa3xx_mfp_write(lcd_detect_pins[i], lcd_detect_mfpr[i]);
  138 + }
  139 +
  140 + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
  141 + id = id << 1;
  142 + gpio = mfp_to_gpio(lcd_detect_pins[i]);
  143 + gpio_direction_input(gpio);
  144 +
  145 + if (gpio_get_value(gpio))
  146 + id = id | 0x1;
  147 + }
  148 +
  149 + /* lcd id, flush out bit 1 */
  150 + lcd_id = id & 0x3d;
  151 +
  152 + /* lcd orientation, portrait or landscape */
  153 + lcd_orientation = (id >> 6) & 0x1;
  154 +
  155 + /* restore the original MFP settings */
  156 + for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++)
  157 + pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
  158 +}
  159 +
  160 +void __init zylonite_pxa320_init(void)
  161 +{
  162 + if (cpu_is_pxa320()) {
  163 + /* initialize MFP */
  164 + pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg));
  165 +
  166 + /* detect LCD panel */
  167 + zylonite_detect_lcd_panel();
  168 +
  169 + /* GPIO pin assignment */
  170 + gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14);
  171 + gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
  172 + }
  173 +}
... ... @@ -333,7 +333,7 @@
333 333 # XScale Core Version 3
334 334 config CPU_XSC3
335 335 bool
336   - depends on ARCH_IXP23XX || ARCH_IOP13XX
  336 + depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
337 337 default y
338 338 select CPU_32v5
339 339 select CPU_ABRT_EV5T
include/asm-arm/arch-pxa/mfp-pxa300.h
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/include/asm-arm/arch-pxa/mfp-pxa300.h
  3 + *
  4 + * PXA300/PXA310 specific MFP configuration definitions
  5 + *
  6 + * Copyright (C) 2007 Marvell International Ltd.
  7 + * 2007-08-21: eric miao <eric.y.miao@gmail.com>
  8 + * initial version
  9 + *
  10 + * This program is free software; you can redistribute it and/or modify
  11 + * it under the terms of the GNU General Public License version 2 as
  12 + * published by the Free Software Foundation.
  13 + */
  14 +
  15 +#ifndef __ASM_ARCH_MFP_PXA300_H
  16 +#define __ASM_ARCH_MFP_PXA300_H
  17 +
  18 +#include <asm/arch/mfp.h>
  19 +
  20 +/* GPIO */
  21 +#define GPIO46_GPIO MFP_CFG(GPIO46, AF1)
  22 +#define GPIO49_GPIO MFP_CFG(GPIO49, AF3)
  23 +#define GPIO50_GPIO MFP_CFG(GPIO50, AF2)
  24 +#define GPIO51_GPIO MFP_CFG(GPIO51, AF3)
  25 +#define GPIO52_GPIO MFP_CFG(GPIO52, AF3)
  26 +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
  27 +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
  28 +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
  29 +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
  30 +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
  31 +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
  32 +
  33 +#ifdef CONFIG_CPU_PXA310
  34 +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
  35 +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
  36 +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
  37 +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
  38 +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
  39 +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
  40 +#endif
  41 +
  42 +/* Chip Select */
  43 +#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1)
  44 +
  45 +/* AC97 */
  46 +#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1)
  47 +#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1)
  48 +#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1)
  49 +#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1)
  50 +#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1)
  51 +#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3)
  52 +#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2)
  53 +#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3)
  54 +#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2)
  55 +#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1)
  56 +#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1)
  57 +
  58 +/* I2C */
  59 +#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH)
  60 +#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH)
  61 +
  62 +/* QCI */
  63 +#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X)
  64 +#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X)
  65 +#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X)
  66 +#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X)
  67 +#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X)
  68 +#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X)
  69 +#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X)
  70 +#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X)
  71 +#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X)
  72 +#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X)
  73 +#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X)
  74 +#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X)
  75 +#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X)
  76 +#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X)
  77 +
  78 +/* KEYPAD */
  79 +#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT)
  80 +#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT)
  81 +#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT)
  82 +#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT)
  83 +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT)
  84 +#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
  85 +#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
  86 +#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT)
  87 +#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT)
  88 +#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT)
  89 +#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
  90 +#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
  91 +#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
  92 +#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
  93 +#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
  94 +#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
  95 +#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
  96 +#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
  97 +#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
  98 +#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
  99 +#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
  100 +#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
  101 +#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
  102 +#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
  103 +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
  104 +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
  105 +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
  106 +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
  107 +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT)
  108 +#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
  109 +#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT)
  110 +#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
  111 +#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
  112 +#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
  113 +#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT)
  114 +
  115 +#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT)
  116 +#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT)
  117 +#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
  118 +#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
  119 +#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT)
  120 +#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT)
  121 +#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT)
  122 +#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT)
  123 +#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT)
  124 +#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT)
  125 +#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
  126 +#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
  127 +#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
  128 +#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
  129 +#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
  130 +#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
  131 +#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
  132 +#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT)
  133 +#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT)
  134 +
  135 +#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
  136 +#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH)
  137 +#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH)
  138 +#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
  139 +#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH)
  140 +#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH)
  141 +#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH)
  142 +#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH)
  143 +#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH)
  144 +#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
  145 +#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
  146 +#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH)
  147 +#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH)
  148 +#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH)
  149 +#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH)
  150 +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
  151 +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
  152 +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
  153 +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
  154 +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
  155 +#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH)
  156 +#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
  157 +#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH)
  158 +#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH)
  159 +
  160 +/* LCD */
  161 +#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X)
  162 +#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X)
  163 +#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X)
  164 +#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X)
  165 +#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X)
  166 +#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X)
  167 +#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X)
  168 +#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X)
  169 +#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X)
  170 +#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X)
  171 +#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X)
  172 +#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X)
  173 +#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X)
  174 +#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X)
  175 +#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X)
  176 +#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X)
  177 +#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X)
  178 +#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X)
  179 +#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X)
  180 +#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X)
  181 +#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X)
  182 +#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS01X)
  183 +#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X)
  184 +#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X)
  185 +
  186 +#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X)
  187 +#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X)
  188 +#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X)
  189 +
  190 +/* Mini-LCD */
  191 +#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X)
  192 +#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X)
  193 +#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X)
  194 +#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X)
  195 +#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X)
  196 +#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X)
  197 +#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X)
  198 +#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X)
  199 +#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X)
  200 +#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X)
  201 +#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X)
  202 +#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X)
  203 +#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X)
  204 +#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X)
  205 +#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X)
  206 +#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X)
  207 +#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X)
  208 +#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X)
  209 +#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X)
  210 +#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X)
  211 +
  212 +/* MMC1 */
  213 +#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
  214 +#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
  215 +#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH)
  216 +#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH)
  217 +#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH)
  218 +#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH)
  219 +#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
  220 +#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
  221 +
  222 +/* MMC2 */
  223 +#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH)
  224 +#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH)
  225 +#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH)
  226 +#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH)
  227 +#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH)
  228 +#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH)
  229 +#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
  230 +#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
  231 +#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
  232 +#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
  233 +#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH)
  234 +#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH)
  235 +
  236 +/* SSP1 */
  237 +#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1)
  238 +#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1)
  239 +#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6)
  240 +#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2)
  241 +#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5)
  242 +#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5)
  243 +#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1)
  244 +#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1)
  245 +#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7)
  246 +#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2)
  247 +#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2)
  248 +#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7)
  249 +#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5)
  250 +#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4)
  251 +#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5)
  252 +#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6)
  253 +#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1)
  254 +#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6)
  255 +#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6)
  256 +#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1)
  257 +
  258 +/* SSP2 */
  259 +#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2)
  260 +#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2)
  261 +#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2)
  262 +#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2)
  263 +#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2)
  264 +#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6)
  265 +#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6)
  266 +#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2)
  267 +#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2)
  268 +#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2)
  269 +#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7)
  270 +#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5)
  271 +#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4)
  272 +#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2)
  273 +#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5)
  274 +#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5)
  275 +#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2)
  276 +#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7)
  277 +#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6)
  278 +#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4)
  279 +#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2)
  280 +#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2)
  281 +#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4)
  282 +#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7)
  283 +
  284 +/* SSP3 */
  285 +#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW)
  286 +#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT)
  287 +#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW)
  288 +#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT)
  289 +#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
  290 +#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT)
  291 +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW)
  292 +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT)
  293 +#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW)
  294 +#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT)
  295 +#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW)
  296 +#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
  297 +
  298 +/* SSP4 */
  299 +#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
  300 +#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
  301 +#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH)
  302 +#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH)
  303 +#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH)
  304 +#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH)
  305 +
  306 +/* UART1 */
  307 +#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT)
  308 +#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT)
  309 +#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT)
  310 +#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT)
  311 +#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT)
  312 +#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT)
  313 +
  314 +#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT)
  315 +#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT)
  316 +#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT)
  317 +#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT)
  318 +#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT)
  319 +#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
  320 +
  321 +#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT)
  322 +#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT)
  323 +#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT)
  324 +#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT)
  325 +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
  326 +#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT)
  327 +
  328 +#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT)
  329 +#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT)
  330 +#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT)
  331 +#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT)
  332 +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
  333 +#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT)
  334 +
  335 +#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT)
  336 +#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT)
  337 +#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT)
  338 +
  339 +#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT)
  340 +#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT)
  341 +#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT)
  342 +
  343 +#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
  344 +#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT)
  345 +#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT)
  346 +#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT)
  347 +#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT)
  348 +#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT)
  349 +#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT)
  350 +#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT)
  351 +
  352 +#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT)
  353 +#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
  354 +#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT)
  355 +#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT)
  356 +#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT)
  357 +#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
  358 +#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT)
  359 +
  360 +/* UART2 */
  361 +#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT)
  362 +#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT)
  363 +#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT)
  364 +#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT)
  365 +
  366 +#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT)
  367 +#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT)
  368 +#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT)
  369 +#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT)
  370 +
  371 +#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT)
  372 +#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT)
  373 +#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT)
  374 +#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT)
  375 +
  376 +#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT)
  377 +#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT)
  378 +#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT)
  379 +#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT)
  380 +
  381 +/* UART3 */
  382 +#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT)
  383 +#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT)
  384 +#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT)
  385 +#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT)
  386 +
  387 +#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT)
  388 +#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT)
  389 +#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT)
  390 +#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT)
  391 +
  392 +#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT)
  393 +#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT)
  394 +#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT)
  395 +#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT)
  396 +#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT)
  397 +#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
  398 +
  399 +#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT)
  400 +#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT)
  401 +#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT)
  402 +#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT)
  403 +#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT)
  404 +#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
  405 +
  406 +/* USB Host */
  407 +#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1)
  408 +#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1)
  409 +
  410 +/* USB P3 */
  411 +#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2)
  412 +#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2)
  413 +#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2)
  414 +#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2)
  415 +#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2)
  416 +#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2)
  417 +
  418 +/* PWM */
  419 +#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1)
  420 +#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1)
  421 +#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1)
  422 +#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1)
  423 +
  424 +/* CIR */
  425 +#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5)
  426 +#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3)
  427 +
  428 +#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5)
  429 +#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2)
  430 +
  431 +#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1)
  432 +#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7)
  433 +#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6)
  434 +#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6)
  435 +#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6)
  436 +#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6)
  437 +#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2)
  438 +#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3)
  439 +#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7)
  440 +#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6)
  441 +
  442 +#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1)
  443 +
  444 +#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1)
  445 +#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1)
  446 +#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1)
  447 +#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1)
  448 +
  449 +#define GPIO9_SCIO MFP_CFG(GPIO9, AF1)
  450 +#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4)
  451 +#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1)
  452 +
  453 +/*
  454 + * PXA300 specific MFP configurations
  455 + */
  456 +#ifdef CONFIG_CPU_PXA300
  457 +#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2)
  458 +#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3)
  459 +#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4)
  460 +#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4)
  461 +#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5)
  462 +#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2)
  463 +#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2)
  464 +#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2)
  465 +#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2)
  466 +#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2)
  467 +#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2)
  468 +#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2)
  469 +
  470 +/* U2D UTMI */
  471 +#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1)
  472 +#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3)
  473 +#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1)
  474 +#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5)
  475 +#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3)
  476 +#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2)
  477 +#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5)
  478 +#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3)
  479 +#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2)
  480 +#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1)
  481 +#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5)
  482 +#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1)
  483 +#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3)
  484 +#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3)
  485 +#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3)
  486 +#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4)
  487 +#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3)
  488 +#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3)
  489 +#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3)
  490 +#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4)
  491 +#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2)
  492 +#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7)
  493 +#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4)
  494 +#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2)
  495 +#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3)
  496 +#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5)
  497 +#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1)
  498 +#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2)
  499 +#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3)
  500 +#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3)
  501 +#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2)
  502 +#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3)
  503 +#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5)
  504 +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3)
  505 +#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5)
  506 +#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3)
  507 +#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4)
  508 +#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3)
  509 +#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7)
  510 +#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5)
  511 +#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3)
  512 +#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5)
  513 +#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3)
  514 +#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3)
  515 +#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3)
  516 +#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3)
  517 +#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3)
  518 +#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3)
  519 +#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3)
  520 +#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3)
  521 +#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3)
  522 +#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3)
  523 +#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3)
  524 +#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3)
  525 +#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3)
  526 +#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3)
  527 +#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3)
  528 +#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3)
  529 +#endif /* CONFIG_CPU_PXA300 */
  530 +
  531 +/*
  532 + * PXA310 specific MFP configurations
  533 + */
  534 +#ifdef CONFIG_CPU_PXA310
  535 +/* USB P2 */
  536 +#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1)
  537 +#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1)
  538 +#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1)
  539 +#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1)
  540 +#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1)
  541 +#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1)
  542 +
  543 +/* MMC1 */
  544 +#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3)
  545 +#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3)
  546 +
  547 +/* MMC3 */
  548 +#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2)
  549 +#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2)
  550 +#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1)
  551 +#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1)
  552 +#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1)
  553 +#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1)
  554 +#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1)
  555 +#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1)
  556 +
  557 +/* ULPI */
  558 +#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1)
  559 +#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3)
  560 +#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3)
  561 +#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3)
  562 +#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3)
  563 +#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3)
  564 +#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3)
  565 +#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3)
  566 +#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3)
  567 +#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1)
  568 +
  569 +#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
  570 +#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
  571 +#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
  572 +#endif /* CONFIG_CPU_PXA310 */
  573 +
  574 +#endif /* __ASM_ARCH_MFP_PXA300_H */
include/asm-arm/arch-pxa/mfp-pxa320.h
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/include/asm-arm/arch-pxa/mfp-pxa320.h
  3 + *
  4 + * PXA320 specific MFP configuration definitions
  5 + *
  6 + * Copyright (C) 2007 Marvell International Ltd.
  7 + * 2007-08-21: eric miao <eric.y.miao@gmail.com>
  8 + * initial version
  9 + *
  10 + * This program is free software; you can redistribute it and/or modify
  11 + * it under the terms of the GNU General Public License version 2 as
  12 + * published by the Free Software Foundation.
  13 + */
  14 +
  15 +#ifndef __ASM_ARCH_MFP_PXA320_H
  16 +#define __ASM_ARCH_MFP_PXA320_H
  17 +
  18 +#include <asm/arch/mfp.h>
  19 +
  20 +/* GPIO */
  21 +#define GPIO46_GPIO MFP_CFG(GPIO6, AF0)
  22 +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
  23 +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
  24 +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
  25 +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
  26 +
  27 +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
  28 +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
  29 +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
  30 +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
  31 +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
  32 +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
  33 +#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0)
  34 +#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0)
  35 +#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0)
  36 +#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0)
  37 +#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0)
  38 +
  39 +/* Chip Select */
  40 +#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1)
  41 +
  42 +/* AC97 */
  43 +#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1)
  44 +#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1)
  45 +#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1)
  46 +#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1)
  47 +#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1)
  48 +#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2)
  49 +#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2)
  50 +#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3)
  51 +#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3)
  52 +#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1)
  53 +#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1)
  54 +
  55 +/* I2C */
  56 +#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH)
  57 +#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH)
  58 +
  59 +/* QCI */
  60 +#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X)
  61 +#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X)
  62 +#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X)
  63 +#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X)
  64 +#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X)
  65 +#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X)
  66 +#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X)
  67 +#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X)
  68 +#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X)
  69 +#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X)
  70 +#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X)
  71 +#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X)
  72 +#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X)
  73 +#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X)
  74 +
  75 +#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5)
  76 +
  77 +#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3)
  78 +#define GPIO0_DRQ MFP_CFG(GPIO0, AF2)
  79 +#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5)
  80 +#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6)
  81 +#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1)
  82 +#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4)
  83 +#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1)
  84 +#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1)
  85 +
  86 +#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT)
  87 +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT)
  88 +#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
  89 +#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
  90 +
  91 +#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT)
  92 +#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT)
  93 +#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
  94 +#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
  95 +#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
  96 +#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
  97 +#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
  98 +#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
  99 +
  100 +#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
  101 +#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
  102 +#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
  103 +#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
  104 +#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
  105 +#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
  106 +#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
  107 +#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
  108 +
  109 +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT)
  110 +#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT)
  111 +
  112 +#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
  113 +#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
  114 +#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
  115 +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
  116 +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
  117 +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
  118 +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
  119 +#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
  120 +
  121 +#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT)
  122 +#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT)
  123 +#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
  124 +#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
  125 +#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
  126 +#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
  127 +#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
  128 +#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
  129 +
  130 +#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH)
  131 +#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH)
  132 +#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
  133 +#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
  134 +#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
  135 +#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH)
  136 +
  137 +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
  138 +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
  139 +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
  140 +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
  141 +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
  142 +#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH)
  143 +#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH)
  144 +#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
  145 +
  146 +/* LCD */
  147 +#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X)
  148 +#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X)
  149 +#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X)
  150 +#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X)
  151 +#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X)
  152 +#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X)
  153 +#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X)
  154 +#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X)
  155 +#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X)
  156 +#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X)
  157 +#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X)
  158 +#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X)
  159 +#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X)
  160 +#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X)
  161 +#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X)
  162 +#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X)
  163 +#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X)
  164 +#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X)
  165 +#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X)
  166 +#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X)
  167 +#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X)
  168 +#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X)
  169 +#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X)
  170 +#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X)
  171 +#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X)
  172 +#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X)
  173 +
  174 +#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X)
  175 +#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X)
  176 +#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X)
  177 +#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X)
  178 +#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X)
  179 +#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X)
  180 +#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X)
  181 +#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X)
  182 +#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X)
  183 +#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X)
  184 +#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X)
  185 +#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X)
  186 +#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X)
  187 +#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X)
  188 +#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X)
  189 +#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X)
  190 +#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X)
  191 +#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X)
  192 +#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X)
  193 +#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X)
  194 +#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X)
  195 +#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X)
  196 +#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X)
  197 +#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X)
  198 +
  199 +/* MMC1 */
  200 +#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH)
  201 +#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH)
  202 +#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH)
  203 +#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH)
  204 +#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH)
  205 +#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
  206 +#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
  207 +#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
  208 +#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
  209 +#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH)
  210 +#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH)
  211 +#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH)
  212 +#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH)
  213 +
  214 +#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH)
  215 +#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH)
  216 +#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH)
  217 +#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH)
  218 +#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
  219 +#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
  220 +
  221 +#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH)
  222 +#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH)
  223 +#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH)
  224 +#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH)
  225 +#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH)
  226 +#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH)
  227 +#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH)
  228 +#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH)
  229 +#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH)
  230 +#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
  231 +#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH)
  232 +#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
  233 +
  234 +/* 1-Wire */
  235 +#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT)
  236 +#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
  237 +
  238 +/* SSP1 */
  239 +#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1)
  240 +#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1)
  241 +#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1)
  242 +#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1)
  243 +#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6)
  244 +#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1)
  245 +#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1)
  246 +#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6)
  247 +
  248 +/* SSP2 */
  249 +#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2)
  250 +#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2)
  251 +#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2)
  252 +#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2)
  253 +#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2)
  254 +#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5)
  255 +#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2)
  256 +#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2)
  257 +#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5)
  258 +
  259 +#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
  260 +#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
  261 +#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
  262 +#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
  263 +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
  264 +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
  265 +#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
  266 +#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW)
  267 +#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT)
  268 +#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW)
  269 +#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT)
  270 +#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW)
  271 +
  272 +#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH)
  273 +#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH)
  274 +#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH)
  275 +#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH)
  276 +#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
  277 +#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
  278 +#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH)
  279 +
  280 +/* UART1 */
  281 +#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT)
  282 +#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT)
  283 +#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT)
  284 +#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT)
  285 +#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT)
  286 +#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT)
  287 +#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT)
  288 +#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT)
  289 +#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT)
  290 +#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT)
  291 +#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT)
  292 +#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT)
  293 +#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT)
  294 +#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT)
  295 +#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT)
  296 +#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT)
  297 +#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT)
  298 +#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT)
  299 +#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT)
  300 +#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT)
  301 +#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT)
  302 +#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT)
  303 +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
  304 +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
  305 +#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT)
  306 +#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
  307 +#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT)
  308 +#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT)
  309 +
  310 +/* UART2 */
  311 +#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT)
  312 +#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT)
  313 +#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT)
  314 +#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT)
  315 +#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
  316 +#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
  317 +#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT)
  318 +#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT)
  319 +
  320 +/* UART3 */
  321 +#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT)
  322 +#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT)
  323 +#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT)
  324 +#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT)
  325 +#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT)
  326 +#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT)
  327 +#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT)
  328 +#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
  329 +#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
  330 +#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT)
  331 +#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT)
  332 +#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
  333 +#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT)
  334 +#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT)
  335 +#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT)
  336 +#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT)
  337 +#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT)
  338 +#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT)
  339 +#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT)
  340 +#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT)
  341 +
  342 +
  343 +/* USB 2.0 UTMI */
  344 +#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1)
  345 +#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3)
  346 +#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1)
  347 +#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5)
  348 +#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3)
  349 +#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2)
  350 +#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5)
  351 +#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3)
  352 +#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1)
  353 +#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5)
  354 +#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1)
  355 +#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3)
  356 +#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3)
  357 +#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3)
  358 +#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4)
  359 +#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3)
  360 +#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3)
  361 +#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3)
  362 +
  363 +#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3)
  364 +#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3)
  365 +#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3)
  366 +#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3)
  367 +#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3)
  368 +#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3)
  369 +#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3)
  370 +#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3)
  371 +
  372 +#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3)
  373 +#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3)
  374 +#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3)
  375 +#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3)
  376 +#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3)
  377 +#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3)
  378 +#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3)
  379 +#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3)
  380 +
  381 +#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4)
  382 +#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2)
  383 +#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7)
  384 +
  385 +#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4)
  386 +#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2)
  387 +#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4)
  388 +#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5)
  389 +
  390 +#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1)
  391 +#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2)
  392 +#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3)
  393 +
  394 +#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3)
  395 +#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2)
  396 +#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3)
  397 +
  398 +#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5)
  399 +#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3)
  400 +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7)
  401 +#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5)
  402 +
  403 +#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4)
  404 +#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5)
  405 +#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7)
  406 +
  407 +#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5)
  408 +#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3)
  409 +#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5)
  410 +
  411 +/* USB Host 1.1 */
  412 +#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1)
  413 +#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1)
  414 +
  415 +/* USB P2 */
  416 +#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2)
  417 +#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4)
  418 +#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4)
  419 +#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2)
  420 +#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2)
  421 +#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2)
  422 +#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2)
  423 +#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2)
  424 +#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2)
  425 +#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2)
  426 +
  427 +/* USB P3 */
  428 +#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2)
  429 +#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2)
  430 +#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2)
  431 +#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2)
  432 +#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2)
  433 +#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2)
  434 +
  435 +#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6)
  436 +#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6)
  437 +
  438 +#define GPIO2_RDY MFP_CFG(GPIO2, AF1)
  439 +#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3)
  440 +
  441 +#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1)
  442 +#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1)
  443 +#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1)
  444 +#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1)
  445 +
  446 +#endif /* __ASM_ARCH_MFP_PXA320_H */
include/asm-arm/arch-pxa/mfp.h
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/include/asm-arm/arch-pxa/mfp.h
  3 + *
  4 + * Multi-Function Pin Definitions
  5 + *
  6 + * Copyright (C) 2007 Marvell International Ltd.
  7 + *
  8 + * 2007-8-21: eric miao <eric.y.miao@gmail.com>
  9 + * initial version
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License version 2 as
  13 + * published by the Free Software Foundation.
  14 + */
  15 +
  16 +#ifndef __ASM_ARCH_MFP_H
  17 +#define __ASM_ARCH_MFP_H
  18 +
  19 +#define MFPR_BASE (0x40e10000)
  20 +#define MFPR_SIZE (PAGE_SIZE)
  21 +
  22 +#define mfp_to_gpio(m) ((m) % 128)
  23 +
  24 +/* list of all the configurable MFP pins */
  25 +enum {
  26 + MFP_PIN_INVALID = -1,
  27 +
  28 + MFP_PIN_GPIO0 = 0,
  29 + MFP_PIN_GPIO1,
  30 + MFP_PIN_GPIO2,
  31 + MFP_PIN_GPIO3,
  32 + MFP_PIN_GPIO4,
  33 + MFP_PIN_GPIO5,
  34 + MFP_PIN_GPIO6,
  35 + MFP_PIN_GPIO7,
  36 + MFP_PIN_GPIO8,
  37 + MFP_PIN_GPIO9,
  38 + MFP_PIN_GPIO10,
  39 + MFP_PIN_GPIO11,
  40 + MFP_PIN_GPIO12,
  41 + MFP_PIN_GPIO13,
  42 + MFP_PIN_GPIO14,
  43 + MFP_PIN_GPIO15,
  44 + MFP_PIN_GPIO16,
  45 + MFP_PIN_GPIO17,
  46 + MFP_PIN_GPIO18,
  47 + MFP_PIN_GPIO19,
  48 + MFP_PIN_GPIO20,
  49 + MFP_PIN_GPIO21,
  50 + MFP_PIN_GPIO22,
  51 + MFP_PIN_GPIO23,
  52 + MFP_PIN_GPIO24,
  53 + MFP_PIN_GPIO25,
  54 + MFP_PIN_GPIO26,
  55 + MFP_PIN_GPIO27,
  56 + MFP_PIN_GPIO28,
  57 + MFP_PIN_GPIO29,
  58 + MFP_PIN_GPIO30,
  59 + MFP_PIN_GPIO31,
  60 + MFP_PIN_GPIO32,
  61 + MFP_PIN_GPIO33,
  62 + MFP_PIN_GPIO34,
  63 + MFP_PIN_GPIO35,
  64 + MFP_PIN_GPIO36,
  65 + MFP_PIN_GPIO37,
  66 + MFP_PIN_GPIO38,
  67 + MFP_PIN_GPIO39,
  68 + MFP_PIN_GPIO40,
  69 + MFP_PIN_GPIO41,
  70 + MFP_PIN_GPIO42,
  71 + MFP_PIN_GPIO43,
  72 + MFP_PIN_GPIO44,
  73 + MFP_PIN_GPIO45,
  74 + MFP_PIN_GPIO46,
  75 + MFP_PIN_GPIO47,
  76 + MFP_PIN_GPIO48,
  77 + MFP_PIN_GPIO49,
  78 + MFP_PIN_GPIO50,
  79 + MFP_PIN_GPIO51,
  80 + MFP_PIN_GPIO52,
  81 + MFP_PIN_GPIO53,
  82 + MFP_PIN_GPIO54,
  83 + MFP_PIN_GPIO55,
  84 + MFP_PIN_GPIO56,
  85 + MFP_PIN_GPIO57,
  86 + MFP_PIN_GPIO58,
  87 + MFP_PIN_GPIO59,
  88 + MFP_PIN_GPIO60,
  89 + MFP_PIN_GPIO61,
  90 + MFP_PIN_GPIO62,
  91 + MFP_PIN_GPIO63,
  92 + MFP_PIN_GPIO64,
  93 + MFP_PIN_GPIO65,
  94 + MFP_PIN_GPIO66,
  95 + MFP_PIN_GPIO67,
  96 + MFP_PIN_GPIO68,
  97 + MFP_PIN_GPIO69,
  98 + MFP_PIN_GPIO70,
  99 + MFP_PIN_GPIO71,
  100 + MFP_PIN_GPIO72,
  101 + MFP_PIN_GPIO73,
  102 + MFP_PIN_GPIO74,
  103 + MFP_PIN_GPIO75,
  104 + MFP_PIN_GPIO76,
  105 + MFP_PIN_GPIO77,
  106 + MFP_PIN_GPIO78,
  107 + MFP_PIN_GPIO79,
  108 + MFP_PIN_GPIO80,
  109 + MFP_PIN_GPIO81,
  110 + MFP_PIN_GPIO82,
  111 + MFP_PIN_GPIO83,
  112 + MFP_PIN_GPIO84,
  113 + MFP_PIN_GPIO85,
  114 + MFP_PIN_GPIO86,
  115 + MFP_PIN_GPIO87,
  116 + MFP_PIN_GPIO88,
  117 + MFP_PIN_GPIO89,
  118 + MFP_PIN_GPIO90,
  119 + MFP_PIN_GPIO91,
  120 + MFP_PIN_GPIO92,
  121 + MFP_PIN_GPIO93,
  122 + MFP_PIN_GPIO94,
  123 + MFP_PIN_GPIO95,
  124 + MFP_PIN_GPIO96,
  125 + MFP_PIN_GPIO97,
  126 + MFP_PIN_GPIO98,
  127 + MFP_PIN_GPIO99,
  128 + MFP_PIN_GPIO100,
  129 + MFP_PIN_GPIO101,
  130 + MFP_PIN_GPIO102,
  131 + MFP_PIN_GPIO103,
  132 + MFP_PIN_GPIO104,
  133 + MFP_PIN_GPIO105,
  134 + MFP_PIN_GPIO106,
  135 + MFP_PIN_GPIO107,
  136 + MFP_PIN_GPIO108,
  137 + MFP_PIN_GPIO109,
  138 + MFP_PIN_GPIO110,
  139 + MFP_PIN_GPIO111,
  140 + MFP_PIN_GPIO112,
  141 + MFP_PIN_GPIO113,
  142 + MFP_PIN_GPIO114,
  143 + MFP_PIN_GPIO115,
  144 + MFP_PIN_GPIO116,
  145 + MFP_PIN_GPIO117,
  146 + MFP_PIN_GPIO118,
  147 + MFP_PIN_GPIO119,
  148 + MFP_PIN_GPIO120,
  149 + MFP_PIN_GPIO121,
  150 + MFP_PIN_GPIO122,
  151 + MFP_PIN_GPIO123,
  152 + MFP_PIN_GPIO124,
  153 + MFP_PIN_GPIO125,
  154 + MFP_PIN_GPIO126,
  155 + MFP_PIN_GPIO127,
  156 + MFP_PIN_GPIO0_2,
  157 + MFP_PIN_GPIO1_2,
  158 + MFP_PIN_GPIO2_2,
  159 + MFP_PIN_GPIO3_2,
  160 + MFP_PIN_GPIO4_2,
  161 + MFP_PIN_GPIO5_2,
  162 + MFP_PIN_GPIO6_2,
  163 + MFP_PIN_GPIO7_2,
  164 + MFP_PIN_GPIO8_2,
  165 + MFP_PIN_GPIO9_2,
  166 + MFP_PIN_GPIO10_2,
  167 + MFP_PIN_GPIO11_2,
  168 + MFP_PIN_GPIO12_2,
  169 + MFP_PIN_GPIO13_2,
  170 + MFP_PIN_GPIO14_2,
  171 + MFP_PIN_GPIO15_2,
  172 + MFP_PIN_GPIO16_2,
  173 + MFP_PIN_GPIO17_2,
  174 +
  175 + MFP_PIN_ULPI_STP,
  176 + MFP_PIN_ULPI_NXT,
  177 + MFP_PIN_ULPI_DIR,
  178 +
  179 + MFP_PIN_nXCVREN,
  180 + MFP_PIN_DF_CLE_nOE,
  181 + MFP_PIN_DF_nADV1_ALE,
  182 + MFP_PIN_DF_SCLK_E,
  183 + MFP_PIN_DF_SCLK_S,
  184 + MFP_PIN_nBE0,
  185 + MFP_PIN_nBE1,
  186 + MFP_PIN_DF_nADV2_ALE,
  187 + MFP_PIN_DF_INT_RnB,
  188 + MFP_PIN_DF_nCS0,
  189 + MFP_PIN_DF_nCS1,
  190 + MFP_PIN_nLUA,
  191 + MFP_PIN_nLLA,
  192 + MFP_PIN_DF_nWE,
  193 + MFP_PIN_DF_ALE_nWE,
  194 + MFP_PIN_DF_nRE_nOE,
  195 + MFP_PIN_DF_ADDR0,
  196 + MFP_PIN_DF_ADDR1,
  197 + MFP_PIN_DF_ADDR2,
  198 + MFP_PIN_DF_ADDR3,
  199 + MFP_PIN_DF_IO0,
  200 + MFP_PIN_DF_IO1,
  201 + MFP_PIN_DF_IO2,
  202 + MFP_PIN_DF_IO3,
  203 + MFP_PIN_DF_IO4,
  204 + MFP_PIN_DF_IO5,
  205 + MFP_PIN_DF_IO6,
  206 + MFP_PIN_DF_IO7,
  207 + MFP_PIN_DF_IO8,
  208 + MFP_PIN_DF_IO9,
  209 + MFP_PIN_DF_IO10,
  210 + MFP_PIN_DF_IO11,
  211 + MFP_PIN_DF_IO12,
  212 + MFP_PIN_DF_IO13,
  213 + MFP_PIN_DF_IO14,
  214 + MFP_PIN_DF_IO15,
  215 +
  216 + MFP_PIN_MAX,
  217 +};
  218 +
  219 +/*
  220 + * Table that determines the low power modes outputs, with actual settings
  221 + * used in parentheses for don't-care values. Except for the float output,
  222 + * the configured driven and pulled levels match, so if there is a need for
  223 + * non-LPM pulled output, the same configuration could probably be used.
  224 + *
  225 + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
  226 + * (bit 7) (bit 8) (bit 14d) (bit 13d)
  227 + *
  228 + * Drive 0 0 0 0 X (1) 0
  229 + * Drive 1 0 1 X (1) 0 0
  230 + * Pull hi (1) 1 X(1) 1 0 0
  231 + * Pull lo (0) 1 X(0) 0 1 0
  232 + * Z (float) 1 X(0) 0 0 0
  233 + */
  234 +#define MFP_LPM_DRIVE_LOW 0x8
  235 +#define MFP_LPM_DRIVE_HIGH 0x6
  236 +#define MFP_LPM_PULL_HIGH 0x7
  237 +#define MFP_LPM_PULL_LOW 0x9
  238 +#define MFP_LPM_FLOAT 0x1
  239 +#define MFP_LPM_PULL_NEITHER 0x0
  240 +
  241 +/*
  242 + * The pullup and pulldown state of the MFP pin is by default determined by
  243 + * selected alternate function. In case some buggy devices need to override
  244 + * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of
  245 + * the following definition as the parameter.
  246 + *
  247 + * Definition pull_sel pullup_en pulldown_en
  248 + * MFP_PULL_HIGH 1 1 0
  249 + * MFP_PULL_LOW 1 0 1
  250 + * MFP_PULL_BOTH 1 1 1
  251 + * MFP_PULL_NONE 1 0 0
  252 + * MFP_PULL_DEFAULT 0 X X
  253 + *
  254 + * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
  255 + * bits, which will cause potential conflicts with the low power mode
  256 + * setting, device drivers should take care of this
  257 + */
  258 +#define MFP_PULL_BOTH (0x7u)
  259 +#define MFP_PULL_HIGH (0x6u)
  260 +#define MFP_PULL_LOW (0x5u)
  261 +#define MFP_PULL_NONE (0x4u)
  262 +#define MFP_PULL_DEFAULT (0x0u)
  263 +
  264 +#define MFP_AF0 (0)
  265 +#define MFP_AF1 (1)
  266 +#define MFP_AF2 (2)
  267 +#define MFP_AF3 (3)
  268 +#define MFP_AF4 (4)
  269 +#define MFP_AF5 (5)
  270 +#define MFP_AF6 (6)
  271 +#define MFP_AF7 (7)
  272 +
  273 +#define MFP_DS01X (0)
  274 +#define MFP_DS02X (1)
  275 +#define MFP_DS03X (2)
  276 +#define MFP_DS04X (3)
  277 +#define MFP_DS06X (4)
  278 +#define MFP_DS08X (5)
  279 +#define MFP_DS10X (6)
  280 +#define MFP_DS12X (7)
  281 +
  282 +#define MFP_EDGE_BOTH 0x3
  283 +#define MFP_EDGE_RISE 0x2
  284 +#define MFP_EDGE_FALL 0x1
  285 +#define MFP_EDGE_NONE 0x0
  286 +
  287 +#define MFPR_AF_MASK 0x0007
  288 +#define MFPR_DRV_MASK 0x1c00
  289 +#define MFPR_RDH_MASK 0x0200
  290 +#define MFPR_LPM_MASK 0xe180
  291 +#define MFPR_PULL_MASK 0xe000
  292 +#define MFPR_EDGE_MASK 0x0070
  293 +
  294 +#define MFPR_ALT_OFFSET 0
  295 +#define MFPR_ERE_OFFSET 4
  296 +#define MFPR_EFE_OFFSET 5
  297 +#define MFPR_EC_OFFSET 6
  298 +#define MFPR_SON_OFFSET 7
  299 +#define MFPR_SD_OFFSET 8
  300 +#define MFPR_SS_OFFSET 9
  301 +#define MFPR_DRV_OFFSET 10
  302 +#define MFPR_PD_OFFSET 13
  303 +#define MFPR_PU_OFFSET 14
  304 +#define MFPR_PS_OFFSET 15
  305 +
  306 +#define MFPR(af, drv, rdh, lpm, edge) \
  307 + (((af) & 0x7) | (((drv) & 0x7) << 10) |\
  308 + (((rdh) & 0x1) << 9) |\
  309 + (((lpm) & 0x3) << 7) |\
  310 + (((lpm) & 0x4) << 12)|\
  311 + (((lpm) & 0x8) << 10)|\
  312 + ((!(edge)) << 6) |\
  313 + (((edge) & 0x1) << 5) |\
  314 + (((edge) & 0x2) << 3))
  315 +
  316 +/*
  317 + * a possible MFP configuration is represented by a 32-bit integer
  318 + * bit 0..15 - MFPR value (16-bit)
  319 + * bit 16..31 - mfp pin index (used to obtain the MFPR offset)
  320 + *
  321 + * to facilitate the definition, the following macros are provided
  322 + *
  323 + * MFPR_DEFAULT - default MFPR value, with
  324 + * alternate function = 0,
  325 + * drive strength = fast 1mA (MFP_DS01X)
  326 + * low power mode = default
  327 + * release dalay hold = false (RDH bit)
  328 + * edge detection = none
  329 + *
  330 + * MFP_CFG - default MFPR value with alternate function
  331 + * MFP_CFG_DRV - default MFPR value with alternate function and
  332 + * pin drive strength
  333 + * MFP_CFG_LPM - default MFPR value with alternate function and
  334 + * low power mode
  335 + * MFP_CFG_X - default MFPR value with alternate function,
  336 + * pin drive strength and low power mode
  337 + *
  338 + * use
  339 + *
  340 + * MFP_CFG_PIN - to get the MFP pin index
  341 + * MFP_CFG_VAL - to get the corresponding MFPR value
  342 + */
  343 +
  344 +typedef uint32_t mfp_cfg_t;
  345 +
  346 +#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff)
  347 +#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff)
  348 +
  349 +#define MFPR_DEFAULT (0x0000)
  350 +
  351 +#define MFP_CFG(pin, af) \
  352 + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af))
  353 +
  354 +#define MFP_CFG_DRV(pin, af, drv) \
  355 + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
  356 + ((MFP_##drv) << 10) | (MFP_##af))
  357 +
  358 +#define MFP_CFG_LPM(pin, af, lpm) \
  359 + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af) |\
  360 + (((MFP_LPM_##lpm) & 0x3) << 7) |\
  361 + (((MFP_LPM_##lpm) & 0x4) << 12) |\
  362 + (((MFP_LPM_##lpm) & 0x8) << 10))
  363 +
  364 +#define MFP_CFG_X(pin, af, drv, lpm) \
  365 + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
  366 + ((MFP_##drv) << 10) | (MFP_##af) |\
  367 + (((MFP_LPM_##lpm) & 0x3) << 7) |\
  368 + (((MFP_LPM_##lpm) & 0x4) << 12) |\
  369 + (((MFP_LPM_##lpm) & 0x8) << 10))
  370 +
  371 +/* common MFP configurations - processor specific ones defined
  372 + * in mfp-pxa3xx.h
  373 + */
  374 +#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
  375 +#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
  376 +#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
  377 +#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
  378 +#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
  379 +#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
  380 +#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
  381 +#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
  382 +#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
  383 +#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
  384 +#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
  385 +#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
  386 +#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
  387 +#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
  388 +#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
  389 +#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
  390 +#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
  391 +#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
  392 +#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
  393 +#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
  394 +#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
  395 +#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
  396 +#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
  397 +#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
  398 +#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
  399 +#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
  400 +#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
  401 +#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
  402 +#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
  403 +#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
  404 +#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
  405 +#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
  406 +#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
  407 +#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
  408 +#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
  409 +#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
  410 +#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
  411 +#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
  412 +#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
  413 +#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
  414 +#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
  415 +#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
  416 +#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
  417 +#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
  418 +#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
  419 +#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
  420 +
  421 +#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
  422 +#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
  423 +
  424 +#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
  425 +#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
  426 +#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
  427 +
  428 +#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
  429 +
  430 +#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
  431 +#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
  432 +#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
  433 +#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
  434 +#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
  435 +#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
  436 +#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
  437 +#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
  438 +#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
  439 +#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
  440 +#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
  441 +#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
  442 +#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
  443 +#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
  444 +#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
  445 +#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
  446 +#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
  447 +#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
  448 +#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
  449 +#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
  450 +#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
  451 +#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
  452 +#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
  453 +#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
  454 +#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
  455 +#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
  456 +#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
  457 +#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
  458 +#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
  459 +#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
  460 +#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
  461 +#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
  462 +#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
  463 +#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
  464 +#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
  465 +#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
  466 +#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
  467 +#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
  468 +#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
  469 +#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
  470 +#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
  471 +#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
  472 +#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
  473 +#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
  474 +#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
  475 +#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
  476 +#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
  477 +#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
  478 +#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
  479 +#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
  480 +#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
  481 +#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
  482 +#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
  483 +#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
  484 +#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
  485 +#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
  486 +#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
  487 +#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
  488 +#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
  489 +#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
  490 +#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
  491 +#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
  492 +#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
  493 +#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
  494 +#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
  495 +
  496 +#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
  497 +#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
  498 +#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
  499 +#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
  500 +#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
  501 +#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
  502 +#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
  503 +
  504 +/*
  505 + * each MFP pin will have a MFPR register, since the offset of the
  506 + * register varies between processors, the processor specific code
  507 + * should initialize the pin offsets by pxa3xx_mfp_init_addr()
  508 + *
  509 + * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
  510 + * structure, which represents a range of MFP pins from "start" to
  511 + * "end", with the offset begining at "offset", to define a single
  512 + * pin, let "end" = -1
  513 + *
  514 + * use
  515 + *
  516 + * MFP_ADDR_X() to define a range of pins
  517 + * MFP_ADDR() to define a single pin
  518 + * MFP_ADDR_END to signal the end of pin offset definitions
  519 + */
  520 +struct pxa3xx_mfp_addr_map {
  521 + unsigned int start;
  522 + unsigned int end;
  523 + unsigned long offset;
  524 +};
  525 +
  526 +#define MFP_ADDR_X(start, end, offset) \
  527 + { MFP_PIN_##start, MFP_PIN_##end, offset }
  528 +
  529 +#define MFP_ADDR(pin, offset) \
  530 + { MFP_PIN_##pin, -1, offset }
  531 +
  532 +#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
  533 +
  534 +struct pxa3xx_mfp_pin {
  535 + unsigned long mfpr_off; /* MFPRxx register offset */
  536 + unsigned long mfpr_val; /* MFPRxx register value */
  537 +};
  538 +
  539 +/*
  540 + * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
  541 + * to the MFPR register
  542 + */
  543 +unsigned long pxa3xx_mfp_read(int mfp);
  544 +void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
  545 +
  546 +/*
  547 + * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
  548 + * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off
  549 + * pxa3xx_mfp_set_lpm - set MFP low power mode state
  550 + * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
  551 + *
  552 + * use these functions to override/change the default configuration
  553 + * done by pxa3xx_mfp_set_config(s)
  554 + */
  555 +void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
  556 +void pxa3xx_mfp_set_rdh(int mfp, int rdh);
  557 +void pxa3xx_mfp_set_lpm(int mfp, int lpm);
  558 +void pxa3xx_mfp_set_edge(int mfp, int edge);
  559 +
  560 +/*
  561 + * pxa3xx_mfp_config - configure the MFPR registers
  562 + *
  563 + * used by board specific initialization code
  564 + */
  565 +void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
  566 +
  567 +/*
  568 + * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
  569 + * index and MFPR register offset
  570 + *
  571 + * used by processor specific code
  572 + */
  573 +void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
  574 +void __init pxa3xx_init_mfp(void);
  575 +
  576 +#endif /* __ASM_ARCH_MFP_H */
include/asm-arm/arch-pxa/pxa-regs.h
Diff comments   View file @ 2c8086a
... ... @@ -1177,7 +1177,7 @@
1177 1177  
1178 1178 #define GPIO_bit(x) (1 << ((x) & 0x1f))
1179 1179  
1180   -#ifdef CONFIG_PXA27x
  1180 +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1181 1181  
1182 1182 /* Interrupt Controller */
1183 1183  
include/asm-arm/arch-pxa/pxa3xx-regs.h
Diff comments   View file @ 2c8086a
  1 +/*
  2 + * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
  3 + *
  4 + * PXA3xx specific register definitions
  5 + *
  6 + * Copyright (C) 2007 Marvell International Ltd.
  7 + *
  8 + * This program is free software; you can redistribute it and/or modify
  9 + * it under the terms of the GNU General Public License version 2 as
  10 + * published by the Free Software Foundation.
  11 + */
  12 +
  13 +#ifndef __ASM_ARCH_PXA3XX_REGS_H
  14 +#define __ASM_ARCH_PXA3XX_REGS_H
  15 +
  16 +/*
  17 + * Application Subsystem Clock
  18 + */
  19 +#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
  20 +#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
  21 +#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
  22 +#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
  23 +#define CKENB __REG(0x41340010) /* B Clock Enable Register */
  24 +#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
  25 +
  26 +/*
  27 + * Clock Enable Bit
  28 + */
  29 +#define CKEN_LCD 1 /* < LCD Clock Enable */
  30 +#define CKEN_USBH 2 /* < USB host clock enable */
  31 +#define CKEN_CAMERA 3 /* < Camera interface clock enable */
  32 +#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
  33 +#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
  34 +#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
  35 +#define CKEN_SMC 9 /* < Static Memory Controller clock enable */
  36 +#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
  37 +#define CKEN_BOOT 11 /* < Boot rom clock enable */
  38 +#define CKEN_MMC1 12 /* < MMC1 Clock enable */
  39 +#define CKEN_MMC2 13 /* < MMC2 clock enable */
  40 +#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
  41 +#define CKEN_CIR 15 /* < Consumer IR Clock Enable */
  42 +#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
  43 +#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
  44 +#define CKEN_TPM 19 /* < TPM clock enable */
  45 +#define CKEN_UDC 20 /* < UDC clock enable */
  46 +#define CKEN_BTUART 21 /* < BTUART clock enable */
  47 +#define CKEN_FFUART 22 /* < FFUART clock enable */
  48 +#define CKEN_STUART 23 /* < STUART clock enable */
  49 +#define CKEN_AC97 24 /* < AC97 clock enable */
  50 +#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
  51 +#define CKEN_SSP1 26 /* < SSP1 clock enable */
  52 +#define CKEN_SSP2 27 /* < SSP2 clock enable */
  53 +#define CKEN_SSP3 28 /* < SSP3 clock enable */
  54 +#define CKEN_SSP4 29 /* < SSP4 clock enable */
  55 +#define CKEN_MSL0 30 /* < MSL0 clock enable */
  56 +#define CKEN_PWM0 32 /* < PWM[0] clock enable */
  57 +#define CKEN_PWM1 33 /* < PWM[1] clock enable */
  58 +#define CKEN_I2C 36 /* < I2C clock enable */
  59 +#define CKEN_INTC 38 /* < Interrupt controller clock enable */
  60 +#define CKEN_GPIO 39 /* < GPIO clock enable */
  61 +#define CKEN_1WIRE 40 /* < 1-wire clock enable */
  62 +#define CKEN_HSIO2 41 /* < HSIO2 clock enable */
  63 +#define CKEN_MINI_IM 48 /* < Mini-IM */
  64 +#define CKEN_MINI_LCD 49 /* < Mini LCD */
  65 +
  66 +#if defined(CONFIG_CPU_PXA310)
  67 +#define CKEN_MMC3 5 /* < MMC3 Clock Enable */
  68 +#define CKEN_MVED 43 /* < MVED clock enable */
  69 +#endif
  70 +
  71 +/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
  72 +#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
  73 +#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */
  74 +
  75 +#endif /* __ASM_ARCH_PXA3XX_REGS_H */
include/asm-arm/arch-pxa/timex.h
Diff comments   View file @ 2c8086a
... ... @@ -21,5 +21,7 @@
21 21 #else
22 22 #define CLOCK_TICK_RATE 3250000
23 23 #endif
  24 +#else
  25 +#define CLOCK_TICK_RATE 3250000
24 26 #endif
include/asm-arm/arch-pxa/zylonite.h
Diff comments   View file @ 2c8086a
  1 +#ifndef __ASM_ARCH_ZYLONITE_H
  2 +#define __ASM_ARCH_ZYLONITE_H
  3 +
  4 +#define ZYLONITE_ETH_PHYS 0x14000000
  5 +
  6 +/* the following variables are processor specific and initialized
  7 + * by the corresponding zylonite_pxa3xx_init()
  8 + */
  9 +extern int gpio_backlight;
  10 +extern int gpio_eth_irq;
  11 +
  12 +extern int lcd_id;
  13 +extern int lcd_orientation;
  14 +
  15 +#ifdef CONFIG_CPU_PXA300
  16 +extern void zylonite_pxa300_init(void);
  17 +#else
  18 +static inline void zylonite_pxa300_init(void)
  19 +{
  20 + if (cpu_is_pxa300() || cpu_is_pxa310())
  21 + panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__);
  22 +}
  23 +#endif
  24 +
  25 +#ifdef CONFIG_CPU_PXA320
  26 +extern void zylonite_pxa320_init(void);
  27 +#else
  28 +static inline void zylonite_pxa320_init(void)
  29 +{
  30 + if (cpu_is_pxa320())
  31 + panic("%s: PXA320 not supported\n", __FUNCTION__);
  32 +}
  33 +#endif
  34 +
  35 +#endif /* __ASM_ARCH_ZYLONITE_H */