Commit 2ffa007eaa01cf5fedd6a71f7d43854339a831ee

Authored by françois romieu
Committed by David S. Miller
1 parent a2da570d62

via-velocity: fix the WOL bug on 1000M full duplex forced mode.

The VIA velocity card can't be waken up by WOL tool on 1000M full
duplex forced mode. This patch fixes the bug.

Signed-off-by: David Lv <DavidLv@viatech.com.cn>
Acked-by: Francois Romieu <romieu@fr.zoreil.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 2 changed files with 13 additions and 4 deletions Side-by-side Diff

drivers/net/via-velocity.c
... ... @@ -2923,6 +2923,7 @@
2923 2923 static int velocity_set_wol(struct velocity_info *vptr)
2924 2924 {
2925 2925 struct mac_regs __iomem *regs = vptr->mac_regs;
  2926 + enum speed_opt spd_dpx = vptr->options.spd_dpx;
2926 2927 static u8 buf[256];
2927 2928 int i;
2928 2929  
... ... @@ -2968,6 +2969,12 @@
2968 2969  
2969 2970 writew(0x0FFF, &regs->WOLSRClr);
2970 2971  
  2972 + if (spd_dpx == SPD_DPX_1000_FULL)
  2973 + goto mac_done;
  2974 +
  2975 + if (spd_dpx != SPD_DPX_AUTO)
  2976 + goto advertise_done;
  2977 +
2971 2978 if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
2972 2979 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
2973 2980 MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
... ... @@ -2978,6 +2985,7 @@
2978 2985 if (vptr->mii_status & VELOCITY_SPEED_1000)
2979 2986 MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
2980 2987  
  2988 +advertise_done:
2981 2989 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, &regs->CHIPGCR);
2982 2990  
2983 2991 {
... ... @@ -2987,6 +2995,7 @@
2987 2995 writeb(GCR, &regs->CHIPGCR);
2988 2996 }
2989 2997  
  2998 +mac_done:
2990 2999 BYTE_REG_BITS_OFF(ISR_PWEI, &regs->ISR);
2991 3000 /* Turn on SWPTAG just before entering power mode */
2992 3001 BYTE_REG_BITS_ON(STICKHW_SWPTAG, &regs->STICKHW);
drivers/net/via-velocity.h
... ... @@ -361,7 +361,7 @@
361 361 #define MAC_REG_CHIPGSR 0x9C
362 362 #define MAC_REG_TESTCFG 0x9D
363 363 #define MAC_REG_DEBUG 0x9E
364   -#define MAC_REG_CHIPGCR 0x9F
  364 +#define MAC_REG_CHIPGCR 0x9F /* Chip Operation and Diagnostic Control */
365 365 #define MAC_REG_WOLCR0_SET 0xA0
366 366 #define MAC_REG_WOLCR1_SET 0xA1
367 367 #define MAC_REG_PWCFG_SET 0xA2
368 368  
... ... @@ -848,10 +848,10 @@
848 848 * Bits in CHIPGCR register
849 849 */
850 850  
851   -#define CHIPGCR_FCGMII 0x80 /* enable GMII mode */
852   -#define CHIPGCR_FCFDX 0x40
  851 +#define CHIPGCR_FCGMII 0x80 /* force GMII (else MII only) */
  852 +#define CHIPGCR_FCFDX 0x40 /* force full duplex */
853 853 #define CHIPGCR_FCRESV 0x20
854   -#define CHIPGCR_FCMODE 0x10
  854 +#define CHIPGCR_FCMODE 0x10 /* enable MAC forced mode */
855 855 #define CHIPGCR_LPSOPT 0x08
856 856 #define CHIPGCR_TM1US 0x04
857 857 #define CHIPGCR_TM0US 0x02