Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit 3126c7bc4106c572ef47e2c220df5a00e7973379

Authored by Russell King 2010-07-15 18:01:17 +0800

Exists in master and in 7 other branches

ARM: AMBA: Add pclk definition for platforms using primecells

Add a dummy clk definition for the APB pclk signal on all platforms
using the AMBA bus infrastructure. This ensures that these platforms
continue to work when the core amba bus code controls the APB pclk.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 12 changed files with 66 additions and 12 deletions Inline Diff

arch/arm/mach-bcmring/core.c
arch/arm/mach-ep93xx/clock.c
arch/arm/mach-integrator/core.c
arch/arm/mach-nomadik/clock.c
arch/arm/mach-omap2/clock3xxx_data.c
arch/arm/mach-realview/core.c
arch/arm/mach-spear3xx/clock.c
arch/arm/mach-spear6xx/clock.c
arch/arm/mach-u300/clock.c
arch/arm/mach-ux500/clock.c
arch/arm/mach-versatile/core.c
arch/arm/mach-vexpress/v2m.c

arch/arm/mach-bcmring/core.c

Diff comments View file @ 3126c7b

 /*
  *  derived from linux/arch/arm/mach-versatile/core.c
  *  linux/arch/arm/mach-bcmring/core.c
  *
  *  Copyright (C) 1999 - 2003 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 /* Portions copyright Broadcom 2008 */
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <mach/csp/mm_addr.h>
 #include <mach/hardware.h>
 #include <asm/clkdev.h>
 #include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <cfg_global.h>
 #include "clock.h"
 #include <csp/secHw.h>
 #include <mach/csp/secHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 #include <mach/csp/tmrHw_reg.h>
 #define AMBA_DEVICE(name, initname, base, plat, size)       \
 static struct amba_device name##_device = {     \
    .dev = {                                     \
       .coherent_dma_mask = ~0,                  \
       .init_name = initname,                    \
       .platform_data = plat                     \
    },                                           \
    .res = {                                     \
       .start = MM_ADDR_IO_##base,               \
 		.end = MM_ADDR_IO_##base + (size) - 1,    \
       .flags = IORESOURCE_MEM                   \
    },                                           \
    .dma_mask = ~0,                              \
    .irq = {                                     \
       IRQ_##base                                \
    }                                            \
 }
 AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
 AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
 static struct clk pll1_clk = {
 	.name = "PLL1",
 	.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
 	.rate_hz = 2000000000,
 	.use_cnt = 7,
 };
 static struct clk uart_clk = {
 	.name = "UART",
 	.type = CLK_TYPE_PROGRAMMABLE,
 	.csp_id = chipcHw_CLOCK_UART,
 	.rate_hz = HW_CFG_UART_CLK_HZ,
 	.parent = &pll1_clk,
 };
+static struct clk dummy_apb_pclk = {
+	.name = "BUSCLK",
+	.type = CLK_TYPE_PRIMARY,
+	.mode = CLK_MODE_XTAL,
+};
 static struct clk_lookup lookups[] = {
-	{			/* UART0 */
+	{			/* Bus clock */
-	 .dev_id = "uarta",
+		.con_id = "apb_pclk",
-	 .clk = &uart_clk,
+		.clk = &dummy_apb_pclk,
-	 }, {			/* UART1 */
+	}, {			/* UART0 */
-	     .dev_id = "uartb",
+		.dev_id = "uarta",
-	     .clk = &uart_clk,
+		.clk = &uart_clk,
-	     }
+	}, {			/* UART1 */
+		.dev_id = "uartb",
+		.clk = &uart_clk,
+	}
 };
 static struct amba_device *amba_devs[] __initdata = {
 	&uartA_device,
 	&uartB_device,
 };
 void __init bcmring_amba_init(void)
 {
 	int i;
 	u32 bus_clock;
 /* Linux is run initially in non-secure mode. Secure peripherals */
 /* generate FIQ, and must be handled in secure mode. Until we have */
 /* a linux security monitor implementation, keep everything in */
 /* non-secure mode. */
 	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
 	secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
 			  secHw_BLK_MASK_KEY_SCAN |
 			  secHw_BLK_MASK_TOUCH_SCREEN |
 			  secHw_BLK_MASK_UART0 |
 			  secHw_BLK_MASK_UART1 |
 			  secHw_BLK_MASK_WATCHDOG |
 			  secHw_BLK_MASK_SPUM |
 			  secHw_BLK_MASK_DDR2 |
 			  secHw_BLK_MASK_SPU |
 			  secHw_BLK_MASK_PKA |
 			  secHw_BLK_MASK_RNG |
 			  secHw_BLK_MASK_RTC |
 			  secHw_BLK_MASK_OTP |
 			  secHw_BLK_MASK_BOOT |
 			  secHw_BLK_MASK_MPU |
 			  secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
 	/* Only the devices attached to the AMBA bus are enabled just before the bus is */
 	/* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
 	/* driver to access these blocks. The bus is probed, and the drivers are loaded. */
 	/* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
 	bus_clock = chipcHw_REG_BUS_CLOCK_GE
 	    | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
 	chipcHw_busInterfaceClockEnable(bus_clock);
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
 }
 /*
  * Where is the timer (VA)?
  */
 #define TIMER0_VA_BASE		 MM_IO_BASE_TMR
 #define TIMER1_VA_BASE		(MM_IO_BASE_TMR + 0x20)
 #define TIMER2_VA_BASE		(MM_IO_BASE_TMR + 0x40)
 #define TIMER3_VA_BASE          (MM_IO_BASE_TMR + 0x60)
 /* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
 #if defined(CONFIG_ARCH_FPGA11107)
 /* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
 /* slow down Linux's sense of time */
 #define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 #define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 #define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
 #define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
 #else
 #define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 #define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 #define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
 #define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
 #endif
 #define TICKS_PER_uSEC     TIMER0_FREQUENCY_MHZ
 /*
  *  These are useconds NOT ticks.
  *
  */
 #define mSEC_1                          1000
 #define mSEC_5                          (mSEC_1 * 5)
 #define mSEC_10                         (mSEC_1 * 10)
 #define mSEC_25                         (mSEC_1 * 25)
 #define SEC_1                           (mSEC_1 * 1000)
 /*
  * How long is the timer interval?
  */
 #define TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_10)
 #if TIMER_INTERVAL >= 0x100000
 #define TIMER_RELOAD	(TIMER_INTERVAL >> 8)
 #define TIMER_DIVISOR	(TIMER_CTRL_DIV256)
 #define TICKS2USECS(x)	(256 * (x) / TICKS_PER_uSEC)
 #elif TIMER_INTERVAL >= 0x10000
 #define TIMER_RELOAD	(TIMER_INTERVAL >> 4)	/* Divide by 16 */
 #define TIMER_DIVISOR	(TIMER_CTRL_DIV16)
 #define TICKS2USECS(x)	(16 * (x) / TICKS_PER_uSEC)
 #else
 #define TIMER_RELOAD	(TIMER_INTERVAL)
 #define TIMER_DIVISOR	(TIMER_CTRL_DIV1)
 #define TICKS2USECS(x)	((x) / TICKS_PER_uSEC)
 #endif
 static void timer_set_mode(enum clock_event_mode mode,
 			   struct clock_event_device *clk)
 {
 	unsigned long ctrl;
 	switch (mode) {
 	case CLOCK_EVT_MODE_PERIODIC:
 		writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 		ctrl = TIMER_CTRL_PERIODIC;
 		ctrl |=
 		    TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 		    TIMER_CTRL_ENABLE;
 		break;
 	case CLOCK_EVT_MODE_ONESHOT:
 		/* period set, and timer enabled in 'next_event' hook */
 		ctrl = TIMER_CTRL_ONESHOT;
 		ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 		break;
 	case CLOCK_EVT_MODE_UNUSED:
 	case CLOCK_EVT_MODE_SHUTDOWN:
 	default:
 		ctrl = 0;
 	}
 	writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
 }
 static int timer_set_next_event(unsigned long evt,
 				struct clock_event_device *unused)
 {
 	unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
 	writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
 	writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
 	return 0;
 }
 static struct clock_event_device timer0_clockevent = {
 	.name = "timer0",
 	.shift = 32,
 	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 	.set_mode = timer_set_mode,
 	.set_next_event = timer_set_next_event,
 };
 /*
  * IRQ handler for the timer
  */
 static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
 {
 	struct clock_event_device *evt = &timer0_clockevent;
 	writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 	evt->event_handler(evt);
 	return IRQ_HANDLED;
 }
 static struct irqaction bcmring_timer_irq = {
 	.name = "bcmring Timer Tick",
 	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 	.handler = bcmring_timer_interrupt,
 };
 static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs)
 {
 	return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
 }
 static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs)
 {
 	return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
 }
 static struct clocksource clocksource_bcmring_timer1 = {
 	.name = "timer1",
 	.rating = 200,
 	.read = bcmring_get_cycles_timer1,
 	.mask = CLOCKSOURCE_MASK(32),
 	.shift = 20,
 	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 static struct clocksource clocksource_bcmring_timer3 = {
 	.name = "timer3",
 	.rating = 100,
 	.read = bcmring_get_cycles_timer3,
 	.mask = CLOCKSOURCE_MASK(32),
 	.shift = 20,
 	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 static int __init bcmring_clocksource_init(void)
 {
 	/* setup timer1 as free-running clocksource */
 	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 	writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
 	writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
 	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 	       TIMER1_VA_BASE + TIMER_CTRL);
 	clocksource_bcmring_timer1.mult =
 	    clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
 				 clocksource_bcmring_timer1.shift);
 	clocksource_register(&clocksource_bcmring_timer1);
 	/* setup timer3 as free-running clocksource */
 	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 	writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
 	writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
 	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 	       TIMER3_VA_BASE + TIMER_CTRL);
 	clocksource_bcmring_timer3.mult =
 	    clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
 				 clocksource_bcmring_timer3.shift);
 	clocksource_register(&clocksource_bcmring_timer3);
 	return 0;
 }
 /*
  * Set up timer interrupt, and return the current time in seconds.
  */
 void __init bcmring_init_timer(void)
 {
 	printk(KERN_INFO "bcmring_init_timer\n");
 	/*
 	 * Initialise to a known state (all timers off)
 	 */
 	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 	/*
 	 * Make irqs happen for the system timer
 	 */
 	setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
 	bcmring_clocksource_init();
 	timer0_clockevent.mult =
 	    div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 	timer0_clockevent.max_delta_ns =
 	    clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 	timer0_clockevent.min_delta_ns =
 	    clockevent_delta2ns(0xf, &timer0_clockevent);
 	timer0_clockevent.cpumask = cpumask_of(0);
 	clockevents_register_device(&timer0_clockevent);
 }
 struct sys_timer bcmring_timer = {
 	.init = bcmring_init_timer,
 };

arch/arm/mach-ep93xx/clock.c

Diff comments View file @ 3126c7b

1	/*	1	/*
2	* arch/arm/mach-ep93xx/clock.c	2	* arch/arm/mach-ep93xx/clock.c
3	* Clock control for Cirrus EP93xx chips.	3	* Clock control for Cirrus EP93xx chips.
4	*	4	*
5	* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>	5	* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6	*	6	*
7	* This program is free software; you can redistribute it and/or modify	7	* This program is free software; you can redistribute it and/or modify
8	* it under the terms of the GNU General Public License as published by	8	* it under the terms of the GNU General Public License as published by
9	* the Free Software Foundation; either version 2 of the License, or (at	9	* the Free Software Foundation; either version 2 of the License, or (at
10	* your option) any later version.	10	* your option) any later version.
11	*/	11	*/
12		12
13	#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt	13	#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
14		14
15	#include <linux/kernel.h>	15	#include <linux/kernel.h>
16	#include <linux/clk.h>	16	#include <linux/clk.h>
17	#include <linux/err.h>	17	#include <linux/err.h>
18	#include <linux/module.h>	18	#include <linux/module.h>
19	#include <linux/string.h>	19	#include <linux/string.h>
20	#include <linux/io.h>	20	#include <linux/io.h>
21	#include <linux/spinlock.h>	21	#include <linux/spinlock.h>
22		22
23	#include <mach/hardware.h>	23	#include <mach/hardware.h>
24		24
25	#include <asm/clkdev.h>	25	#include <asm/clkdev.h>
26	#include <asm/div64.h>	26	#include <asm/div64.h>
27		27
28		28
29	struct clk {	29	struct clk {
30	struct clk *parent;	30	struct clk *parent;
31	unsigned long rate;	31	unsigned long rate;
32	int users;	32	int users;
33	int sw_locked;	33	int sw_locked;
34	void __iomem *enable_reg;	34	void __iomem *enable_reg;
35	u32 enable_mask;	35	u32 enable_mask;
36		36
37	unsigned long (get_rate)(struct clk clk);	37	unsigned long (get_rate)(struct clk clk);
38	int (set_rate)(struct clk clk, unsigned long rate);	38	int (set_rate)(struct clk clk, unsigned long rate);
39	};	39	};
40		40
41		41
42	static unsigned long get_uart_rate(struct clk *clk);	42	static unsigned long get_uart_rate(struct clk *clk);
43		43
44	static int set_keytchclk_rate(struct clk *clk, unsigned long rate);	44	static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
45	static int set_div_rate(struct clk *clk, unsigned long rate);	45	static int set_div_rate(struct clk *clk, unsigned long rate);
46		46
47		47
48	static struct clk clk_xtali = {	48	static struct clk clk_xtali = {
49	.rate = EP93XX_EXT_CLK_RATE,	49	.rate = EP93XX_EXT_CLK_RATE,
50	};	50	};
51	static struct clk clk_uart1 = {	51	static struct clk clk_uart1 = {
52	.parent = &clk_xtali,	52	.parent = &clk_xtali,
53	.sw_locked = 1,	53	.sw_locked = 1,
54	.enable_reg = EP93XX_SYSCON_DEVCFG,	54	.enable_reg = EP93XX_SYSCON_DEVCFG,
55	.enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,	55	.enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
56	.get_rate = get_uart_rate,	56	.get_rate = get_uart_rate,
57	};	57	};
58	static struct clk clk_uart2 = {	58	static struct clk clk_uart2 = {
59	.parent = &clk_xtali,	59	.parent = &clk_xtali,
60	.sw_locked = 1,	60	.sw_locked = 1,
61	.enable_reg = EP93XX_SYSCON_DEVCFG,	61	.enable_reg = EP93XX_SYSCON_DEVCFG,
62	.enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,	62	.enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
63	.get_rate = get_uart_rate,	63	.get_rate = get_uart_rate,
64	};	64	};
65	static struct clk clk_uart3 = {	65	static struct clk clk_uart3 = {
66	.parent = &clk_xtali,	66	.parent = &clk_xtali,
67	.sw_locked = 1,	67	.sw_locked = 1,
68	.enable_reg = EP93XX_SYSCON_DEVCFG,	68	.enable_reg = EP93XX_SYSCON_DEVCFG,
69	.enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,	69	.enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
70	.get_rate = get_uart_rate,	70	.get_rate = get_uart_rate,
71	};	71	};
72	static struct clk clk_pll1 = {	72	static struct clk clk_pll1 = {
73	.parent = &clk_xtali,	73	.parent = &clk_xtali,
74	};	74	};
75	static struct clk clk_f = {	75	static struct clk clk_f = {
76	.parent = &clk_pll1,	76	.parent = &clk_pll1,
77	};	77	};
78	static struct clk clk_h = {	78	static struct clk clk_h = {
79	.parent = &clk_pll1,	79	.parent = &clk_pll1,
80	};	80	};
81	static struct clk clk_p = {	81	static struct clk clk_p = {
82	.parent = &clk_pll1,	82	.parent = &clk_pll1,
83	};	83	};
84	static struct clk clk_pll2 = {	84	static struct clk clk_pll2 = {
85	.parent = &clk_xtali,	85	.parent = &clk_xtali,
86	};	86	};
87	static struct clk clk_usb_host = {	87	static struct clk clk_usb_host = {
88	.parent = &clk_pll2,	88	.parent = &clk_pll2,
89	.enable_reg = EP93XX_SYSCON_PWRCNT,	89	.enable_reg = EP93XX_SYSCON_PWRCNT,
90	.enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,	90	.enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
91	};	91	};
92	static struct clk clk_keypad = {	92	static struct clk clk_keypad = {
93	.parent = &clk_xtali,	93	.parent = &clk_xtali,
94	.sw_locked = 1,	94	.sw_locked = 1,
95	.enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,	95	.enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
96	.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,	96	.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
97	.set_rate = set_keytchclk_rate,	97	.set_rate = set_keytchclk_rate,
98	};	98	};
99	static struct clk clk_spi = {	99	static struct clk clk_spi = {
100	.parent = &clk_xtali,	100	.parent = &clk_xtali,
101	.rate = EP93XX_EXT_CLK_RATE,	101	.rate = EP93XX_EXT_CLK_RATE,
102	};	102	};
103	static struct clk clk_pwm = {	103	static struct clk clk_pwm = {
104	.parent = &clk_xtali,	104	.parent = &clk_xtali,
105	.rate = EP93XX_EXT_CLK_RATE,	105	.rate = EP93XX_EXT_CLK_RATE,
106	};	106	};
107		107
108	static struct clk clk_video = {	108	static struct clk clk_video = {
109	.sw_locked = 1,	109	.sw_locked = 1,
110	.enable_reg = EP93XX_SYSCON_VIDCLKDIV,	110	.enable_reg = EP93XX_SYSCON_VIDCLKDIV,
111	.enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,	111	.enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
112	.set_rate = set_div_rate,	112	.set_rate = set_div_rate,
113	};	113	};
114		114
115	/* DMA Clocks */	115	/* DMA Clocks */
116	static struct clk clk_m2p0 = {	116	static struct clk clk_m2p0 = {
117	.parent = &clk_h,	117	.parent = &clk_h,
118	.enable_reg = EP93XX_SYSCON_PWRCNT,	118	.enable_reg = EP93XX_SYSCON_PWRCNT,
119	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,	119	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
120	};	120	};
121	static struct clk clk_m2p1 = {	121	static struct clk clk_m2p1 = {
122	.parent = &clk_h,	122	.parent = &clk_h,
123	.enable_reg = EP93XX_SYSCON_PWRCNT,	123	.enable_reg = EP93XX_SYSCON_PWRCNT,
124	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,	124	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
125	};	125	};
126	static struct clk clk_m2p2 = {	126	static struct clk clk_m2p2 = {
127	.parent = &clk_h,	127	.parent = &clk_h,
128	.enable_reg = EP93XX_SYSCON_PWRCNT,	128	.enable_reg = EP93XX_SYSCON_PWRCNT,
129	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,	129	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
130	};	130	};
131	static struct clk clk_m2p3 = {	131	static struct clk clk_m2p3 = {
132	.parent = &clk_h,	132	.parent = &clk_h,
133	.enable_reg = EP93XX_SYSCON_PWRCNT,	133	.enable_reg = EP93XX_SYSCON_PWRCNT,
134	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,	134	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
135	};	135	};
136	static struct clk clk_m2p4 = {	136	static struct clk clk_m2p4 = {
137	.parent = &clk_h,	137	.parent = &clk_h,
138	.enable_reg = EP93XX_SYSCON_PWRCNT,	138	.enable_reg = EP93XX_SYSCON_PWRCNT,
139	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,	139	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
140	};	140	};
141	static struct clk clk_m2p5 = {	141	static struct clk clk_m2p5 = {
142	.parent = &clk_h,	142	.parent = &clk_h,
143	.enable_reg = EP93XX_SYSCON_PWRCNT,	143	.enable_reg = EP93XX_SYSCON_PWRCNT,
144	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,	144	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
145	};	145	};
146	static struct clk clk_m2p6 = {	146	static struct clk clk_m2p6 = {
147	.parent = &clk_h,	147	.parent = &clk_h,
148	.enable_reg = EP93XX_SYSCON_PWRCNT,	148	.enable_reg = EP93XX_SYSCON_PWRCNT,
149	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,	149	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
150	};	150	};
151	static struct clk clk_m2p7 = {	151	static struct clk clk_m2p7 = {
152	.parent = &clk_h,	152	.parent = &clk_h,
153	.enable_reg = EP93XX_SYSCON_PWRCNT,	153	.enable_reg = EP93XX_SYSCON_PWRCNT,
154	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,	154	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
155	};	155	};
156	static struct clk clk_m2p8 = {	156	static struct clk clk_m2p8 = {
157	.parent = &clk_h,	157	.parent = &clk_h,
158	.enable_reg = EP93XX_SYSCON_PWRCNT,	158	.enable_reg = EP93XX_SYSCON_PWRCNT,
159	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,	159	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
160	};	160	};
161	static struct clk clk_m2p9 = {	161	static struct clk clk_m2p9 = {
162	.parent = &clk_h,	162	.parent = &clk_h,
163	.enable_reg = EP93XX_SYSCON_PWRCNT,	163	.enable_reg = EP93XX_SYSCON_PWRCNT,
164	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,	164	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
165	};	165	};
166	static struct clk clk_m2m0 = {	166	static struct clk clk_m2m0 = {
167	.parent = &clk_h,	167	.parent = &clk_h,
168	.enable_reg = EP93XX_SYSCON_PWRCNT,	168	.enable_reg = EP93XX_SYSCON_PWRCNT,
169	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,	169	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
170	};	170	};
171	static struct clk clk_m2m1 = {	171	static struct clk clk_m2m1 = {
172	.parent = &clk_h,	172	.parent = &clk_h,
173	.enable_reg = EP93XX_SYSCON_PWRCNT,	173	.enable_reg = EP93XX_SYSCON_PWRCNT,
174	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,	174	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
175	};	175	};
176		176
177	#define INIT_CK(dev,con,ck) \	177	#define INIT_CK(dev,con,ck) \
178	{ .dev_id = dev, .con_id = con, .clk = ck }	178	{ .dev_id = dev, .con_id = con, .clk = ck }
179		179
180	static struct clk_lookup clocks[] = {	180	static struct clk_lookup clocks[] = {
181	INIT_CK(NULL, "xtali", &clk_xtali),	181	INIT_CK(NULL, "xtali", &clk_xtali),
182	INIT_CK("apb:uart1", NULL, &clk_uart1),	182	INIT_CK("apb:uart1", NULL, &clk_uart1),
183	INIT_CK("apb:uart2", NULL, &clk_uart2),	183	INIT_CK("apb:uart2", NULL, &clk_uart2),
184	INIT_CK("apb:uart3", NULL, &clk_uart3),	184	INIT_CK("apb:uart3", NULL, &clk_uart3),
185	INIT_CK(NULL, "pll1", &clk_pll1),	185	INIT_CK(NULL, "pll1", &clk_pll1),
186	INIT_CK(NULL, "fclk", &clk_f),	186	INIT_CK(NULL, "fclk", &clk_f),
187	INIT_CK(NULL, "hclk", &clk_h),	187	INIT_CK(NULL, "hclk", &clk_h),
188	INIT_CK(NULL, "pclk", &clk_p),	188	INIT_CK(NULL, "apb_pclk", &clk_p),
189	INIT_CK(NULL, "pll2", &clk_pll2),	189	INIT_CK(NULL, "pll2", &clk_pll2),
190	INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),	190	INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
191	INIT_CK("ep93xx-keypad", NULL, &clk_keypad),	191	INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
192	INIT_CK("ep93xx-fb", NULL, &clk_video),	192	INIT_CK("ep93xx-fb", NULL, &clk_video),
193	INIT_CK("ep93xx-spi.0", NULL, &clk_spi),	193	INIT_CK("ep93xx-spi.0", NULL, &clk_spi),
194	INIT_CK(NULL, "pwm_clk", &clk_pwm),	194	INIT_CK(NULL, "pwm_clk", &clk_pwm),
195	INIT_CK(NULL, "m2p0", &clk_m2p0),	195	INIT_CK(NULL, "m2p0", &clk_m2p0),
196	INIT_CK(NULL, "m2p1", &clk_m2p1),	196	INIT_CK(NULL, "m2p1", &clk_m2p1),
197	INIT_CK(NULL, "m2p2", &clk_m2p2),	197	INIT_CK(NULL, "m2p2", &clk_m2p2),
198	INIT_CK(NULL, "m2p3", &clk_m2p3),	198	INIT_CK(NULL, "m2p3", &clk_m2p3),
199	INIT_CK(NULL, "m2p4", &clk_m2p4),	199	INIT_CK(NULL, "m2p4", &clk_m2p4),
200	INIT_CK(NULL, "m2p5", &clk_m2p5),	200	INIT_CK(NULL, "m2p5", &clk_m2p5),
201	INIT_CK(NULL, "m2p6", &clk_m2p6),	201	INIT_CK(NULL, "m2p6", &clk_m2p6),
202	INIT_CK(NULL, "m2p7", &clk_m2p7),	202	INIT_CK(NULL, "m2p7", &clk_m2p7),
203	INIT_CK(NULL, "m2p8", &clk_m2p8),	203	INIT_CK(NULL, "m2p8", &clk_m2p8),
204	INIT_CK(NULL, "m2p9", &clk_m2p9),	204	INIT_CK(NULL, "m2p9", &clk_m2p9),
205	INIT_CK(NULL, "m2m0", &clk_m2m0),	205	INIT_CK(NULL, "m2m0", &clk_m2m0),
206	INIT_CK(NULL, "m2m1", &clk_m2m1),	206	INIT_CK(NULL, "m2m1", &clk_m2m1),
207	};	207	};
208		208
209	static DEFINE_SPINLOCK(clk_lock);	209	static DEFINE_SPINLOCK(clk_lock);
210		210
211	static void __clk_enable(struct clk *clk)	211	static void __clk_enable(struct clk *clk)
212	{	212	{
213	if (!clk->users++) {	213	if (!clk->users++) {
214	if (clk->parent)	214	if (clk->parent)
215	__clk_enable(clk->parent);	215	__clk_enable(clk->parent);
216		216
217	if (clk->enable_reg) {	217	if (clk->enable_reg) {
218	u32 v;	218	u32 v;
219		219
220	v = __raw_readl(clk->enable_reg);	220	v = __raw_readl(clk->enable_reg);
221	v \|= clk->enable_mask;	221	v \|= clk->enable_mask;
222	if (clk->sw_locked)	222	if (clk->sw_locked)
223	ep93xx_syscon_swlocked_write(v, clk->enable_reg);	223	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
224	else	224	else
225	__raw_writel(v, clk->enable_reg);	225	__raw_writel(v, clk->enable_reg);
226	}	226	}
227	}	227	}
228	}	228	}
229		229
230	int clk_enable(struct clk *clk)	230	int clk_enable(struct clk *clk)
231	{	231	{
232	unsigned long flags;	232	unsigned long flags;
233		233
234	if (!clk)	234	if (!clk)
235	return -EINVAL;	235	return -EINVAL;
236		236
237	spin_lock_irqsave(&clk_lock, flags);	237	spin_lock_irqsave(&clk_lock, flags);
238	__clk_enable(clk);	238	__clk_enable(clk);
239	spin_unlock_irqrestore(&clk_lock, flags);	239	spin_unlock_irqrestore(&clk_lock, flags);
240		240
241	return 0;	241	return 0;
242	}	242	}
243	EXPORT_SYMBOL(clk_enable);	243	EXPORT_SYMBOL(clk_enable);
244		244
245	static void __clk_disable(struct clk *clk)	245	static void __clk_disable(struct clk *clk)
246	{	246	{
247	if (!--clk->users) {	247	if (!--clk->users) {
248	if (clk->enable_reg) {	248	if (clk->enable_reg) {
249	u32 v;	249	u32 v;
250		250
251	v = __raw_readl(clk->enable_reg);	251	v = __raw_readl(clk->enable_reg);
252	v &= ~clk->enable_mask;	252	v &= ~clk->enable_mask;
253	if (clk->sw_locked)	253	if (clk->sw_locked)
254	ep93xx_syscon_swlocked_write(v, clk->enable_reg);	254	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
255	else	255	else
256	__raw_writel(v, clk->enable_reg);	256	__raw_writel(v, clk->enable_reg);
257	}	257	}
258		258
259	if (clk->parent)	259	if (clk->parent)
260	__clk_disable(clk->parent);	260	__clk_disable(clk->parent);
261	}	261	}
262	}	262	}
263		263
264	void clk_disable(struct clk *clk)	264	void clk_disable(struct clk *clk)
265	{	265	{
266	unsigned long flags;	266	unsigned long flags;
267		267
268	if (!clk)	268	if (!clk)
269	return;	269	return;
270		270
271	spin_lock_irqsave(&clk_lock, flags);	271	spin_lock_irqsave(&clk_lock, flags);
272	__clk_disable(clk);	272	__clk_disable(clk);
273	spin_unlock_irqrestore(&clk_lock, flags);	273	spin_unlock_irqrestore(&clk_lock, flags);
274	}	274	}
275	EXPORT_SYMBOL(clk_disable);	275	EXPORT_SYMBOL(clk_disable);
276		276
277	static unsigned long get_uart_rate(struct clk *clk)	277	static unsigned long get_uart_rate(struct clk *clk)
278	{	278	{
279	unsigned long rate = clk_get_rate(clk->parent);	279	unsigned long rate = clk_get_rate(clk->parent);
280	u32 value;	280	u32 value;
281		281
282	value = __raw_readl(EP93XX_SYSCON_PWRCNT);	282	value = __raw_readl(EP93XX_SYSCON_PWRCNT);
283	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)	283	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
284	return rate;	284	return rate;
285	else	285	else
286	return rate / 2;	286	return rate / 2;
287	}	287	}
288		288
289	unsigned long clk_get_rate(struct clk *clk)	289	unsigned long clk_get_rate(struct clk *clk)
290	{	290	{
291	if (clk->get_rate)	291	if (clk->get_rate)
292	return clk->get_rate(clk);	292	return clk->get_rate(clk);
293		293
294	return clk->rate;	294	return clk->rate;
295	}	295	}
296	EXPORT_SYMBOL(clk_get_rate);	296	EXPORT_SYMBOL(clk_get_rate);
297		297
298	static int set_keytchclk_rate(struct clk *clk, unsigned long rate)	298	static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
299	{	299	{
300	u32 val;	300	u32 val;
301	u32 div_bit;	301	u32 div_bit;
302		302
303	val = __raw_readl(clk->enable_reg);	303	val = __raw_readl(clk->enable_reg);
304		304
305	/*	305	/*
306	* The Key Matrix and ADC clocks are configured using the same	306	* The Key Matrix and ADC clocks are configured using the same
307	* System Controller register. The clock used will be either	307	* System Controller register. The clock used will be either
308	* 1/4 or 1/16 the external clock rate depending on the	308	* 1/4 or 1/16 the external clock rate depending on the
309	* EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	309	* EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
310	* bit being set or cleared.	310	* bit being set or cleared.
311	*/	311	*/
312	div_bit = clk->enable_mask >> 15;	312	div_bit = clk->enable_mask >> 15;
313		313
314	if (rate == EP93XX_KEYTCHCLK_DIV4)	314	if (rate == EP93XX_KEYTCHCLK_DIV4)
315	val \|= div_bit;	315	val \|= div_bit;
316	else if (rate == EP93XX_KEYTCHCLK_DIV16)	316	else if (rate == EP93XX_KEYTCHCLK_DIV16)
317	val &= ~div_bit;	317	val &= ~div_bit;
318	else	318	else
319	return -EINVAL;	319	return -EINVAL;
320		320
321	ep93xx_syscon_swlocked_write(val, clk->enable_reg);	321	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
322	clk->rate = rate;	322	clk->rate = rate;
323	return 0;	323	return 0;
324	}	324	}
325		325
326	static int calc_clk_div(struct clk *clk, unsigned long rate,	326	static int calc_clk_div(struct clk *clk, unsigned long rate,
327	int psel, int esel, int pdiv, int div)	327	int psel, int esel, int pdiv, int div)
328	{	328	{
329	struct clk *mclk;	329	struct clk *mclk;
330	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;	330	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
331	int i, found = 0, __div = 0, __pdiv = 0;	331	int i, found = 0, __div = 0, __pdiv = 0;
332		332
333	/* Don't exceed the maximum rate */	333	/* Don't exceed the maximum rate */
334	max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),	334	max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
335	clk_xtali.rate / 4);	335	clk_xtali.rate / 4);
336	rate = min(rate, max_rate);	336	rate = min(rate, max_rate);
337		337
338	/*	338	/*
339	* Try the two pll's and the external clock	339	* Try the two pll's and the external clock
340	* Because the valid predividers are 2, 2.5 and 3, we multiply	340	* Because the valid predividers are 2, 2.5 and 3, we multiply
341	* all the clocks by 2 to avoid floating point math.	341	* all the clocks by 2 to avoid floating point math.
342	*	342	*
343	* This is based on the algorithm in the ep93xx raster guide:	343	* This is based on the algorithm in the ep93xx raster guide:
344	* http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf	344	* http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
345	*	345	*
346	*/	346	*/
347	for (i = 0; i < 3; i++) {	347	for (i = 0; i < 3; i++) {
348	if (i == 0)	348	if (i == 0)
349	mclk = &clk_xtali;	349	mclk = &clk_xtali;
350	else if (i == 1)	350	else if (i == 1)
351	mclk = &clk_pll1;	351	mclk = &clk_pll1;
352	else	352	else
353	mclk = &clk_pll2;	353	mclk = &clk_pll2;
354	mclk_rate = mclk->rate * 2;	354	mclk_rate = mclk->rate * 2;
355		355
356	/* Try each predivider value */	356	/* Try each predivider value */
357	for (__pdiv = 4; __pdiv <= 6; __pdiv++) {	357	for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
358	__div = mclk_rate / (rate * __pdiv);	358	__div = mclk_rate / (rate * __pdiv);
359	if (__div < 2 \|\| __div > 127)	359	if (__div < 2 \|\| __div > 127)
360	continue;	360	continue;
361		361
362	actual_rate = mclk_rate / (__pdiv * __div);	362	actual_rate = mclk_rate / (__pdiv * __div);
363		363
364	if (!found \|\| abs(actual_rate - rate) < rate_err) {	364	if (!found \|\| abs(actual_rate - rate) < rate_err) {
365	*pdiv = __pdiv - 3;	365	*pdiv = __pdiv - 3;
366	*div = __div;	366	*div = __div;
367	*psel = (i == 2);	367	*psel = (i == 2);
368	*esel = (i != 0);	368	*esel = (i != 0);
369	clk->parent = mclk;	369	clk->parent = mclk;
370	clk->rate = actual_rate;	370	clk->rate = actual_rate;
371	rate_err = abs(actual_rate - rate);	371	rate_err = abs(actual_rate - rate);
372	found = 1;	372	found = 1;
373	}	373	}
374	}	374	}
375	}	375	}
376		376
377	if (!found)	377	if (!found)
378	return -EINVAL;	378	return -EINVAL;
379		379
380	return 0;	380	return 0;
381	}	381	}
382		382
383	static int set_div_rate(struct clk *clk, unsigned long rate)	383	static int set_div_rate(struct clk *clk, unsigned long rate)
384	{	384	{
385	int err, psel = 0, esel = 0, pdiv = 0, div = 0;	385	int err, psel = 0, esel = 0, pdiv = 0, div = 0;
386	u32 val;	386	u32 val;
387		387
388	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);	388	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
389	if (err)	389	if (err)
390	return err;	390	return err;
391		391
392	/* Clear the esel, psel, pdiv and div bits */	392	/* Clear the esel, psel, pdiv and div bits */
393	val = __raw_readl(clk->enable_reg);	393	val = __raw_readl(clk->enable_reg);
394	val &= ~0x7fff;	394	val &= ~0x7fff;
395		395
396	/* Set the new esel, psel, pdiv and div bits for the new clock rate */	396	/* Set the new esel, psel, pdiv and div bits for the new clock rate */
397	val \|= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) \|	397	val \|= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) \|
398	(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) \|	398	(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) \|
399	(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) \| div;	399	(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) \| div;
400	ep93xx_syscon_swlocked_write(val, clk->enable_reg);	400	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
401	return 0;	401	return 0;
402	}	402	}
403		403
404	int clk_set_rate(struct clk *clk, unsigned long rate)	404	int clk_set_rate(struct clk *clk, unsigned long rate)
405	{	405	{
406	if (clk->set_rate)	406	if (clk->set_rate)
407	return clk->set_rate(clk, rate);	407	return clk->set_rate(clk, rate);
408		408
409	return -EINVAL;	409	return -EINVAL;
410	}	410	}
411	EXPORT_SYMBOL(clk_set_rate);	411	EXPORT_SYMBOL(clk_set_rate);
412		412
413		413
414	static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };	414	static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
415	static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };	415	static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
416	static char pclk_divisors[] = { 1, 2, 4, 8 };	416	static char pclk_divisors[] = { 1, 2, 4, 8 };
417		417
418	/*	418	/*
419	* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS	419	* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
420	*/	420	*/
421	static unsigned long calc_pll_rate(u32 config_word)	421	static unsigned long calc_pll_rate(u32 config_word)
422	{	422	{
423	unsigned long long rate;	423	unsigned long long rate;
424	int i;	424	int i;
425		425
426	rate = clk_xtali.rate;	426	rate = clk_xtali.rate;
427	rate = ((config_word >> 11) & 0x1f) + 1; / X1FBD */	427	rate = ((config_word >> 11) & 0x1f) + 1; / X1FBD */
428	rate = ((config_word >> 5) & 0x3f) + 1; / X2FBD */	428	rate = ((config_word >> 5) & 0x3f) + 1; / X2FBD */
429	do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */	429	do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
430	for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */	430	for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
431	rate >>= 1;	431	rate >>= 1;
432		432
433	return (unsigned long)rate;	433	return (unsigned long)rate;
434	}	434	}
435		435
436	static void __init ep93xx_dma_clock_init(void)	436	static void __init ep93xx_dma_clock_init(void)
437	{	437	{
438	clk_m2p0.rate = clk_h.rate;	438	clk_m2p0.rate = clk_h.rate;
439	clk_m2p1.rate = clk_h.rate;	439	clk_m2p1.rate = clk_h.rate;
440	clk_m2p2.rate = clk_h.rate;	440	clk_m2p2.rate = clk_h.rate;
441	clk_m2p3.rate = clk_h.rate;	441	clk_m2p3.rate = clk_h.rate;
442	clk_m2p4.rate = clk_h.rate;	442	clk_m2p4.rate = clk_h.rate;
443	clk_m2p5.rate = clk_h.rate;	443	clk_m2p5.rate = clk_h.rate;
444	clk_m2p6.rate = clk_h.rate;	444	clk_m2p6.rate = clk_h.rate;
445	clk_m2p7.rate = clk_h.rate;	445	clk_m2p7.rate = clk_h.rate;
446	clk_m2p8.rate = clk_h.rate;	446	clk_m2p8.rate = clk_h.rate;
447	clk_m2p9.rate = clk_h.rate;	447	clk_m2p9.rate = clk_h.rate;
448	clk_m2m0.rate = clk_h.rate;	448	clk_m2m0.rate = clk_h.rate;
449	clk_m2m1.rate = clk_h.rate;	449	clk_m2m1.rate = clk_h.rate;
450	}	450	}
451		451
452	static int __init ep93xx_clock_init(void)	452	static int __init ep93xx_clock_init(void)
453	{	453	{
454	u32 value;	454	u32 value;
455		455
456	/* Determine the bootloader configured pll1 rate */	456	/* Determine the bootloader configured pll1 rate */
457	value = __raw_readl(EP93XX_SYSCON_CLKSET1);	457	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
458	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))	458	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
459	clk_pll1.rate = clk_xtali.rate;	459	clk_pll1.rate = clk_xtali.rate;
460	else	460	else
461	clk_pll1.rate = calc_pll_rate(value);	461	clk_pll1.rate = calc_pll_rate(value);
462		462
463	/* Initialize the pll1 derived clocks */	463	/* Initialize the pll1 derived clocks */
464	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];	464	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
465	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];	465	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
466	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];	466	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
467	ep93xx_dma_clock_init();	467	ep93xx_dma_clock_init();
468		468
469	/* Determine the bootloader configured pll2 rate */	469	/* Determine the bootloader configured pll2 rate */
470	value = __raw_readl(EP93XX_SYSCON_CLKSET2);	470	value = __raw_readl(EP93XX_SYSCON_CLKSET2);
471	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))	471	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
472	clk_pll2.rate = clk_xtali.rate;	472	clk_pll2.rate = clk_xtali.rate;
473	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)	473	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
474	clk_pll2.rate = calc_pll_rate(value);	474	clk_pll2.rate = calc_pll_rate(value);
475	else	475	else
476	clk_pll2.rate = 0;	476	clk_pll2.rate = 0;
477		477
478	/* Initialize the pll2 derived clocks */	478	/* Initialize the pll2 derived clocks */
479	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);	479	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
480		480
481	/*	481	/*
482	* EP93xx SSP clock rate was doubled in version E2. For more information	482	* EP93xx SSP clock rate was doubled in version E2. For more information
483	* see:	483	* see:
484	* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf	484	* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
485	*/	485	*/
486	if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)	486	if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
487	clk_spi.rate /= 2;	487	clk_spi.rate /= 2;
488		488
489	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",	489	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
490	clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);	490	clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
491	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",	491	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
492	clk_f.rate / 1000000, clk_h.rate / 1000000,	492	clk_f.rate / 1000000, clk_h.rate / 1000000,
493	clk_p.rate / 1000000);	493	clk_p.rate / 1000000);
494		494
495	clkdev_add_table(clocks, ARRAY_SIZE(clocks));	495	clkdev_add_table(clocks, ARRAY_SIZE(clocks));
496	return 0;	496	return 0;
497	}	497	}
498	arch_initcall(ep93xx_clock_init);	498	arch_initcall(ep93xx_clock_init);
499		499

arch/arm/mach-integrator/core.c

Diff comments View file @ 3126c7b

 /*
  *  linux/arch/arm/mach-integrator/core.c
  *
  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2, as
  * published by the Free Software Foundation.
  */
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
 #include <linux/io.h>
 #include <asm/clkdev.h>
 #include <mach/clkdev.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <asm/irq.h>
 #include <mach/cm.h>
 #include <asm/system.h>
 #include <asm/leds.h>
 #include <asm/mach/time.h>
 static struct amba_pl010_data integrator_uart_data;
 static struct amba_device rtc_device = {
 	.dev		= {
 		.init_name = "mb:15",
 	},
 	.res		= {
 		.start	= INTEGRATOR_RTC_BASE,
 		.end	= INTEGRATOR_RTC_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	.irq		= { IRQ_RTCINT, NO_IRQ },
 	.periphid	= 0x00041030,
 };
 static struct amba_device uart0_device = {
 	.dev		= {
 		.init_name = "mb:16",
 		.platform_data = &integrator_uart_data,
 	},
 	.res		= {
 		.start	= INTEGRATOR_UART0_BASE,
 		.end	= INTEGRATOR_UART0_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	.irq		= { IRQ_UARTINT0, NO_IRQ },
 	.periphid	= 0x0041010,
 };
 static struct amba_device uart1_device = {
 	.dev		= {
 		.init_name = "mb:17",
 		.platform_data = &integrator_uart_data,
 	},
 	.res		= {
 		.start	= INTEGRATOR_UART1_BASE,
 		.end	= INTEGRATOR_UART1_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	.irq		= { IRQ_UARTINT1, NO_IRQ },
 	.periphid	= 0x0041010,
 };
 static struct amba_device kmi0_device = {
 	.dev		= {
 		.init_name = "mb:18",
 	},
 	.res		= {
 		.start	= KMI0_BASE,
 		.end	= KMI0_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	.irq		= { IRQ_KMIINT0, NO_IRQ },
 	.periphid	= 0x00041050,
 };
 static struct amba_device kmi1_device = {
 	.dev		= {
 		.init_name = "mb:19",
 	},
 	.res		= {
 		.start	= KMI1_BASE,
 		.end	= KMI1_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	.irq		= { IRQ_KMIINT1, NO_IRQ },
 	.periphid	= 0x00041050,
 };
 static struct amba_device *amba_devs[] __initdata = {
 	&rtc_device,
 	&uart0_device,
 	&uart1_device,
 	&kmi0_device,
 	&kmi1_device,
 };
 /*
  * These are fixed clocks.
  */
 static struct clk clk24mhz = {
 	.rate	= 24000000,
 };
 static struct clk uartclk = {
 	.rate	= 14745600,
 };
+static struct clk dummy_apb_pclk;
 static struct clk_lookup lookups[] = {
-	{	/* UART0 */
+	{	/* Bus clock */
+		.con_id		= "apb_pclk",
+		.clk		= &dummy_apb_pclk,
+	}, {	/* UART0 */
 		.dev_id		= "mb:16",
 		.clk		= &uartclk,
 	}, {	/* UART1 */
 		.dev_id		= "mb:17",
 		.clk		= &uartclk,
 	}, {	/* KMI0 */
 		.dev_id		= "mb:18",
 		.clk		= &clk24mhz,
 	}, {	/* KMI1 */
 		.dev_id		= "mb:19",
 		.clk		= &clk24mhz,
 	}, {	/* MMCI - IntegratorCP */
 		.dev_id		= "mb:1c",
 		.clk		= &uartclk,
 	}
 };
 static int __init integrator_init(void)
 {
 	int i;
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
 	return 0;
 }
 arch_initcall(integrator_init);
 /*
  * On the Integrator platform, the port RTS and DTR are provided by
  * bits in the following SC_CTRLS register bits:
  *        RTS  DTR
  *  UART0  7    6
  *  UART1  5    4
  */
 #define SC_CTRLC	IO_ADDRESS(INTEGRATOR_SC_CTRLC)
 #define SC_CTRLS	IO_ADDRESS(INTEGRATOR_SC_CTRLS)
 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 {
 	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 	if (dev == &uart0_device) {
 		rts_mask = 1 << 4;
 		dtr_mask = 1 << 5;
 	} else {
 		rts_mask = 1 << 6;
 		dtr_mask = 1 << 7;
 	}
 	if (mctrl & TIOCM_RTS)
 		ctrlc |= rts_mask;
 	else
 		ctrls |= rts_mask;
 	if (mctrl & TIOCM_DTR)
 		ctrlc |= dtr_mask;
 	else
 		ctrls |= dtr_mask;
 	__raw_writel(ctrls, SC_CTRLS);
 	__raw_writel(ctrlc, SC_CTRLC);
 }
 static struct amba_pl010_data integrator_uart_data = {
 	.set_mctrl = integrator_uart_set_mctrl,
 };
 #define CM_CTRL	IO_ADDRESS(INTEGRATOR_HDR_CTRL)
 static DEFINE_SPINLOCK(cm_lock);
 /**
  * cm_control - update the CM_CTRL register.
  * @mask: bits to change
  * @set: bits to set
  */
 void cm_control(u32 mask, u32 set)
 {
 	unsigned long flags;
 	u32 val;
 	spin_lock_irqsave(&cm_lock, flags);
 	val = readl(CM_CTRL) & ~mask;
 	writel(val | set, CM_CTRL);
 	spin_unlock_irqrestore(&cm_lock, flags);
 }
 EXPORT_SYMBOL(cm_control);

arch/arm/mach-nomadik/clock.c

Diff comments View file @ 3126c7b

 /*
  *  linux/arch/arm/mach-nomadik/clock.c
  *
  *  Copyright (C) 2009 Alessandro Rubini
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/errno.h>
 #include <linux/clk.h>
 #include <asm/clkdev.h>
 #include "clock.h"
 /*
  * The nomadik board uses generic clocks, but the serial pl011 file
  * calls clk_enable(), clk_disable(), clk_get_rate(), so we provide them
  */
 unsigned long clk_get_rate(struct clk *clk)
 {
 	return clk->rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
 /* enable and disable do nothing */
 int clk_enable(struct clk *clk)
 {
 	return 0;
 }
 EXPORT_SYMBOL(clk_enable);
 void clk_disable(struct clk *clk)
 {
 }
 EXPORT_SYMBOL(clk_disable);
 static struct clk clk_24 = {
 	.rate = 2400000,
 };
 static struct clk clk_48 = {
 	.rate = 48 * 1000 * 1000,
 };
 /*
  * Catch-all default clock to satisfy drivers using the clk API.  We don't
  * model the actual hardware clocks yet.
  */
 static struct clk clk_default;
 #define CLK(_clk, dev)				\
 	{					\
 		.clk		= _clk,		\
 		.dev_id		= dev,		\
 	}
 static struct clk_lookup lookups[] = {
+	{
+		.con_id		= "apb_pclk",
+		.clk		= &clk_default,
+	},
 	CLK(&clk_24, "mtu0"),
 	CLK(&clk_24, "mtu1"),
 	CLK(&clk_48, "uart0"),
 	CLK(&clk_48, "uart1"),
 	CLK(&clk_default, "gpio.0"),
 	CLK(&clk_default, "gpio.1"),
 	CLK(&clk_default, "gpio.2"),
 	CLK(&clk_default, "gpio.3"),
 	CLK(&clk_default, "rng"),
 };
 int __init clk_init(void)
 {
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 	return 0;
 }

arch/arm/mach-omap2/clock3xxx_data.c

Diff comments View file @ 3126c7b

 /*
  * OMAP3 clock data
  *
  * Copyright (C) 2007-2010 Texas Instruments, Inc.
  * Copyright (C) 2007-2010 Nokia Corporation
  *
  * Written by Paul Walmsley
  * With many device clock fixes by Kevin Hilman and Jouni Högander
  * DPLL bypass clock support added by Roman Tereshonkov
  *
  */
 /*
  * Virtual clocks are introduced as convenient tools.
  * They are sources for other clocks and not supposed
  * to be requested from drivers directly.
  */
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/list.h>
 #include <plat/control.h>
 #include <plat/clkdev_omap.h>
 #include "clock.h"
 #include "clock3xxx.h"
 #include "clock34xx.h"
 #include "clock36xx.h"
 #include "clock3517.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
 #include "prm.h"
 #include "prm-regbits-34xx.h"
 /*
  * clocks
  */
 #define OMAP_CM_REGADDR		OMAP34XX_CM_REGADDR
 /* Maximum DPLL multiplier, divider values for OMAP3 */
 #define OMAP3_MAX_DPLL_MULT		2047
 #define OMAP3630_MAX_JTYPE_DPLL_MULT	4095
 #define OMAP3_MAX_DPLL_DIV		128
 /*
  * DPLL1 supplies clock to the MPU.
  * DPLL2 supplies clock to the IVA2.
  * DPLL3 supplies CORE domain clocks.
  * DPLL4 supplies peripheral clocks.
  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  */
 /* Forward declarations for DPLL bypass clocks */
 static struct clk dpll1_fck;
 static struct clk dpll2_fck;
 /* PRM CLOCKS */
 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
 static struct clk omap_32k_fck = {
 	.name		= "omap_32k_fck",
 	.ops		= &clkops_null,
 	.rate		= 32768,
 };
 static struct clk secure_32k_fck = {
 	.name		= "secure_32k_fck",
 	.ops		= &clkops_null,
 	.rate		= 32768,
 };
 /* Virtual source clocks for osc_sys_ck */
 static struct clk virt_12m_ck = {
 	.name		= "virt_12m_ck",
 	.ops		= &clkops_null,
 	.rate		= 12000000,
 };
 static struct clk virt_13m_ck = {
 	.name		= "virt_13m_ck",
 	.ops		= &clkops_null,
 	.rate		= 13000000,
 };
 static struct clk virt_16_8m_ck = {
 	.name		= "virt_16_8m_ck",
 	.ops		= &clkops_null,
 	.rate		= 16800000,
 };
 static struct clk virt_19_2m_ck = {
 	.name		= "virt_19_2m_ck",
 	.ops		= &clkops_null,
 	.rate		= 19200000,
 };
 static struct clk virt_26m_ck = {
 	.name		= "virt_26m_ck",
 	.ops		= &clkops_null,
 	.rate		= 26000000,
 };
 static struct clk virt_38_4m_ck = {
 	.name		= "virt_38_4m_ck",
 	.ops		= &clkops_null,
 	.rate		= 38400000,
 };
 static const struct clksel_rate osc_sys_12m_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate osc_sys_13m_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 	{ .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 0 }
 };
 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate osc_sys_26m_rates[] = {
 	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 	{ .div = 1, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel osc_sys_clksel[] = {
 	{ .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 	{ .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 	{ .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 	{ .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 	{ .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 	{ .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 	{ .parent = NULL },
 };
 /* Oscillator clock */
 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 static struct clk osc_sys_ck = {
 	.name		= "osc_sys_ck",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP3430_PRM_CLKSEL,
 	.clksel_mask	= OMAP3430_SYS_CLKIN_SEL_MASK,
 	.clksel		= osc_sys_clksel,
 	/* REVISIT: deal with autoextclkmode? */
 	.recalc		= &omap2_clksel_recalc,
 };
 static const struct clksel_rate div2_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel sys_clksel[] = {
 	{ .parent = &osc_sys_ck, .rates = div2_rates },
 	{ .parent = NULL }
 };
 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 static struct clk sys_ck = {
 	.name		= "sys_ck",
 	.ops		= &clkops_null,
 	.parent		= &osc_sys_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP3430_PRM_CLKSRC_CTRL,
 	.clksel_mask	= OMAP_SYSCLKDIV_MASK,
 	.clksel		= sys_clksel,
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk sys_altclk = {
 	.name		= "sys_altclk",
 	.ops		= &clkops_null,
 };
 /* Optional external clock input for some McBSPs */
 static struct clk mcbsp_clks = {
 	.name		= "mcbsp_clks",
 	.ops		= &clkops_null,
 };
 /* PRM EXTERNAL CLOCK OUTPUT */
 static struct clk sys_clkout1 = {
 	.name		= "sys_clkout1",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &osc_sys_ck,
 	.enable_reg	= OMAP3430_PRM_CLKOUT_CTRL,
 	.enable_bit	= OMAP3430_CLKOUT_EN_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 /* DPLLS */
 /* CM CLOCKS */
 static const struct clksel_rate div16_dpll_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate dpll4_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 	{ .div = 17, .val = 17, .flags = RATE_IN_36XX },
 	{ .div = 18, .val = 18, .flags = RATE_IN_36XX },
 	{ .div = 19, .val = 19, .flags = RATE_IN_36XX },
 	{ .div = 20, .val = 20, .flags = RATE_IN_36XX },
 	{ .div = 21, .val = 21, .flags = RATE_IN_36XX },
 	{ .div = 22, .val = 22, .flags = RATE_IN_36XX },
 	{ .div = 23, .val = 23, .flags = RATE_IN_36XX },
 	{ .div = 24, .val = 24, .flags = RATE_IN_36XX },
 	{ .div = 25, .val = 25, .flags = RATE_IN_36XX },
 	{ .div = 26, .val = 26, .flags = RATE_IN_36XX },
 	{ .div = 27, .val = 27, .flags = RATE_IN_36XX },
 	{ .div = 28, .val = 28, .flags = RATE_IN_36XX },
 	{ .div = 29, .val = 29, .flags = RATE_IN_36XX },
 	{ .div = 30, .val = 30, .flags = RATE_IN_36XX },
 	{ .div = 31, .val = 31, .flags = RATE_IN_36XX },
 	{ .div = 32, .val = 32, .flags = RATE_IN_36XX },
 	{ .div = 0 }
 };
 /* DPLL1 */
 /* MPU clock source */
 /* Type: DPLL */
 static struct dpll_data dpll1_dd = {
 	.mult_div1_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 	.mult_mask	= OMAP3430_MPU_DPLL_MULT_MASK,
 	.div1_mask	= OMAP3430_MPU_DPLL_DIV_MASK,
 	.clk_bypass	= &dpll1_fck,
 	.clk_ref	= &sys_ck,
 	.freqsel_mask	= OMAP3430_MPU_DPLL_FREQSEL_MASK,
 	.control_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 	.enable_mask	= OMAP3430_EN_MPU_DPLL_MASK,
 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	.auto_recal_bit	= OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 	.recal_en_bit	= OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 	.recal_st_bit	= OMAP3430_MPU_DPLL_ST_SHIFT,
 	.autoidle_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 	.autoidle_mask	= OMAP3430_AUTO_MPU_DPLL_MASK,
 	.idlest_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 	.idlest_mask	= OMAP3430_ST_MPU_CLK_MASK,
 	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 	.min_divider	= 1,
 	.max_divider	= OMAP3_MAX_DPLL_DIV,
 	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 static struct clk dpll1_ck = {
 	.name		= "dpll1_ck",
 	.ops		= &clkops_null,
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll1_dd,
 	.round_rate	= &omap2_dpll_round_rate,
 	.set_rate	= &omap3_noncore_dpll_set_rate,
 	.clkdm_name	= "dpll1_clkdm",
 	.recalc		= &omap3_dpll_recalc,
 };
 /*
  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  * DPLL isn't bypassed.
  */
 static struct clk dpll1_x2_ck = {
 	.name		= "dpll1_x2_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll1_ck,
 	.clkdm_name	= "dpll1_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 	{ .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 	{ .parent = NULL }
 };
 /*
  * Does not exist in the TRM - needed to separate the M2 divider from
  * bypass selection in mpu_ck
  */
 static struct clk dpll1_x2m2_ck = {
 	.name		= "dpll1_x2m2_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll1_x2_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 	.clksel_mask	= OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 	.clksel		= div16_dpll1_x2m2_clksel,
 	.clkdm_name	= "dpll1_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* DPLL2 */
 /* IVA2 clock source */
 /* Type: DPLL */
 static struct dpll_data dpll2_dd = {
 	.mult_div1_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 	.mult_mask	= OMAP3430_IVA2_DPLL_MULT_MASK,
 	.div1_mask	= OMAP3430_IVA2_DPLL_DIV_MASK,
 	.clk_bypass	= &dpll2_fck,
 	.clk_ref	= &sys_ck,
 	.freqsel_mask	= OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 	.control_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 	.enable_mask	= OMAP3430_EN_IVA2_DPLL_MASK,
 	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 				(1 << DPLL_LOW_POWER_BYPASS),
 	.auto_recal_bit	= OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 	.recal_en_bit	= OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 	.recal_st_bit	= OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 	.autoidle_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 	.autoidle_mask	= OMAP3430_AUTO_IVA2_DPLL_MASK,
 	.idlest_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 	.idlest_mask	= OMAP3430_ST_IVA2_CLK_MASK,
 	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 	.min_divider	= 1,
 	.max_divider	= OMAP3_MAX_DPLL_DIV,
 	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 static struct clk dpll2_ck = {
 	.name		= "dpll2_ck",
 	.ops		= &clkops_omap3_noncore_dpll_ops,
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll2_dd,
 	.round_rate	= &omap2_dpll_round_rate,
 	.set_rate	= &omap3_noncore_dpll_set_rate,
 	.clkdm_name	= "dpll2_clkdm",
 	.recalc		= &omap3_dpll_recalc,
 };
 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 	{ .parent = &dpll2_ck, .rates = div16_dpll_rates },
 	{ .parent = NULL }
 };
 /*
  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
  * or CLKOUTX2. CLKOUT seems most plausible.
  */
 static struct clk dpll2_m2_ck = {
 	.name		= "dpll2_m2_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll2_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 					  OMAP3430_CM_CLKSEL2_PLL),
 	.clksel_mask	= OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 	.clksel		= div16_dpll2_m2x2_clksel,
 	.clkdm_name	= "dpll2_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /*
  * DPLL3
  * Source clock for all interfaces and for some device fclks
  * REVISIT: Also supports fast relock bypass - not included below
  */
 static struct dpll_data dpll3_dd = {
 	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.mult_mask	= OMAP3430_CORE_DPLL_MULT_MASK,
 	.div1_mask	= OMAP3430_CORE_DPLL_DIV_MASK,
 	.clk_bypass	= &sys_ck,
 	.clk_ref	= &sys_ck,
 	.freqsel_mask	= OMAP3430_CORE_DPLL_FREQSEL_MASK,
 	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_mask	= OMAP3430_EN_CORE_DPLL_MASK,
 	.auto_recal_bit	= OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 	.recal_en_bit	= OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 	.recal_st_bit	= OMAP3430_CORE_DPLL_ST_SHIFT,
 	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 	.autoidle_mask	= OMAP3430_AUTO_CORE_DPLL_MASK,
 	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 	.idlest_mask	= OMAP3430_ST_CORE_CLK_MASK,
 	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 	.min_divider	= 1,
 	.max_divider	= OMAP3_MAX_DPLL_DIV,
 	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 static struct clk dpll3_ck = {
 	.name		= "dpll3_ck",
 	.ops		= &clkops_null,
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll3_dd,
 	.round_rate	= &omap2_dpll_round_rate,
 	.clkdm_name	= "dpll3_clkdm",
 	.recalc		= &omap3_dpll_recalc,
 };
 /*
  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  * DPLL isn't bypassed
  */
 static struct clk dpll3_x2_ck = {
 	.name		= "dpll3_x2_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll3_ck,
 	.clkdm_name	= "dpll3_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 static const struct clksel_rate div31_dpll3_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
 	{ .div = 0 },
 };
 static const struct clksel div31_dpll3m2_clksel[] = {
 	{ .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 	{ .parent = NULL }
 };
 /* DPLL3 output M2 - primary control point for CORE speed */
 static struct clk dpll3_m2_ck = {
 	.name		= "dpll3_m2_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll3_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 	.clksel		= div31_dpll3m2_clksel,
 	.clkdm_name	= "dpll3_clkdm",
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap3_core_dpll_m2_set_rate,
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk core_ck = {
 	.name		= "core_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll3_m2_ck,
 	.recalc		= &followparent_recalc,
 };
 static struct clk dpll3_m2x2_ck = {
 	.name		= "dpll3_m2x2_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll3_m2_ck,
 	.clkdm_name	= "dpll3_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static const struct clksel div16_dpll3_clksel[] = {
 	{ .parent = &dpll3_ck, .rates = div16_dpll_rates },
 	{ .parent = NULL }
 };
 /* This virtual clock is the source for dpll3_m3x2_ck */
 static struct clk dpll3_m3_ck = {
 	.name		= "dpll3_m3_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll3_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_DIV_DPLL3_MASK,
 	.clksel		= div16_dpll3_clksel,
 	.clkdm_name	= "dpll3_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll3_m3x2_ck = {
 	.name		= "dpll3_m3x2_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &dpll3_m3_ck,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_EMU_CORE_SHIFT,
 	.flags		= INVERT_ENABLE,
 	.clkdm_name	= "dpll3_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 static struct clk emu_core_alwon_ck = {
 	.name		= "emu_core_alwon_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll3_m3x2_ck,
 	.clkdm_name	= "dpll3_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* DPLL4 */
 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 /* Type: DPLL */
 static struct dpll_data dpll4_dd;
 static struct dpll_data dpll4_dd_34xx __initdata = {
 	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 	.mult_mask	= OMAP3430_PERIPH_DPLL_MULT_MASK,
 	.div1_mask	= OMAP3430_PERIPH_DPLL_DIV_MASK,
 	.clk_bypass	= &sys_ck,
 	.clk_ref	= &sys_ck,
 	.freqsel_mask	= OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_mask	= OMAP3430_EN_PERIPH_DPLL_MASK,
 	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 	.auto_recal_bit	= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 	.recal_en_bit	= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 	.recal_st_bit	= OMAP3430_PERIPH_DPLL_ST_SHIFT,
 	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 	.autoidle_mask	= OMAP3430_AUTO_PERIPH_DPLL_MASK,
 	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 	.idlest_mask	= OMAP3430_ST_PERIPH_CLK_MASK,
 	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 	.min_divider	= 1,
 	.max_divider	= OMAP3_MAX_DPLL_DIV,
 	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 static struct dpll_data dpll4_dd_3630 __initdata = {
 	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 	.mult_mask	= OMAP3630_PERIPH_DPLL_MULT_MASK,
 	.div1_mask	= OMAP3430_PERIPH_DPLL_DIV_MASK,
 	.clk_bypass	= &sys_ck,
 	.clk_ref	= &sys_ck,
 	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_mask	= OMAP3430_EN_PERIPH_DPLL_MASK,
 	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 	.auto_recal_bit	= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 	.recal_en_bit	= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 	.recal_st_bit	= OMAP3430_PERIPH_DPLL_ST_SHIFT,
 	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 	.autoidle_mask	= OMAP3430_AUTO_PERIPH_DPLL_MASK,
 	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 	.idlest_mask	= OMAP3430_ST_PERIPH_CLK_MASK,
 	.max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 	.min_divider	= 1,
 	.max_divider	= OMAP3_MAX_DPLL_DIV,
 	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
 	.flags		= DPLL_J_TYPE
 };
 static struct clk dpll4_ck = {
 	.name		= "dpll4_ck",
 	.ops		= &clkops_omap3_noncore_dpll_ops,
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll4_dd,
 	.round_rate	= &omap2_dpll_round_rate,
 	.set_rate	= &omap3_dpll4_set_rate,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap3_dpll_recalc,
 };
 /*
  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  * DPLL isn't bypassed --
  * XXX does this serve any downstream clocks?
  */
 static struct clk dpll4_x2_ck = {
 	.name		= "dpll4_x2_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll4_ck,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 static const struct clksel dpll4_clksel[] = {
 	{ .parent = &dpll4_ck, .rates = dpll4_rates },
 	{ .parent = NULL }
 };
 /* This virtual clock is the source for dpll4_m2x2_ck */
 static struct clk dpll4_m2_ck = {
 	.name		= "dpll4_m2_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll4_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 	.clksel_mask	= OMAP3630_DIV_96M_MASK,
 	.clksel		= dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m2x2_ck = {
 	.name		= "dpll4_m2x2_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &dpll4_m2_ck,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_96M_SHIFT,
 	.flags		= INVERT_ENABLE,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 /*
  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
  * CM_96K_(F)CLK.
  */
 /* Adding 192MHz Clock node needed by SGX */
 static struct clk omap_192m_alwon_fck = {
 	.name		= "omap_192m_alwon_fck",
 	.ops		= &clkops_null,
 	.parent		= &dpll4_m2x2_ck,
 	.recalc		= &followparent_recalc,
 };
 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_36XX },
 	{ .div = 2, .val = 2, .flags = RATE_IN_36XX },
 	{ .div = 0 }
 };
 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 	{ .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
 	{ .parent = NULL }
 };
 static const struct clksel_rate omap_96m_dpll_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate omap_96m_sys_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static struct clk omap_96m_alwon_fck = {
 	.name		= "omap_96m_alwon_fck",
 	.ops		= &clkops_null,
 	.parent		= &dpll4_m2x2_ck,
 	.recalc		= &followparent_recalc,
 };
 static struct clk omap_96m_alwon_fck_3630 = {
 	.name		= "omap_96m_alwon_fck",
 	.parent		= &omap_192m_alwon_fck,
 	.init		= &omap2_init_clksel_parent,
 	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3630_CLKSEL_96M_MASK,
 	.clksel		= omap_96m_alwon_fck_clksel
 };
 static struct clk cm_96m_fck = {
 	.name		= "cm_96m_fck",
 	.ops		= &clkops_null,
 	.parent		= &omap_96m_alwon_fck,
 	.recalc		= &followparent_recalc,
 };
 static const struct clksel omap_96m_fck_clksel[] = {
 	{ .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 	{ .parent = &sys_ck,	 .rates = omap_96m_sys_rates },
 	{ .parent = NULL }
 };
 static struct clk omap_96m_fck = {
 	.name		= "omap_96m_fck",
 	.ops		= &clkops_null,
 	.parent		= &sys_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_SOURCE_96M_MASK,
 	.clksel		= omap_96m_fck_clksel,
 	.recalc		= &omap2_clksel_recalc,
 };
 /* This virtual clock is the source for dpll4_m3x2_ck */
 static struct clk dpll4_m3_ck = {
 	.name		= "dpll4_m3_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll4_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_TV_MASK,
 	.clksel		= dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m3x2_ck = {
 	.name		= "dpll4_m3x2_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &dpll4_m3_ck,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_TV_SHIFT,
 	.flags		= INVERT_ENABLE,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate omap_54m_alt_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel omap_54m_clksel[] = {
 	{ .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 	{ .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 	{ .parent = NULL }
 };
 static struct clk omap_54m_fck = {
 	.name		= "omap_54m_fck",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_SOURCE_54M_MASK,
 	.clksel		= omap_54m_clksel,
 	.recalc		= &omap2_clksel_recalc,
 };
 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 	{ .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate omap_48m_alt_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel omap_48m_clksel[] = {
 	{ .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 	{ .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 	{ .parent = NULL }
 };
 static struct clk omap_48m_fck = {
 	.name		= "omap_48m_fck",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_SOURCE_48M_MASK,
 	.clksel		= omap_48m_clksel,
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk omap_12m_fck = {
 	.name		= "omap_12m_fck",
 	.ops		= &clkops_null,
 	.parent		= &omap_48m_fck,
 	.fixed_div	= 4,
 	.recalc		= &omap_fixed_divisor_recalc,
 };
 /* This virtual clock is the source for dpll4_m4x2_ck */
 static struct clk dpll4_m4_ck = {
 	.name		= "dpll4_m4_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll4_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_DSS1_MASK,
 	.clksel		= dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 	.set_rate	= &omap2_clksel_set_rate,
 	.round_rate	= &omap2_clksel_round_rate,
 };
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m4x2_ck = {
 	.name		= "dpll4_m4x2_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &dpll4_m4_ck,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_DSS1_SHIFT,
 	.flags		= INVERT_ENABLE,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 /* This virtual clock is the source for dpll4_m5x2_ck */
 static struct clk dpll4_m5_ck = {
 	.name		= "dpll4_m5_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll4_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,
 	.clksel		= dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
 	.set_rate	= &omap2_clksel_set_rate,
 	.round_rate	= &omap2_clksel_round_rate,
 	.recalc		= &omap2_clksel_recalc,
 };
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m5x2_ck = {
 	.name		= "dpll4_m5x2_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &dpll4_m5_ck,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_CAM_SHIFT,
 	.flags		= INVERT_ENABLE,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 /* This virtual clock is the source for dpll4_m6x2_ck */
 static struct clk dpll4_m6_ck = {
 	.name		= "dpll4_m6_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll4_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_DIV_DPLL4_MASK,
 	.clksel		= dpll4_clksel,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m6x2_ck = {
 	.name		= "dpll4_m6x2_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &dpll4_m6_ck,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 	.flags		= INVERT_ENABLE,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 static struct clk emu_per_alwon_ck = {
 	.name		= "emu_per_alwon_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll4_m6x2_ck,
 	.clkdm_name	= "dpll4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* DPLL5 */
 /* Supplies 120MHz clock, USIM source clock */
 /* Type: DPLL */
 /* 3430ES2 only */
 static struct dpll_data dpll5_dd = {
 	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 	.mult_mask	= OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 	.div1_mask	= OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 	.clk_bypass	= &sys_ck,
 	.clk_ref	= &sys_ck,
 	.freqsel_mask	= OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 	.enable_mask	= OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 	.auto_recal_bit	= OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 	.recal_en_bit	= OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 	.recal_st_bit	= OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 	.autoidle_mask	= OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 	.idlest_mask	= OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 	.min_divider	= 1,
 	.max_divider	= OMAP3_MAX_DPLL_DIV,
 	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 static struct clk dpll5_ck = {
 	.name		= "dpll5_ck",
 	.ops		= &clkops_omap3_noncore_dpll_ops,
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll5_dd,
 	.round_rate	= &omap2_dpll_round_rate,
 	.set_rate	= &omap3_noncore_dpll_set_rate,
 	.clkdm_name	= "dpll5_clkdm",
 	.recalc		= &omap3_dpll_recalc,
 };
 static const struct clksel div16_dpll5_clksel[] = {
 	{ .parent = &dpll5_ck, .rates = div16_dpll_rates },
 	{ .parent = NULL }
 };
 static struct clk dpll5_m2_ck = {
 	.name		= "dpll5_m2_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll5_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 	.clksel_mask	= OMAP3430ES2_DIV_120M_MASK,
 	.clksel		= div16_dpll5_clksel,
 	.clkdm_name	= "dpll5_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* CM EXTERNAL CLOCK OUTPUTS */
 static const struct clksel_rate clkout2_src_core_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate clkout2_src_sys_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate clkout2_src_96m_rates[] = {
 	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate clkout2_src_54m_rates[] = {
 	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel clkout2_src_clksel[] = {
 	{ .parent = &core_ck,		.rates = clkout2_src_core_rates },
 	{ .parent = &sys_ck,		.rates = clkout2_src_sys_rates },
 	{ .parent = &cm_96m_fck,	.rates = clkout2_src_96m_rates },
 	{ .parent = &omap_54m_fck,	.rates = clkout2_src_54m_rates },
 	{ .parent = NULL }
 };
 static struct clk clkout2_src_ck = {
 	.name		= "clkout2_src_ck",
 	.ops		= &clkops_omap2_dflt,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP3430_CM_CLKOUT_CTRL,
 	.enable_bit	= OMAP3430_CLKOUT2_EN_SHIFT,
 	.clksel_reg	= OMAP3430_CM_CLKOUT_CTRL,
 	.clksel_mask	= OMAP3430_CLKOUT2SOURCE_MASK,
 	.clksel		= clkout2_src_clksel,
 	.clkdm_name	= "core_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static const struct clksel_rate sys_clkout2_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 4, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 8, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 16, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel sys_clkout2_clksel[] = {
 	{ .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 	{ .parent = NULL },
 };
 static struct clk sys_clkout2 = {
 	.name		= "sys_clkout2",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP3430_CM_CLKOUT_CTRL,
 	.clksel_mask	= OMAP3430_CLKOUT2_DIV_MASK,
 	.clksel		= sys_clkout2_clksel,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate
 };
 /* CM OUTPUT CLOCKS */
 static struct clk corex2_fck = {
 	.name		= "corex2_fck",
 	.ops		= &clkops_null,
 	.parent		= &dpll3_m2x2_ck,
 	.recalc		= &followparent_recalc,
 };
 /* DPLL power domain clock controls */
 static const struct clksel_rate div4_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel div4_core_clksel[] = {
 	{ .parent = &core_ck, .rates = div4_rates },
 	{ .parent = NULL }
 };
 /*
  * REVISIT: Are these in DPLL power domain or CM power domain? docs
  * may be inconsistent here?
  */
 static struct clk dpll1_fck = {
 	.name		= "dpll1_fck",
 	.ops		= &clkops_null,
 	.parent		= &core_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 	.clksel_mask	= OMAP3430_MPU_CLK_SRC_MASK,
 	.clksel		= div4_core_clksel,
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk mpu_ck = {
 	.name		= "mpu_ck",
 	.ops		= &clkops_null,
 	.parent		= &dpll1_x2m2_ck,
 	.clkdm_name	= "mpu_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
 static const struct clksel_rate arm_fck_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel arm_fck_clksel[] = {
 	{ .parent = &mpu_ck, .rates = arm_fck_rates },
 	{ .parent = NULL }
 };
 static struct clk arm_fck = {
 	.name		= "arm_fck",
 	.ops		= &clkops_null,
 	.parent		= &mpu_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 	.clksel_mask	= OMAP3430_ST_MPU_CLK_MASK,
 	.clksel		= arm_fck_clksel,
 	.clkdm_name	= "mpu_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* XXX What about neon_clkdm ? */
 /*
  * REVISIT: This clock is never specifically defined in the 3430 TRM,
  * although it is referenced - so this is a guess
  */
 static struct clk emu_mpu_alwon_ck = {
 	.name		= "emu_mpu_alwon_ck",
 	.ops		= &clkops_null,
 	.parent		= &mpu_ck,
 	.recalc		= &followparent_recalc,
 };
 static struct clk dpll2_fck = {
 	.name		= "dpll2_fck",
 	.ops		= &clkops_null,
 	.parent		= &core_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 	.clksel_mask	= OMAP3430_IVA2_CLK_SRC_MASK,
 	.clksel		= div4_core_clksel,
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk iva2_ck = {
 	.name		= "iva2_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &dpll2_m2_ck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 	.clkdm_name	= "iva2_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* Common interface clocks */
 static const struct clksel div2_core_clksel[] = {
 	{ .parent = &core_ck, .rates = div2_rates },
 	{ .parent = NULL }
 };
 static struct clk l3_ick = {
 	.name		= "l3_ick",
 	.ops		= &clkops_null,
 	.parent		= &core_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_L3_MASK,
 	.clksel		= div2_core_clksel,
 	.clkdm_name	= "core_l3_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static const struct clksel div2_l3_clksel[] = {
 	{ .parent = &l3_ick, .rates = div2_rates },
 	{ .parent = NULL }
 };
 static struct clk l4_ick = {
 	.name		= "l4_ick",
 	.ops		= &clkops_null,
 	.parent		= &l3_ick,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_L4_MASK,
 	.clksel		= div2_l3_clksel,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static const struct clksel div2_l4_clksel[] = {
 	{ .parent = &l4_ick, .rates = div2_rates },
 	{ .parent = NULL }
 };
 static struct clk rm_ick = {
 	.name		= "rm_ick",
 	.ops		= &clkops_null,
 	.parent		= &l4_ick,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_RM_MASK,
 	.clksel		= div2_l4_clksel,
 	.recalc		= &omap2_clksel_recalc,
 };
 /* GFX power domain */
 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
 static const struct clksel gfx_l3_clksel[] = {
 	{ .parent = &l3_ick, .rates = gfx_l3_rates },
 	{ .parent = NULL }
 };
 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
 static struct clk gfx_l3_ck = {
 	.name		= "gfx_l3_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &l3_ick,
 	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP_EN_GFX_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk gfx_l3_fck = {
 	.name		= "gfx_l3_fck",
 	.ops		= &clkops_null,
 	.parent		= &gfx_l3_ck,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP_CLKSEL_GFX_MASK,
 	.clksel		= gfx_l3_clksel,
 	.clkdm_name	= "gfx_3430es1_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk gfx_l3_ick = {
 	.name		= "gfx_l3_ick",
 	.ops		= &clkops_null,
 	.parent		= &gfx_l3_ck,
 	.clkdm_name	= "gfx_3430es1_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gfx_cg1_ck = {
 	.name		= "gfx_cg1_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &gfx_l3_fck, /* REVISIT: correct? */
 	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES1_EN_2D_SHIFT,
 	.clkdm_name	= "gfx_3430es1_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gfx_cg2_ck = {
 	.name		= "gfx_cg2_ck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &gfx_l3_fck, /* REVISIT: correct? */
 	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES1_EN_3D_SHIFT,
 	.clkdm_name	= "gfx_3430es1_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* SGX power domain - 3430ES2 only */
 static const struct clksel_rate sgx_core_rates[] = {
 	{ .div = 2, .val = 5, .flags = RATE_IN_36XX },
 	{ .div = 3, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 4, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 6, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel_rate sgx_192m_rates[] = {
 	{ .div = 1,  .val = 4, .flags = RATE_IN_36XX },
 	{ .div = 0 },
 };
 static const struct clksel_rate sgx_corex2_rates[] = {
 	{ .div = 3, .val = 6, .flags = RATE_IN_36XX },
 	{ .div = 5, .val = 7, .flags = RATE_IN_36XX },
 	{ .div = 0 },
 };
 static const struct clksel_rate sgx_96m_rates[] = {
 	{ .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel sgx_clksel[] = {
 	{ .parent = &core_ck,	 .rates = sgx_core_rates },
 	{ .parent = &cm_96m_fck, .rates = sgx_96m_rates },
 	{ .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
 	{ .parent = &corex2_fck, .rates = sgx_corex2_rates },
 	{ .parent = NULL }
 };
 static struct clk sgx_fck = {
 	.name		= "sgx_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430ES2_CLKSEL_SGX_MASK,
 	.clksel		= sgx_clksel,
 	.clkdm_name	= "sgx_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 	.set_rate	= &omap2_clksel_set_rate,
 	.round_rate	= &omap2_clksel_round_rate
 };
 static struct clk sgx_ick = {
 	.name		= "sgx_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &l3_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
 	.clkdm_name	= "sgx_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* CORE power domain */
 static struct clk d2d_26m_fck = {
 	.name		= "d2d_26m_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &sys_ck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430ES1_EN_D2D_SHIFT,
 	.clkdm_name	= "d2d_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk modem_fck = {
 	.name		= "modem_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &sys_ck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MODEM_SHIFT,
 	.clkdm_name	= "d2d_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk sad2d_ick = {
 	.name		= "sad2d_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &l3_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_SAD2D_SHIFT,
 	.clkdm_name	= "d2d_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mad2d_ick = {
 	.name		= "mad2d_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &l3_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
 	.enable_bit	= OMAP3430_EN_MAD2D_SHIFT,
 	.clkdm_name	= "d2d_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static const struct clksel omap343x_gpt_clksel[] = {
 	{ .parent = &omap_32k_fck, .rates = gpt_32k_rates },
 	{ .parent = &sys_ck,	   .rates = gpt_sys_rates },
 	{ .parent = NULL}
 };
 static struct clk gpt10_fck = {
 	.name		= "gpt10_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &sys_ck,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_GPT10_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT10_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk gpt11_fck = {
 	.name		= "gpt11_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &sys_ck,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_GPT11_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT11_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk cpefuse_fck = {
 	.name		= "cpefuse_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &sys_ck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 	.enable_bit	= OMAP3430ES2_EN_CPEFUSE_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk ts_fck = {
 	.name		= "ts_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &omap_32k_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 	.enable_bit	= OMAP3430ES2_EN_TS_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk usbtll_fck = {
 	.name		= "usbtll_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &dpll5_m2_ck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 /* CORE 96M FCLK-derived clocks */
 static struct clk core_96m_fck = {
 	.name		= "core_96m_fck",
 	.ops		= &clkops_null,
 	.parent		= &omap_96m_fck,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mmchs3_fck = {
 	.name		= "mmchs3_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430ES2_EN_MMC3_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mmchs2_fck = {
 	.name		= "mmchs2_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MMC2_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mspro_fck = {
 	.name		= "mspro_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MSPRO_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mmchs1_fck = {
 	.name		= "mmchs1_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MMC1_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk i2c3_fck = {
 	.name		= "i2c3_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C3_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk i2c2_fck = {
 	.name		= "i2c2_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C2_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk i2c1_fck = {
 	.name		= "i2c1_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C1_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /*
  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
  */
 static const struct clksel_rate common_mcbsp_96m_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel mcbsp_15_clksel[] = {
 	{ .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
 	{ .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
 	{ .parent = NULL }
 };
 static struct clk mcbsp5_fck = {
 	.name		= "mcbsp5_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 	.clksel_mask	= OMAP2_MCBSP5_CLKS_MASK,
 	.clksel		= mcbsp_15_clksel,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk mcbsp1_fck = {
 	.name		= "mcbsp1_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
 	.clksel_mask	= OMAP2_MCBSP1_CLKS_MASK,
 	.clksel		= mcbsp_15_clksel,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* CORE_48M_FCK-derived clocks */
 static struct clk core_48m_fck = {
 	.name		= "core_48m_fck",
 	.ops		= &clkops_null,
 	.parent		= &omap_48m_fck,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcspi4_fck = {
 	.name		= "mcspi4_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI4_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcspi3_fck = {
 	.name		= "mcspi3_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI3_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcspi2_fck = {
 	.name		= "mcspi2_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI2_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcspi1_fck = {
 	.name		= "mcspi1_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI1_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk uart2_fck = {
 	.name		= "uart2_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_UART2_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk uart1_fck = {
 	.name		= "uart1_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_UART1_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk fshostusb_fck = {
 	.name		= "fshostusb_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 /* CORE_12M_FCK based clocks */
 static struct clk core_12m_fck = {
 	.name		= "core_12m_fck",
 	.ops		= &clkops_null,
 	.parent		= &omap_12m_fck,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk hdq_fck = {
 	.name		= "hdq_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_12m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_HDQ_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 /* DPLL3-derived clock */
 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 	{ .div = 0 }
 };
 static const struct clksel ssi_ssr_clksel[] = {
 	{ .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
 	{ .parent = NULL }
 };
 static struct clk ssi_ssr_fck_3430es1 = {
 	.name		= "ssi_ssr_fck",
 	.ops		= &clkops_omap2_dflt,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_SSI_MASK,
 	.clksel		= ssi_ssr_clksel,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk ssi_ssr_fck_3430es2 = {
 	.name		= "ssi_ssr_fck",
 	.ops		= &clkops_omap3430es2_ssi_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_SSI_MASK,
 	.clksel		= ssi_ssr_clksel,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk ssi_sst_fck_3430es1 = {
 	.name		= "ssi_sst_fck",
 	.ops		= &clkops_null,
 	.parent		= &ssi_ssr_fck_3430es1,
 	.fixed_div	= 2,
 	.recalc		= &omap_fixed_divisor_recalc,
 };
 static struct clk ssi_sst_fck_3430es2 = {
 	.name		= "ssi_sst_fck",
 	.ops		= &clkops_null,
 	.parent		= &ssi_ssr_fck_3430es2,
 	.fixed_div	= 2,
 	.recalc		= &omap_fixed_divisor_recalc,
 };
 /* CORE_L3_ICK based clocks */
 /*
  * XXX must add clk_enable/clk_disable for these if standard code won't
  * handle it
  */
 static struct clk core_l3_ick = {
 	.name		= "core_l3_ick",
 	.ops		= &clkops_null,
 	.parent		= &l3_ick,
 	.clkdm_name	= "core_l3_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk hsotgusb_ick_3430es1 = {
 	.name		= "hsotgusb_ick",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &core_l3_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_HSOTGUSB_SHIFT,
 	.clkdm_name	= "core_l3_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk hsotgusb_ick_3430es2 = {
 	.name		= "hsotgusb_ick",
 	.ops		= &clkops_omap3430es2_hsotgusb_wait,
 	.parent		= &core_l3_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_HSOTGUSB_SHIFT,
 	.clkdm_name	= "core_l3_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk sdrc_ick = {
 	.name		= "sdrc_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l3_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_SDRC_SHIFT,
 	.flags		= ENABLE_ON_INIT,
 	.clkdm_name	= "core_l3_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpmc_fck = {
 	.name		= "gpmc_fck",
 	.ops		= &clkops_null,
 	.parent		= &core_l3_ick,
 	.flags		= ENABLE_ON_INIT, /* huh? */
 	.clkdm_name	= "core_l3_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* SECURITY_L3_ICK based clocks */
 static struct clk security_l3_ick = {
 	.name		= "security_l3_ick",
 	.ops		= &clkops_null,
 	.parent		= &l3_ick,
 	.recalc		= &followparent_recalc,
 };
 static struct clk pka_ick = {
 	.name		= "pka_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &security_l3_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_PKA_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 /* CORE_L4_ICK based clocks */
 static struct clk core_l4_ick = {
 	.name		= "core_l4_ick",
 	.ops		= &clkops_null,
 	.parent		= &l4_ick,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk usbtll_ick = {
 	.name		= "usbtll_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
 	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mmchs3_ick = {
 	.name		= "mmchs3_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430ES2_EN_MMC3_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* Intersystem Communication Registers - chassis mode only */
 static struct clk icr_ick = {
 	.name		= "icr_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_ICR_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk aes2_ick = {
 	.name		= "aes2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_AES2_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk sha12_ick = {
 	.name		= "sha12_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_SHA12_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk des2_ick = {
 	.name		= "des2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_DES2_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mmchs2_ick = {
 	.name		= "mmchs2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MMC2_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mmchs1_ick = {
 	.name		= "mmchs1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MMC1_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mspro_ick = {
 	.name		= "mspro_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MSPRO_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk hdq_ick = {
 	.name		= "hdq_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_HDQ_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcspi4_ick = {
 	.name		= "mcspi4_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI4_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcspi3_ick = {
 	.name		= "mcspi3_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI3_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcspi2_ick = {
 	.name		= "mcspi2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI2_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcspi1_ick = {
 	.name		= "mcspi1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI1_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk i2c3_ick = {
 	.name		= "i2c3_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C3_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk i2c2_ick = {
 	.name		= "i2c2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C2_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk i2c1_ick = {
 	.name		= "i2c1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C1_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk uart2_ick = {
 	.name		= "uart2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_UART2_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk uart1_ick = {
 	.name		= "uart1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_UART1_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt11_ick = {
 	.name		= "gpt11_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_GPT11_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt10_ick = {
 	.name		= "gpt10_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_GPT10_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcbsp5_ick = {
 	.name		= "mcbsp5_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcbsp1_ick = {
 	.name		= "mcbsp1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk fac_ick = {
 	.name		= "fac_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430ES1_EN_FAC_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mailboxes_ick = {
 	.name		= "mailboxes_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MAILBOXES_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk omapctrl_ick = {
 	.name		= "omapctrl_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_OMAPCTRL_SHIFT,
 	.flags		= ENABLE_ON_INIT,
 	.recalc		= &followparent_recalc,
 };
 /* SSI_L4_ICK based clocks */
 static struct clk ssi_l4_ick = {
 	.name		= "ssi_l4_ick",
 	.ops		= &clkops_null,
 	.parent		= &l4_ick,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk ssi_ick_3430es1 = {
 	.name		= "ssi_ick",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &ssi_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk ssi_ick_3430es2 = {
 	.name		= "ssi_ick",
 	.ops		= &clkops_omap3430es2_ssi_wait,
 	.parent		= &ssi_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
  * but l4_ick makes more sense to me */
 static const struct clksel usb_l4_clksel[] = {
 	{ .parent = &l4_ick, .rates = div2_rates },
 	{ .parent = NULL },
 };
 static struct clk usb_l4_ick = {
 	.name		= "usb_l4_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &l4_ick,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
 	.clksel		= usb_l4_clksel,
 	.recalc		= &omap2_clksel_recalc,
 };
 /* SECURITY_L4_ICK2 based clocks */
 static struct clk security_l4_ick2 = {
 	.name		= "security_l4_ick2",
 	.ops		= &clkops_null,
 	.parent		= &l4_ick,
 	.recalc		= &followparent_recalc,
 };
 static struct clk aes1_ick = {
 	.name		= "aes1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &security_l4_ick2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_AES1_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk rng_ick = {
 	.name		= "rng_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &security_l4_ick2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_RNG_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk sha11_ick = {
 	.name		= "sha11_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &security_l4_ick2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_SHA11_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk des1_ick = {
 	.name		= "des1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &security_l4_ick2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_DES1_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 /* DSS */
 static struct clk dss1_alwon_fck_3430es1 = {
 	.name		= "dss1_alwon_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &dpll4_m4x2_ck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_DSS1_SHIFT,
 	.clkdm_name	= "dss_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk dss1_alwon_fck_3430es2 = {
 	.name		= "dss1_alwon_fck",
 	.ops		= &clkops_omap3430es2_dss_usbhost_wait,
 	.parent		= &dpll4_m4x2_ck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_DSS1_SHIFT,
 	.clkdm_name	= "dss_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk dss_tv_fck = {
 	.name		= "dss_tv_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &omap_54m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_TV_SHIFT,
 	.clkdm_name	= "dss_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk dss_96m_fck = {
 	.name		= "dss_96m_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &omap_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_TV_SHIFT,
 	.clkdm_name	= "dss_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk dss2_alwon_fck = {
 	.name		= "dss2_alwon_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &sys_ck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_DSS2_SHIFT,
 	.clkdm_name	= "dss_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk dss_ick_3430es1 = {
 	/* Handles both L3 and L4 clocks */
 	.name		= "dss_ick",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
 	.clkdm_name	= "dss_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk dss_ick_3430es2 = {
 	/* Handles both L3 and L4 clocks */
 	.name		= "dss_ick",
 	.ops		= &clkops_omap3430es2_dss_usbhost_wait,
 	.parent		= &l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
 	.clkdm_name	= "dss_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* CAM */
 static struct clk cam_mclk = {
 	.name		= "cam_mclk",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &dpll4_m5x2_ck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_CAM_SHIFT,
 	.clkdm_name	= "cam_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk cam_ick = {
 	/* Handles both L3 and L4 clocks */
 	.name		= "cam_ick",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_CAM_SHIFT,
 	.clkdm_name	= "cam_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk csi2_96m_fck = {
 	.name		= "csi2_96m_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &core_96m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_CSI2_SHIFT,
 	.clkdm_name	= "cam_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* USBHOST - 3430ES2 only */
 static struct clk usbhost_120m_fck = {
 	.name		= "usbhost_120m_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &dpll5_m2_ck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USBHOST2_SHIFT,
 	.clkdm_name	= "usbhost_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk usbhost_48m_fck = {
 	.name		= "usbhost_48m_fck",
 	.ops		= &clkops_omap3430es2_dss_usbhost_wait,
 	.parent		= &omap_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USBHOST1_SHIFT,
 	.clkdm_name	= "usbhost_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk usbhost_ick = {
 	/* Handles both L3 and L4 clocks */
 	.name		= "usbhost_ick",
 	.ops		= &clkops_omap3430es2_dss_usbhost_wait,
 	.parent		= &l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USBHOST_SHIFT,
 	.clkdm_name	= "usbhost_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* WKUP */
 static const struct clksel_rate usim_96m_rates[] = {
 	{ .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
 	{ .div = 10, .val = 6, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel_rate usim_120m_rates[] = {
 	{ .div = 4,  .val = 7,	.flags = RATE_IN_3XXX },
 	{ .div = 8,  .val = 8,	.flags = RATE_IN_3XXX },
 	{ .div = 16, .val = 9,	.flags = RATE_IN_3XXX },
 	{ .div = 20, .val = 10, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel usim_clksel[] = {
 	{ .parent = &omap_96m_fck,	.rates = usim_96m_rates },
 	{ .parent = &dpll5_m2_ck,	.rates = usim_120m_rates },
 	{ .parent = &sys_ck,		.rates = div2_rates },
 	{ .parent = NULL },
 };
 /* 3430ES2 only */
 static struct clk usim_fck = {
 	.name		= "usim_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USIMOCP_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430ES2_CLKSEL_USIMOCP_MASK,
 	.clksel		= usim_clksel,
 	.recalc		= &omap2_clksel_recalc,
 };
 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
 static struct clk gpt1_fck = {
 	.name		= "gpt1_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT1_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT1_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk wkup_32k_fck = {
 	.name		= "wkup_32k_fck",
 	.ops		= &clkops_null,
 	.parent		= &omap_32k_fck,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio1_dbck = {
 	.name		= "gpio1_dbck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &wkup_32k_fck,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk wdt2_fck = {
 	.name		= "wdt2_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &wkup_32k_fck,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_WDT2_SHIFT,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk wkup_l4_ick = {
 	.name		= "wkup_l4_ick",
 	.ops		= &clkops_null,
 	.parent		= &sys_ck,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* 3430ES2 only */
 /* Never specifically named in the TRM, so we have to infer a likely name */
 static struct clk usim_ick = {
 	.name		= "usim_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &wkup_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USIMOCP_SHIFT,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk wdt2_ick = {
 	.name		= "wdt2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &wkup_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_WDT2_SHIFT,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk wdt1_ick = {
 	.name		= "wdt1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &wkup_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_WDT1_SHIFT,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio1_ick = {
 	.name		= "gpio1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &wkup_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk omap_32ksync_ick = {
 	.name		= "omap_32ksync_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &wkup_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_32KSYNC_SHIFT,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* XXX This clock no longer exists in 3430 TRM rev F */
 static struct clk gpt12_ick = {
 	.name		= "gpt12_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &wkup_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT12_SHIFT,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt1_ick = {
 	.name		= "gpt1_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &wkup_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT1_SHIFT,
 	.clkdm_name	= "wkup_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* PER clock domain */
 static struct clk per_96m_fck = {
 	.name		= "per_96m_fck",
 	.ops		= &clkops_null,
 	.parent		= &omap_96m_alwon_fck,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk per_48m_fck = {
 	.name		= "per_48m_fck",
 	.ops		= &clkops_null,
 	.parent		= &omap_48m_fck,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk uart3_fck = {
 	.name		= "uart3_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_48m_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_UART3_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt2_fck = {
 	.name		= "gpt2_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT2_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT2_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk gpt3_fck = {
 	.name		= "gpt3_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT3_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT3_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk gpt4_fck = {
 	.name		= "gpt4_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT4_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT4_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk gpt5_fck = {
 	.name		= "gpt5_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT5_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT5_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk gpt6_fck = {
 	.name		= "gpt6_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT6_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT6_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk gpt7_fck = {
 	.name		= "gpt7_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT7_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT7_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk gpt8_fck = {
 	.name		= "gpt8_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT8_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT8_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk gpt9_fck = {
 	.name		= "gpt9_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT9_SHIFT,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_GPT9_MASK,
 	.clksel		= omap343x_gpt_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk per_32k_alwon_fck = {
 	.name		= "per_32k_alwon_fck",
 	.ops		= &clkops_null,
 	.parent		= &omap_32k_fck,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio6_dbck = {
 	.name		= "gpio6_dbck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio5_dbck = {
 	.name		= "gpio5_dbck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio4_dbck = {
 	.name		= "gpio4_dbck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio3_dbck = {
 	.name		= "gpio3_dbck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio2_dbck = {
 	.name		= "gpio2_dbck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk wdt3_fck = {
 	.name		= "wdt3_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_WDT3_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk per_l4_ick = {
 	.name		= "per_l4_ick",
 	.ops		= &clkops_null,
 	.parent		= &l4_ick,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio6_ick = {
 	.name		= "gpio6_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio5_ick = {
 	.name		= "gpio5_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio4_ick = {
 	.name		= "gpio4_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio3_ick = {
 	.name		= "gpio3_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpio2_ick = {
 	.name		= "gpio2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk wdt3_ick = {
 	.name		= "wdt3_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_WDT3_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk uart3_ick = {
 	.name		= "uart3_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_UART3_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt9_ick = {
 	.name		= "gpt9_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT9_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt8_ick = {
 	.name		= "gpt8_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT8_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt7_ick = {
 	.name		= "gpt7_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT7_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt6_ick = {
 	.name		= "gpt6_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT6_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt5_ick = {
 	.name		= "gpt5_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT5_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt4_ick = {
 	.name		= "gpt4_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT4_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt3_ick = {
 	.name		= "gpt3_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT3_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk gpt2_ick = {
 	.name		= "gpt2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT2_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcbsp2_ick = {
 	.name		= "mcbsp2_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcbsp3_ick = {
 	.name		= "mcbsp3_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static struct clk mcbsp4_ick = {
 	.name		= "mcbsp4_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &per_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &followparent_recalc,
 };
 static const struct clksel mcbsp_234_clksel[] = {
 	{ .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
 	{ .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
 	{ .parent = NULL }
 };
 static struct clk mcbsp2_fck = {
 	.name		= "mcbsp2_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
 	.clksel_mask	= OMAP2_MCBSP2_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk mcbsp3_fck = {
 	.name		= "mcbsp3_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 	.clksel_mask	= OMAP2_MCBSP3_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk mcbsp4_fck = {
 	.name		= "mcbsp4_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 	.clksel_mask	= OMAP2_MCBSP4_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.clkdm_name	= "per_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* EMU clocks */
 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
 static const struct clksel_rate emu_src_sys_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel_rate emu_src_core_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel_rate emu_src_per_rates[] = {
 	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel_rate emu_src_mpu_rates[] = {
 	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel emu_src_clksel[] = {
 	{ .parent = &sys_ck,		.rates = emu_src_sys_rates },
 	{ .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
 	{ .parent = &emu_per_alwon_ck,	.rates = emu_src_per_rates },
 	{ .parent = &emu_mpu_alwon_ck,	.rates = emu_src_mpu_rates },
 	{ .parent = NULL },
 };
 /*
  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
  * to switch the source of some of the EMU clocks.
  * XXX Are there CLKEN bits for these EMU clks?
  */
 static struct clk emu_src_ck = {
 	.name		= "emu_src_ck",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_MUX_CTRL_MASK,
 	.clksel		= emu_src_clksel,
 	.clkdm_name	= "emu_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static const struct clksel_rate pclk_emu_rates[] = {
 	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel pclk_emu_clksel[] = {
 	{ .parent = &emu_src_ck, .rates = pclk_emu_rates },
 	{ .parent = NULL },
 };
 static struct clk pclk_fck = {
 	.name		= "pclk_fck",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CLKSEL_PCLK_MASK,
 	.clksel		= pclk_emu_clksel,
 	.clkdm_name	= "emu_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static const struct clksel_rate pclkx2_emu_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel pclkx2_emu_clksel[] = {
 	{ .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
 	{ .parent = NULL },
 };
 static struct clk pclkx2_fck = {
 	.name		= "pclkx2_fck",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CLKSEL_PCLKX2_MASK,
 	.clksel		= pclkx2_emu_clksel,
 	.clkdm_name	= "emu_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static const struct clksel atclk_emu_clksel[] = {
 	{ .parent = &emu_src_ck, .rates = div2_rates },
 	{ .parent = NULL },
 };
 static struct clk atclk_fck = {
 	.name		= "atclk_fck",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CLKSEL_ATCLK_MASK,
 	.clksel		= atclk_emu_clksel,
 	.clkdm_name	= "emu_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static struct clk traceclk_src_fck = {
 	.name		= "traceclk_src_fck",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_TRACE_MUX_CTRL_MASK,
 	.clksel		= emu_src_clksel,
 	.clkdm_name	= "emu_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 static const struct clksel_rate traceclk_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 	{ .div = 0 },
 };
 static const struct clksel traceclk_clksel[] = {
 	{ .parent = &traceclk_src_fck, .rates = traceclk_rates },
 	{ .parent = NULL },
 };
 static struct clk traceclk_fck = {
 	.name		= "traceclk_fck",
 	.ops		= &clkops_null,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CLKSEL_TRACECLK_MASK,
 	.clksel		= traceclk_clksel,
 	.clkdm_name	= "emu_clkdm",
 	.recalc		= &omap2_clksel_recalc,
 };
 /* SR clocks */
 /* SmartReflex fclk (VDD1) */
 static struct clk sr1_fck = {
 	.name		= "sr1_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &sys_ck,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_SR1_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 /* SmartReflex fclk (VDD2) */
 static struct clk sr2_fck = {
 	.name		= "sr2_fck",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &sys_ck,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_SR2_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk sr_l4_ick = {
 	.name		= "sr_l4_ick",
 	.ops		= &clkops_null, /* RMK: missing? */
 	.parent		= &l4_ick,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
 /* SECURE_32K_FCK clocks */
 static struct clk gpt12_fck = {
 	.name		= "gpt12_fck",
 	.ops		= &clkops_null,
 	.parent		= &secure_32k_fck,
 	.recalc		= &followparent_recalc,
 };
 static struct clk wdt1_fck = {
 	.name		= "wdt1_fck",
 	.ops		= &clkops_null,
 	.parent		= &secure_32k_fck,
 	.recalc		= &followparent_recalc,
 };
 /* Clocks for AM35XX */
 static struct clk ipss_ick = {
 	.name		= "ipss_ick",
 	.ops		= &clkops_am35xx_ipss_wait,
 	.parent		= &core_l3_ick,
 	.clkdm_name	= "core_l3_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= AM35XX_EN_IPSS_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk emac_ick = {
 	.name		= "emac_ick",
 	.ops		= &clkops_am35xx_ipss_module_wait,
 	.parent		= &ipss_ick,
 	.clkdm_name	= "core_l3_clkdm",
 	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
 	.enable_bit	= AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk rmii_ck = {
 	.name		= "rmii_ck",
 	.ops		= &clkops_null,
 	.rate		= 50000000,
 };
 static struct clk emac_fck = {
 	.name		= "emac_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &rmii_ck,
 	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
 	.enable_bit	= AM35XX_CPGMAC_FCLK_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk hsotgusb_ick_am35xx = {
 	.name		= "hsotgusb_ick",
 	.ops		= &clkops_am35xx_ipss_module_wait,
 	.parent		= &ipss_ick,
 	.clkdm_name	= "core_l3_clkdm",
 	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
 	.enable_bit	= AM35XX_USBOTG_VBUSP_CLK_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk hsotgusb_fck_am35xx = {
 	.name		= "hsotgusb_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &sys_ck,
 	.clkdm_name	= "core_l3_clkdm",
 	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
 	.enable_bit	= AM35XX_USBOTG_FCLK_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk hecc_ck = {
 	.name		= "hecc_ck",
 	.ops		= &clkops_am35xx_ipss_module_wait,
 	.parent		= &sys_ck,
 	.clkdm_name	= "core_l3_clkdm",
 	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
 	.enable_bit	= AM35XX_HECC_VBUSP_CLK_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk vpfe_ick = {
 	.name		= "vpfe_ick",
 	.ops		= &clkops_am35xx_ipss_module_wait,
 	.parent		= &ipss_ick,
 	.clkdm_name	= "core_l3_clkdm",
 	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
 	.enable_bit	= AM35XX_VPFE_VBUSP_CLK_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 static struct clk pclk_ck = {
 	.name		= "pclk_ck",
 	.ops		= &clkops_null,
 	.rate		= 27000000,
 };
 static struct clk vpfe_fck = {
 	.name		= "vpfe_fck",
 	.ops		= &clkops_omap2_dflt,
 	.parent		= &pclk_ck,
 	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
 	.enable_bit	= AM35XX_VPFE_FCLK_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 /*
  * The UART1/2 functional clock acts as the functional
  * clock for UART4. No separate fclk control available.
  */
 static struct clk uart4_ick_am35xx = {
 	.name		= "uart4_ick",
 	.ops		= &clkops_omap2_dflt_wait,
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= AM35XX_EN_UART4_SHIFT,
 	.clkdm_name	= "core_l4_clkdm",
 	.recalc		= &followparent_recalc,
 };
+static struct clk dummy_apb_pclk = {
+	.name		= "apb_pclk",
+	.ops		= &clkops_null,
+};
 /*
  * clkdev
  */
 /* XXX At some point we should rename this file to clock3xxx_data.c */
 static struct omap_clk omap3xxx_clks[] = {
+	CLK(NULL,	"apb_pclk",	&dummy_apb_pclk,	CK_3XXX),
 	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_3XXX),
 	CLK(NULL,	"virt_12m_ck",	&virt_12m_ck,	CK_3XXX),
 	CLK(NULL,	"virt_13m_ck",	&virt_13m_ck,	CK_3XXX),
 	CLK(NULL,	"virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
 	CLK(NULL,	"virt_26m_ck",	&virt_26m_ck,	CK_3XXX),
 	CLK(NULL,	"virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
 	CLK(NULL,	"osc_sys_ck",	&osc_sys_ck,	CK_3XXX),
 	CLK(NULL,	"sys_ck",	&sys_ck,	CK_3XXX),
 	CLK(NULL,	"sys_altclk",	&sys_altclk,	CK_3XXX),
 	CLK(NULL,	"mcbsp_clks",	&mcbsp_clks,	CK_3XXX),
 	CLK(NULL,	"sys_clkout1",	&sys_clkout1,	CK_3XXX),
 	CLK(NULL,	"dpll1_ck",	&dpll1_ck,	CK_3XXX),
 	CLK(NULL,	"dpll1_x2_ck",	&dpll1_x2_ck,	CK_3XXX),
 	CLK(NULL,	"dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
 	CLK(NULL,	"dpll2_ck",	&dpll2_ck,	CK_343X),
 	CLK(NULL,	"dpll2_m2_ck",	&dpll2_m2_ck,	CK_343X),
 	CLK(NULL,	"dpll3_ck",	&dpll3_ck,	CK_3XXX),
 	CLK(NULL,	"core_ck",	&core_ck,	CK_3XXX),
 	CLK(NULL,	"dpll3_x2_ck",	&dpll3_x2_ck,	CK_3XXX),
 	CLK(NULL,	"dpll3_m2_ck",	&dpll3_m2_ck,	CK_3XXX),
 	CLK(NULL,	"dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
 	CLK(NULL,	"dpll3_m3_ck",	&dpll3_m3_ck,	CK_3XXX),
 	CLK(NULL,	"dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
 	CLK("etb",	"emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
 	CLK(NULL,	"dpll4_ck",	&dpll4_ck,	CK_3XXX),
 	CLK(NULL,	"dpll4_x2_ck",	&dpll4_x2_ck,	CK_3XXX),
 	CLK(NULL,	"omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
 	CLK(NULL,	"omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
 	CLK(NULL,	"omap_96m_fck",	&omap_96m_fck,	CK_3XXX),
 	CLK(NULL,	"cm_96m_fck",	&cm_96m_fck,	CK_3XXX),
 	CLK(NULL,	"omap_54m_fck",	&omap_54m_fck,	CK_3XXX),
 	CLK(NULL,	"omap_48m_fck",	&omap_48m_fck,	CK_3XXX),
 	CLK(NULL,	"omap_12m_fck",	&omap_12m_fck,	CK_3XXX),
 	CLK(NULL,	"dpll4_m2_ck",	&dpll4_m2_ck,	CK_3XXX),
 	CLK(NULL,	"dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
 	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX),
 	CLK(NULL,	"dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
 	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX),
 	CLK(NULL,	"dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
 	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX),
 	CLK(NULL,	"dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
 	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX),
 	CLK(NULL,	"dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
 	CLK("etb",	"emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
 	CLK(NULL,	"dpll5_ck",	&dpll5_ck,	CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"dpll5_m2_ck",	&dpll5_m2_ck,	CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
 	CLK(NULL,	"sys_clkout2",	&sys_clkout2,	CK_3XXX),
 	CLK(NULL,	"corex2_fck",	&corex2_fck,	CK_3XXX),
 	CLK(NULL,	"dpll1_fck",	&dpll1_fck,	CK_3XXX),
 	CLK(NULL,	"mpu_ck",	&mpu_ck,	CK_3XXX),
 	CLK(NULL,	"arm_fck",	&arm_fck,	CK_3XXX),
 	CLK("etb",	"emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
 	CLK(NULL,	"dpll2_fck",	&dpll2_fck,	CK_343X),
 	CLK(NULL,	"iva2_ck",	&iva2_ck,	CK_343X),
 	CLK(NULL,	"l3_ick",	&l3_ick,	CK_3XXX),
 	CLK(NULL,	"l4_ick",	&l4_ick,	CK_3XXX),
 	CLK(NULL,	"rm_ick",	&rm_ick,	CK_3XXX),
 	CLK(NULL,	"gfx_l3_ck",	&gfx_l3_ck,	CK_3430ES1),
 	CLK(NULL,	"gfx_l3_fck",	&gfx_l3_fck,	CK_3430ES1),
 	CLK(NULL,	"gfx_l3_ick",	&gfx_l3_ick,	CK_3430ES1),
 	CLK(NULL,	"gfx_cg1_ck",	&gfx_cg1_ck,	CK_3430ES1),
 	CLK(NULL,	"gfx_cg2_ck",	&gfx_cg2_ck,	CK_3430ES1),
 	CLK(NULL,	"sgx_fck",	&sgx_fck,	CK_3430ES2 | CK_3517),
 	CLK(NULL,	"sgx_ick",	&sgx_ick,	CK_3430ES2 | CK_3517),
 	CLK(NULL,	"d2d_26m_fck",	&d2d_26m_fck,	CK_3430ES1),
 	CLK(NULL,	"modem_fck",	&modem_fck,	CK_343X),
 	CLK(NULL,	"sad2d_ick",	&sad2d_ick,	CK_343X),
 	CLK(NULL,	"mad2d_ick",	&mad2d_ick,	CK_343X),
 	CLK(NULL,	"gpt10_fck",	&gpt10_fck,	CK_3XXX),
 	CLK(NULL,	"gpt11_fck",	&gpt11_fck,	CK_3XXX),
 	CLK(NULL,	"cpefuse_fck",	&cpefuse_fck,	CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"ts_fck",	&ts_fck,	CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"usbtll_fck",	&usbtll_fck,	CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"core_96m_fck",	&core_96m_fck,	CK_3XXX),
 	CLK("mmci-omap-hs.2",	"fck",	&mmchs3_fck,	CK_3430ES2 | CK_AM35XX),
 	CLK("mmci-omap-hs.1",	"fck",	&mmchs2_fck,	CK_3XXX),
 	CLK(NULL,	"mspro_fck",	&mspro_fck,	CK_343X),
 	CLK("mmci-omap-hs.0",	"fck",	&mmchs1_fck,	CK_3XXX),
 	CLK("i2c_omap.3", "fck",	&i2c3_fck,	CK_3XXX),
 	CLK("i2c_omap.2", "fck",	&i2c2_fck,	CK_3XXX),
 	CLK("i2c_omap.1", "fck",	&i2c1_fck,	CK_3XXX),
 	CLK("omap-mcbsp.5", "fck",	&mcbsp5_fck,	CK_3XXX),
 	CLK("omap-mcbsp.1", "fck",	&mcbsp1_fck,	CK_3XXX),
 	CLK(NULL,	"core_48m_fck",	&core_48m_fck,	CK_3XXX),
 	CLK("omap2_mcspi.4", "fck",	&mcspi4_fck,	CK_3XXX),
 	CLK("omap2_mcspi.3", "fck",	&mcspi3_fck,	CK_3XXX),
 	CLK("omap2_mcspi.2", "fck",	&mcspi2_fck,	CK_3XXX),
 	CLK("omap2_mcspi.1", "fck",	&mcspi1_fck,	CK_3XXX),
 	CLK(NULL,	"uart2_fck",	&uart2_fck,	CK_3XXX),
 	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_3XXX),
 	CLK(NULL,	"fshostusb_fck", &fshostusb_fck, CK_3430ES1),
 	CLK(NULL,	"core_12m_fck",	&core_12m_fck,	CK_3XXX),
 	CLK("omap_hdq.0", "fck",	&hdq_fck,	CK_3XXX),
 	CLK(NULL,	"ssi_ssr_fck",	&ssi_ssr_fck_3430es1,	CK_3430ES1),
 	CLK(NULL,	"ssi_ssr_fck",	&ssi_ssr_fck_3430es2,	CK_3430ES2),
 	CLK(NULL,	"ssi_sst_fck",	&ssi_sst_fck_3430es1,	CK_3430ES1),
 	CLK(NULL,	"ssi_sst_fck",	&ssi_sst_fck_3430es2,	CK_3430ES2),
 	CLK(NULL,	"core_l3_ick",	&core_l3_ick,	CK_3XXX),
 	CLK("musb_hdrc",	"ick",	&hsotgusb_ick_3430es1,	CK_3430ES1),
 	CLK("musb_hdrc",	"ick",	&hsotgusb_ick_3430es2,	CK_3430ES2),
 	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_3XXX),
 	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_3XXX),
 	CLK(NULL,	"security_l3_ick", &security_l3_ick, CK_343X),
 	CLK(NULL,	"pka_ick",	&pka_ick,	CK_343X),
 	CLK(NULL,	"core_l4_ick",	&core_l4_ick,	CK_3XXX),
 	CLK(NULL,	"usbtll_ick",	&usbtll_ick,	CK_3430ES2 | CK_AM35XX),
 	CLK("mmci-omap-hs.2",	"ick",	&mmchs3_ick,	CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"icr_ick",	&icr_ick,	CK_343X),
 	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_343X),
 	CLK("omap-sham",	"ick",	&sha12_ick,	CK_343X),
 	CLK(NULL,	"des2_ick",	&des2_ick,	CK_343X),
 	CLK("mmci-omap-hs.1",	"ick",	&mmchs2_ick,	CK_3XXX),
 	CLK("mmci-omap-hs.0",	"ick",	&mmchs1_ick,	CK_3XXX),
 	CLK(NULL,	"mspro_ick",	&mspro_ick,	CK_343X),
 	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_3XXX),
 	CLK("omap2_mcspi.4", "ick",	&mcspi4_ick,	CK_3XXX),
 	CLK("omap2_mcspi.3", "ick",	&mcspi3_ick,	CK_3XXX),
 	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_3XXX),
 	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_3XXX),
 	CLK("i2c_omap.3", "ick",	&i2c3_ick,	CK_3XXX),
 	CLK("i2c_omap.2", "ick",	&i2c2_ick,	CK_3XXX),
 	CLK("i2c_omap.1", "ick",	&i2c1_ick,	CK_3XXX),
 	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_3XXX),
 	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_3XXX),
 	CLK(NULL,	"gpt11_ick",	&gpt11_ick,	CK_3XXX),
 	CLK(NULL,	"gpt10_ick",	&gpt10_ick,	CK_3XXX),
 	CLK("omap-mcbsp.5", "ick",	&mcbsp5_ick,	CK_3XXX),
 	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_3XXX),
 	CLK(NULL,	"fac_ick",	&fac_ick,	CK_3430ES1),
 	CLK(NULL,	"mailboxes_ick", &mailboxes_ick, CK_343X),
 	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_3XXX),
 	CLK(NULL,	"ssi_l4_ick",	&ssi_l4_ick,	CK_343X),
 	CLK(NULL,	"ssi_ick",	&ssi_ick_3430es1,	CK_3430ES1),
 	CLK(NULL,	"ssi_ick",	&ssi_ick_3430es2,	CK_3430ES2),
 	CLK(NULL,	"usb_l4_ick",	&usb_l4_ick,	CK_3430ES1),
 	CLK(NULL,	"security_l4_ick2", &security_l4_ick2, CK_343X),
 	CLK(NULL,	"aes1_ick",	&aes1_ick,	CK_343X),
 	CLK("omap_rng",	"ick",		&rng_ick,	CK_343X),
 	CLK(NULL,	"sha11_ick",	&sha11_ick,	CK_343X),
 	CLK(NULL,	"des1_ick",	&des1_ick,	CK_343X),
 	CLK("omapdss",	"dss1_fck",	&dss1_alwon_fck_3430es1, CK_3430ES1),
 	CLK("omapdss",	"dss1_fck",	&dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
 	CLK("omapdss",	"tv_fck",	&dss_tv_fck,	CK_3XXX),
 	CLK("omapdss",	"video_fck",	&dss_96m_fck,	CK_3XXX),
 	CLK("omapdss",	"dss2_fck",	&dss2_alwon_fck, CK_3XXX),
 	CLK("omapdss",	"ick",		&dss_ick_3430es1,	CK_3430ES1),
 	CLK("omapdss",	"ick",		&dss_ick_3430es2,	CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"cam_mclk",	&cam_mclk,	CK_343X),
 	CLK(NULL,	"cam_ick",	&cam_ick,	CK_343X),
 	CLK(NULL,	"csi2_96m_fck",	&csi2_96m_fck,	CK_343X),
 	CLK(NULL,	"usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"usbhost_ick",	&usbhost_ick,	CK_3430ES2 | CK_AM35XX),
 	CLK(NULL,	"usim_fck",	&usim_fck,	CK_3430ES2),
 	CLK(NULL,	"gpt1_fck",	&gpt1_fck,	CK_3XXX),
 	CLK(NULL,	"wkup_32k_fck",	&wkup_32k_fck,	CK_3XXX),
 	CLK(NULL,	"gpio1_dbck",	&gpio1_dbck,	CK_3XXX),
 	CLK("omap_wdt",	"fck",		&wdt2_fck,	CK_3XXX),
 	CLK(NULL,	"wkup_l4_ick",	&wkup_l4_ick,	CK_343X),
 	CLK(NULL,	"usim_ick",	&usim_ick,	CK_3430ES2),
 	CLK("omap_wdt",	"ick",		&wdt2_ick,	CK_3XXX),
 	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_3XXX),
 	CLK(NULL,	"gpio1_ick",	&gpio1_ick,	CK_3XXX),
 	CLK(NULL,	"omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
 	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_3XXX),
 	CLK(NULL,	"gpt1_ick",	&gpt1_ick,	CK_3XXX),
 	CLK(NULL,	"per_96m_fck",	&per_96m_fck,	CK_3XXX),
 	CLK(NULL,	"per_48m_fck",	&per_48m_fck,	CK_3XXX),
 	CLK(NULL,	"uart3_fck",	&uart3_fck,	CK_3XXX),
 	CLK(NULL,	"gpt2_fck",	&gpt2_fck,	CK_3XXX),
 	CLK(NULL,	"gpt3_fck",	&gpt3_fck,	CK_3XXX),
 	CLK(NULL,	"gpt4_fck",	&gpt4_fck,	CK_3XXX),
 	CLK(NULL,	"gpt5_fck",	&gpt5_fck,	CK_3XXX),
 	CLK(NULL,	"gpt6_fck",	&gpt6_fck,	CK_3XXX),
 	CLK(NULL,	"gpt7_fck",	&gpt7_fck,	CK_3XXX),
 	CLK(NULL,	"gpt8_fck",	&gpt8_fck,	CK_3XXX),
 	CLK(NULL,	"gpt9_fck",	&gpt9_fck,	CK_3XXX),
 	CLK(NULL,	"per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
 	CLK(NULL,	"gpio6_dbck",	&gpio6_dbck,	CK_3XXX),
 	CLK(NULL,	"gpio5_dbck",	&gpio5_dbck,	CK_3XXX),
 	CLK(NULL,	"gpio4_dbck",	&gpio4_dbck,	CK_3XXX),
 	CLK(NULL,	"gpio3_dbck",	&gpio3_dbck,	CK_3XXX),
 	CLK(NULL,	"gpio2_dbck",	&gpio2_dbck,	CK_3XXX),
 	CLK(NULL,	"wdt3_fck",	&wdt3_fck,	CK_3XXX),
 	CLK(NULL,	"per_l4_ick",	&per_l4_ick,	CK_3XXX),
 	CLK(NULL,	"gpio6_ick",	&gpio6_ick,	CK_3XXX),
 	CLK(NULL,	"gpio5_ick",	&gpio5_ick,	CK_3XXX),
 	CLK(NULL,	"gpio4_ick",	&gpio4_ick,	CK_3XXX),
 	CLK(NULL,	"gpio3_ick",	&gpio3_ick,	CK_3XXX),
 	CLK(NULL,	"gpio2_ick",	&gpio2_ick,	CK_3XXX),
 	CLK(NULL,	"wdt3_ick",	&wdt3_ick,	CK_3XXX),
 	CLK(NULL,	"uart3_ick",	&uart3_ick,	CK_3XXX),
 	CLK(NULL,	"gpt9_ick",	&gpt9_ick,	CK_3XXX),
 	CLK(NULL,	"gpt8_ick",	&gpt8_ick,	CK_3XXX),
 	CLK(NULL,	"gpt7_ick",	&gpt7_ick,	CK_3XXX),
 	CLK(NULL,	"gpt6_ick",	&gpt6_ick,	CK_3XXX),
 	CLK(NULL,	"gpt5_ick",	&gpt5_ick,	CK_3XXX),
 	CLK(NULL,	"gpt4_ick",	&gpt4_ick,	CK_3XXX),
 	CLK(NULL,	"gpt3_ick",	&gpt3_ick,	CK_3XXX),
 	CLK(NULL,	"gpt2_ick",	&gpt2_ick,	CK_3XXX),
 	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_3XXX),
 	CLK("omap-mcbsp.3", "ick",	&mcbsp3_ick,	CK_3XXX),
 	CLK("omap-mcbsp.4", "ick",	&mcbsp4_ick,	CK_3XXX),
 	CLK("omap-mcbsp.2", "fck",	&mcbsp2_fck,	CK_3XXX),
 	CLK("omap-mcbsp.3", "fck",	&mcbsp3_fck,	CK_3XXX),
 	CLK("omap-mcbsp.4", "fck",	&mcbsp4_fck,	CK_3XXX),
 	CLK("etb",	"emu_src_ck",	&emu_src_ck,	CK_3XXX),
 	CLK(NULL,	"pclk_fck",	&pclk_fck,	CK_3XXX),
 	CLK(NULL,	"pclkx2_fck",	&pclkx2_fck,	CK_3XXX),
 	CLK(NULL,	"atclk_fck",	&atclk_fck,	CK_3XXX),
 	CLK(NULL,	"traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
 	CLK(NULL,	"traceclk_fck",	&traceclk_fck,	CK_3XXX),
 	CLK(NULL,	"sr1_fck",	&sr1_fck,	CK_343X),
 	CLK(NULL,	"sr2_fck",	&sr2_fck,	CK_343X),
 	CLK(NULL,	"sr_l4_ick",	&sr_l4_ick,	CK_343X),
 	CLK(NULL,	"secure_32k_fck", &secure_32k_fck, CK_3XXX),
 	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_3XXX),
 	CLK(NULL,	"wdt1_fck",	&wdt1_fck,	CK_3XXX),
 	CLK(NULL,	"ipss_ick",	&ipss_ick,	CK_AM35XX),
 	CLK(NULL,	"rmii_ck",	&rmii_ck,	CK_AM35XX),
 	CLK(NULL,	"pclk_ck",	&pclk_ck,	CK_AM35XX),
 	CLK("davinci_emac",	"emac_clk",	&emac_ick,	CK_AM35XX),
 	CLK("davinci_emac",	"phy_clk",	&emac_fck,	CK_AM35XX),
 	CLK("vpfe-capture",	"master",	&vpfe_ick,	CK_AM35XX),
 	CLK("vpfe-capture",	"slave",	&vpfe_fck,	CK_AM35XX),
 	CLK("musb_hdrc",	"ick",		&hsotgusb_ick_am35xx,	CK_AM35XX),
 	CLK("musb_hdrc",	"fck",		&hsotgusb_fck_am35xx,	CK_AM35XX),
 	CLK(NULL,	"hecc_ck",	&hecc_ck,	CK_AM35XX),
 	CLK(NULL,	"uart4_ick",	&uart4_ick_am35xx,	CK_AM35XX),
 };
 int __init omap3xxx_clk_init(void)
 {
 	struct omap_clk *c;
 	u32 cpu_clkflg = CK_3XXX;
 	if (cpu_is_omap34xx()) {
 		cpu_mask = RATE_IN_3XXX;
 		cpu_clkflg |= CK_343X;
 		/*
 		 * Update this if there are further clock changes between ES2
 		 * and production parts
 		 */
 		if (omap_rev() == OMAP3430_REV_ES1_0) {
 			/* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
 			cpu_clkflg |= CK_3430ES1;
 		} else {
 			cpu_mask |= RATE_IN_3430ES2PLUS;
 			cpu_clkflg |= CK_3430ES2;
 		}
 	} else if (cpu_is_omap3517()) {
 		cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
 		cpu_clkflg |= CK_3517;
 	} else if (cpu_is_omap3505()) {
 		cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
 		cpu_clkflg |= CK_3505;
 	}
 	if (omap3_has_192mhz_clk())
 		omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
 	if (cpu_is_omap3630()) {
 		cpu_mask |= RATE_IN_36XX;
 		cpu_clkflg |= CK_36XX;
 		/*
 		 * XXX This type of dynamic rewriting of the clock tree is
 		 * deprecated and should be revised soon.
 		 *
 		 * For 3630: override clkops_omap2_dflt_wait for the
 		 * clocks affected from PWRDN reset Limitation
 		 */
 		dpll3_m3x2_ck.ops =
 				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
 		dpll4_m2x2_ck.ops =
 				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
 		dpll4_m3x2_ck.ops =
 				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
 		dpll4_m4x2_ck.ops =
 				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
 		dpll4_m5x2_ck.ops =
 				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
 		dpll4_m6x2_ck.ops =
 				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
 	}
 	/*
 	 * XXX This type of dynamic rewriting of the clock tree is
 	 * deprecated and should be revised soon.
 	 */
 	if (cpu_is_omap3630())
 		dpll4_dd = dpll4_dd_3630;
 	else
 		dpll4_dd = dpll4_dd_34xx;
 	clk_init(&omap2_clk_functions);
 	for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
 	     c++)
 		clk_preinit(c->lk.clk);
 	for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
 	     c++)
 		if (c->cpu & cpu_clkflg) {
 			clkdev_add(&c->lk);
 			clk_register(c->lk.clk);
 			omap2_init_clk_clkdm(c->lk.clk);
 		}
 	recalculate_root_clocks();
 	printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
 	       "%ld.%01ld/%ld/%ld MHz\n",
 	       (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
 	       (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
 	/*
 	 * Only enable those clocks we will need, let the drivers
 	 * enable other clocks as necessary
 	 */
 	clk_enable_init_clocks();
 	/*
 	 * Lock DPLL5 and put it in autoidle.
 	 */
 	if (omap_rev() >= OMAP3430_REV_ES2_0)
 		omap3_clk_lock_dpll5();
 	/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
 	sdrc_ick_p = clk_get(NULL, "sdrc_ick");
 	arm_fck_p = clk_get(NULL, "arm_fck");
 	return 0;
 }

arch/arm/mach-realview/core.c

Diff comments View file @ 3126c7b

 /*
  *  linux/arch/arm/mach-realview/core.c
  *
  *  Copyright (C) 1999 - 2003 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/sysdev.h>
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/ata_platform.h>
 #include <linux/amba/mmci.h>
 #include <linux/gfp.h>
 #include <asm/clkdev.h>
 #include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/gic.h>
 #include <mach/clkdev.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
 #include <plat/timer-sp.h>
 #include "core.h"
 /* used by entry-macro.S and platsmp.c */
 void __iomem *gic_cpu_base_addr;
 #ifdef CONFIG_ZONE_DMA
 /*
  * Adjust the zones if there are restrictions for DMA access.
  */
 void __init realview_adjust_zones(int node, unsigned long *size,
 				  unsigned long *hole)
 {
 	unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
 	if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
 		return;
 	size[ZONE_NORMAL] = size[0] - dma_size;
 	size[ZONE_DMA] = dma_size;
 	hole[ZONE_NORMAL] = hole[0];
 	hole[ZONE_DMA] = 0;
 }
 #endif
 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
 static int realview_flash_init(void)
 {
 	u32 val;
 	val = __raw_readl(REALVIEW_FLASHCTRL);
 	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 	__raw_writel(val, REALVIEW_FLASHCTRL);
 	return 0;
 }
 static void realview_flash_exit(void)
 {
 	u32 val;
 	val = __raw_readl(REALVIEW_FLASHCTRL);
 	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 	__raw_writel(val, REALVIEW_FLASHCTRL);
 }
 static void realview_flash_set_vpp(int on)
 {
 	u32 val;
 	val = __raw_readl(REALVIEW_FLASHCTRL);
 	if (on)
 		val |= REALVIEW_FLASHPROG_FLVPPEN;
 	else
 		val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 	__raw_writel(val, REALVIEW_FLASHCTRL);
 }
 static struct flash_platform_data realview_flash_data = {
 	.map_name		= "cfi_probe",
 	.width			= 4,
 	.init			= realview_flash_init,
 	.exit			= realview_flash_exit,
 	.set_vpp		= realview_flash_set_vpp,
 };
 struct platform_device realview_flash_device = {
 	.name			= "armflash",
 	.id			= 0,
 	.dev			= {
 		.platform_data	= &realview_flash_data,
 	},
 };
 int realview_flash_register(struct resource *res, u32 num)
 {
 	realview_flash_device.resource = res;
 	realview_flash_device.num_resources = num;
 	return platform_device_register(&realview_flash_device);
 }
 static struct smsc911x_platform_config smsc911x_config = {
 	.flags		= SMSC911X_USE_32BIT,
 	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
 	.phy_interface	= PHY_INTERFACE_MODE_MII,
 };
 static struct platform_device realview_eth_device = {
 	.name		= "smsc911x",
 	.id		= 0,
 	.num_resources	= 2,
 };
 int realview_eth_register(const char *name, struct resource *res)
 {
 	if (name)
 		realview_eth_device.name = name;
 	realview_eth_device.resource = res;
 	if (strcmp(realview_eth_device.name, "smsc911x") == 0)
 		realview_eth_device.dev.platform_data = &smsc911x_config;
 	return platform_device_register(&realview_eth_device);
 }
 struct platform_device realview_usb_device = {
 	.name			= "isp1760",
 	.num_resources		= 2,
 };
 int realview_usb_register(struct resource *res)
 {
 	realview_usb_device.resource = res;
 	return platform_device_register(&realview_usb_device);
 }
 static struct pata_platform_info pata_platform_data = {
 	.ioport_shift		= 1,
 };
 static struct resource pata_resources[] = {
 	[0] = {
 		.start		= REALVIEW_CF_BASE,
 		.end		= REALVIEW_CF_BASE + 0xff,
 		.flags		= IORESOURCE_MEM,
 	},
 	[1] = {
 		.start		= REALVIEW_CF_BASE + 0x100,
 		.end		= REALVIEW_CF_BASE + SZ_4K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 };
 struct platform_device realview_cf_device = {
 	.name			= "pata_platform",
 	.id			= -1,
 	.num_resources		= ARRAY_SIZE(pata_resources),
 	.resource		= pata_resources,
 	.dev			= {
 		.platform_data	= &pata_platform_data,
 	},
 };
 static struct resource realview_i2c_resource = {
 	.start		= REALVIEW_I2C_BASE,
 	.end		= REALVIEW_I2C_BASE + SZ_4K - 1,
 	.flags		= IORESOURCE_MEM,
 };
 struct platform_device realview_i2c_device = {
 	.name		= "versatile-i2c",
 	.id		= 0,
 	.num_resources	= 1,
 	.resource	= &realview_i2c_resource,
 };
 static struct i2c_board_info realview_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 	},
 };
 static int __init realview_i2c_init(void)
 {
 	return i2c_register_board_info(0, realview_i2c_board_info,
 				       ARRAY_SIZE(realview_i2c_board_info));
 }
 arch_initcall(realview_i2c_init);
 #define REALVIEW_SYSMCI	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 /*
  * This is only used if GPIOLIB support is disabled
  */
 static unsigned int realview_mmc_status(struct device *dev)
 {
 	struct amba_device *adev = container_of(dev, struct amba_device, dev);
 	u32 mask;
 	if (adev->res.start == REALVIEW_MMCI0_BASE)
 		mask = 1;
 	else
 		mask = 2;
 	return !(readl(REALVIEW_SYSMCI) & mask);
 }
 struct mmci_platform_data realview_mmc0_plat_data = {
 	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
 	.status		= realview_mmc_status,
 	.gpio_wp	= 17,
 	.gpio_cd	= 16,
 };
 struct mmci_platform_data realview_mmc1_plat_data = {
 	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
 	.status		= realview_mmc_status,
 	.gpio_wp	= 19,
 	.gpio_cd	= 18,
 };
 /*
  * Clock handling
  */
 static const struct icst_params realview_oscvco_params = {
 	.ref		= 24000000,
 	.vco_max	= ICST307_VCO_MAX,
 	.vco_min	= ICST307_VCO_MIN,
 	.vd_min		= 4 + 8,
 	.vd_max		= 511 + 8,
 	.rd_min		= 1 + 2,
 	.rd_max		= 127 + 2,
 	.s2div		= icst307_s2div,
 	.idx2s		= icst307_idx2s,
 };
 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
 {
 	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 	u32 val;
 	val = readl(clk->vcoreg) & ~0x7ffff;
 	val |= vco.v | (vco.r << 9) | (vco.s << 16);
 	writel(0xa05f, sys_lock);
 	writel(val, clk->vcoreg);
 	writel(0, sys_lock);
 }
 static const struct clk_ops oscvco_clk_ops = {
 	.round	= icst_clk_round,
 	.set	= icst_clk_set,
 	.setvco	= realview_oscvco_set,
 };
 static struct clk oscvco_clk = {
 	.ops	= &oscvco_clk_ops,
 	.params	= &realview_oscvco_params,
 };
 /*
  * These are fixed clocks.
  */
 static struct clk ref24_clk = {
 	.rate	= 24000000,
 };
+static struct clk dummy_apb_pclk;
 static struct clk_lookup lookups[] = {
-	{	/* UART0 */
+	{	/* Bus clock */
+		.con_id		= "apb_pclk",
+		.clk		= &dummy_apb_pclk,
+	}, {	/* UART0 */
 		.dev_id		= "dev:uart0",
 		.clk		= &ref24_clk,
 	}, {	/* UART1 */
 		.dev_id		= "dev:uart1",
 		.clk		= &ref24_clk,
 	}, {	/* UART2 */
 		.dev_id		= "dev:uart2",
 		.clk		= &ref24_clk,
 	}, {	/* UART3 */
 		.dev_id		= "fpga:uart3",
 		.clk		= &ref24_clk,
 	}, {	/* KMI0 */
 		.dev_id		= "fpga:kmi0",
 		.clk		= &ref24_clk,
 	}, {	/* KMI1 */
 		.dev_id		= "fpga:kmi1",
 		.clk		= &ref24_clk,
 	}, {	/* MMC0 */
 		.dev_id		= "fpga:mmc0",
 		.clk		= &ref24_clk,
 	}, {	/* EB:CLCD */
 		.dev_id		= "dev:clcd",
 		.clk		= &oscvco_clk,
 	}, {	/* PB:CLCD */
 		.dev_id		= "issp:clcd",
 		.clk		= &oscvco_clk,
 	}
 };
 static int __init clk_init(void)
 {
 	if (machine_is_realview_pb1176())
 		oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 	else
 		oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 	return 0;
 }
 arch_initcall(clk_init);
 /*
  * CLCD support.
  */
 #define SYS_CLCD_NLCDIOON	(1 << 2)
 #define SYS_CLCD_VDDPOSSWITCH	(1 << 3)
 #define SYS_CLCD_PWR3V5SWITCH	(1 << 4)
 #define SYS_CLCD_ID_MASK	(0x1f << 8)
 #define SYS_CLCD_ID_SANYO_3_8	(0x00 << 8)
 #define SYS_CLCD_ID_UNKNOWN_8_4	(0x01 << 8)
 #define SYS_CLCD_ID_EPSON_2_2	(0x02 << 8)
 #define SYS_CLCD_ID_SANYO_2_5	(0x07 << 8)
 #define SYS_CLCD_ID_VGA		(0x1f << 8)
 static struct clcd_panel vga = {
 	.mode		= {
 		.name		= "VGA",
 		.refresh	= 60,
 		.xres		= 640,
 		.yres		= 480,
 		.pixclock	= 39721,
 		.left_margin	= 40,
 		.right_margin	= 24,
 		.upper_margin	= 32,
 		.lower_margin	= 11,
 		.hsync_len	= 96,
 		.vsync_len	= 2,
 		.sync		= 0,
 		.vmode		= FB_VMODE_NONINTERLACED,
 	},
 	.width		= -1,
 	.height		= -1,
 	.tim2		= TIM2_BCD | TIM2_IPC,
 	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 	.bpp		= 16,
 };
 static struct clcd_panel xvga = {
 	.mode		= {
 		.name		= "XVGA",
 		.refresh	= 60,
 		.xres		= 1024,
 		.yres		= 768,
 		.pixclock	= 15748,
 		.left_margin	= 152,
 		.right_margin	= 48,
 		.upper_margin	= 23,
 		.lower_margin	= 3,
 		.hsync_len	= 104,
 		.vsync_len	= 4,
 		.sync		= 0,
 		.vmode		= FB_VMODE_NONINTERLACED,
 	},
 	.width		= -1,
 	.height		= -1,
 	.tim2		= TIM2_BCD | TIM2_IPC,
 	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 	.bpp		= 16,
 };
 static struct clcd_panel sanyo_3_8_in = {
 	.mode		= {
 		.name		= "Sanyo QVGA",
 		.refresh	= 116,
 		.xres		= 320,
 		.yres		= 240,
 		.pixclock	= 100000,
 		.left_margin	= 6,
 		.right_margin	= 6,
 		.upper_margin	= 5,
 		.lower_margin	= 5,
 		.hsync_len	= 6,
 		.vsync_len	= 6,
 		.sync		= 0,
 		.vmode		= FB_VMODE_NONINTERLACED,
 	},
 	.width		= -1,
 	.height		= -1,
 	.tim2		= TIM2_BCD,
 	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 	.bpp		= 16,
 };
 static struct clcd_panel sanyo_2_5_in = {
 	.mode		= {
 		.name		= "Sanyo QVGA Portrait",
 		.refresh	= 116,
 		.xres		= 240,
 		.yres		= 320,
 		.pixclock	= 100000,
 		.left_margin	= 20,
 		.right_margin	= 10,
 		.upper_margin	= 2,
 		.lower_margin	= 2,
 		.hsync_len	= 10,
 		.vsync_len	= 2,
 		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 		.vmode		= FB_VMODE_NONINTERLACED,
 	},
 	.width		= -1,
 	.height		= -1,
 	.tim2		= TIM2_IVS | TIM2_IHS | TIM2_IPC,
 	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 	.bpp		= 16,
 };
 static struct clcd_panel epson_2_2_in = {
 	.mode		= {
 		.name		= "Epson QCIF",
 		.refresh	= 390,
 		.xres		= 176,
 		.yres		= 220,
 		.pixclock	= 62500,
 		.left_margin	= 3,
 		.right_margin	= 2,
 		.upper_margin	= 1,
 		.lower_margin	= 0,
 		.hsync_len	= 3,
 		.vsync_len	= 2,
 		.sync		= 0,
 		.vmode		= FB_VMODE_NONINTERLACED,
 	},
 	.width		= -1,
 	.height		= -1,
 	.tim2		= TIM2_BCD | TIM2_IPC,
 	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 	.bpp		= 16,
 };
 /*
  * Detect which LCD panel is connected, and return the appropriate
  * clcd_panel structure.  Note: we do not have any information on
  * the required timings for the 8.4in panel, so we presently assume
  * VGA timings.
  */
 static struct clcd_panel *realview_clcd_panel(void)
 {
 	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 	struct clcd_panel *vga_panel;
 	struct clcd_panel *panel;
 	u32 val;
 	if (machine_is_realview_eb())
 		vga_panel = &vga;
 	else
 		vga_panel = &xvga;
 	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 	if (val == SYS_CLCD_ID_SANYO_3_8)
 		panel = &sanyo_3_8_in;
 	else if (val == SYS_CLCD_ID_SANYO_2_5)
 		panel = &sanyo_2_5_in;
 	else if (val == SYS_CLCD_ID_EPSON_2_2)
 		panel = &epson_2_2_in;
 	else if (val == SYS_CLCD_ID_VGA)
 		panel = vga_panel;
 	else {
 		printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 			val);
 		panel = vga_panel;
 	}
 	return panel;
 }
 /*
  * Disable all display connectors on the interface module.
  */
 static void realview_clcd_disable(struct clcd_fb *fb)
 {
 	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 	u32 val;
 	val = readl(sys_clcd);
 	val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 	writel(val, sys_clcd);
 }
 /*
  * Enable the relevant connector on the interface module.
  */
 static void realview_clcd_enable(struct clcd_fb *fb)
 {
 	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 	u32 val;
 	/*
 	 * Enable the PSUs
 	 */
 	val = readl(sys_clcd);
 	val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 	writel(val, sys_clcd);
 }
 static int realview_clcd_setup(struct clcd_fb *fb)
 {
 	unsigned long framesize;
 	dma_addr_t dma;
 	if (machine_is_realview_eb())
 		/* VGA, 16bpp */
 		framesize = 640 * 480 * 2;
 	else
 		/* XVGA, 16bpp */
 		framesize = 1024 * 768 * 2;
 	fb->panel		= realview_clcd_panel();
 	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 						    &dma, GFP_KERNEL | GFP_DMA);
 	if (!fb->fb.screen_base) {
 		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 		return -ENOMEM;
 	}
 	fb->fb.fix.smem_start	= dma;
 	fb->fb.fix.smem_len	= framesize;
 	return 0;
 }
 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 {
 	return dma_mmap_writecombine(&fb->dev->dev, vma,
 				     fb->fb.screen_base,
 				     fb->fb.fix.smem_start,
 				     fb->fb.fix.smem_len);
 }
 static void realview_clcd_remove(struct clcd_fb *fb)
 {
 	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 			      fb->fb.screen_base, fb->fb.fix.smem_start);
 }
 struct clcd_board clcd_plat_data = {
 	.name		= "RealView",
 	.check		= clcdfb_check,
 	.decode		= clcdfb_decode,
 	.disable	= realview_clcd_disable,
 	.enable		= realview_clcd_enable,
 	.setup		= realview_clcd_setup,
 	.mmap		= realview_clcd_mmap,
 	.remove		= realview_clcd_remove,
 };
 #ifdef CONFIG_LEDS
 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 void realview_leds_event(led_event_t ledevt)
 {
 	unsigned long flags;
 	u32 val;
 	u32 led = 1 << smp_processor_id();
 	local_irq_save(flags);
 	val = readl(VA_LEDS_BASE);
 	switch (ledevt) {
 	case led_idle_start:
 		val = val & ~led;
 		break;
 	case led_idle_end:
 		val = val | led;
 		break;
 	case led_timer:
 		val = val ^ REALVIEW_SYS_LED7;
 		break;
 	case led_halted:
 		val = 0;
 		break;
 	default:
 		break;
 	}
 	writel(val, VA_LEDS_BASE);
 	local_irq_restore(flags);
 }
 #endif	/* CONFIG_LEDS */
 /*
  * Where is the timer (VA)?
  */
 void __iomem *timer0_va_base;
 void __iomem *timer1_va_base;
 void __iomem *timer2_va_base;
 void __iomem *timer3_va_base;
 /*
  * Set up the clock source and clock events devices
  */
 void __init realview_timer_init(unsigned int timer_irq)
 {
 	u32 val;
 	/*
 	 * set clock frequency:
 	 *	REALVIEW_REFCLK is 32KHz
 	 *	REALVIEW_TIMCLK is 1MHz
 	 */
 	val = readl(__io_address(REALVIEW_SCTL_BASE));
 	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 	       (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 	       (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 	       (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 	       __io_address(REALVIEW_SCTL_BASE));
 	/*
 	 * Initialise to a known state (all timers off)
 	 */
 	writel(0, timer0_va_base + TIMER_CTRL);
 	writel(0, timer1_va_base + TIMER_CTRL);
 	writel(0, timer2_va_base + TIMER_CTRL);
 	writel(0, timer3_va_base + TIMER_CTRL);
 	sp804_clocksource_init(timer3_va_base);
 	sp804_clockevents_init(timer0_va_base, timer_irq);
 }
 /*
  * Setup the memory banks.
  */
 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
 		    struct meminfo *meminfo)
 {
 	/*
 	 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
 	 * Half of this is mirrored at 0.
 	 */
 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
 	meminfo->bank[0].start = 0x70000000;
 	meminfo->bank[0].size = SZ_512M;
 	meminfo->nr_banks = 1;
 #else
 	meminfo->bank[0].start = 0;
 	meminfo->bank[0].size = SZ_256M;
 	meminfo->nr_banks = 1;
 #endif
 }

arch/arm/mach-spear3xx/clock.c

Diff comments View file @ 3126c7b

 /*
  * arch/arm/mach-spear3xx/clock.c
  *
  * SPEAr3xx machines clock framework source file
  *
  * Copyright (C) 2009 ST Microelectronics
  * Viresh Kumar<viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <mach/misc_regs.h>
 #include <plat/clock.h>
 /* root clks */
 /* 32 KHz oscillator clock */
 static struct clk osc_32k_clk = {
 	.flags = ALWAYS_ENABLED,
 	.rate = 32000,
 };
 /* 24 MHz oscillator clock */
 static struct clk osc_24m_clk = {
 	.flags = ALWAYS_ENABLED,
 	.rate = 24000000,
 };
 /* clock derived from 32 KHz osc clk */
 /* rtc clock */
 static struct clk rtc_clk = {
 	.pclk = &osc_32k_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = RTC_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* clock derived from 24 MHz osc clk */
 /* pll1 configuration structure */
 static struct pll_clk_config pll1_config = {
 	.mode_reg = PLL1_CTR,
 	.cfg_reg = PLL1_FRQ,
 };
 /* PLL1 clock */
 static struct clk pll1_clk = {
 	.pclk = &osc_24m_clk,
 	.en_reg = PLL1_CTR,
 	.en_reg_bit = PLL_ENABLE,
 	.recalc = &pll1_clk_recalc,
 	.private_data = &pll1_config,
 };
 /* PLL3 48 MHz clock */
 static struct clk pll3_48m_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &osc_24m_clk,
 	.rate = 48000000,
 };
 /* watch dog timer clock */
 static struct clk wdt_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &osc_24m_clk,
 	.recalc = &follow_parent,
 };
 /* clock derived from pll1 clk */
 /* cpu clock */
 static struct clk cpu_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &pll1_clk,
 	.recalc = &follow_parent,
 };
 /* ahb configuration structure */
 static struct bus_clk_config ahb_config = {
 	.reg = CORE_CLK_CFG,
 	.mask = PLL_HCLK_RATIO_MASK,
 	.shift = PLL_HCLK_RATIO_SHIFT,
 };
 /* ahb clock */
 static struct clk ahb_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &pll1_clk,
 	.recalc = &bus_clk_recalc,
 	.private_data = &ahb_config,
 };
 /* uart configurations */
 static struct aux_clk_config uart_config = {
 	.synth_reg = UART_CLK_SYNT,
 };
 /* uart parents */
 static struct pclk_info uart_pclk_info[] = {
 	{
 		.pclk = &pll1_clk,
 		.pclk_mask = AUX_CLK_PLL1_MASK,
 		.scalable = 1,
 	}, {
 		.pclk = &pll3_48m_clk,
 		.pclk_mask = AUX_CLK_PLL3_MASK,
 		.scalable = 0,
 	},
 };
 /* uart parent select structure */
 static struct pclk_sel uart_pclk_sel = {
 	.pclk_info = uart_pclk_info,
 	.pclk_count = ARRAY_SIZE(uart_pclk_info),
 	.pclk_sel_reg = PERIP_CLK_CFG,
 	.pclk_sel_mask = UART_CLK_MASK,
 };
 /* uart clock */
 static struct clk uart_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = UART_CLK_ENB,
 	.pclk_sel = &uart_pclk_sel,
 	.pclk_sel_shift = UART_CLK_SHIFT,
 	.recalc = &aux_clk_recalc,
 	.private_data = &uart_config,
 };
 /* firda configurations */
 static struct aux_clk_config firda_config = {
 	.synth_reg = FIRDA_CLK_SYNT,
 };
 /* firda parents */
 static struct pclk_info firda_pclk_info[] = {
 	{
 		.pclk = &pll1_clk,
 		.pclk_mask = AUX_CLK_PLL1_MASK,
 		.scalable = 1,
 	}, {
 		.pclk = &pll3_48m_clk,
 		.pclk_mask = AUX_CLK_PLL3_MASK,
 		.scalable = 0,
 	},
 };
 /* firda parent select structure */
 static struct pclk_sel firda_pclk_sel = {
 	.pclk_info = firda_pclk_info,
 	.pclk_count = ARRAY_SIZE(firda_pclk_info),
 	.pclk_sel_reg = PERIP_CLK_CFG,
 	.pclk_sel_mask = FIRDA_CLK_MASK,
 };
 /* firda clock */
 static struct clk firda_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = FIRDA_CLK_ENB,
 	.pclk_sel = &firda_pclk_sel,
 	.pclk_sel_shift = FIRDA_CLK_SHIFT,
 	.recalc = &aux_clk_recalc,
 	.private_data = &firda_config,
 };
 /* gpt parents */
 static struct pclk_info gpt_pclk_info[] = {
 	{
 		.pclk = &pll1_clk,
 		.pclk_mask = AUX_CLK_PLL1_MASK,
 		.scalable = 1,
 	}, {
 		.pclk = &pll3_48m_clk,
 		.pclk_mask = AUX_CLK_PLL3_MASK,
 		.scalable = 0,
 	},
 };
 /* gpt parent select structure */
 static struct pclk_sel gpt_pclk_sel = {
 	.pclk_info = gpt_pclk_info,
 	.pclk_count = ARRAY_SIZE(gpt_pclk_info),
 	.pclk_sel_reg = PERIP_CLK_CFG,
 	.pclk_sel_mask = GPT_CLK_MASK,
 };
 /* gpt0 configurations */
 static struct aux_clk_config gpt0_config = {
 	.synth_reg = PRSC1_CLK_CFG,
 };
 /* gpt0 timer clock */
 static struct clk gpt0_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk_sel = &gpt_pclk_sel,
 	.pclk_sel_shift = GPT0_CLK_SHIFT,
 	.recalc = &gpt_clk_recalc,
 	.private_data = &gpt0_config,
 };
 /* gpt1 configurations */
 static struct aux_clk_config gpt1_config = {
 	.synth_reg = PRSC2_CLK_CFG,
 };
 /* gpt1 timer clock */
 static struct clk gpt1_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = GPT1_CLK_ENB,
 	.pclk_sel = &gpt_pclk_sel,
 	.pclk_sel_shift = GPT1_CLK_SHIFT,
 	.recalc = &gpt_clk_recalc,
 	.private_data = &gpt1_config,
 };
 /* gpt2 configurations */
 static struct aux_clk_config gpt2_config = {
 	.synth_reg = PRSC3_CLK_CFG,
 };
 /* gpt2 timer clock */
 static struct clk gpt2_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = GPT2_CLK_ENB,
 	.pclk_sel = &gpt_pclk_sel,
 	.pclk_sel_shift = GPT2_CLK_SHIFT,
 	.recalc = &gpt_clk_recalc,
 	.private_data = &gpt2_config,
 };
 /* clock derived from pll3 clk */
 /* usbh clock */
 static struct clk usbh_clk = {
 	.pclk = &pll3_48m_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = USBH_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* usbd clock */
 static struct clk usbd_clk = {
 	.pclk = &pll3_48m_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = USBD_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* clcd clock */
 static struct clk clcd_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &pll3_48m_clk,
 	.recalc = &follow_parent,
 };
 /* clock derived from ahb clk */
 /* apb configuration structure */
 static struct bus_clk_config apb_config = {
 	.reg = CORE_CLK_CFG,
 	.mask = HCLK_PCLK_RATIO_MASK,
 	.shift = HCLK_PCLK_RATIO_SHIFT,
 };
 /* apb clock */
 static struct clk apb_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &ahb_clk,
 	.recalc = &bus_clk_recalc,
 	.private_data = &apb_config,
 };
 /* i2c clock */
 static struct clk i2c_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = I2C_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* dma clock */
 static struct clk dma_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = DMA_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* jpeg clock */
 static struct clk jpeg_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = JPEG_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* gmac clock */
 static struct clk gmac_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = GMAC_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* smi clock */
 static struct clk smi_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = SMI_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* c3 clock */
 static struct clk c3_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = C3_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* clock derived from apb clk */
 /* adc clock */
 static struct clk adc_clk = {
 	.pclk = &apb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = ADC_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* ssp clock */
 static struct clk ssp_clk = {
 	.pclk = &apb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = SSP_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* gpio clock */
 static struct clk gpio_clk = {
 	.pclk = &apb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = GPIO_CLK_ENB,
 	.recalc = &follow_parent,
 };
+static struct clk dummy_apb_pclk;
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
+	{ .con_id = "apb_pclk",	.clk = &dummy_apb_pclk},
 	/* root clks */
 	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
 	{ .con_id = "osc_24m_clk",	.clk = &osc_24m_clk},
 	/* clock derived from 32 KHz osc clk */
 	{ .dev_id = "rtc",		.clk = &rtc_clk},
 	/* clock derived from 24 MHz osc clk */
 	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
 	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
 	{ .dev_id = "wdt",		.clk = &wdt_clk},
 	/* clock derived from pll1 clk */
 	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
 	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
 	{ .dev_id = "uart",		.clk = &uart_clk},
 	{ .dev_id = "firda",		.clk = &firda_clk},
 	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
 	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
 	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
 	/* clock derived from pll3 clk */
 	{ .dev_id = "usbh",		.clk = &usbh_clk},
 	{ .dev_id = "usbd",		.clk = &usbd_clk},
 	{ .dev_id = "clcd",		.clk = &clcd_clk},
 	/* clock derived from ahb clk */
 	{ .con_id = "apb_clk",		.clk = &apb_clk},
 	{ .dev_id = "i2c",		.clk = &i2c_clk},
 	{ .dev_id = "dma",		.clk = &dma_clk},
 	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
 	{ .dev_id = "gmac",		.clk = &gmac_clk},
 	{ .dev_id = "smi",		.clk = &smi_clk},
 	{ .dev_id = "c3",		.clk = &c3_clk},
 	/* clock derived from apb clk */
 	{ .dev_id = "adc",		.clk = &adc_clk},
 	{ .dev_id = "ssp",		.clk = &ssp_clk},
 	{ .dev_id = "gpio",		.clk = &gpio_clk},
 };
 void __init clk_init(void)
 {
 	int i;
 	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
 		clk_register(&spear_clk_lookups[i]);
 	recalc_root_clocks();
 }

arch/arm/mach-spear6xx/clock.c

Diff comments View file @ 3126c7b

 /*
  * arch/arm/mach-spear6xx/clock.c
  *
  * SPEAr6xx machines clock framework source file
  *
  * Copyright (C) 2009 ST Microelectronics
  * Viresh Kumar<viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <mach/misc_regs.h>
 #include <plat/clock.h>
 /* root clks */
 /* 32 KHz oscillator clock */
 static struct clk osc_32k_clk = {
 	.flags = ALWAYS_ENABLED,
 	.rate = 32000,
 };
 /* 30 MHz oscillator clock */
 static struct clk osc_30m_clk = {
 	.flags = ALWAYS_ENABLED,
 	.rate = 30000000,
 };
 /* clock derived from 32 KHz osc clk */
 /* rtc clock */
 static struct clk rtc_clk = {
 	.pclk = &osc_32k_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = RTC_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* clock derived from 30 MHz osc clk */
 /* pll1 configuration structure */
 static struct pll_clk_config pll1_config = {
 	.mode_reg = PLL1_CTR,
 	.cfg_reg = PLL1_FRQ,
 };
 /* PLL1 clock */
 static struct clk pll1_clk = {
 	.pclk = &osc_30m_clk,
 	.en_reg = PLL1_CTR,
 	.en_reg_bit = PLL_ENABLE,
 	.recalc = &pll1_clk_recalc,
 	.private_data = &pll1_config,
 };
 /* PLL3 48 MHz clock */
 static struct clk pll3_48m_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &osc_30m_clk,
 	.rate = 48000000,
 };
 /* watch dog timer clock */
 static struct clk wdt_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &osc_30m_clk,
 	.recalc = &follow_parent,
 };
 /* clock derived from pll1 clk */
 /* cpu clock */
 static struct clk cpu_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &pll1_clk,
 	.recalc = &follow_parent,
 };
 /* ahb configuration structure */
 static struct bus_clk_config ahb_config = {
 	.reg = CORE_CLK_CFG,
 	.mask = PLL_HCLK_RATIO_MASK,
 	.shift = PLL_HCLK_RATIO_SHIFT,
 };
 /* ahb clock */
 static struct clk ahb_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &pll1_clk,
 	.recalc = &bus_clk_recalc,
 	.private_data = &ahb_config,
 };
 /* uart parents */
 static struct pclk_info uart_pclk_info[] = {
 	{
 		.pclk = &pll1_clk,
 		.pclk_mask = AUX_CLK_PLL1_MASK,
 		.scalable = 1,
 	}, {
 		.pclk = &pll3_48m_clk,
 		.pclk_mask = AUX_CLK_PLL3_MASK,
 		.scalable = 0,
 	},
 };
 /* uart parent select structure */
 static struct pclk_sel uart_pclk_sel = {
 	.pclk_info = uart_pclk_info,
 	.pclk_count = ARRAY_SIZE(uart_pclk_info),
 	.pclk_sel_reg = PERIP_CLK_CFG,
 	.pclk_sel_mask = UART_CLK_MASK,
 };
 /* uart configurations */
 static struct aux_clk_config uart_config = {
 	.synth_reg = UART_CLK_SYNT,
 };
 /* uart0 clock */
 static struct clk uart0_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = UART0_CLK_ENB,
 	.pclk_sel = &uart_pclk_sel,
 	.pclk_sel_shift = UART_CLK_SHIFT,
 	.recalc = &aux_clk_recalc,
 	.private_data = &uart_config,
 };
 /* uart1 clock */
 static struct clk uart1_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = UART1_CLK_ENB,
 	.pclk_sel = &uart_pclk_sel,
 	.pclk_sel_shift = UART_CLK_SHIFT,
 	.recalc = &aux_clk_recalc,
 	.private_data = &uart_config,
 };
 /* firda configurations */
 static struct aux_clk_config firda_config = {
 	.synth_reg = FIRDA_CLK_SYNT,
 };
 /* firda parents */
 static struct pclk_info firda_pclk_info[] = {
 	{
 		.pclk = &pll1_clk,
 		.pclk_mask = AUX_CLK_PLL1_MASK,
 		.scalable = 1,
 	}, {
 		.pclk = &pll3_48m_clk,
 		.pclk_mask = AUX_CLK_PLL3_MASK,
 		.scalable = 0,
 	},
 };
 /* firda parent select structure */
 static struct pclk_sel firda_pclk_sel = {
 	.pclk_info = firda_pclk_info,
 	.pclk_count = ARRAY_SIZE(firda_pclk_info),
 	.pclk_sel_reg = PERIP_CLK_CFG,
 	.pclk_sel_mask = FIRDA_CLK_MASK,
 };
 /* firda clock */
 static struct clk firda_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = FIRDA_CLK_ENB,
 	.pclk_sel = &firda_pclk_sel,
 	.pclk_sel_shift = FIRDA_CLK_SHIFT,
 	.recalc = &aux_clk_recalc,
 	.private_data = &firda_config,
 };
 /* clcd configurations */
 static struct aux_clk_config clcd_config = {
 	.synth_reg = CLCD_CLK_SYNT,
 };
 /* clcd parents */
 static struct pclk_info clcd_pclk_info[] = {
 	{
 		.pclk = &pll1_clk,
 		.pclk_mask = AUX_CLK_PLL1_MASK,
 		.scalable = 1,
 	}, {
 		.pclk = &pll3_48m_clk,
 		.pclk_mask = AUX_CLK_PLL3_MASK,
 		.scalable = 0,
 	},
 };
 /* clcd parent select structure */
 static struct pclk_sel clcd_pclk_sel = {
 	.pclk_info = clcd_pclk_info,
 	.pclk_count = ARRAY_SIZE(clcd_pclk_info),
 	.pclk_sel_reg = PERIP_CLK_CFG,
 	.pclk_sel_mask = CLCD_CLK_MASK,
 };
 /* clcd clock */
 static struct clk clcd_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = CLCD_CLK_ENB,
 	.pclk_sel = &clcd_pclk_sel,
 	.pclk_sel_shift = CLCD_CLK_SHIFT,
 	.recalc = &aux_clk_recalc,
 	.private_data = &clcd_config,
 };
 /* gpt parents */
 static struct pclk_info gpt_pclk_info[] = {
 	{
 		.pclk = &pll1_clk,
 		.pclk_mask = AUX_CLK_PLL1_MASK,
 		.scalable = 1,
 	}, {
 		.pclk = &pll3_48m_clk,
 		.pclk_mask = AUX_CLK_PLL3_MASK,
 		.scalable = 0,
 	},
 };
 /* gpt parent select structure */
 static struct pclk_sel gpt_pclk_sel = {
 	.pclk_info = gpt_pclk_info,
 	.pclk_count = ARRAY_SIZE(gpt_pclk_info),
 	.pclk_sel_reg = PERIP_CLK_CFG,
 	.pclk_sel_mask = GPT_CLK_MASK,
 };
 /* gpt0_1 configurations */
 static struct aux_clk_config gpt0_1_config = {
 	.synth_reg = PRSC1_CLK_CFG,
 };
 /* gpt0 ARM1 subsystem timer clock */
 static struct clk gpt0_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk_sel = &gpt_pclk_sel,
 	.pclk_sel_shift = GPT0_CLK_SHIFT,
 	.recalc = &gpt_clk_recalc,
 	.private_data = &gpt0_1_config,
 };
 /* gpt1 timer clock */
 static struct clk gpt1_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk_sel = &gpt_pclk_sel,
 	.pclk_sel_shift = GPT1_CLK_SHIFT,
 	.recalc = &gpt_clk_recalc,
 	.private_data = &gpt0_1_config,
 };
 /* gpt2 configurations */
 static struct aux_clk_config gpt2_config = {
 	.synth_reg = PRSC2_CLK_CFG,
 };
 /* gpt2 timer clock */
 static struct clk gpt2_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = GPT2_CLK_ENB,
 	.pclk_sel = &gpt_pclk_sel,
 	.pclk_sel_shift = GPT2_CLK_SHIFT,
 	.recalc = &gpt_clk_recalc,
 	.private_data = &gpt2_config,
 };
 /* gpt3 configurations */
 static struct aux_clk_config gpt3_config = {
 	.synth_reg = PRSC3_CLK_CFG,
 };
 /* gpt3 timer clock */
 static struct clk gpt3_clk = {
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = GPT3_CLK_ENB,
 	.pclk_sel = &gpt_pclk_sel,
 	.pclk_sel_shift = GPT3_CLK_SHIFT,
 	.recalc = &gpt_clk_recalc,
 	.private_data = &gpt3_config,
 };
 /* clock derived from pll3 clk */
 /* usbh0 clock */
 static struct clk usbh0_clk = {
 	.pclk = &pll3_48m_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = USBH0_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* usbh1 clock */
 static struct clk usbh1_clk = {
 	.pclk = &pll3_48m_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = USBH1_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* usbd clock */
 static struct clk usbd_clk = {
 	.pclk = &pll3_48m_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = USBD_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* clock derived from ahb clk */
 /* apb configuration structure */
 static struct bus_clk_config apb_config = {
 	.reg = CORE_CLK_CFG,
 	.mask = HCLK_PCLK_RATIO_MASK,
 	.shift = HCLK_PCLK_RATIO_SHIFT,
 };
 /* apb clock */
 static struct clk apb_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &ahb_clk,
 	.recalc = &bus_clk_recalc,
 	.private_data = &apb_config,
 };
 /* i2c clock */
 static struct clk i2c_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = I2C_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* dma clock */
 static struct clk dma_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = DMA_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* jpeg clock */
 static struct clk jpeg_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = JPEG_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* gmac clock */
 static struct clk gmac_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = GMAC_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* smi clock */
 static struct clk smi_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = SMI_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* fsmc clock */
 static struct clk fsmc_clk = {
 	.pclk = &ahb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = FSMC_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* clock derived from apb clk */
 /* adc clock */
 static struct clk adc_clk = {
 	.pclk = &apb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = ADC_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* ssp0 clock */
 static struct clk ssp0_clk = {
 	.pclk = &apb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = SSP0_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* ssp1 clock */
 static struct clk ssp1_clk = {
 	.pclk = &apb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = SSP1_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* ssp2 clock */
 static struct clk ssp2_clk = {
 	.pclk = &apb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = SSP2_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* gpio0 ARM subsystem clock */
 static struct clk gpio0_clk = {
 	.flags = ALWAYS_ENABLED,
 	.pclk = &apb_clk,
 	.recalc = &follow_parent,
 };
 /* gpio1 clock */
 static struct clk gpio1_clk = {
 	.pclk = &apb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = GPIO1_CLK_ENB,
 	.recalc = &follow_parent,
 };
 /* gpio2 clock */
 static struct clk gpio2_clk = {
 	.pclk = &apb_clk,
 	.en_reg = PERIP1_CLK_ENB,
 	.en_reg_bit = GPIO2_CLK_ENB,
 	.recalc = &follow_parent,
 };
+static struct clk dummy_apb_pclk;
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
+	{ .con_id = "apb_pclk",	.clk = &dummy_apb_pclk},
 	/* root clks */
 	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
 	{ .con_id = "osc_30m_clk",	.clk = &osc_30m_clk},
 	/* clock derived from 32 KHz os		 clk */
 	{ .dev_id = "rtc",		.clk = &rtc_clk},
 	/* clock derived from 30 MHz os		 clk */
 	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
 	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
 	{ .dev_id = "wdt",		.clk = &wdt_clk},
 	/* clock derived from pll1 clk */
 	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
 	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
 	{ .dev_id = "uart0",		.clk = &uart0_clk},
 	{ .dev_id = "uart1",		.clk = &uart1_clk},
 	{ .dev_id = "firda",		.clk = &firda_clk},
 	{ .dev_id = "clcd",		.clk = &clcd_clk},
 	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
 	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
 	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
 	{ .dev_id = "gpt3",		.clk = &gpt3_clk},
 	/* clock derived from pll3 clk */
 	{ .dev_id = "usbh0",		.clk = &usbh0_clk},
 	{ .dev_id = "usbh1",		.clk = &usbh1_clk},
 	{ .dev_id = "usbd",		.clk = &usbd_clk},
 	/* clock derived from ahb clk */
 	{ .con_id = "apb_clk",		.clk = &apb_clk},
 	{ .dev_id = "i2c",		.clk = &i2c_clk},
 	{ .dev_id = "dma",		.clk = &dma_clk},
 	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
 	{ .dev_id = "gmac",		.clk = &gmac_clk},
 	{ .dev_id = "smi",		.clk = &smi_clk},
 	{ .dev_id = "fsmc",		.clk = &fsmc_clk},
 	/* clock derived from apb clk */
 	{ .dev_id = "adc",		.clk = &adc_clk},
 	{ .dev_id = "ssp0",		.clk = &ssp0_clk},
 	{ .dev_id = "ssp1",		.clk = &ssp1_clk},
 	{ .dev_id = "ssp2",		.clk = &ssp2_clk},
 	{ .dev_id = "gpio0",		.clk = &gpio0_clk},
 	{ .dev_id = "gpio1",		.clk = &gpio1_clk},
 	{ .dev_id = "gpio2",		.clk = &gpio2_clk},
 };
 void __init clk_init(void)
 {
 	int i;
 	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
 		clk_register(&spear_clk_lookups[i]);
 	recalc_root_clocks();
 }

arch/arm/mach-u300/clock.c

Diff comments View file @ 3126c7b

 /*
  *
  * arch/arm/mach-u300/clock.c
  *
  *
  * Copyright (C) 2007-2009 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * Define clocks in the app platform.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
  *
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/string.h>
 #include <linux/clk.h>
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
 #include <linux/debugfs.h>
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/timer.h>
 #include <linux/io.h>
 #include <linux/seq_file.h>
 #include <asm/clkdev.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
 #include "clock.h"
 /*
  * TODO:
  * - move all handling of the CCR register into this file and create
  *   a spinlock for the CCR register
  * - switch to the clkdevice lookup mechanism that maps clocks to
  *   device ID:s instead when it becomes available in kernel 2.6.29.
  * - implement rate get/set for all clocks that need it.
  */
 /*
  * Syscon clock I/O registers lock so clock requests don't collide
  * NOTE: this is a local lock only used to lock access to clock and
  * reset registers in syscon.
  */
 static DEFINE_SPINLOCK(syscon_clkreg_lock);
 static DEFINE_SPINLOCK(syscon_resetreg_lock);
 /*
  * The clocking hierarchy currently looks like this.
  * NOTE: the idea is NOT to show how the clocks are routed on the chip!
  * The ideas is to show dependencies, so a clock higher up in the
  * hierarchy has to be on in order for another clock to be on. Now,
  * both CPU and DMA can actually be on top of the hierarchy, and that
  * is not modeled currently. Instead we have the backbone AMBA bus on
  * top. This bus cannot be programmed in any way but conceptually it
  * needs to be active for the bridges and devices to transport data.
  *
  * Please be aware that a few clocks are hw controlled, which mean that
  * the hw itself can turn on/off or change the rate of the clock when
  * needed!
  *
  *  AMBA bus
  *  |
  *  +- CPU
  *  +- NANDIF NAND Flash interface
  *  +- SEMI Shared Memory interface
  *  +- ISP Image Signal Processor (U335 only)
  *  +- CDS (U335 only)
  *  +- DMA Direct Memory Access Controller
  *  +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
  *  +- APEX
  *  +- VIDEO_ENC AVE2/3 Video Encoder
  *  +- XGAM Graphics Accelerator Controller
  *  +- AHB
  *  |
  *  +- ahb:0 AHB Bridge
  *  |  |
  *  |  +- ahb:1 INTCON Interrupt controller
  *  |  +- ahb:3 MSPRO  Memory Stick Pro controller
  *  |  +- ahb:4 EMIF   External Memory interface
  *  |
  *  +- fast:0 FAST bridge
  *  |  |
  *  |  +- fast:1 MMCSD MMC/SD card reader controller
  *  |  +- fast:2 I2S0  PCM I2S channel 0 controller
  *  |  +- fast:3 I2S1  PCM I2S channel 1 controller
  *  |  +- fast:4 I2C0  I2C channel 0 controller
  *  |  +- fast:5 I2C1  I2C channel 1 controller
  *  |  +- fast:6 SPI   SPI controller
  *  |  +- fast:7 UART1 Secondary UART (U335 only)
  *  |
  *  +- slow:0 SLOW bridge
  *     |
  *     +- slow:1 SYSCON (not possible to control)
  *     +- slow:2 WDOG Watchdog
  *     +- slow:3 UART0 primary UART
  *     +- slow:4 TIMER_APP Application timer - used in Linux
  *     +- slow:5 KEYPAD controller
  *     +- slow:6 GPIO controller
  *     +- slow:7 RTC controller
  *     +- slow:8 BT Bus Tracer (not used currently)
  *     +- slow:9 EH Event Handler (not used currently)
  *     +- slow:a TIMER_ACC Access style timer (not used currently)
  *     +- slow:b PPM (U335 only, what is that?)
  */
 /*
  * Reset control functions. We remember if a block has been
  * taken out of reset and don't remove the reset assertion again
  * and vice versa. Currently we only remove resets so the
  * enablement function is defined out.
  */
 static void syscon_block_reset_enable(struct clk *clk)
 {
 	u16 val;
 	unsigned long iflags;
 	/* Not all blocks support resetting */
 	if (!clk->res_reg || !clk->res_mask)
 		return;
 	spin_lock_irqsave(&syscon_resetreg_lock, iflags);
 	val = readw(clk->res_reg);
 	val |= clk->res_mask;
 	writew(val, clk->res_reg);
 	spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
 	clk->reset = true;
 }
 static void syscon_block_reset_disable(struct clk *clk)
 {
 	u16 val;
 	unsigned long iflags;
 	/* Not all blocks support resetting */
 	if (!clk->res_reg || !clk->res_mask)
 		return;
 	spin_lock_irqsave(&syscon_resetreg_lock, iflags);
 	val = readw(clk->res_reg);
 	val &= ~clk->res_mask;
 	writew(val, clk->res_reg);
 	spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
 	clk->reset = false;
 }
 int __clk_get(struct clk *clk)
 {
 	u16 val;
 	/* The MMC and MSPRO clocks need some special set-up */
 	if (!strcmp(clk->name, "MCLK")) {
 		/* Set default MMC clock divisor to 18.9 MHz */
 		writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
 		val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
 		/* Disable the MMC feedback clock */
 		val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
 		/* Disable MSPRO frequency */
 		val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
 		writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
 	}
 	if (!strcmp(clk->name, "MSPRO")) {
 		val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
 		/* Disable the MMC feedback clock */
 		val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
 		/* Enable MSPRO frequency */
 		val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
 		writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
 	}
 	return 1;
 }
 EXPORT_SYMBOL(__clk_get);
 void __clk_put(struct clk *clk)
 {
 }
 EXPORT_SYMBOL(__clk_put);
 static void syscon_clk_disable(struct clk *clk)
 {
 	unsigned long iflags;
 	/* Don't touch the hardware controlled clocks */
 	if (clk->hw_ctrld)
 		return;
 	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
 	writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
 	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
 }
 static void syscon_clk_enable(struct clk *clk)
 {
 	unsigned long iflags;
 	/* Don't touch the hardware controlled clocks */
 	if (clk->hw_ctrld)
 		return;
 	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
 	writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
 	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
 }
 static u16 syscon_clk_get_rate(void)
 {
 	u16 val;
 	unsigned long iflags;
 	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
 	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
 	return val;
 }
 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
 static void enable_i2s0_vcxo(void)
 {
 	u16 val;
 	unsigned long iflags;
 	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
 	/* Set I2S0 to use the VCXO 26 MHz clock */
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val |= U300_SYSCON_CCR_TURN_VCXO_ON;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
 	val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
 	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
 }
 static void enable_i2s1_vcxo(void)
 {
 	u16 val;
 	unsigned long iflags;
 	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
 	/* Set I2S1 to use the VCXO 26 MHz clock */
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val |= U300_SYSCON_CCR_TURN_VCXO_ON;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
 	val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
 	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
 }
 static void disable_i2s0_vcxo(void)
 {
 	u16 val;
 	unsigned long iflags;
 	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
 	/* Disable I2S0 use of the VCXO 26 MHz clock */
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	/* Deactivate VCXO if noone else is using VCXO */
 	if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
 		val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
 	val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
 	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
 }
 static void disable_i2s1_vcxo(void)
 {
 	u16 val;
 	unsigned long iflags;
 	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
 	/* Disable I2S1 use of the VCXO 26 MHz clock */
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	/* Deactivate VCXO if noone else is using VCXO */
 	if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
 		val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
 	val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
 	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
 }
 #endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
 static void syscon_clk_rate_set_mclk(unsigned long rate)
 {
 	u16 val;
 	u32 reg;
 	unsigned long iflags;
 	switch (rate) {
 	case 18900000:
 		val = 0x0054;
 		break;
 	case 20800000:
 		val = 0x0044;
 		break;
 	case 23100000:
 		val = 0x0043;
 		break;
 	case 26000000:
 		val = 0x0033;
 		break;
 	case 29700000:
 		val = 0x0032;
 		break;
 	case 34700000:
 		val = 0x0022;
 		break;
 	case 41600000:
 		val = 0x0021;
 		break;
 	case 52000000:
 		val = 0x0011;
 		break;
 	case 104000000:
 		val = 0x0000;
 		break;
 	default:
 		printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
 		       rate);
 		return;
 	}
 	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
 	reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
 		~U300_SYSCON_MMF0R_MASK;
 	writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
 	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
 }
 void syscon_clk_rate_set_cpuclk(unsigned long rate)
 {
 	u16 val;
 	unsigned long iflags;
 	switch (rate) {
 	case 13000000:
 		val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
 		break;
 	case 52000000:
 		val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
 		break;
 	case 104000000:
 		val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
 		break;
 	case 208000000:
 		val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
 		break;
 	default:
 		return;
 	}
 	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
 	val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
 		~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
 }
 EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
 void clk_disable(struct clk *clk)
 {
 	unsigned long iflags;
 	spin_lock_irqsave(&clk->lock, iflags);
 	if (clk->usecount > 0 && !(--clk->usecount)) {
 		/* some blocks lack clocking registers and cannot be disabled */
 		if (clk->disable)
 			clk->disable(clk);
 		if (likely((u32)clk->parent))
 			clk_disable(clk->parent);
 	}
 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
 	if (unlikely(!strcmp(clk->name, "I2S0")))
 		disable_i2s0_vcxo();
 	if (unlikely(!strcmp(clk->name, "I2S1")))
 		disable_i2s1_vcxo();
 #endif
 	spin_unlock_irqrestore(&clk->lock, iflags);
 }
 EXPORT_SYMBOL(clk_disable);
 int clk_enable(struct clk *clk)
 {
 	int ret = 0;
 	unsigned long iflags;
 	spin_lock_irqsave(&clk->lock, iflags);
 	if (clk->usecount++ == 0) {
 		if (likely((u32)clk->parent))
 			ret = clk_enable(clk->parent);
 		if (unlikely(ret != 0))
 			clk->usecount--;
 		else {
 			/* remove reset line (we never enable reset again) */
 			syscon_block_reset_disable(clk);
 			/* clocks without enable function are always on */
 			if (clk->enable)
 				clk->enable(clk);
 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
 			if (unlikely(!strcmp(clk->name, "I2S0")))
 				enable_i2s0_vcxo();
 			if (unlikely(!strcmp(clk->name, "I2S1")))
 				enable_i2s1_vcxo();
 #endif
 		}
 	}
 	spin_unlock_irqrestore(&clk->lock, iflags);
 	return ret;
 }
 EXPORT_SYMBOL(clk_enable);
 /* Returns the clock rate in Hz */
 static unsigned long clk_get_rate_cpuclk(struct clk *clk)
 {
 	u16 val;
 	val = syscon_clk_get_rate();
 	switch (val) {
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
 		return 13000000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
 		return 52000000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
 		return 104000000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
 		return 208000000;
 	default:
 		break;
 	}
 	return clk->rate;
 }
 static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
 {
 	u16 val;
 	val = syscon_clk_get_rate();
 	switch (val) {
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
 		return 6500000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
 		return 26000000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
 		return 52000000;
 	default:
 		break;
 	}
 	return clk->rate;
 }
 static unsigned long clk_get_rate_emif_clk(struct clk *clk)
 {
 	u16 val;
 	val = syscon_clk_get_rate();
 	switch (val) {
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
 		return 13000000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
 		return 52000000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
 		return 104000000;
 	default:
 		break;
 	}
 	return clk->rate;
 }
 static unsigned long clk_get_rate_xgamclk(struct clk *clk)
 {
 	u16 val;
 	val = syscon_clk_get_rate();
 	switch (val) {
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
 		return 6500000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
 		return 26000000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
 		return 52000000;
 	default:
 		break;
 	}
 	return clk->rate;
 }
 static unsigned long clk_get_rate_mclk(struct clk *clk)
 {
 	u16 val;
 	val = syscon_clk_get_rate();
 	switch (val) {
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
 		/*
 		 * Here, the 208 MHz PLL gets shut down and the always
 		 * on 13 MHz PLL used for RTC etc kicks into use
 		 * instead.
 		 */
 		return 13000000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
 	{
 		/*
 		 * This clock is under program control. The register is
 		 * divided in two nybbles, bit 7-4 gives cycles-1 to count
 		 * high, bit 3-0 gives cycles-1 to count low. Distribute
 		 * these with no more than 1 cycle difference between
 		 * low and high and add low and high to get the actual
 		 * divisor. The base PLL is 208 MHz. Writing 0x00 will
 		 * divide by 1 and 1 so the highest frequency possible
 		 * is 104 MHz.
 		 *
 		 * e.g. 0x54 =>
 		 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
 		 */
 		u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
 			U300_SYSCON_MMF0R_MASK;
 		switch (val) {
 		case 0x0054:
 			return 18900000;
 		case 0x0044:
 			return 20800000;
 		case 0x0043:
 			return 23100000;
 		case 0x0033:
 			return 26000000;
 		case 0x0032:
 			return 29700000;
 		case 0x0022:
 			return 34700000;
 		case 0x0021:
 			return 41600000;
 		case 0x0011:
 			return 52000000;
 		case 0x0000:
 			return 104000000;
 		default:
 			break;
 		}
 	}
 	default:
 		break;
 	}
 	return clk->rate;
 }
 static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
 {
 	u16 val;
 	val = syscon_clk_get_rate();
 	switch (val) {
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
 		return 13000000;
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
 	case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
 		return 26000000;
 	default:
 		break;
 	}
 	return clk->rate;
 }
 unsigned long clk_get_rate(struct clk *clk)
 {
 	if (clk->get_rate)
 		return clk->get_rate(clk);
 	else
 		return clk->rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
 static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
 {
 	if (rate <= 18900000)
 		return 18900000;
 	if (rate <= 20800000)
 		return 20800000;
 	if (rate <= 23100000)
 		return 23100000;
 	if (rate <= 26000000)
 		return 26000000;
 	if (rate <= 29700000)
 		return 29700000;
 	if (rate <= 34700000)
 		return 34700000;
 	if (rate <= 41600000)
 		return 41600000;
 	if (rate <= 52000000)
 		return 52000000;
 	return -EINVAL;
 }
 static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
 {
 	if (rate <= 13000000)
 		return 13000000;
 	if (rate <= 52000000)
 		return 52000000;
 	if (rate <= 104000000)
 		return 104000000;
 	if (rate <= 208000000)
 		return 208000000;
 	return -EINVAL;
 }
 /*
  * This adjusts a requested rate to the closest exact rate
  * a certain clock can provide. For a fixed clock it's
  * mostly clk->rate.
  */
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
 	/* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */
 	/* Else default to fixed value */
 	if (clk->round_rate) {
 		return (long) clk->round_rate(clk, rate);
 	} else {
 		printk(KERN_ERR "clock: Failed to round rate of %s\n",
 		       clk->name);
 	}
 	return (long) clk->rate;
 }
 EXPORT_SYMBOL(clk_round_rate);
 static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
 {
 	syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
 	return 0;
 }
 static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
 {
 	syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
 	return 0;
 }
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	/* TODO: set for EMIFCLK and AHBCLK */
 	/* Else assume the clock is fixed and fail */
 	if (clk->set_rate) {
 		return clk->set_rate(clk, rate);
 	} else {
 		printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
 		       clk->name, rate);
 		return -EINVAL;
 	}
 }
 EXPORT_SYMBOL(clk_set_rate);
 /*
  * Clock definitions. The clock parents are set to respective
  * bridge and the clock framework makes sure that the clocks have
  * parents activated and are brought out of reset when in use.
  *
  * Clocks that have hw_ctrld = true are hw controlled, and the hw
  * can by itself turn these clocks on and off.
  * So in other words, we don't really have to care about them.
  */
 static struct clk amba_clk = {
 	.name	    = "AMBA",
 	.rate	    = 52000000, /* this varies! */
 	.hw_ctrld   = true,
 	.reset	    = false,
 	.lock       = __SPIN_LOCK_UNLOCKED(amba_clk.lock),
 };
 /*
  * These blocks are connected directly to the AMBA bus
  * with no bridge.
  */
 static struct clk cpu_clk = {
 	.name	    = "CPU",
 	.parent	    = &amba_clk,
 	.rate	    = 208000000, /* this varies! */
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_CPU_RESET_EN,
 	.set_rate   = clk_set_rate_cpuclk,
 	.get_rate   = clk_get_rate_cpuclk,
 	.round_rate = clk_round_rate_cpuclk,
 	.lock       = __SPIN_LOCK_UNLOCKED(cpu_clk.lock),
 };
 static struct clk nandif_clk = {
 	.name       = "NANDIF",
 	.parent	    = &amba_clk,
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_NANDIF_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_NANDIF_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(nandif_clk.lock),
 };
 static struct clk semi_clk = {
 	.name       = "SEMI",
 	.parent	    = &amba_clk,
 	.rate       = 0, /* FIXME */
 	/* It is not possible to reset SEMI */
 	.hw_ctrld   = false,
 	.reset	    = false,
 	.clk_val    = U300_SYSCON_SBCER_SEMI_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(semi_clk.lock),
 };
 #ifdef CONFIG_MACH_U300_BS335
 static struct clk isp_clk = {
 	.name	    = "ISP",
 	.parent	    = &amba_clk,
 	.rate	    = 0, /* FIXME */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_ISP_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_ISP_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(isp_clk.lock),
 };
 static struct clk cds_clk = {
 	.name	    = "CDS",
 	.parent	    = &amba_clk,
 	.rate	    = 0, /* FIXME */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_CDS_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_CDS_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(cds_clk.lock),
 };
 #endif
 static struct clk dma_clk = {
 	.name       = "DMA",
 	.parent	    = &amba_clk,
 	.rate       = 52000000, /* this varies! */
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_DMAC_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_DMAC_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(dma_clk.lock),
 };
 static struct clk aaif_clk = {
 	.name       = "AAIF",
 	.parent	    = &amba_clk,
 	.rate       = 52000000, /* this varies! */
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_AAIF_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_AAIF_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(aaif_clk.lock),
 };
 static struct clk apex_clk = {
 	.name       = "APEX",
 	.parent	    = &amba_clk,
 	.rate       = 0, /* FIXME */
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_APEX_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_APEX_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(apex_clk.lock),
 };
 static struct clk video_enc_clk = {
 	.name       = "VIDEO_ENC",
 	.parent	    = &amba_clk,
 	.rate       = 208000000, /* this varies! */
 	.hw_ctrld   = false,
 	.reset	    = false,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	/* This has XGAM in the name but refers to the video encoder */
 	.res_mask   = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(video_enc_clk.lock),
 };
 static struct clk xgam_clk = {
 	.name       = "XGAMCLK",
 	.parent	    = &amba_clk,
 	.rate       = 52000000, /* this varies! */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_XGAM_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_XGAM_CLK_EN,
 	.get_rate   = clk_get_rate_xgamclk,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(xgam_clk.lock),
 };
 /* This clock is used to activate the video encoder */
 static struct clk ahb_clk = {
 	.name	    = "AHB",
 	.parent	    = &amba_clk,
 	.rate	    = 52000000, /* this varies! */
 	.hw_ctrld   = false, /* This one is set to false due to HW bug */
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_AHB_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_AHB_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.get_rate   = clk_get_rate_ahb_clk,
 	.lock       = __SPIN_LOCK_UNLOCKED(ahb_clk.lock),
 };
 /*
  * Clocks on the AHB bridge
  */
 static struct clk ahb_subsys_clk = {
 	.name	    = "AHB_SUBSYS",
 	.parent	    = &amba_clk,
 	.rate	    = 52000000, /* this varies! */
 	.hw_ctrld   = true,
 	.reset	    = false,
 	.clk_val    = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.get_rate   = clk_get_rate_ahb_clk,
 	.lock       = __SPIN_LOCK_UNLOCKED(ahb_subsys_clk.lock),
 };
 static struct clk intcon_clk = {
 	.name	    = "INTCON",
 	.parent	    = &ahb_subsys_clk,
 	.rate	    = 52000000, /* this varies! */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_INTCON_RESET_EN,
 	/* INTCON can be reset but not clock-gated */
 	.lock       = __SPIN_LOCK_UNLOCKED(intcon_clk.lock),
 };
 static struct clk mspro_clk = {
 	.name       = "MSPRO",
 	.parent	    = &ahb_subsys_clk,
 	.rate       = 0, /* FIXME */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_MSPRO_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_MSPRO_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(mspro_clk.lock),
 };
 static struct clk emif_clk = {
 	.name	    = "EMIF",
 	.parent	    = &ahb_subsys_clk,
 	.rate	    = 104000000, /* this varies! */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
 	.res_mask   = U300_SYSCON_RRR_EMIF_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_EMIF_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.get_rate   = clk_get_rate_emif_clk,
 	.lock       = __SPIN_LOCK_UNLOCKED(emif_clk.lock),
 };
 /*
  * Clocks on the FAST bridge
  */
 static struct clk fast_clk = {
 	.name	    = "FAST_BRIDGE",
 	.parent	    = &amba_clk,
 	.rate	    = 13000000, /* this varies! */
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
 	.res_mask   = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
 	.clk_val    = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(fast_clk.lock),
 };
 static struct clk mmcsd_clk = {
 	.name       = "MCLK",
 	.parent	    = &fast_clk,
 	.rate       = 18900000, /* this varies! */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
 	.res_mask   = U300_SYSCON_RFR_MMC_RESET_ENABLE,
 	.clk_val    = U300_SYSCON_SBCER_MMC_CLK_EN,
 	.get_rate   = clk_get_rate_mclk,
 	.set_rate   = clk_set_rate_mclk,
 	.round_rate = clk_round_rate_mclk,
 	.disable    = syscon_clk_disable,
 	.enable     = syscon_clk_enable,
 	.lock       = __SPIN_LOCK_UNLOCKED(mmcsd_clk.lock),
 };
 static struct clk i2s0_clk = {
 	.name       = "i2s0",
 	.parent	    = &fast_clk,
 	.rate       = 26000000, /* this varies! */
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
 	.res_mask   = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
 	.clk_val    = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.get_rate   = clk_get_rate_i2s_i2c_spi,
 	.lock       = __SPIN_LOCK_UNLOCKED(i2s0_clk.lock),
 };
 static struct clk i2s1_clk = {
 	.name       = "i2s1",
 	.parent	    = &fast_clk,
 	.rate       = 26000000, /* this varies! */
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
 	.res_mask   = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
 	.clk_val    = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.get_rate   = clk_get_rate_i2s_i2c_spi,
 	.lock       = __SPIN_LOCK_UNLOCKED(i2s1_clk.lock),
 };
 static struct clk i2c0_clk = {
 	.name       = "I2C0",
 	.parent	    = &fast_clk,
 	.rate       = 26000000, /* this varies! */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
 	.res_mask   = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
 	.clk_val    = U300_SYSCON_SBCER_I2C0_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.get_rate   = clk_get_rate_i2s_i2c_spi,
 	.lock       = __SPIN_LOCK_UNLOCKED(i2c0_clk.lock),
 };
 static struct clk i2c1_clk = {
 	.name       = "I2C1",
 	.parent	    = &fast_clk,
 	.rate       = 26000000, /* this varies! */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
 	.res_mask   = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
 	.clk_val    = U300_SYSCON_SBCER_I2C1_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.get_rate   = clk_get_rate_i2s_i2c_spi,
 	.lock       = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock),
 };
 static struct clk spi_clk = {
 	.name       = "SPI",
 	.parent	    = &fast_clk,
 	.rate       = 26000000, /* this varies! */
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
 	.res_mask   = U300_SYSCON_RFR_SPI_RESET_ENABLE,
 	.clk_val    = U300_SYSCON_SBCER_SPI_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.get_rate   = clk_get_rate_i2s_i2c_spi,
 	.lock       = __SPIN_LOCK_UNLOCKED(spi_clk.lock),
 };
 #ifdef CONFIG_MACH_U300_BS335
 static struct clk uart1_clk = {
 	.name	    = "UART1",
 	.parent	    = &fast_clk,
 	.rate	    = 13000000,
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
 	.res_mask   = U300_SYSCON_RFR_UART1_RESET_ENABLE,
 	.clk_val    = U300_SYSCON_SBCER_UART1_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(uart1_clk.lock),
 };
 #endif
 /*
  * Clocks on the SLOW bridge
  */
 static struct clk slow_clk = {
 	.name	    = "SLOW_BRIDGE",
 	.parent	    = &amba_clk,
 	.rate	    = 13000000,
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(slow_clk.lock),
 };
 /* TODO: implement SYSCON clock? */
 static struct clk wdog_clk = {
 	.name	    = "WDOG",
 	.parent	    = &slow_clk,
 	.hw_ctrld   = false,
 	.rate	    = 32768,
 	.reset	    = false,
 	/* This is always on, cannot be enabled/disabled or reset */
 	.lock       = __SPIN_LOCK_UNLOCKED(wdog_clk.lock),
 };
 /* This one is hardwired to PLL13 */
 static struct clk uart_clk = {
 	.name	    = "UARTCLK",
 	.parent	    = &slow_clk,
 	.rate	    = 13000000,
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_UART_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_UART_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(uart_clk.lock),
 };
 static struct clk keypad_clk = {
 	.name       = "KEYPAD",
 	.parent	    = &slow_clk,
 	.rate       = 32768,
 	.hw_ctrld   = false,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_KEYPAD_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(keypad_clk.lock),
 };
 static struct clk gpio_clk = {
 	.name       = "GPIO",
 	.parent	    = &slow_clk,
 	.rate       = 13000000,
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_GPIO_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_GPIO_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(gpio_clk.lock),
 };
 static struct clk rtc_clk = {
 	.name	    = "RTC",
 	.parent	    = &slow_clk,
 	.rate	    = 32768,
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_RTC_RESET_EN,
 	/* This clock is always on, cannot be enabled/disabled */
 	.lock       = __SPIN_LOCK_UNLOCKED(rtc_clk.lock),
 };
 static struct clk bustr_clk = {
 	.name       = "BUSTR",
 	.parent	    = &slow_clk,
 	.rate       = 13000000,
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_BTR_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_BTR_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(bustr_clk.lock),
 };
 static struct clk evhist_clk = {
 	.name       = "EVHIST",
 	.parent	    = &slow_clk,
 	.rate       = 13000000,
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_EH_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_EH_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(evhist_clk.lock),
 };
 static struct clk timer_clk = {
 	.name       = "TIMER",
 	.parent	    = &slow_clk,
 	.rate       = 13000000,
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(timer_clk.lock),
 };
 static struct clk app_timer_clk = {
 	.name       = "TIMER_APP",
 	.parent	    = &slow_clk,
 	.rate       = 13000000,
 	.hw_ctrld   = true,
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_APP_TMR_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(app_timer_clk.lock),
 };
 #ifdef CONFIG_MACH_U300_BS335
 static struct clk ppm_clk = {
 	.name	    = "PPM",
 	.parent	    = &slow_clk,
 	.rate	    = 0, /* FIXME */
 	.hw_ctrld   = true, /* TODO: Look up if it is hw ctrld or not */
 	.reset	    = true,
 	.res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
 	.res_mask   = U300_SYSCON_RSR_PPM_RESET_EN,
 	.clk_val    = U300_SYSCON_SBCER_PPM_CLK_EN,
 	.enable     = syscon_clk_enable,
 	.disable    = syscon_clk_disable,
 	.lock       = __SPIN_LOCK_UNLOCKED(ppm_clk.lock),
 };
 #endif
+static struct clk dummy_apb_pclk;
 #define DEF_LOOKUP(devid, clkref)		\
 	{					\
 	.dev_id = devid,			\
 	.clk = clkref,				\
 	}
 /*
  * Here we only define clocks that are meaningful to
  * look up through clockdevice.
  */
 static struct clk_lookup lookups[] = {
+	{
+		.con_id = "apb_pclk",
+		.clk = &dummy_apb_pclk,
+	},
 	/* Connected directly to the AMBA bus */
 	DEF_LOOKUP("amba",      &amba_clk),
 	DEF_LOOKUP("cpu",       &cpu_clk),
 	DEF_LOOKUP("fsmc",      &nandif_clk),
 	DEF_LOOKUP("semi",      &semi_clk),
 #ifdef CONFIG_MACH_U300_BS335
 	DEF_LOOKUP("isp",       &isp_clk),
 	DEF_LOOKUP("cds",       &cds_clk),
 #endif
 	DEF_LOOKUP("dma",       &dma_clk),
 	DEF_LOOKUP("msl",       &aaif_clk),
 	DEF_LOOKUP("apex",      &apex_clk),
 	DEF_LOOKUP("video_enc", &video_enc_clk),
 	DEF_LOOKUP("xgam",      &xgam_clk),
 	DEF_LOOKUP("ahb",       &ahb_clk),
 	/* AHB bridge clocks */
 	DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk),
 	DEF_LOOKUP("intcon",    &intcon_clk),
 	DEF_LOOKUP("mspro",     &mspro_clk),
 	DEF_LOOKUP("pl172",     &emif_clk),
 	/* FAST bridge clocks */
 	DEF_LOOKUP("fast",      &fast_clk),
 	DEF_LOOKUP("mmci",      &mmcsd_clk),
 	/*
 	 * The .0 and .1 identifiers on these comes from the platform device
 	 * .id field and are assigned when the platform devices are registered.
 	 */
 	DEF_LOOKUP("i2s.0",     &i2s0_clk),
 	DEF_LOOKUP("i2s.1",     &i2s1_clk),
 	DEF_LOOKUP("stu300.0",  &i2c0_clk),
 	DEF_LOOKUP("stu300.1",  &i2c1_clk),
 	DEF_LOOKUP("pl022",     &spi_clk),
 #ifdef CONFIG_MACH_U300_BS335
 	DEF_LOOKUP("uart1",     &uart1_clk),
 #endif
 	/* SLOW bridge clocks */
 	DEF_LOOKUP("slow",      &slow_clk),
 	DEF_LOOKUP("coh901327_wdog",      &wdog_clk),
 	DEF_LOOKUP("uart0",     &uart_clk),
 	DEF_LOOKUP("apptimer",  &app_timer_clk),
 	DEF_LOOKUP("coh901461-keypad",    &keypad_clk),
 	DEF_LOOKUP("u300-gpio", &gpio_clk),
 	DEF_LOOKUP("rtc-coh901331",      &rtc_clk),
 	DEF_LOOKUP("bustr",     &bustr_clk),
 	DEF_LOOKUP("evhist",    &evhist_clk),
 	DEF_LOOKUP("timer",     &timer_clk),
 #ifdef CONFIG_MACH_U300_BS335
 	DEF_LOOKUP("ppm",       &ppm_clk),
 #endif
 };
 static void __init clk_register(void)
 {
 	/* Register the lookups */
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 }
 /*
  * These are the clocks for cells registered as primecell drivers
  * on the AMBA bus. These must be on during AMBA device registration
  * since the bus probe will attempt to read magic configuration
  * registers for these devices. If they are deactivated these probes
  * will fail.
  *
  *
  * Please note that on emif, both RAM and NAND is connected in dual
  * RAM phones. On single RAM phones, ram is on semi and NAND on emif.
  *
  */
 void u300_clock_primecells(void)
 {
 	clk_enable(&intcon_clk);
 	clk_enable(&uart_clk);
 #ifdef CONFIG_MACH_U300_BS335
 	clk_enable(&uart1_clk);
 #endif
 	clk_enable(&spi_clk);
 	clk_enable(&mmcsd_clk);
 }
 EXPORT_SYMBOL(u300_clock_primecells);
 void u300_unclock_primecells(void)
 {
 	clk_disable(&intcon_clk);
 	clk_disable(&uart_clk);
 #ifdef CONFIG_MACH_U300_BS335
 	clk_disable(&uart1_clk);
 #endif
 	clk_disable(&spi_clk);
 	clk_disable(&mmcsd_clk);
 }
 EXPORT_SYMBOL(u300_unclock_primecells);
 /*
  * The interrupt controller is enabled before the clock API is registered.
  */
 void u300_enable_intcon_clock(void)
 {
 	clk_enable(&intcon_clk);
 }
 EXPORT_SYMBOL(u300_enable_intcon_clock);
 /*
  * The timer is enabled before the clock API is registered.
  */
 void u300_enable_timer_clock(void)
 {
 	clk_enable(&app_timer_clk);
 }
 EXPORT_SYMBOL(u300_enable_timer_clock);
 #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
 /*
  * The following makes it possible to view the status (especially
  * reference count and reset status) for the clocks in the platform
  * by looking into the special file <debugfs>/u300_clocks
  */
 /* A list of all clocks in the platform */
 static struct clk *clks[] = {
 	/* Top node clock for the AMBA bus */
 	&amba_clk,
 	/* Connected directly to the AMBA bus */
 	&cpu_clk,
 	&nandif_clk,
 	&semi_clk,
 #ifdef CONFIG_MACH_U300_BS335
 	&isp_clk,
 	&cds_clk,
 #endif
 	&dma_clk,
 	&aaif_clk,
 	&apex_clk,
 	&video_enc_clk,
 	&xgam_clk,
 	&ahb_clk,
 	/* AHB bridge clocks */
 	&ahb_subsys_clk,
 	&intcon_clk,
 	&mspro_clk,
 	&emif_clk,
 	/* FAST bridge clocks */
 	&fast_clk,
 	&mmcsd_clk,
 	&i2s0_clk,
 	&i2s1_clk,
 	&i2c0_clk,
 	&i2c1_clk,
 	&spi_clk,
 #ifdef CONFIG_MACH_U300_BS335
 	&uart1_clk,
 #endif
 	/* SLOW bridge clocks */
 	&slow_clk,
 	&wdog_clk,
 	&uart_clk,
 	&app_timer_clk,
 	&keypad_clk,
 	&gpio_clk,
 	&rtc_clk,
 	&bustr_clk,
 	&evhist_clk,
 	&timer_clk,
 #ifdef CONFIG_MACH_U300_BS335
 	&ppm_clk,
 #endif
 };
 static int u300_clocks_show(struct seq_file *s, void *data)
 {
 	struct clk *clk;
 	int i;
 	seq_printf(s, "CLOCK           DEVICE          RESET STATE\t" \
 		   "ACTIVE\tUSERS\tHW CTRL FREQ\n");
 	seq_printf(s, "---------------------------------------------" \
 		   "-----------------------------------------\n");
 	for (i = 0; i < ARRAY_SIZE(clks); i++) {
 		clk = clks[i];
 		if (clk != ERR_PTR(-ENOENT)) {
 			/* Format clock and device name nicely */
 			char cdp[33];
 			int chars;
 			chars = snprintf(&cdp[0], 17, "%s", clk->name);
 			while (chars < 16) {
 				cdp[chars] = ' ';
 				chars++;
 			}
 			chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
 					 dev_name(clk->dev) : "N/A");
 			while (chars < 16) {
 				cdp[chars+16] = ' ';
 				chars++;
 			}
 			cdp[32] = '\0';
 			if (clk->get_rate)
 				seq_printf(s,
 					   "%s%s\t%s\t%d\t%s\t%lu Hz\n",
 					   &cdp[0],
 					   clk->reset ?
 					   "ASSERTED" : "RELEASED",
 					   clk->usecount ? "ON" : "OFF",
 					   clk->usecount,
 					   clk->hw_ctrld  ? "YES" : "NO ",
 					   clk->get_rate(clk));
 			else
 				seq_printf(s,
 					   "%s%s\t%s\t%d\t%s\t" \
 					   "(unknown rate)\n",
 					   &cdp[0],
 					   clk->reset ?
 					   "ASSERTED" : "RELEASED",
 					   clk->usecount ? "ON" : "OFF",
 					   clk->usecount,
 					   clk->hw_ctrld  ? "YES" : "NO ");
 		}
 	}
 	return 0;
 }
 static int u300_clocks_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, u300_clocks_show, NULL);
 }
 static const struct file_operations u300_clocks_operations = {
 	.open		= u300_clocks_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 };
 static int __init init_clk_read_debugfs(void)
 {
 	/* Expose a simple debugfs interface to view all clocks */
 	(void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
 				   NULL, NULL,
 				   &u300_clocks_operations);
 	return 0;
 }
 /*
  * This needs to come in after the core_initcall() for the
  * overall clocks, because debugfs is not available until
  * the subsystems come up.
  */
 module_init(init_clk_read_debugfs);
 #endif
 static int __init u300_clock_init(void)
 {
 	u16 val;
 	/*
 	 * FIXME: shall all this powermanagement stuff really live here???
 	 */
 	/* Set system to run at PLL208, max performance, a known state. */
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
 	/* Wait for the PLL208 to lock if not locked in yet */
 	while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
 		 U300_SYSCON_CSR_PLL208_LOCK_IND));
 	/* Power management enable */
 	val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
 	val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
 	writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
 	clk_register();
 	/*
 	 * Some of these may be on when we boot the system so make sure they
 	 * are turned OFF.
 	 */
 	syscon_block_reset_enable(&timer_clk);
 	timer_clk.disable(&timer_clk);
 	/*
 	 * These shall be turned on by default when we boot the system
 	 * so make sure they are ON. (Adding CPU here is a bit too much.)
 	 * These clocks will be claimed by drivers later.
 	 */
 	syscon_block_reset_disable(&semi_clk);
 	syscon_block_reset_disable(&emif_clk);
 	semi_clk.enable(&semi_clk);
 	emif_clk.enable(&emif_clk);
 	return 0;
 }
 /* initialize clocking early to be available later in the boot */
 core_initcall(u300_clock_init);

arch/arm/mach-ux500/clock.c

Diff comments View file @ 3126c7b

 /*
  *  Copyright (C) 2009 ST-Ericsson
  *  Copyright (C) 2009 STMicroelectronics
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <asm/clkdev.h>
 #include <plat/mtu.h>
 #include <mach/hardware.h>
 #include "clock.h"
 #define PRCC_PCKEN		0x00
 #define PRCC_PCKDIS		0x04
 #define PRCC_KCKEN		0x08
 #define PRCC_KCKDIS		0x0C
 #define PRCM_YYCLKEN0_MGT_SET	0x510
 #define PRCM_YYCLKEN1_MGT_SET	0x514
 #define PRCM_YYCLKEN0_MGT_CLR	0x518
 #define PRCM_YYCLKEN1_MGT_CLR	0x51C
 #define PRCM_YYCLKEN0_MGT_VAL	0x520
 #define PRCM_YYCLKEN1_MGT_VAL	0x524
 #define PRCM_SVAMMDSPCLK_MGT	0x008
 #define PRCM_SIAMMDSPCLK_MGT	0x00C
 #define PRCM_SGACLK_MGT		0x014
 #define PRCM_UARTCLK_MGT	0x018
 #define PRCM_MSP02CLK_MGT	0x01C
 #define PRCM_MSP1CLK_MGT	0x288
 #define PRCM_I2CCLK_MGT		0x020
 #define PRCM_SDMMCCLK_MGT	0x024
 #define PRCM_SLIMCLK_MGT	0x028
 #define PRCM_PER1CLK_MGT	0x02C
 #define PRCM_PER2CLK_MGT	0x030
 #define PRCM_PER3CLK_MGT	0x034
 #define PRCM_PER5CLK_MGT	0x038
 #define PRCM_PER6CLK_MGT	0x03C
 #define PRCM_PER7CLK_MGT	0x040
 #define PRCM_LCDCLK_MGT		0x044
 #define PRCM_BMLCLK_MGT		0x04C
 #define PRCM_HSITXCLK_MGT	0x050
 #define PRCM_HSIRXCLK_MGT	0x054
 #define PRCM_HDMICLK_MGT	0x058
 #define PRCM_APEATCLK_MGT	0x05C
 #define PRCM_APETRACECLK_MGT	0x060
 #define PRCM_MCDECLK_MGT	0x064
 #define PRCM_IPI2CCLK_MGT	0x068
 #define PRCM_DSIALTCLK_MGT	0x06C
 #define PRCM_DMACLK_MGT		0x074
 #define PRCM_B2R2CLK_MGT	0x078
 #define PRCM_TVCLK_MGT		0x07C
 #define PRCM_TCR		0x1C8
 #define PRCM_TCR_STOPPED	(1 << 16)
 #define PRCM_TCR_DOZE_MODE	(1 << 17)
 #define PRCM_UNIPROCLK_MGT	0x278
 #define PRCM_SSPCLK_MGT		0x280
 #define PRCM_RNGCLK_MGT		0x284
 #define PRCM_UICCCLK_MGT	0x27C
 #define PRCM_MGT_ENABLE		(1 << 8)
 static DEFINE_SPINLOCK(clocks_lock);
 static void __clk_enable(struct clk *clk)
 {
 	if (clk->enabled++ == 0) {
 		if (clk->parent_cluster)
 			__clk_enable(clk->parent_cluster);
 		if (clk->parent_periph)
 			__clk_enable(clk->parent_periph);
 		if (clk->ops && clk->ops->enable)
 			clk->ops->enable(clk);
 	}
 }
 int clk_enable(struct clk *clk)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&clocks_lock, flags);
 	__clk_enable(clk);
 	spin_unlock_irqrestore(&clocks_lock, flags);
 	return 0;
 }
 EXPORT_SYMBOL(clk_enable);
 static void __clk_disable(struct clk *clk)
 {
 	if (--clk->enabled == 0) {
 		if (clk->ops && clk->ops->disable)
 			clk->ops->disable(clk);
 		if (clk->parent_periph)
 			__clk_disable(clk->parent_periph);
 		if (clk->parent_cluster)
 			__clk_disable(clk->parent_cluster);
 	}
 }
 void clk_disable(struct clk *clk)
 {
 	unsigned long flags;
 	WARN_ON(!clk->enabled);
 	spin_lock_irqsave(&clocks_lock, flags);
 	__clk_disable(clk);
 	spin_unlock_irqrestore(&clocks_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 /*
  * The MTU has a separate, rather complex muxing setup
  * with alternative parents (peripheral cluster or
  * ULP or fixed 32768 Hz) depending on settings
  */
 static unsigned long clk_mtu_get_rate(struct clk *clk)
 {
 	void __iomem *addr = __io_address(UX500_PRCMU_BASE)
 		+ PRCM_TCR;
 	u32 tcr = readl(addr);
 	int mtu = (int) clk->data;
 	/*
 	 * One of these is selected eventually
 	 * TODO: Replace the constant with a reference
 	 * to the ULP source once this is modeled.
 	 */
 	unsigned long clk32k = 32768;
 	unsigned long mturate;
 	unsigned long retclk;
 	/* Get the rate from the parent as a default */
 	if (clk->parent_periph)
 		mturate = clk_get_rate(clk->parent_periph);
 	else if (clk->parent_cluster)
 		mturate = clk_get_rate(clk->parent_cluster);
 	else
 		/* We need to be connected SOMEWHERE */
 		BUG();
 	/*
 	 * Are we in doze mode?
 	 * In this mode the parent peripheral or the fixed 32768 Hz
 	 * clock is fed into the block.
 	 */
 	if (!(tcr & PRCM_TCR_DOZE_MODE)) {
 		/*
 		 * Here we're using the clock input from the APE ULP
 		 * clock domain. But first: are the timers stopped?
 		 */
 		if (tcr & PRCM_TCR_STOPPED) {
 			clk32k = 0;
 			mturate = 0;
 		} else {
 			/* Else default mode: 0 and 2.4 MHz */
 			clk32k = 0;
 			if (cpu_is_u5500())
 				/* DB5500 divides by 8 */
 				mturate /= 8;
 			else if (cpu_is_u8500ed()) {
 				/*
 				 * This clocking setting must not be used
 				 * in the ED chip, it is simply not
 				 * connected anywhere!
 				 */
 				mturate = 0;
 				BUG();
 			} else
 				/*
 				 * In this mode the ulp38m4 clock is divided
 				 * by a factor 16, on the DB8500 typically
 				 * 38400000 / 16 ~ 2.4 MHz.
 				 * TODO: Replace the constant with a reference
 				 * to the ULP source once this is modeled.
 				 */
 				mturate = 38400000 / 16;
 		}
 	}
 	/* Return the clock selected for this MTU */
 	if (tcr & (1 << mtu))
 		retclk = clk32k;
 	else
 		retclk = mturate;
 	pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
 	return retclk;
 }
 unsigned long clk_get_rate(struct clk *clk)
 {
 	unsigned long rate;
 	/*
 	 * If there is a custom getrate callback for this clock,
 	 * it will take precedence.
 	 */
 	if (clk->get_rate)
 		return clk->get_rate(clk);
 	if (clk->ops && clk->ops->get_rate)
 		return clk->ops->get_rate(clk);
 	rate = clk->rate;
 	if (!rate) {
 		if (clk->parent_periph)
 			rate = clk_get_rate(clk->parent_periph);
 		else if (clk->parent_cluster)
 			rate = clk_get_rate(clk->parent_cluster);
 	}
 	return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
 	/*TODO*/
 	return rate;
 }
 EXPORT_SYMBOL(clk_round_rate);
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	clk->rate = rate;
 	return 0;
 }
 EXPORT_SYMBOL(clk_set_rate);
 static void clk_prcmu_enable(struct clk *clk)
 {
 	void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
 				   + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
 	writel(1 << clk->prcmu_cg_bit, cg_set_reg);
 }
 static void clk_prcmu_disable(struct clk *clk)
 {
 	void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
 				   + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
 	writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
 }
 /* ED doesn't have the combined set/clr registers */
 static void clk_prcmu_ed_enable(struct clk *clk)
 {
 	void __iomem *addr = __io_address(U8500_PRCMU_BASE)
 			     + clk->prcmu_cg_mgt;
 	writel(readl(addr) | PRCM_MGT_ENABLE, addr);
 }
 static void clk_prcmu_ed_disable(struct clk *clk)
 {
 	void __iomem *addr = __io_address(U8500_PRCMU_BASE)
 			     + clk->prcmu_cg_mgt;
 	writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
 }
 static struct clkops clk_prcmu_ops = {
 	.enable = clk_prcmu_enable,
 	.disable = clk_prcmu_disable,
 };
 static unsigned int clkrst_base[] = {
 	[1] = U8500_CLKRST1_BASE,
 	[2] = U8500_CLKRST2_BASE,
 	[3] = U8500_CLKRST3_BASE,
 	[5] = U8500_CLKRST5_BASE,
 	[6] = U8500_CLKRST6_BASE,
 	[7] = U8500_CLKRST7_BASE_ED,
 };
 static void clk_prcc_enable(struct clk *clk)
 {
 	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
 	if (clk->prcc_kernel != -1)
 		writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
 	if (clk->prcc_bus != -1)
 		writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
 }
 static void clk_prcc_disable(struct clk *clk)
 {
 	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
 	if (clk->prcc_bus != -1)
 		writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
 	if (clk->prcc_kernel != -1)
 		writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
 }
 static struct clkops clk_prcc_ops = {
 	.enable = clk_prcc_enable,
 	.disable = clk_prcc_disable,
 };
 static struct clk clk_32khz = {
 	.rate = 32000,
 };
 /*
  * PRCMU level clock gating
  */
 /* Bank 0 */
 static DEFINE_PRCMU_CLK(svaclk,		0x0, 2, SVAMMDSPCLK);
 static DEFINE_PRCMU_CLK(siaclk,		0x0, 3, SIAMMDSPCLK);
 static DEFINE_PRCMU_CLK(sgaclk,		0x0, 4, SGACLK);
 static DEFINE_PRCMU_CLK_RATE(uartclk,	0x0, 5, UARTCLK, 38400000);
 static DEFINE_PRCMU_CLK(msp02clk,	0x0, 6, MSP02CLK);
 static DEFINE_PRCMU_CLK(msp1clk,	0x0, 7, MSP1CLK); /* v1 */
 static DEFINE_PRCMU_CLK_RATE(i2cclk,	0x0, 8, I2CCLK, 48000000);
 static DEFINE_PRCMU_CLK_RATE(sdmmcclk,	0x0, 9, SDMMCCLK, 50000000);
 static DEFINE_PRCMU_CLK(slimclk,	0x0, 10, SLIMCLK);
 static DEFINE_PRCMU_CLK(per1clk,	0x0, 11, PER1CLK);
 static DEFINE_PRCMU_CLK(per2clk,	0x0, 12, PER2CLK);
 static DEFINE_PRCMU_CLK(per3clk,	0x0, 13, PER3CLK);
 static DEFINE_PRCMU_CLK(per5clk,	0x0, 14, PER5CLK);
 static DEFINE_PRCMU_CLK_RATE(per6clk,	0x0, 15, PER6CLK, 133330000);
 static DEFINE_PRCMU_CLK_RATE(per7clk,	0x0, 16, PER7CLK, 100000000);
 static DEFINE_PRCMU_CLK(lcdclk,		0x0, 17, LCDCLK);
 static DEFINE_PRCMU_CLK(bmlclk,		0x0, 18, BMLCLK);
 static DEFINE_PRCMU_CLK(hsitxclk,	0x0, 19, HSITXCLK);
 static DEFINE_PRCMU_CLK(hsirxclk,	0x0, 20, HSIRXCLK);
 static DEFINE_PRCMU_CLK(hdmiclk,	0x0, 21, HDMICLK);
 static DEFINE_PRCMU_CLK(apeatclk,	0x0, 22, APEATCLK);
 static DEFINE_PRCMU_CLK(apetraceclk,	0x0, 23, APETRACECLK);
 static DEFINE_PRCMU_CLK(mcdeclk,	0x0, 24, MCDECLK);
 static DEFINE_PRCMU_CLK(ipi2clk,	0x0, 25, IPI2CCLK);
 static DEFINE_PRCMU_CLK(dsialtclk,	0x0, 26, DSIALTCLK); /* v1 */
 static DEFINE_PRCMU_CLK(dmaclk,		0x0, 27, DMACLK);
 static DEFINE_PRCMU_CLK(b2r2clk,	0x0, 28, B2R2CLK);
 static DEFINE_PRCMU_CLK(tvclk,		0x0, 29, TVCLK);
 static DEFINE_PRCMU_CLK(uniproclk,	0x0, 30, UNIPROCLK); /* v1 */
 static DEFINE_PRCMU_CLK_RATE(sspclk,	0x0, 31, SSPCLK, 48000000); /* v1 */
 /* Bank 1 */
 static DEFINE_PRCMU_CLK(rngclk,		0x4, 0, RNGCLK); /* v1 */
 static DEFINE_PRCMU_CLK(uiccclk,	0x4, 1, UICCCLK); /* v1 */
 /*
  * PRCC level clock gating
  * Format: per#, clk, PCKEN bit, KCKEN bit, parent
  */
 /* Peripheral Cluster #1 */
 static DEFINE_PRCC_CLK(1, i2c4, 	10, 9, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, gpio0,	9, -1, NULL);
 static DEFINE_PRCC_CLK(1, slimbus0, 	8,  8, &clk_slimclk);
 static DEFINE_PRCC_CLK(1, spi3_ed, 	7,  7, NULL);
 static DEFINE_PRCC_CLK(1, spi3_v1, 	7, -1, NULL);
 static DEFINE_PRCC_CLK(1, i2c2, 	6,  6, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, sdi0,		5,  5, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(1, msp1_ed, 	4,  4, &clk_msp02clk);
 static DEFINE_PRCC_CLK(1, msp1_v1, 	4,  4, &clk_msp1clk);
 static DEFINE_PRCC_CLK(1, msp0, 	3,  3, &clk_msp02clk);
 static DEFINE_PRCC_CLK(1, i2c1, 	2,  2, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, uart1, 	1,  1, &clk_uartclk);
 static DEFINE_PRCC_CLK(1, uart0, 	0,  0, &clk_uartclk);
 /* Peripheral Cluster #2 */
 static DEFINE_PRCC_CLK(2, gpio1_ed,	12, -1, NULL);
 static DEFINE_PRCC_CLK(2, ssitx_ed, 	11, -1, NULL);
 static DEFINE_PRCC_CLK(2, ssirx_ed, 	10, -1, NULL);
 static DEFINE_PRCC_CLK(2, spi0_ed, 	 9, -1, NULL);
 static DEFINE_PRCC_CLK(2, sdi3_ed, 	 8,  6, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, sdi1_ed, 	 7,  5, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, msp2_ed, 	 6,  4, &clk_msp02clk);
 static DEFINE_PRCC_CLK(2, sdi4_ed, 	 4,  2, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, pwl_ed,	 3,  1, NULL);
 static DEFINE_PRCC_CLK(2, spi1_ed, 	 2, -1, NULL);
 static DEFINE_PRCC_CLK(2, spi2_ed, 	 1, -1, NULL);
 static DEFINE_PRCC_CLK(2, i2c3_ed, 	 0,  0, &clk_i2cclk);
 static DEFINE_PRCC_CLK(2, gpio1_v1,	11, -1, NULL);
 static DEFINE_PRCC_CLK(2, ssitx_v1, 	10,  7, NULL);
 static DEFINE_PRCC_CLK(2, ssirx_v1, 	 9,  6, NULL);
 static DEFINE_PRCC_CLK(2, spi0_v1, 	 8, -1, NULL);
 static DEFINE_PRCC_CLK(2, sdi3_v1, 	 7,  5, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, sdi1_v1, 	 6,  4, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, msp2_v1, 	 5,  3, &clk_msp02clk);
 static DEFINE_PRCC_CLK(2, sdi4_v1, 	 4,  2, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, pwl_v1,	 3,  1, NULL);
 static DEFINE_PRCC_CLK(2, spi1_v1, 	 2, -1, NULL);
 static DEFINE_PRCC_CLK(2, spi2_v1, 	 1, -1, NULL);
 static DEFINE_PRCC_CLK(2, i2c3_v1, 	 0,  0, &clk_i2cclk);
 /* Peripheral Cluster #3 */
 static DEFINE_PRCC_CLK(3, gpio2, 	8, -1, NULL);
 static DEFINE_PRCC_CLK(3, sdi5, 	7,  7, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(3, uart2, 	6,  6, &clk_uartclk);
 static DEFINE_PRCC_CLK(3, ske, 		5,  5, &clk_32khz);
 static DEFINE_PRCC_CLK(3, sdi2, 	4,  4, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(3, i2c0, 	3,  3, &clk_i2cclk);
 static DEFINE_PRCC_CLK(3, ssp1_ed, 	2,  2, &clk_i2cclk);
 static DEFINE_PRCC_CLK(3, ssp0_ed, 	1,  1, &clk_i2cclk);
 static DEFINE_PRCC_CLK(3, ssp1_v1, 	2,  2, &clk_sspclk);
 static DEFINE_PRCC_CLK(3, ssp0_v1, 	1,  1, &clk_sspclk);
 static DEFINE_PRCC_CLK(3, fsmc, 	0, -1, NULL);
 /* Peripheral Cluster #4 is in the always on domain */
 /* Peripheral Cluster #5 */
 static DEFINE_PRCC_CLK(5, gpio3, 	1, -1, NULL);
 static DEFINE_PRCC_CLK(5, usb_ed, 	0,  0, &clk_i2cclk);
 static DEFINE_PRCC_CLK(5, usb_v1, 	0,  0, NULL);
 /* Peripheral Cluster #6 */
 /* MTU ID in data */
 static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
 static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
 static DEFINE_PRCC_CLK(6, cfgreg_v1, 	6,  6, NULL);
 static DEFINE_PRCC_CLK(6, dmc_ed, 	6,  6, NULL);
 static DEFINE_PRCC_CLK(6, hash1, 	5, -1, NULL);
 static DEFINE_PRCC_CLK(6, unipro_v1, 	4,  1, &clk_uniproclk);
 static DEFINE_PRCC_CLK(6, cryp1_ed, 	4, -1, NULL);
 static DEFINE_PRCC_CLK(6, pka, 		3, -1, NULL);
 static DEFINE_PRCC_CLK(6, hash0, 	2, -1, NULL);
 static DEFINE_PRCC_CLK(6, cryp0, 	1, -1, NULL);
 static DEFINE_PRCC_CLK(6, rng_ed, 	0,  0, &clk_i2cclk);
 static DEFINE_PRCC_CLK(6, rng_v1, 	0,  0, &clk_rngclk);
 /* Peripheral Cluster #7 */
 static DEFINE_PRCC_CLK(7, tzpc0_ed, 	4, -1, NULL);
 /* MTU ID in data */
 static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
 static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
 static DEFINE_PRCC_CLK(7, wdg_ed, 	1, -1, NULL);
 static DEFINE_PRCC_CLK(7, cfgreg_ed, 	0, -1, NULL);
+static struct clk clk_dummy_apb_pclk;
 static struct clk_lookup u8500_common_clks[] = {
+	CLK(dummy_apb_pclk, NULL,	"apb_pclk"),
 	/* Peripheral Cluster #1 */
 	CLK(gpio0,	"gpio.0",	NULL),
 	CLK(gpio0,	"gpio.1",	NULL),
 	CLK(slimbus0,	"slimbus0",	NULL),
 	CLK(i2c2,	"nmk-i2c.2",	NULL),
 	CLK(sdi0,	"sdi0",		NULL),
 	CLK(msp0,	"msp0",		NULL),
 	CLK(i2c1,	"nmk-i2c.1",	NULL),
 	CLK(uart1,	"uart1",	NULL),
 	CLK(uart0,	"uart0",	NULL),
 	/* Peripheral Cluster #3 */
 	CLK(gpio2,	"gpio.2",	NULL),
 	CLK(gpio2,	"gpio.3",	NULL),
 	CLK(gpio2,	"gpio.4",	NULL),
 	CLK(gpio2,	"gpio.5",	NULL),
 	CLK(sdi5,	"sdi5",		NULL),
 	CLK(uart2,	"uart2",	NULL),
 	CLK(ske,	"ske",		NULL),
 	CLK(sdi2,	"sdi2",		NULL),
 	CLK(i2c0,	"nmk-i2c.0",	NULL),
 	CLK(fsmc,	"fsmc",		NULL),
 	/* Peripheral Cluster #5 */
 	CLK(gpio3,	"gpio.8",	NULL),
 	/* Peripheral Cluster #6 */
 	CLK(hash1,	"hash1",	NULL),
 	CLK(pka,	"pka",		NULL),
 	CLK(hash0,	"hash0",	NULL),
 	CLK(cryp0,	"cryp0",	NULL),
 	/* PRCMU level clock gating */
 	/* Bank 0 */
 	CLK(svaclk,	"sva",		NULL),
 	CLK(siaclk,	"sia",		NULL),
 	CLK(sgaclk,	"sga",		NULL),
 	CLK(slimclk,	"slim",		NULL),
 	CLK(lcdclk,	"lcd",		NULL),
 	CLK(bmlclk,	"bml",		NULL),
 	CLK(hsitxclk,	"stm-hsi.0",	NULL),
 	CLK(hsirxclk,	"stm-hsi.1",	NULL),
 	CLK(hdmiclk,	"hdmi",		NULL),
 	CLK(apeatclk,	"apeat",	NULL),
 	CLK(apetraceclk,	"apetrace",	NULL),
 	CLK(mcdeclk,	"mcde",		NULL),
 	CLK(ipi2clk,	"ipi2",		NULL),
 	CLK(dmaclk,	"dma40.0",	NULL),
 	CLK(b2r2clk,	"b2r2",		NULL),
 	CLK(tvclk,	"tv",		NULL),
 };
 static struct clk_lookup u8500_ed_clks[] = {
 	/* Peripheral Cluster #1 */
 	CLK(spi3_ed,	"spi3",		NULL),
 	CLK(msp1_ed,	"msp1",		NULL),
 	/* Peripheral Cluster #2 */
 	CLK(gpio1_ed,	"gpio.6",	NULL),
 	CLK(gpio1_ed,	"gpio.7",	NULL),
 	CLK(ssitx_ed,	"ssitx",	NULL),
 	CLK(ssirx_ed,	"ssirx",	NULL),
 	CLK(spi0_ed,	"spi0",		NULL),
 	CLK(sdi3_ed,	"sdi3",		NULL),
 	CLK(sdi1_ed,	"sdi1",		NULL),
 	CLK(msp2_ed,	"msp2",		NULL),
 	CLK(sdi4_ed,	"sdi4",		NULL),
 	CLK(pwl_ed,	"pwl",		NULL),
 	CLK(spi1_ed,	"spi1",		NULL),
 	CLK(spi2_ed,	"spi2",		NULL),
 	CLK(i2c3_ed,	"nmk-i2c.3",	NULL),
 	/* Peripheral Cluster #3 */
 	CLK(ssp1_ed,	"ssp1",		NULL),
 	CLK(ssp0_ed,	"ssp0",		NULL),
 	/* Peripheral Cluster #5 */
 	CLK(usb_ed,	"musb_hdrc.0",	"usb"),
 	/* Peripheral Cluster #6 */
 	CLK(dmc_ed,	"dmc",		NULL),
 	CLK(cryp1_ed,	"cryp1",	NULL),
 	CLK(rng_ed,	"rng",		NULL),
 	/* Peripheral Cluster #7 */
 	CLK(tzpc0_ed,	"tzpc0",	NULL),
 	CLK(mtu1_ed,	"mtu1",		NULL),
 	CLK(mtu0_ed,	"mtu0",		NULL),
 	CLK(wdg_ed,	"wdg",		NULL),
 	CLK(cfgreg_ed,	"cfgreg",	NULL),
 };
 static struct clk_lookup u8500_v1_clks[] = {
 	/* Peripheral Cluster #1 */
 	CLK(i2c4,	"nmk-i2c.4", 	NULL),
 	CLK(spi3_v1,	"spi3",		NULL),
 	CLK(msp1_v1,	"msp1",		NULL),
 	/* Peripheral Cluster #2 */
 	CLK(gpio1_v1,	"gpio.6",	NULL),
 	CLK(gpio1_v1,	"gpio.7",	NULL),
 	CLK(ssitx_v1,	"ssitx",	NULL),
 	CLK(ssirx_v1,	"ssirx",	NULL),
 	CLK(spi0_v1,	"spi0",		NULL),
 	CLK(sdi3_v1,	"sdi3",		NULL),
 	CLK(sdi1_v1,	"sdi1",		NULL),
 	CLK(msp2_v1,	"msp2",		NULL),
 	CLK(sdi4_v1,	"sdi4",		NULL),
 	CLK(pwl_v1,	"pwl",		NULL),
 	CLK(spi1_v1,	"spi1",		NULL),
 	CLK(spi2_v1,	"spi2",		NULL),
 	CLK(i2c3_v1,	"nmk-i2c.3",	NULL),
 	/* Peripheral Cluster #3 */
 	CLK(ssp1_v1,	"ssp1",		NULL),
 	CLK(ssp0_v1,	"ssp0",		NULL),
 	/* Peripheral Cluster #5 */
 	CLK(usb_v1,	"musb_hdrc.0",	"usb"),
 	/* Peripheral Cluster #6 */
 	CLK(mtu1_v1,	"mtu1",		NULL),
 	CLK(mtu0_v1,	"mtu0",		NULL),
 	CLK(cfgreg_v1,	"cfgreg",	NULL),
 	CLK(hash1,	"hash1",	NULL),
 	CLK(unipro_v1,	"unipro",	NULL),
 	CLK(rng_v1,	"rng",		NULL),
 	/* PRCMU level clock gating */
 	/* Bank 0 */
 	CLK(uniproclk,	"uniproclk",	NULL),
 	CLK(dsialtclk,	"dsialt",	NULL),
 	/* Bank 1 */
 	CLK(rngclk,	"rng",		NULL),
 	CLK(uiccclk,	"uicc",		NULL),
 };
 int __init clk_init(void)
 {
 	if (cpu_is_u8500ed()) {
 		clk_prcmu_ops.enable = clk_prcmu_ed_enable;
 		clk_prcmu_ops.disable = clk_prcmu_ed_disable;
 		clk_per6clk.rate = 100000000;
 	} else if (cpu_is_u5500()) {
 		/* Clock tree for U5500 not implemented yet */
 		clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
 		clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
 		clk_per6clk.rate = 26000000;
 	}
 	clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
 	if (cpu_is_u8500ed())
 		clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
 	else
 		clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
 	return 0;
 }

arch/arm/mach-versatile/core.c

Diff comments View file @ 3126c7b

 /*
  *  linux/arch/arm/mach-versatile/core.c
  *
  *  Copyright (C) 1999 - 2003 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
 #include <linux/gfp.h>
 #include <asm/clkdev.h>
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <mach/clkdev.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <plat/timer-sp.h>
 #include "core.h"
 /*
  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  * is the (PA >> 12).
  *
  * Setup a VA for the Versatile Vectored Interrupt Controller.
  */
 #define VA_VIC_BASE		__io_address(VERSATILE_VIC_BASE)
 #define VA_SIC_BASE		__io_address(VERSATILE_SIC_BASE)
 static void sic_mask_irq(unsigned int irq)
 {
 	irq -= IRQ_SIC_START;
 	writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 }
 static void sic_unmask_irq(unsigned int irq)
 {
 	irq -= IRQ_SIC_START;
 	writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
 }
 static struct irq_chip sic_chip = {
 	.name	= "SIC",
 	.ack	= sic_mask_irq,
 	.mask	= sic_mask_irq,
 	.unmask	= sic_unmask_irq,
 };
 static void
 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
 {
 	unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
 	if (status == 0) {
 		do_bad_IRQ(irq, desc);
 		return;
 	}
 	do {
 		irq = ffs(status) - 1;
 		status &= ~(1 << irq);
 		irq += IRQ_SIC_START;
 		generic_handle_irq(irq);
 	} while (status);
 }
 #if 1
 #define IRQ_MMCI0A	IRQ_VICSOURCE22
 #define IRQ_AACI	IRQ_VICSOURCE24
 #define IRQ_ETH		IRQ_VICSOURCE25
 #define PIC_MASK	0xFFD00000
 #else
 #define IRQ_MMCI0A	IRQ_SIC_MMCI0A
 #define IRQ_AACI	IRQ_SIC_AACI
 #define IRQ_ETH		IRQ_SIC_ETH
 #define PIC_MASK	0
 #endif
 void __init versatile_init_irq(void)
 {
 	unsigned int i;
 	vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
 	set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 	/* Do second interrupt controller */
 	writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 	for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 		if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 			set_irq_chip(i, &sic_chip);
 			set_irq_handler(i, handle_level_irq);
 			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 		}
 	}
 	/*
 	 * Interrupts on secondary controller from 0 to 8 are routed to
 	 * source 31 on PIC.
 	 * Interrupts from 21 to 31 are routed directly to the VIC on
 	 * the corresponding number on primary controller. This is controlled
 	 * by setting PIC_ENABLEx.
 	 */
 	writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 }
 static struct map_desc versatile_io_desc[] __initdata = {
 	{
 		.virtual	=  IO_ADDRESS(VERSATILE_SYS_BASE),
 		.pfn		= __phys_to_pfn(VERSATILE_SYS_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	=  IO_ADDRESS(VERSATILE_SIC_BASE),
 		.pfn		= __phys_to_pfn(VERSATILE_SIC_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	=  IO_ADDRESS(VERSATILE_VIC_BASE),
 		.pfn		= __phys_to_pfn(VERSATILE_VIC_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	=  IO_ADDRESS(VERSATILE_SCTL_BASE),
 		.pfn		= __phys_to_pfn(VERSATILE_SCTL_BASE),
 		.length		= SZ_4K * 9,
 		.type		= MT_DEVICE
 	},
 #ifdef CONFIG_MACH_VERSATILE_AB
  	{
 		.virtual	=  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 		.pfn		= __phys_to_pfn(VERSATILE_GPIO0_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	=  IO_ADDRESS(VERSATILE_IB2_BASE),
 		.pfn		= __phys_to_pfn(VERSATILE_IB2_BASE),
 		.length		= SZ_64M,
 		.type		= MT_DEVICE
 	},
 #endif
 #ifdef CONFIG_DEBUG_LL
  	{
 		.virtual	=  IO_ADDRESS(VERSATILE_UART0_BASE),
 		.pfn		= __phys_to_pfn(VERSATILE_UART0_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	},
 #endif
 #ifdef CONFIG_PCI
  	{
 		.virtual	=  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	=  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_BASE),
 		.length		= VERSATILE_PCI_BASE_SIZE,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	=  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 		.length		= VERSATILE_PCI_CFG_BASE_SIZE,
 		.type		= MT_DEVICE
 	},
 #if 0
  	{
 		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE0,
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 		.length		= SZ_16M,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE1,
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 		.length		= SZ_16M,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE2,
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 		.length		= SZ_16M,
 		.type		= MT_DEVICE
 	},
 #endif
 #endif
 };
 void __init versatile_map_io(void)
 {
 	iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 }
 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 static int versatile_flash_init(void)
 {
 	u32 val;
 	val = __raw_readl(VERSATILE_FLASHCTRL);
 	val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 	__raw_writel(val, VERSATILE_FLASHCTRL);
 	return 0;
 }
 static void versatile_flash_exit(void)
 {
 	u32 val;
 	val = __raw_readl(VERSATILE_FLASHCTRL);
 	val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 	__raw_writel(val, VERSATILE_FLASHCTRL);
 }
 static void versatile_flash_set_vpp(int on)
 {
 	u32 val;
 	val = __raw_readl(VERSATILE_FLASHCTRL);
 	if (on)
 		val |= VERSATILE_FLASHPROG_FLVPPEN;
 	else
 		val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 	__raw_writel(val, VERSATILE_FLASHCTRL);
 }
 static struct flash_platform_data versatile_flash_data = {
 	.map_name		= "cfi_probe",
 	.width			= 4,
 	.init			= versatile_flash_init,
 	.exit			= versatile_flash_exit,
 	.set_vpp		= versatile_flash_set_vpp,
 };
 static struct resource versatile_flash_resource = {
 	.start			= VERSATILE_FLASH_BASE,
 	.end			= VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 	.flags			= IORESOURCE_MEM,
 };
 static struct platform_device versatile_flash_device = {
 	.name			= "armflash",
 	.id			= 0,
 	.dev			= {
 		.platform_data	= &versatile_flash_data,
 	},
 	.num_resources		= 1,
 	.resource		= &versatile_flash_resource,
 };
 static struct resource smc91x_resources[] = {
 	[0] = {
 		.start		= VERSATILE_ETH_BASE,
 		.end		= VERSATILE_ETH_BASE + SZ_64K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 	[1] = {
 		.start		= IRQ_ETH,
 		.end		= IRQ_ETH,
 		.flags		= IORESOURCE_IRQ,
 	},
 };
 static struct platform_device smc91x_device = {
 	.name		= "smc91x",
 	.id		= 0,
 	.num_resources	= ARRAY_SIZE(smc91x_resources),
 	.resource	= smc91x_resources,
 };
 static struct resource versatile_i2c_resource = {
 	.start			= VERSATILE_I2C_BASE,
 	.end			= VERSATILE_I2C_BASE + SZ_4K - 1,
 	.flags			= IORESOURCE_MEM,
 };
 static struct platform_device versatile_i2c_device = {
 	.name			= "versatile-i2c",
 	.id			= 0,
 	.num_resources		= 1,
 	.resource		= &versatile_i2c_resource,
 };
 static struct i2c_board_info versatile_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 	},
 };
 static int __init versatile_i2c_init(void)
 {
 	return i2c_register_board_info(0, versatile_i2c_board_info,
 				       ARRAY_SIZE(versatile_i2c_board_info));
 }
 arch_initcall(versatile_i2c_init);
 #define VERSATILE_SYSMCI	(__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 unsigned int mmc_status(struct device *dev)
 {
 	struct amba_device *adev = container_of(dev, struct amba_device, dev);
 	u32 mask;
 	if (adev->res.start == VERSATILE_MMCI0_BASE)
 		mask = 1;
 	else
 		mask = 2;
 	return readl(VERSATILE_SYSMCI) & mask;
 }
 static struct mmci_platform_data mmc0_plat_data = {
 	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
 	.status		= mmc_status,
 	.gpio_wp	= -1,
 	.gpio_cd	= -1,
 };
 /*
  * Clock handling
  */
 static const struct icst_params versatile_oscvco_params = {
 	.ref		= 24000000,
 	.vco_max	= ICST307_VCO_MAX,
 	.vco_min	= ICST307_VCO_MIN,
 	.vd_min		= 4 + 8,
 	.vd_max		= 511 + 8,
 	.rd_min		= 1 + 2,
 	.rd_max		= 127 + 2,
 	.s2div		= icst307_s2div,
 	.idx2s		= icst307_idx2s,
 };
 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 {
 	void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 	u32 val;
 	val = readl(clk->vcoreg) & ~0x7ffff;
 	val |= vco.v | (vco.r << 9) | (vco.s << 16);
 	writel(0xa05f, sys_lock);
 	writel(val, clk->vcoreg);
 	writel(0, sys_lock);
 }
 static const struct clk_ops osc4_clk_ops = {
 	.round	= icst_clk_round,
 	.set	= icst_clk_set,
 	.setvco	= versatile_oscvco_set,
 };
 static struct clk osc4_clk = {
 	.ops	= &osc4_clk_ops,
 	.params	= &versatile_oscvco_params,
 };
 /*
  * These are fixed clocks.
  */
 static struct clk ref24_clk = {
 	.rate	= 24000000,
 };
+static struct clk dummy_apb_pclk;
 static struct clk_lookup lookups[] = {
-	{	/* UART0 */
+	{	/* AMBA bus clock */
+		.con_id		= "apb_pclk",
+		.clk		= &dummy_apb_pclk,
+	}, {	/* UART0 */
 		.dev_id		= "dev:f1",
 		.clk		= &ref24_clk,
 	}, {	/* UART1 */
 		.dev_id		= "dev:f2",
 		.clk		= &ref24_clk,
 	}, {	/* UART2 */
 		.dev_id		= "dev:f3",
 		.clk		= &ref24_clk,
 	}, {	/* UART3 */
 		.dev_id		= "fpga:09",
 		.clk		= &ref24_clk,
 	}, {	/* KMI0 */
 		.dev_id		= "fpga:06",
 		.clk		= &ref24_clk,
 	}, {	/* KMI1 */
 		.dev_id		= "fpga:07",
 		.clk		= &ref24_clk,
 	}, {	/* MMC0 */
 		.dev_id		= "fpga:05",
 		.clk		= &ref24_clk,
 	}, {	/* MMC1 */
 		.dev_id		= "fpga:0b",
 		.clk		= &ref24_clk,
 	}, {	/* CLCD */
 		.dev_id		= "dev:20",
 		.clk		= &osc4_clk,
 	}
 };
 /*
  * CLCD support.
  */
 #define SYS_CLCD_MODE_MASK	(3 << 0)
 #define SYS_CLCD_MODE_888	(0 << 0)
 #define SYS_CLCD_MODE_5551	(1 << 0)
 #define SYS_CLCD_MODE_565_RLSB	(2 << 0)
 #define SYS_CLCD_MODE_565_BLSB	(3 << 0)
 #define SYS_CLCD_NLCDIOON	(1 << 2)
 #define SYS_CLCD_VDDPOSSWITCH	(1 << 3)
 #define SYS_CLCD_PWR3V5SWITCH	(1 << 4)
 #define SYS_CLCD_ID_MASK	(0x1f << 8)
 #define SYS_CLCD_ID_SANYO_3_8	(0x00 << 8)
 #define SYS_CLCD_ID_UNKNOWN_8_4	(0x01 << 8)
 #define SYS_CLCD_ID_EPSON_2_2	(0x02 << 8)
 #define SYS_CLCD_ID_SANYO_2_5	(0x07 << 8)
 #define SYS_CLCD_ID_VGA		(0x1f << 8)
 static struct clcd_panel vga = {
 	.mode		= {
 		.name		= "VGA",
 		.refresh	= 60,
 		.xres		= 640,
 		.yres		= 480,
 		.pixclock	= 39721,
 		.left_margin	= 40,
 		.right_margin	= 24,
 		.upper_margin	= 32,
 		.lower_margin	= 11,
 		.hsync_len	= 96,
 		.vsync_len	= 2,
 		.sync		= 0,
 		.vmode		= FB_VMODE_NONINTERLACED,
 	},
 	.width		= -1,
 	.height		= -1,
 	.tim2		= TIM2_BCD | TIM2_IPC,
 	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 	.bpp		= 16,
 };
 static struct clcd_panel sanyo_3_8_in = {
 	.mode		= {
 		.name		= "Sanyo QVGA",
 		.refresh	= 116,
 		.xres		= 320,
 		.yres		= 240,
 		.pixclock	= 100000,
 		.left_margin	= 6,
 		.right_margin	= 6,
 		.upper_margin	= 5,
 		.lower_margin	= 5,
 		.hsync_len	= 6,
 		.vsync_len	= 6,
 		.sync		= 0,
 		.vmode		= FB_VMODE_NONINTERLACED,
 	},
 	.width		= -1,
 	.height		= -1,
 	.tim2		= TIM2_BCD,
 	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 	.bpp		= 16,
 };
 static struct clcd_panel sanyo_2_5_in = {
 	.mode		= {
 		.name		= "Sanyo QVGA Portrait",
 		.refresh	= 116,
 		.xres		= 240,
 		.yres		= 320,
 		.pixclock	= 100000,
 		.left_margin	= 20,
 		.right_margin	= 10,
 		.upper_margin	= 2,
 		.lower_margin	= 2,
 		.hsync_len	= 10,
 		.vsync_len	= 2,
 		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 		.vmode		= FB_VMODE_NONINTERLACED,
 	},
 	.width		= -1,
 	.height		= -1,
 	.tim2		= TIM2_IVS | TIM2_IHS | TIM2_IPC,
 	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 	.bpp		= 16,
 };
 static struct clcd_panel epson_2_2_in = {
 	.mode		= {
 		.name		= "Epson QCIF",
 		.refresh	= 390,
 		.xres		= 176,
 		.yres		= 220,
 		.pixclock	= 62500,
 		.left_margin	= 3,
 		.right_margin	= 2,
 		.upper_margin	= 1,
 		.lower_margin	= 0,
 		.hsync_len	= 3,
 		.vsync_len	= 2,
 		.sync		= 0,
 		.vmode		= FB_VMODE_NONINTERLACED,
 	},
 	.width		= -1,
 	.height		= -1,
 	.tim2		= TIM2_BCD | TIM2_IPC,
 	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 	.bpp		= 16,
 };
 /*
  * Detect which LCD panel is connected, and return the appropriate
  * clcd_panel structure.  Note: we do not have any information on
  * the required timings for the 8.4in panel, so we presently assume
  * VGA timings.
  */
 static struct clcd_panel *versatile_clcd_panel(void)
 {
 	void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 	struct clcd_panel *panel = &vga;
 	u32 val;
 	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 	if (val == SYS_CLCD_ID_SANYO_3_8)
 		panel = &sanyo_3_8_in;
 	else if (val == SYS_CLCD_ID_SANYO_2_5)
 		panel = &sanyo_2_5_in;
 	else if (val == SYS_CLCD_ID_EPSON_2_2)
 		panel = &epson_2_2_in;
 	else if (val == SYS_CLCD_ID_VGA)
 		panel = &vga;
 	else {
 		printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 			val);
 		panel = &vga;
 	}
 	return panel;
 }
 /*
  * Disable all display connectors on the interface module.
  */
 static void versatile_clcd_disable(struct clcd_fb *fb)
 {
 	void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 	u32 val;
 	val = readl(sys_clcd);
 	val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 	writel(val, sys_clcd);
 #ifdef CONFIG_MACH_VERSATILE_AB
 	/*
 	 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 	 */
 	if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 		void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 		unsigned long ctrl;
 		ctrl = readl(versatile_ib2_ctrl);
 		ctrl &= ~0x01;
 		writel(ctrl, versatile_ib2_ctrl);
 	}
 #endif
 }
 /*
  * Enable the relevant connector on the interface module.
  */
 static void versatile_clcd_enable(struct clcd_fb *fb)
 {
 	void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 	u32 val;
 	val = readl(sys_clcd);
 	val &= ~SYS_CLCD_MODE_MASK;
 	switch (fb->fb.var.green.length) {
 	case 5:
 		val |= SYS_CLCD_MODE_5551;
 		break;
 	case 6:
 		val |= SYS_CLCD_MODE_565_RLSB;
 		break;
 	case 8:
 		val |= SYS_CLCD_MODE_888;
 		break;
 	}
 	/*
 	 * Set the MUX
 	 */
 	writel(val, sys_clcd);
 	/*
 	 * And now enable the PSUs
 	 */
 	val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 	writel(val, sys_clcd);
 #ifdef CONFIG_MACH_VERSATILE_AB
 	/*
 	 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 	 */
 	if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 		void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 		unsigned long ctrl;
 		ctrl = readl(versatile_ib2_ctrl);
 		ctrl |= 0x01;
 		writel(ctrl, versatile_ib2_ctrl);
 	}
 #endif
 }
 static unsigned long framesize = SZ_1M;
 static int versatile_clcd_setup(struct clcd_fb *fb)
 {
 	dma_addr_t dma;
 	fb->panel		= versatile_clcd_panel();
 	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 						    &dma, GFP_KERNEL);
 	if (!fb->fb.screen_base) {
 		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 		return -ENOMEM;
 	}
 	fb->fb.fix.smem_start	= dma;
 	fb->fb.fix.smem_len	= framesize;
 	return 0;
 }
 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 {
 	return dma_mmap_writecombine(&fb->dev->dev, vma,
 				     fb->fb.screen_base,
 				     fb->fb.fix.smem_start,
 				     fb->fb.fix.smem_len);
 }
 static void versatile_clcd_remove(struct clcd_fb *fb)
 {
 	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 			      fb->fb.screen_base, fb->fb.fix.smem_start);
 }
 static struct clcd_board clcd_plat_data = {
 	.name		= "Versatile",
 	.check		= clcdfb_check,
 	.decode		= clcdfb_decode,
 	.disable	= versatile_clcd_disable,
 	.enable		= versatile_clcd_enable,
 	.setup		= versatile_clcd_setup,
 	.mmap		= versatile_clcd_mmap,
 	.remove		= versatile_clcd_remove,
 };
 static struct pl061_platform_data gpio0_plat_data = {
 	.gpio_base	= 0,
 	.irq_base	= IRQ_GPIO0_START,
 };
 static struct pl061_platform_data gpio1_plat_data = {
 	.gpio_base	= 8,
 	.irq_base	= IRQ_GPIO1_START,
 };
 #define AACI_IRQ	{ IRQ_AACI, NO_IRQ }
 #define AACI_DMA	{ 0x80, 0x81 }
 #define MMCI0_IRQ	{ IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 #define MMCI0_DMA	{ 0x84, 0 }
 #define KMI0_IRQ	{ IRQ_SIC_KMI0, NO_IRQ }
 #define KMI0_DMA	{ 0, 0 }
 #define KMI1_IRQ	{ IRQ_SIC_KMI1, NO_IRQ }
 #define KMI1_DMA	{ 0, 0 }
 /*
  * These devices are connected directly to the multi-layer AHB switch
  */
 #define SMC_IRQ		{ NO_IRQ, NO_IRQ }
 #define SMC_DMA		{ 0, 0 }
 #define MPMC_IRQ	{ NO_IRQ, NO_IRQ }
 #define MPMC_DMA	{ 0, 0 }
 #define CLCD_IRQ	{ IRQ_CLCDINT, NO_IRQ }
 #define CLCD_DMA	{ 0, 0 }
 #define DMAC_IRQ	{ IRQ_DMAINT, NO_IRQ }
 #define DMAC_DMA	{ 0, 0 }
 /*
  * These devices are connected via the core APB bridge
  */
 #define SCTL_IRQ	{ NO_IRQ, NO_IRQ }
 #define SCTL_DMA	{ 0, 0 }
 #define WATCHDOG_IRQ	{ IRQ_WDOGINT, NO_IRQ }
 #define WATCHDOG_DMA	{ 0, 0 }
 #define GPIO0_IRQ	{ IRQ_GPIOINT0, NO_IRQ }
 #define GPIO0_DMA	{ 0, 0 }
 #define GPIO1_IRQ	{ IRQ_GPIOINT1, NO_IRQ }
 #define GPIO1_DMA	{ 0, 0 }
 #define RTC_IRQ		{ IRQ_RTCINT, NO_IRQ }
 #define RTC_DMA		{ 0, 0 }
 /*
  * These devices are connected via the DMA APB bridge
  */
 #define SCI_IRQ		{ IRQ_SCIINT, NO_IRQ }
 #define SCI_DMA		{ 7, 6 }
 #define UART0_IRQ	{ IRQ_UARTINT0, NO_IRQ }
 #define UART0_DMA	{ 15, 14 }
 #define UART1_IRQ	{ IRQ_UARTINT1, NO_IRQ }
 #define UART1_DMA	{ 13, 12 }
 #define UART2_IRQ	{ IRQ_UARTINT2, NO_IRQ }
 #define UART2_DMA	{ 11, 10 }
 #define SSP_IRQ		{ IRQ_SSPINT, NO_IRQ }
 #define SSP_DMA		{ 9, 8 }
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 /* DevChip Primecells */
 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 static struct amba_device *amba_devs[] __initdata = {
 	&dmac_device,
 	&uart0_device,
 	&uart1_device,
 	&uart2_device,
 	&smc_device,
 	&mpmc_device,
 	&clcd_device,
 	&sctl_device,
 	&wdog_device,
 	&gpio0_device,
 	&gpio1_device,
 	&rtc_device,
 	&sci0_device,
 	&ssp0_device,
 	&aaci_device,
 	&mmc0_device,
 	&kmi0_device,
 	&kmi1_device,
 };
 #ifdef CONFIG_LEDS
 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 static void versatile_leds_event(led_event_t ledevt)
 {
 	unsigned long flags;
 	u32 val;
 	local_irq_save(flags);
 	val = readl(VA_LEDS_BASE);
 	switch (ledevt) {
 	case led_idle_start:
 		val = val & ~VERSATILE_SYS_LED0;
 		break;
 	case led_idle_end:
 		val = val | VERSATILE_SYS_LED0;
 		break;
 	case led_timer:
 		val = val ^ VERSATILE_SYS_LED1;
 		break;
 	case led_halted:
 		val = 0;
 		break;
 	default:
 		break;
 	}
 	writel(val, VA_LEDS_BASE);
 	local_irq_restore(flags);
 }
 #endif	/* CONFIG_LEDS */
 void __init versatile_init(void)
 {
 	int i;
 	osc4_clk.vcoreg	= __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 	platform_device_register(&versatile_flash_device);
 	platform_device_register(&versatile_i2c_device);
 	platform_device_register(&smc91x_device);
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
 #ifdef CONFIG_LEDS
 	leds_event = versatile_leds_event;
 #endif
 }
 /*
  * Where is the timer (VA)?
  */
 #define TIMER0_VA_BASE		 __io_address(VERSATILE_TIMER0_1_BASE)
 #define TIMER1_VA_BASE		(__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 #define TIMER2_VA_BASE		 __io_address(VERSATILE_TIMER2_3_BASE)
 #define TIMER3_VA_BASE		(__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 /*
  * Set up timer interrupt, and return the current time in seconds.
  */
 static void __init versatile_timer_init(void)
 {
 	u32 val;
 	/*
 	 * set clock frequency:
 	 *	VERSATILE_REFCLK is 32KHz
 	 *	VERSATILE_TIMCLK is 1MHz
 	 */
 	val = readl(__io_address(VERSATILE_SCTL_BASE));
 	writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 	       (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 	       (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 	       (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 	       __io_address(VERSATILE_SCTL_BASE));
 	/*
 	 * Initialise to a known state (all timers off)
 	 */
 	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 	sp804_clocksource_init(TIMER3_VA_BASE);
 	sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
 }
 struct sys_timer versatile_timer = {
 	.init		= versatile_timer_init,
 };

arch/arm/mach-vexpress/v2m.c

Diff comments View file @ 3126c7b

 /*
  * Versatile Express V2M Motherboard Support
  */
 #include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 #include <linux/spinlock.h>
 #include <linux/sysdev.h>
 #include <linux/usb/isp1760.h>
 #include <asm/clkdev.h>
 #include <asm/sizes.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/arm_timer.h>
 #include <mach/clkdev.h>
 #include <mach/motherboard.h>
 #include <plat/timer-sp.h>
 #include "core.h"
 #define V2M_PA_CS0	0x40000000
 #define V2M_PA_CS1	0x44000000
 #define V2M_PA_CS2	0x48000000
 #define V2M_PA_CS3	0x4c000000
 #define V2M_PA_CS7	0x10000000
 static struct map_desc v2m_io_desc[] __initdata = {
 	{
 		.virtual	= __MMIO_P2V(V2M_PA_CS7),
 		.pfn		= __phys_to_pfn(V2M_PA_CS7),
 		.length		= SZ_128K,
 		.type		= MT_DEVICE,
 	},
 };
 void __init v2m_map_io(struct map_desc *tile, size_t num)
 {
 	iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
 	iotable_init(tile, num);
 }
 static void v2m_timer_init(void)
 {
 	writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
 	writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
 	sp804_clocksource_init(MMIO_P2V(V2M_TIMER1));
 	sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0);
 }
 struct sys_timer v2m_timer = {
 	.init	= v2m_timer_init,
 };
 static DEFINE_SPINLOCK(v2m_cfg_lock);
 int v2m_cfg_write(u32 devfn, u32 data)
 {
 	/* Configuration interface broken? */
 	u32 val;
 	printk("%s: writing %08x to %08x\n", __func__, data, devfn);
 	devfn |= SYS_CFG_START | SYS_CFG_WRITE;
 	spin_lock(&v2m_cfg_lock);
 	val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
 	writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
 	writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
 	writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
 	do {
 		val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
 	} while (val == 0);
 	spin_unlock(&v2m_cfg_lock);
 	return !!(val & SYS_CFG_ERR);
 }
 int v2m_cfg_read(u32 devfn, u32 *data)
 {
 	u32 val;
 	devfn |= SYS_CFG_START;
 	spin_lock(&v2m_cfg_lock);
 	writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
 	writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
 	mb();
 	do {
 		cpu_relax();
 		val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
 	} while (val == 0);
 	*data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
 	spin_unlock(&v2m_cfg_lock);
 	return !!(val & SYS_CFG_ERR);
 }
 static struct resource v2m_pcie_i2c_resource = {
 	.start	= V2M_SERIAL_BUS_PCI,
 	.end	= V2M_SERIAL_BUS_PCI + SZ_4K - 1,
 	.flags	= IORESOURCE_MEM,
 };
 static struct platform_device v2m_pcie_i2c_device = {
 	.name		= "versatile-i2c",
 	.id		= 0,
 	.num_resources	= 1,
 	.resource	= &v2m_pcie_i2c_resource,
 };
 static struct resource v2m_ddc_i2c_resource = {
 	.start	= V2M_SERIAL_BUS_DVI,
 	.end	= V2M_SERIAL_BUS_DVI + SZ_4K - 1,
 	.flags	= IORESOURCE_MEM,
 };
 static struct platform_device v2m_ddc_i2c_device = {
 	.name		= "versatile-i2c",
 	.id		= 1,
 	.num_resources	= 1,
 	.resource	= &v2m_ddc_i2c_resource,
 };
 static struct resource v2m_eth_resources[] = {
 	{
 		.start	= V2M_LAN9118,
 		.end	= V2M_LAN9118 + SZ_64K - 1,
 		.flags	= IORESOURCE_MEM,
 	}, {
 		.start	= IRQ_V2M_LAN9118,
 		.end	= IRQ_V2M_LAN9118,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 static struct smsc911x_platform_config v2m_eth_config = {
 	.flags		= SMSC911X_USE_32BIT,
 	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
 	.phy_interface	= PHY_INTERFACE_MODE_MII,
 };
 static struct platform_device v2m_eth_device = {
 	.name		= "smsc911x",
 	.id		= -1,
 	.resource	= v2m_eth_resources,
 	.num_resources	= ARRAY_SIZE(v2m_eth_resources),
 	.dev.platform_data = &v2m_eth_config,
 };
 static struct resource v2m_usb_resources[] = {
 	{
 		.start	= V2M_ISP1761,
 		.end	= V2M_ISP1761 + SZ_128K - 1,
 		.flags	= IORESOURCE_MEM,
 	}, {
 		.start	= IRQ_V2M_ISP1761,
 		.end	= IRQ_V2M_ISP1761,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 static struct isp1760_platform_data v2m_usb_config = {
 	.is_isp1761		= true,
 	.bus_width_16		= false,
 	.port1_otg		= true,
 	.analog_oc		= false,
 	.dack_polarity_high	= false,
 	.dreq_polarity_high	= false,
 };
 static struct platform_device v2m_usb_device = {
 	.name		= "isp1760",
 	.id		= -1,
 	.resource	= v2m_usb_resources,
 	.num_resources	= ARRAY_SIZE(v2m_usb_resources),
 	.dev.platform_data = &v2m_usb_config,
 };
 static int v2m_flash_init(void)
 {
 	writel(0, MMIO_P2V(V2M_SYS_FLASH));
 	return 0;
 }
 static void v2m_flash_exit(void)
 {
 	writel(0, MMIO_P2V(V2M_SYS_FLASH));
 }
 static void v2m_flash_set_vpp(int on)
 {
 	writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
 }
 static struct flash_platform_data v2m_flash_data = {
 	.map_name	= "cfi_probe",
 	.width		= 4,
 	.init		= v2m_flash_init,
 	.exit		= v2m_flash_exit,
 	.set_vpp	= v2m_flash_set_vpp,
 };
 static struct resource v2m_flash_resources[] = {
 	{
 		.start	= V2M_NOR0,
 		.end	= V2M_NOR0 + SZ_64M - 1,
 		.flags	= IORESOURCE_MEM,
 	}, {
 		.start	= V2M_NOR1,
 		.end	= V2M_NOR1 + SZ_64M - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 static struct platform_device v2m_flash_device = {
 	.name		= "armflash",
 	.id		= -1,
 	.resource	= v2m_flash_resources,
 	.num_resources	= ARRAY_SIZE(v2m_flash_resources),
 	.dev.platform_data = &v2m_flash_data,
 };
 static unsigned int v2m_mmci_status(struct device *dev)
 {
 	return !(readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0));
 }
 static struct mmci_platform_data v2m_mmci_data = {
 	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
 	.status		= v2m_mmci_status,
 };
 static AMBA_DEVICE(aaci,  "mb:aaci",  V2M_AACI, NULL);
 static AMBA_DEVICE(mmci,  "mb:mmci",  V2M_MMCI, &v2m_mmci_data);
 static AMBA_DEVICE(kmi0,  "mb:kmi0",  V2M_KMI0, NULL);
 static AMBA_DEVICE(kmi1,  "mb:kmi1",  V2M_KMI1, NULL);
 static AMBA_DEVICE(uart0, "mb:uart0", V2M_UART0, NULL);
 static AMBA_DEVICE(uart1, "mb:uart1", V2M_UART1, NULL);
 static AMBA_DEVICE(uart2, "mb:uart2", V2M_UART2, NULL);
 static AMBA_DEVICE(uart3, "mb:uart3", V2M_UART3, NULL);
 static AMBA_DEVICE(wdt,   "mb:wdt",   V2M_WDT, NULL);
 static AMBA_DEVICE(rtc,   "mb:rtc",   V2M_RTC, NULL);
 static struct amba_device *v2m_amba_devs[] __initdata = {
 	&aaci_device,
 	&mmci_device,
 	&kmi0_device,
 	&kmi1_device,
 	&uart0_device,
 	&uart1_device,
 	&uart2_device,
 	&uart3_device,
 	&wdt_device,
 	&rtc_device,
 };
 static long v2m_osc_round(struct clk *clk, unsigned long rate)
 {
 	return rate;
 }
 static int v2m_osc1_set(struct clk *clk, unsigned long rate)
 {
 	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate);
 }
 static const struct clk_ops osc1_clk_ops = {
 	.round	= v2m_osc_round,
 	.set	= v2m_osc1_set,
 };
 static struct clk osc1_clk = {
 	.ops	= &osc1_clk_ops,
 	.rate	= 24000000,
 };
 static struct clk osc2_clk = {
 	.rate	= 24000000,
 };
+static struct clk dummy_apb_pclk;
 static struct clk_lookup v2m_lookups[] = {
-	{	/* UART0 */
+	{	/* AMBA bus clock */
+		.con_id		= "apb_pclk",
+		.clk		= &dummy_apb_pclk,
+	}, {	/* UART0 */
 		.dev_id		= "mb:uart0",
 		.clk		= &osc2_clk,
 	}, {	/* UART1 */
 		.dev_id		= "mb:uart1",
 		.clk		= &osc2_clk,
 	}, {	/* UART2 */
 		.dev_id		= "mb:uart2",
 		.clk		= &osc2_clk,
 	}, {	/* UART3 */
 		.dev_id		= "mb:uart3",
 		.clk		= &osc2_clk,
 	}, {	/* KMI0 */
 		.dev_id		= "mb:kmi0",
 		.clk		= &osc2_clk,
 	}, {	/* KMI1 */
 		.dev_id		= "mb:kmi1",
 		.clk		= &osc2_clk,
 	}, {	/* MMC0 */
 		.dev_id		= "mb:mmci",
 		.clk		= &osc2_clk,
 	}, {	/* CLCD */
 		.dev_id		= "mb:clcd",
 		.clk		= &osc1_clk,
 	},
 };
 static void v2m_power_off(void)
 {
 	if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0))
 		printk(KERN_EMERG "Unable to shutdown\n");
 }
 static void v2m_restart(char str, const char *cmd)
 {
 	if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
 		printk(KERN_EMERG "Unable to reboot\n");
 }
 static int __init v2m_init(void)
 {
 	int i;
 	clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
 	platform_device_register(&v2m_pcie_i2c_device);
 	platform_device_register(&v2m_ddc_i2c_device);
 	platform_device_register(&v2m_flash_device);
 	platform_device_register(&v2m_eth_device);
 	platform_device_register(&v2m_usb_device);
 	for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
 		amba_device_register(v2m_amba_devs[i], &iomem_resource);
 	pm_power_off = v2m_power_off;
 	arm_pm_restart = v2m_restart;
 	return 0;
 }
 arch_initcall(v2m_init);