Commit 3126c7bc4106c572ef47e2c220df5a00e7973379

Authored by Russell King
1 parent 2f7989efd4

ARM: AMBA: Add pclk definition for platforms using primecells

Add a dummy clk definition for the APB pclk signal on all platforms
using the AMBA bus infrastructure.  This ensures that these platforms
continue to work when the core amba bus code controls the APB pclk.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 12 changed files with 66 additions and 12 deletions Side-by-side Diff

arch/arm/mach-bcmring/core.c
... ... @@ -91,14 +91,23 @@
91 91 .parent = &pll1_clk,
92 92 };
93 93  
  94 +static struct clk dummy_apb_pclk = {
  95 + .name = "BUSCLK",
  96 + .type = CLK_TYPE_PRIMARY,
  97 + .mode = CLK_MODE_XTAL,
  98 +};
  99 +
94 100 static struct clk_lookup lookups[] = {
95   - { /* UART0 */
96   - .dev_id = "uarta",
97   - .clk = &uart_clk,
98   - }, { /* UART1 */
99   - .dev_id = "uartb",
100   - .clk = &uart_clk,
101   - }
  101 + { /* Bus clock */
  102 + .con_id = "apb_pclk",
  103 + .clk = &dummy_apb_pclk,
  104 + }, { /* UART0 */
  105 + .dev_id = "uarta",
  106 + .clk = &uart_clk,
  107 + }, { /* UART1 */
  108 + .dev_id = "uartb",
  109 + .clk = &uart_clk,
  110 + }
102 111 };
103 112  
104 113 static struct amba_device *amba_devs[] __initdata = {
arch/arm/mach-ep93xx/clock.c
... ... @@ -185,7 +185,7 @@
185 185 INIT_CK(NULL, "pll1", &clk_pll1),
186 186 INIT_CK(NULL, "fclk", &clk_f),
187 187 INIT_CK(NULL, "hclk", &clk_h),
188   - INIT_CK(NULL, "pclk", &clk_p),
  188 + INIT_CK(NULL, "apb_pclk", &clk_p),
189 189 INIT_CK(NULL, "pll2", &clk_pll2),
190 190 INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
191 191 INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
arch/arm/mach-integrator/core.c
... ... @@ -119,8 +119,13 @@
119 119 .rate = 14745600,
120 120 };
121 121  
  122 +static struct clk dummy_apb_pclk;
  123 +
122 124 static struct clk_lookup lookups[] = {
123   - { /* UART0 */
  125 + { /* Bus clock */
  126 + .con_id = "apb_pclk",
  127 + .clk = &dummy_apb_pclk,
  128 + }, { /* UART0 */
124 129 .dev_id = "mb:16",
125 130 .clk = &uartclk,
126 131 }, { /* UART1 */
arch/arm/mach-nomadik/clock.c
... ... @@ -53,6 +53,10 @@
53 53 }
54 54  
55 55 static struct clk_lookup lookups[] = {
  56 + {
  57 + .con_id = "apb_pclk",
  58 + .clk = &clk_default,
  59 + },
56 60 CLK(&clk_24, "mtu0"),
57 61 CLK(&clk_24, "mtu1"),
58 62 CLK(&clk_48, "uart0"),
arch/arm/mach-omap2/clock3xxx_data.c
... ... @@ -3166,6 +3166,10 @@
3166 3166 .recalc = &followparent_recalc,
3167 3167 };
3168 3168  
  3169 +static struct clk dummy_apb_pclk = {
  3170 + .name = "apb_pclk",
  3171 + .ops = &clkops_null,
  3172 +};
3169 3173  
3170 3174 /*
3171 3175 * clkdev
... ... @@ -3173,6 +3177,7 @@
3173 3177  
3174 3178 /* XXX At some point we should rename this file to clock3xxx_data.c */
3175 3179 static struct omap_clk omap3xxx_clks[] = {
  3180 + CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3176 3181 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3177 3182 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3178 3183 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
arch/arm/mach-realview/core.c
... ... @@ -300,8 +300,13 @@
300 300 .rate = 24000000,
301 301 };
302 302  
  303 +static struct clk dummy_apb_pclk;
  304 +
303 305 static struct clk_lookup lookups[] = {
304   - { /* UART0 */
  306 + { /* Bus clock */
  307 + .con_id = "apb_pclk",
  308 + .clk = &dummy_apb_pclk,
  309 + }, { /* UART0 */
305 310 .dev_id = "dev:uart0",
306 311 .clk = &ref24_clk,
307 312 }, { /* UART1 */
arch/arm/mach-spear3xx/clock.c
... ... @@ -341,8 +341,11 @@
341 341 .recalc = &follow_parent,
342 342 };
343 343  
  344 +static struct clk dummy_apb_pclk;
  345 +
344 346 /* array of all spear 3xx clock lookups */
345 347 static struct clk_lookup spear_clk_lookups[] = {
  348 + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
346 349 /* root clks */
347 350 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
348 351 { .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
arch/arm/mach-spear6xx/clock.c
... ... @@ -428,8 +428,11 @@
428 428 .recalc = &follow_parent,
429 429 };
430 430  
  431 +static struct clk dummy_apb_pclk;
  432 +
431 433 /* array of all spear 6xx clock lookups */
432 434 static struct clk_lookup spear_clk_lookups[] = {
  435 + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
433 436 /* root clks */
434 437 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
435 438 { .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
arch/arm/mach-u300/clock.c
... ... @@ -1212,6 +1212,8 @@
1212 1212 };
1213 1213 #endif
1214 1214  
  1215 +static struct clk dummy_apb_pclk;
  1216 +
1215 1217 #define DEF_LOOKUP(devid, clkref) \
1216 1218 { \
1217 1219 .dev_id = devid, \
... ... @@ -1223,6 +1225,10 @@
1223 1225 * look up through clockdevice.
1224 1226 */
1225 1227 static struct clk_lookup lookups[] = {
  1228 + {
  1229 + .con_id = "apb_pclk",
  1230 + .clk = &dummy_apb_pclk,
  1231 + },
1226 1232 /* Connected directly to the AMBA bus */
1227 1233 DEF_LOOKUP("amba", &amba_clk),
1228 1234 DEF_LOOKUP("cpu", &cpu_clk),
arch/arm/mach-ux500/clock.c
... ... @@ -453,7 +453,11 @@
453 453 static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
454 454 static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
455 455  
  456 +static struct clk clk_dummy_apb_pclk;
  457 +
456 458 static struct clk_lookup u8500_common_clks[] = {
  459 + CLK(dummy_apb_pclk, NULL, "apb_pclk"),
  460 +
457 461 /* Peripheral Cluster #1 */
458 462 CLK(gpio0, "gpio.0", NULL),
459 463 CLK(gpio0, "gpio.1", NULL),
arch/arm/mach-versatile/core.c
... ... @@ -400,8 +400,13 @@
400 400 .rate = 24000000,
401 401 };
402 402  
  403 +static struct clk dummy_apb_pclk;
  404 +
403 405 static struct clk_lookup lookups[] = {
404   - { /* UART0 */
  406 + { /* AMBA bus clock */
  407 + .con_id = "apb_pclk",
  408 + .clk = &dummy_apb_pclk,
  409 + }, { /* UART0 */
405 410 .dev_id = "dev:f1",
406 411 .clk = &ref24_clk,
407 412 }, { /* UART1 */
arch/arm/mach-vexpress/v2m.c
... ... @@ -298,8 +298,13 @@
298 298 .rate = 24000000,
299 299 };
300 300  
  301 +static struct clk dummy_apb_pclk;
  302 +
301 303 static struct clk_lookup v2m_lookups[] = {
302   - { /* UART0 */
  304 + { /* AMBA bus clock */
  305 + .con_id = "apb_pclk",
  306 + .clk = &dummy_apb_pclk,
  307 + }, { /* UART0 */
303 308 .dev_id = "mb:uart0",
304 309 .clk = &osc2_clk,
305 310 }, { /* UART1 */